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3 * Copyright © 2014 Broadcom
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26 * @file vc4_qpu_schedule.c
28 * The basic model of the list scheduler is to take a basic block, compute a
29 * DAG of the dependencies, and make a list of the DAG heads. Heuristically
30 * pick a DAG head, then put all the children that are now DAG heads into the
31 * list of things to schedule.
33 * The goal of scheduling here is to pack pairs of operations together in a
34 * single QPU instruction.
39 #include "util/ralloc.h"
43 struct schedule_node_child;
45 struct schedule_node {
46 struct list_head link;
47 struct queued_qpu_inst *inst;
48 struct schedule_node_child *children;
50 uint32_t child_array_size;
51 uint32_t parent_count;
53 /* Longest cycles + n->latency of any parent of this node. */
54 uint32_t unblocked_time;
57 * Minimum number of cycles from scheduling this instruction until the
58 * end of the program, based on the slowest dependency chain through
64 * cycles between this instruction being scheduled and when its result
70 * Which uniform from uniform_data[] this instruction read, or -1 if
71 * not reading a uniform.
76 struct schedule_node_child {
77 struct schedule_node *node;
78 bool write_after_read;
81 /* When walking the instructions in reverse, we need to swap before/after in
84 enum direction { F, R };
86 struct schedule_state {
87 struct schedule_node *last_r[6];
88 struct schedule_node *last_ra[32];
89 struct schedule_node *last_rb[32];
90 struct schedule_node *last_sf;
91 struct schedule_node *last_vpm_read;
92 struct schedule_node *last_tmu_write;
93 struct schedule_node *last_tlb;
94 struct schedule_node *last_vpm;
96 /* Estimated cycle when the current instruction would start. */
101 add_dep(struct schedule_state *state,
102 struct schedule_node *before,
103 struct schedule_node *after,
106 bool write_after_read = !write && state->dir == R;
108 if (!before || !after)
111 assert(before != after);
113 if (state->dir == R) {
114 struct schedule_node *t = before;
119 for (int i = 0; i < before->child_count; i++) {
120 if (before->children[i].node == after &&
121 (before->children[i].write_after_read == write_after_read)) {
126 if (before->child_array_size <= before->child_count) {
127 before->child_array_size = MAX2(before->child_array_size * 2, 16);
128 before->children = reralloc(before, before->children,
129 struct schedule_node_child,
130 before->child_array_size);
133 before->children[before->child_count].node = after;
134 before->children[before->child_count].write_after_read =
136 before->child_count++;
137 after->parent_count++;
141 add_read_dep(struct schedule_state *state,
142 struct schedule_node *before,
143 struct schedule_node *after)
145 add_dep(state, before, after, false);
149 add_write_dep(struct schedule_state *state,
150 struct schedule_node **before,
151 struct schedule_node *after)
153 add_dep(state, *before, after, true);
158 qpu_writes_r4(uint64_t inst)
160 uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
163 case QPU_SIG_COLOR_LOAD:
164 case QPU_SIG_LOAD_TMU0:
165 case QPU_SIG_LOAD_TMU1:
166 case QPU_SIG_ALPHA_MASK_LOAD:
174 process_raddr_deps(struct schedule_state *state, struct schedule_node *n,
175 uint32_t raddr, bool is_a)
179 add_write_dep(state, &state->last_r[5], n);
183 add_write_dep(state, &state->last_vpm_read, n);
189 case QPU_R_XY_PIXEL_COORD:
190 case QPU_R_MS_REV_FLAGS:
196 add_read_dep(state, state->last_ra[raddr], n);
198 add_read_dep(state, state->last_rb[raddr], n);
200 fprintf(stderr, "unknown raddr %d\n", raddr);
208 is_tmu_write(uint32_t waddr)
226 reads_uniform(uint64_t inst)
228 if (QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_LOAD_IMM)
231 return (QPU_GET_FIELD(inst, QPU_RADDR_A) == QPU_R_UNIF ||
232 (QPU_GET_FIELD(inst, QPU_RADDR_B) == QPU_R_UNIF &&
233 QPU_GET_FIELD(inst, QPU_SIG) != QPU_SIG_SMALL_IMM) ||
234 is_tmu_write(QPU_GET_FIELD(inst, QPU_WADDR_ADD)) ||
235 is_tmu_write(QPU_GET_FIELD(inst, QPU_WADDR_MUL)));
239 process_mux_deps(struct schedule_state *state, struct schedule_node *n,
242 if (mux != QPU_MUX_A && mux != QPU_MUX_B)
243 add_read_dep(state, state->last_r[mux], n);
248 process_waddr_deps(struct schedule_state *state, struct schedule_node *n,
249 uint32_t waddr, bool is_add)
251 uint64_t inst = n->inst->inst;
252 bool is_a = is_add ^ ((inst & QPU_WS) != 0);
256 add_write_dep(state, &state->last_ra[waddr], n);
258 add_write_dep(state, &state->last_rb[waddr], n);
260 } else if (is_tmu_write(waddr)) {
261 add_write_dep(state, &state->last_tmu_write, n);
262 } else if (qpu_waddr_is_tlb(waddr) ||
263 waddr == QPU_W_MS_FLAGS) {
264 add_write_dep(state, &state->last_tlb, n);
272 add_write_dep(state, &state->last_r[waddr - QPU_W_ACC0],
277 add_write_dep(state, &state->last_vpm, n);
280 case QPU_W_VPMVCD_SETUP:
282 add_write_dep(state, &state->last_vpm_read, n);
284 add_write_dep(state, &state->last_vpm, n);
287 case QPU_W_SFU_RECIP:
288 case QPU_W_SFU_RECIPSQRT:
291 add_write_dep(state, &state->last_r[4], n);
294 case QPU_W_TLB_STENCIL_SETUP:
295 /* This isn't a TLB operation that does things like
296 * implicitly lock the scoreboard, but it does have to
297 * appear before TLB_Z, and each of the TLB_STENCILs
298 * have to schedule in the same order relative to each
301 add_write_dep(state, &state->last_tlb, n);
305 add_write_dep(state, &state->last_tlb, n);
312 fprintf(stderr, "Unknown waddr %d\n", waddr);
319 process_cond_deps(struct schedule_state *state, struct schedule_node *n,
324 case QPU_COND_ALWAYS:
327 add_read_dep(state, state->last_sf, n);
333 * Common code for dependencies that need to be tracked both forward and
336 * This is for things like "all reads of r4 have to happen between the r4
337 * writes that surround them".
340 calculate_deps(struct schedule_state *state, struct schedule_node *n)
342 uint64_t inst = n->inst->inst;
343 uint32_t add_op = QPU_GET_FIELD(inst, QPU_OP_ADD);
344 uint32_t mul_op = QPU_GET_FIELD(inst, QPU_OP_MUL);
345 uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
346 uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
347 uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
348 uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
349 uint32_t add_a = QPU_GET_FIELD(inst, QPU_ADD_A);
350 uint32_t add_b = QPU_GET_FIELD(inst, QPU_ADD_B);
351 uint32_t mul_a = QPU_GET_FIELD(inst, QPU_MUL_A);
352 uint32_t mul_b = QPU_GET_FIELD(inst, QPU_MUL_B);
353 uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
355 if (sig != QPU_SIG_LOAD_IMM) {
356 process_raddr_deps(state, n, raddr_a, true);
357 if (sig != QPU_SIG_SMALL_IMM)
358 process_raddr_deps(state, n, raddr_b, false);
361 if (add_op != QPU_A_NOP) {
362 process_mux_deps(state, n, add_a);
363 process_mux_deps(state, n, add_b);
365 if (mul_op != QPU_M_NOP) {
366 process_mux_deps(state, n, mul_a);
367 process_mux_deps(state, n, mul_b);
370 process_waddr_deps(state, n, waddr_add, true);
371 process_waddr_deps(state, n, waddr_mul, false);
372 if (qpu_writes_r4(inst))
373 add_write_dep(state, &state->last_r[4], n);
376 case QPU_SIG_SW_BREAKPOINT:
378 case QPU_SIG_THREAD_SWITCH:
379 case QPU_SIG_LAST_THREAD_SWITCH:
380 case QPU_SIG_SMALL_IMM:
381 case QPU_SIG_LOAD_IMM:
384 case QPU_SIG_LOAD_TMU0:
385 case QPU_SIG_LOAD_TMU1:
386 /* TMU loads are coming from a FIFO, so ordering is important.
388 add_write_dep(state, &state->last_tmu_write, n);
391 case QPU_SIG_COLOR_LOAD:
392 add_read_dep(state, state->last_tlb, n);
395 case QPU_SIG_PROG_END:
396 case QPU_SIG_WAIT_FOR_SCOREBOARD:
397 case QPU_SIG_SCOREBOARD_UNLOCK:
398 case QPU_SIG_COVERAGE_LOAD:
399 case QPU_SIG_COLOR_LOAD_END:
400 case QPU_SIG_ALPHA_MASK_LOAD:
402 fprintf(stderr, "Unhandled signal bits %d\n", sig);
406 process_cond_deps(state, n, QPU_GET_FIELD(inst, QPU_COND_ADD));
407 process_cond_deps(state, n, QPU_GET_FIELD(inst, QPU_COND_ADD));
409 add_write_dep(state, &state->last_sf, n);
413 calculate_forward_deps(struct vc4_compile *c, struct list_head *schedule_list)
415 struct schedule_state state;
417 memset(&state, 0, sizeof(state));
420 list_for_each_entry(struct schedule_node, node, schedule_list, link)
421 calculate_deps(&state, node);
425 calculate_reverse_deps(struct vc4_compile *c, struct list_head *schedule_list)
427 struct list_head *node;
428 struct schedule_state state;
430 memset(&state, 0, sizeof(state));
433 for (node = schedule_list->prev; schedule_list != node; node = node->prev) {
434 calculate_deps(&state, (struct schedule_node *)node);
438 struct choose_scoreboard {
440 int last_sfu_write_tick;
441 uint32_t last_waddr_a, last_waddr_b;
445 reads_too_soon_after_write(struct choose_scoreboard *scoreboard, uint64_t inst)
447 uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
448 uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
449 uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
450 uint32_t src_muxes[] = {
451 QPU_GET_FIELD(inst, QPU_ADD_A),
452 QPU_GET_FIELD(inst, QPU_ADD_B),
453 QPU_GET_FIELD(inst, QPU_MUL_A),
454 QPU_GET_FIELD(inst, QPU_MUL_B),
456 for (int i = 0; i < ARRAY_SIZE(src_muxes); i++) {
457 if ((src_muxes[i] == QPU_MUX_A &&
459 scoreboard->last_waddr_a == raddr_a) ||
460 (src_muxes[i] == QPU_MUX_B &&
461 sig != QPU_SIG_SMALL_IMM &&
463 scoreboard->last_waddr_b == raddr_b)) {
467 if (src_muxes[i] == QPU_MUX_R4) {
468 if (scoreboard->tick -
469 scoreboard->last_sfu_write_tick <= 2) {
479 pixel_scoreboard_too_soon(struct choose_scoreboard *scoreboard, uint64_t inst)
481 return (scoreboard->tick < 2 && qpu_inst_is_tlb(inst));
485 get_instruction_priority(uint64_t inst)
487 uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
488 uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
489 uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
490 uint32_t baseline_score;
491 uint32_t next_score = 0;
493 /* Schedule TLB operations as late as possible, to get more
494 * parallelism between shaders.
496 if (qpu_inst_is_tlb(inst))
500 /* Schedule texture read results collection late to hide latency. */
501 if (sig == QPU_SIG_LOAD_TMU0 || sig == QPU_SIG_LOAD_TMU1)
505 /* Default score for things that aren't otherwise special. */
506 baseline_score = next_score;
509 /* Schedule texture read setup early to hide their latency better. */
510 if (is_tmu_write(waddr_add) || is_tmu_write(waddr_mul))
514 return baseline_score;
517 static struct schedule_node *
518 choose_instruction_to_schedule(struct choose_scoreboard *scoreboard,
519 struct list_head *schedule_list,
520 struct schedule_node *prev_inst)
522 struct schedule_node *chosen = NULL;
525 list_for_each_entry(struct schedule_node, n, schedule_list, link) {
526 uint64_t inst = n->inst->inst;
528 /* "An instruction must not read from a location in physical
529 * regfile A or B that was written to by the previous
532 if (reads_too_soon_after_write(scoreboard, inst))
535 /* "A scoreboard wait must not occur in the first two
536 * instructions of a fragment shader. This is either the
537 * explicit Wait for Scoreboard signal or an implicit wait
538 * with the first tile-buffer read or write instruction."
540 if (pixel_scoreboard_too_soon(scoreboard, inst))
543 /* If we're trying to pair with another instruction, check
544 * that they're compatible.
547 if (prev_inst->uniform != -1 && n->uniform != -1)
550 inst = qpu_merge_inst(prev_inst->inst->inst, inst);
555 int prio = get_instruction_priority(inst);
557 /* Found a valid instruction. If nothing better comes along,
566 if (prio > chosen_prio) {
569 } else if (prio < chosen_prio) {
573 if (n->delay > chosen->delay) {
576 } else if (n->delay < chosen->delay) {
585 update_scoreboard_for_chosen(struct choose_scoreboard *scoreboard,
588 uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
589 uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
591 if (!(inst & QPU_WS)) {
592 scoreboard->last_waddr_a = waddr_add;
593 scoreboard->last_waddr_b = waddr_mul;
595 scoreboard->last_waddr_b = waddr_add;
596 scoreboard->last_waddr_a = waddr_mul;
599 if ((waddr_add >= QPU_W_SFU_RECIP && waddr_add <= QPU_W_SFU_LOG) ||
600 (waddr_mul >= QPU_W_SFU_RECIP && waddr_mul <= QPU_W_SFU_LOG)) {
601 scoreboard->last_sfu_write_tick = scoreboard->tick;
606 dump_state(struct list_head *schedule_list)
608 list_for_each_entry(struct schedule_node, n, schedule_list, link) {
609 fprintf(stderr, " t=%4d: ", n->unblocked_time);
610 vc4_qpu_disasm(&n->inst->inst, 1);
611 fprintf(stderr, "\n");
613 for (int i = 0; i < n->child_count; i++) {
614 struct schedule_node *child = n->children[i].node;
618 fprintf(stderr, " - ");
619 vc4_qpu_disasm(&child->inst->inst, 1);
620 fprintf(stderr, " (%d parents, %c)\n",
622 n->children[i].write_after_read ? 'w' : 'r');
627 /** Recursive computation of the delay member of a node. */
629 compute_delay(struct schedule_node *n)
631 if (!n->child_count) {
634 for (int i = 0; i < n->child_count; i++) {
635 if (!n->children[i].node->delay)
636 compute_delay(n->children[i].node);
637 n->delay = MAX2(n->delay,
638 n->children[i].node->delay + n->latency);
644 mark_instruction_scheduled(struct list_head *schedule_list,
646 struct schedule_node *node,
652 for (int i = node->child_count - 1; i >= 0; i--) {
653 struct schedule_node *child =
654 node->children[i].node;
659 if (war_only && !node->children[i].write_after_read)
662 /* If the requirement is only that the node not appear before
663 * the last read of its destination, then it can be scheduled
664 * immediately after (or paired with!) the thing reading the
667 int latency_from_previous = war_only ? 0 : node->latency;
668 child->unblocked_time = MAX2(child->unblocked_time,
669 time + latency_from_previous);
670 child->parent_count--;
671 if (child->parent_count == 0)
672 list_add(&child->link, schedule_list);
674 node->children[i].node = NULL;
679 schedule_instructions(struct vc4_compile *c, struct list_head *schedule_list)
681 struct choose_scoreboard scoreboard;
684 /* We reorder the uniforms as we schedule instructions, so save the
685 * old data off and replace it.
687 uint32_t *uniform_data = c->uniform_data;
688 enum quniform_contents *uniform_contents = c->uniform_contents;
689 c->uniform_contents = ralloc_array(c, enum quniform_contents,
691 c->uniform_data = ralloc_array(c, uint32_t, c->num_uniforms);
692 c->uniform_array_size = c->num_uniforms;
693 uint32_t next_uniform = 0;
695 memset(&scoreboard, 0, sizeof(scoreboard));
696 scoreboard.last_waddr_a = ~0;
697 scoreboard.last_waddr_b = ~0;
698 scoreboard.last_sfu_write_tick = -10;
701 fprintf(stderr, "initial deps:\n");
702 dump_state(schedule_list);
703 fprintf(stderr, "\n");
706 /* Remove non-DAG heads from the list. */
707 list_for_each_entry_safe(struct schedule_node, n, schedule_list, link) {
708 if (n->parent_count != 0)
712 while (!list_empty(schedule_list)) {
713 struct schedule_node *chosen =
714 choose_instruction_to_schedule(&scoreboard,
717 struct schedule_node *merge = NULL;
719 /* If there are no valid instructions to schedule, drop a NOP
722 uint64_t inst = chosen ? chosen->inst->inst : qpu_NOP();
725 fprintf(stderr, "t=%4d: current list:\n",
727 dump_state(schedule_list);
728 fprintf(stderr, "t=%4d: chose: ", time);
729 vc4_qpu_disasm(&inst, 1);
730 fprintf(stderr, "\n");
733 /* Schedule this instruction onto the QPU list. Also try to
734 * find an instruction to pair with it.
737 time = MAX2(chosen->unblocked_time, time);
738 list_del(&chosen->link);
739 mark_instruction_scheduled(schedule_list, time,
741 if (chosen->uniform != -1) {
742 c->uniform_data[next_uniform] =
743 uniform_data[chosen->uniform];
744 c->uniform_contents[next_uniform] =
745 uniform_contents[chosen->uniform];
749 merge = choose_instruction_to_schedule(&scoreboard,
753 time = MAX2(merge->unblocked_time, time);
754 list_del(&merge->link);
755 inst = qpu_merge_inst(inst, merge->inst->inst);
757 if (merge->uniform != -1) {
758 c->uniform_data[next_uniform] =
759 uniform_data[merge->uniform];
760 c->uniform_contents[next_uniform] =
761 uniform_contents[merge->uniform];
766 fprintf(stderr, "t=%4d: merging: ",
768 vc4_qpu_disasm(&merge->inst->inst, 1);
769 fprintf(stderr, "\n");
770 fprintf(stderr, " resulting in: ");
771 vc4_qpu_disasm(&inst, 1);
772 fprintf(stderr, "\n");
778 fprintf(stderr, "\n");
781 qpu_serialize_one_inst(c, inst);
783 update_scoreboard_for_chosen(&scoreboard, inst);
785 /* Now that we've scheduled a new instruction, some of its
786 * children can be promoted to the list of instructions ready to
787 * be scheduled. Update the children's unblocked time for this
788 * DAG edge as we do so.
790 mark_instruction_scheduled(schedule_list, time, chosen, false);
791 mark_instruction_scheduled(schedule_list, time, merge, false);
797 assert(next_uniform == c->num_uniforms);
802 static uint32_t waddr_latency(uint32_t waddr)
807 /* Some huge number, really. */
808 if (waddr >= QPU_W_TMU0_S && waddr <= QPU_W_TMU1_B)
812 case QPU_W_SFU_RECIP:
813 case QPU_W_SFU_RECIPSQRT:
823 instruction_latency(uint64_t inst)
825 return MAX2(waddr_latency(QPU_GET_FIELD(inst, QPU_WADDR_ADD)),
826 waddr_latency(QPU_GET_FIELD(inst, QPU_WADDR_MUL)));
830 qpu_schedule_instructions(struct vc4_compile *c)
832 void *mem_ctx = ralloc_context(NULL);
833 struct list_head schedule_list;
835 list_inithead(&schedule_list);
838 fprintf(stderr, "Pre-schedule instructions\n");
839 list_for_each_entry(struct queued_qpu_inst, q,
840 &c->qpu_inst_list, link) {
841 vc4_qpu_disasm(&q->inst, 1);
842 fprintf(stderr, "\n");
844 fprintf(stderr, "\n");
847 /* Wrap each instruction in a scheduler structure. */
848 uint32_t next_uniform = 0;
849 while (!list_empty(&c->qpu_inst_list)) {
850 struct queued_qpu_inst *inst =
851 (struct queued_qpu_inst *)c->qpu_inst_list.next;
852 struct schedule_node *n = rzalloc(mem_ctx, struct schedule_node);
855 n->latency = instruction_latency(inst->inst);
857 if (reads_uniform(inst->inst)) {
858 n->uniform = next_uniform++;
862 list_del(&inst->link);
863 list_addtail(&n->link, &schedule_list);
865 assert(next_uniform == c->num_uniforms);
867 calculate_forward_deps(c, &schedule_list);
868 calculate_reverse_deps(c, &schedule_list);
870 list_for_each_entry(struct schedule_node, n, &schedule_list, link) {
874 uint32_t cycles = schedule_instructions(c, &schedule_list);
877 fprintf(stderr, "Post-schedule instructions\n");
878 vc4_qpu_disasm(c->qpu_insts, c->qpu_inst_count);
879 fprintf(stderr, "\n");
882 ralloc_free(mem_ctx);