2 * Copyright © 2014 Broadcom
3 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "os/os_misc.h"
26 #include "pipe/p_defines.h"
27 #include "pipe/p_screen.h"
28 #include "pipe/p_state.h"
30 #include "util/u_debug.h"
31 #include "util/u_memory.h"
32 #include "util/u_format.h"
33 #include "util/ralloc.h"
35 #include "vc4_screen.h"
36 #include "vc4_context.h"
37 #include "vc4_resource.h"
39 static const struct debug_named_value debug_options[] = {
41 "Dump command list during creation" },
42 { "qpu", VC4_DEBUG_QPU,
43 "Dump generated QPU instructions" },
44 { "qir", VC4_DEBUG_QIR,
45 "Dump QPU IR during program compile" },
46 { "nir", VC4_DEBUG_NIR,
47 "Dump NIR during program compile" },
48 { "tgsi", VC4_DEBUG_TGSI,
49 "Dump TGSI during program compile" },
50 { "shaderdb", VC4_DEBUG_SHADERDB,
51 "Dump program compile information for shader-db analysis" },
52 { "perf", VC4_DEBUG_PERF,
53 "Print during performance-related events" },
54 { "norast", VC4_DEBUG_NORAST,
55 "Skip actual hardware execution of commands" },
56 { "always_flush", VC4_DEBUG_ALWAYS_FLUSH,
57 "Flush after each draw call" },
58 { "always_sync", VC4_DEBUG_ALWAYS_SYNC,
59 "Wait for finish after each flush" },
61 { "dump", VC4_DEBUG_DUMP,
62 "Write a GPU command stream trace file" },
67 DEBUG_GET_ONCE_FLAGS_OPTION(vc4_debug, "VC4_DEBUG", debug_options, 0)
71 vc4_screen_get_name(struct pipe_screen *pscreen)
77 vc4_screen_get_vendor(struct pipe_screen *pscreen)
83 vc4_screen_destroy(struct pipe_screen *pscreen)
85 vc4_bufmgr_destroy(pscreen);
90 vc4_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
93 /* Supported features (boolean caps). */
94 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
95 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
96 case PIPE_CAP_NPOT_TEXTURES:
97 case PIPE_CAP_USER_CONSTANT_BUFFERS:
98 case PIPE_CAP_TEXTURE_SHADOW_MAP:
99 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
100 case PIPE_CAP_TWO_SIDED_STENCIL:
101 case PIPE_CAP_USER_INDEX_BUFFERS:
102 case PIPE_CAP_TEXTURE_MULTISAMPLE:
103 case PIPE_CAP_TEXTURE_SWIZZLE:
106 /* lying for GL 2.0 */
107 case PIPE_CAP_OCCLUSION_QUERY:
108 case PIPE_CAP_POINT_SPRITE:
111 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
114 case PIPE_CAP_GLSL_FEATURE_LEVEL:
117 case PIPE_CAP_MAX_VIEWPORTS:
120 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
121 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
124 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
127 /* Unsupported features. */
128 case PIPE_CAP_ANISOTROPIC_FILTER:
129 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
130 case PIPE_CAP_CUBE_MAP_ARRAY:
131 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
132 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
133 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
134 case PIPE_CAP_SEAMLESS_CUBE_MAP:
135 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
136 case PIPE_CAP_TGSI_INSTANCEID:
137 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
138 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
139 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
140 case PIPE_CAP_COMPUTE:
141 case PIPE_CAP_START_INSTANCE:
142 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
143 case PIPE_CAP_SHADER_STENCIL_EXPORT:
144 case PIPE_CAP_TGSI_TEXCOORD:
145 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
146 case PIPE_CAP_CONDITIONAL_RENDER:
147 case PIPE_CAP_PRIMITIVE_RESTART:
148 case PIPE_CAP_TEXTURE_BARRIER:
150 case PIPE_CAP_INDEP_BLEND_ENABLE:
151 case PIPE_CAP_INDEP_BLEND_FUNC:
152 case PIPE_CAP_DEPTH_CLIP_DISABLE:
153 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
154 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
155 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
156 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
157 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
158 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
159 case PIPE_CAP_USER_VERTEX_BUFFERS:
160 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
161 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
162 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
163 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
164 case PIPE_CAP_TEXTURE_GATHER_SM5:
165 case PIPE_CAP_FAKE_SW_MSAA:
166 case PIPE_CAP_TEXTURE_QUERY_LOD:
167 case PIPE_CAP_SAMPLE_SHADING:
168 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
169 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
170 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
171 case PIPE_CAP_MAX_TEXEL_OFFSET:
172 case PIPE_CAP_MAX_VERTEX_STREAMS:
173 case PIPE_CAP_DRAW_INDIRECT:
174 case PIPE_CAP_MULTI_DRAW_INDIRECT:
175 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
176 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
177 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
178 case PIPE_CAP_SAMPLER_VIEW_TARGET:
179 case PIPE_CAP_CLIP_HALFZ:
180 case PIPE_CAP_VERTEXID_NOBASE:
181 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
182 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
183 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
184 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
185 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
186 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
187 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
188 case PIPE_CAP_DEPTH_BOUNDS_TEST:
189 case PIPE_CAP_TGSI_TXQS:
190 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
191 case PIPE_CAP_SHAREABLE_SHADERS:
192 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
193 case PIPE_CAP_CLEAR_TEXTURE:
194 case PIPE_CAP_DRAW_PARAMETERS:
195 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
196 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
197 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
198 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
199 case PIPE_CAP_INVALIDATE_BUFFER:
203 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
204 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
205 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
206 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
209 /* Geometry shader output, unsupported. */
210 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
211 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
215 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
216 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
217 return VC4_MAX_MIP_LEVELS;
218 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
219 /* Note: Not supported in hardware, just faking it. */
221 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
224 /* Render targets. */
225 case PIPE_CAP_MAX_RENDER_TARGETS:
229 case PIPE_CAP_QUERY_TIME_ELAPSED:
230 case PIPE_CAP_QUERY_TIMESTAMP:
233 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
234 case PIPE_CAP_MIN_TEXEL_OFFSET:
237 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
240 case PIPE_CAP_ENDIANNESS:
241 return PIPE_ENDIAN_LITTLE;
243 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
246 case PIPE_CAP_VENDOR_ID:
248 case PIPE_CAP_DEVICE_ID:
250 case PIPE_CAP_ACCELERATED:
252 case PIPE_CAP_VIDEO_MEMORY: {
253 uint64_t system_memory;
255 if (!os_get_total_physical_memory(&system_memory))
258 return (int)(system_memory >> 20);
264 fprintf(stderr, "unknown param %d\n", param);
270 vc4_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
273 case PIPE_CAPF_MAX_LINE_WIDTH:
274 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
277 case PIPE_CAPF_MAX_POINT_WIDTH:
278 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
281 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
283 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
285 case PIPE_CAPF_GUARD_BAND_LEFT:
286 case PIPE_CAPF_GUARD_BAND_TOP:
287 case PIPE_CAPF_GUARD_BAND_RIGHT:
288 case PIPE_CAPF_GUARD_BAND_BOTTOM:
291 fprintf(stderr, "unknown paramf %d\n", param);
297 vc4_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
298 enum pipe_shader_cap param)
300 if (shader != PIPE_SHADER_VERTEX &&
301 shader != PIPE_SHADER_FRAGMENT) {
305 /* this is probably not totally correct.. but it's a start: */
307 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
308 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
309 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
310 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
312 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
314 case PIPE_SHADER_CAP_MAX_INPUTS:
315 if (shader == PIPE_SHADER_FRAGMENT)
319 case PIPE_SHADER_CAP_MAX_OUTPUTS:
320 return shader == PIPE_SHADER_FRAGMENT ? 1 : 8;
321 case PIPE_SHADER_CAP_MAX_TEMPS:
322 return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
323 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
324 return 16 * 1024 * sizeof(float);
325 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
327 case PIPE_SHADER_CAP_MAX_PREDS:
328 return 0; /* nothing uses this */
329 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
331 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
332 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
333 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
335 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
337 case PIPE_SHADER_CAP_SUBROUTINES:
339 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
341 case PIPE_SHADER_CAP_INTEGERS:
343 case PIPE_SHADER_CAP_DOUBLES:
344 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
345 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
346 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
347 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
349 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
350 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
351 return VC4_MAX_TEXTURE_SAMPLERS;
352 case PIPE_SHADER_CAP_PREFERRED_IR:
353 return PIPE_SHADER_IR_TGSI;
354 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
356 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
359 fprintf(stderr, "unknown shader param %d\n", param);
366 vc4_screen_is_format_supported(struct pipe_screen *pscreen,
367 enum pipe_format format,
368 enum pipe_texture_target target,
369 unsigned sample_count,
374 if ((target >= PIPE_MAX_TEXTURE_TYPES) ||
375 !util_format_is_supported(format, usage)) {
379 if (usage & PIPE_BIND_VERTEX_BUFFER) {
381 case PIPE_FORMAT_R32G32B32A32_FLOAT:
382 case PIPE_FORMAT_R32G32B32_FLOAT:
383 case PIPE_FORMAT_R32G32_FLOAT:
384 case PIPE_FORMAT_R32_FLOAT:
385 case PIPE_FORMAT_R32G32B32A32_SNORM:
386 case PIPE_FORMAT_R32G32B32_SNORM:
387 case PIPE_FORMAT_R32G32_SNORM:
388 case PIPE_FORMAT_R32_SNORM:
389 case PIPE_FORMAT_R32G32B32A32_SSCALED:
390 case PIPE_FORMAT_R32G32B32_SSCALED:
391 case PIPE_FORMAT_R32G32_SSCALED:
392 case PIPE_FORMAT_R32_SSCALED:
393 case PIPE_FORMAT_R16G16B16A16_UNORM:
394 case PIPE_FORMAT_R16G16B16_UNORM:
395 case PIPE_FORMAT_R16G16_UNORM:
396 case PIPE_FORMAT_R16_UNORM:
397 case PIPE_FORMAT_R16G16B16A16_SNORM:
398 case PIPE_FORMAT_R16G16B16_SNORM:
399 case PIPE_FORMAT_R16G16_SNORM:
400 case PIPE_FORMAT_R16_SNORM:
401 case PIPE_FORMAT_R16G16B16A16_USCALED:
402 case PIPE_FORMAT_R16G16B16_USCALED:
403 case PIPE_FORMAT_R16G16_USCALED:
404 case PIPE_FORMAT_R16_USCALED:
405 case PIPE_FORMAT_R16G16B16A16_SSCALED:
406 case PIPE_FORMAT_R16G16B16_SSCALED:
407 case PIPE_FORMAT_R16G16_SSCALED:
408 case PIPE_FORMAT_R16_SSCALED:
409 case PIPE_FORMAT_R8G8B8A8_UNORM:
410 case PIPE_FORMAT_R8G8B8_UNORM:
411 case PIPE_FORMAT_R8G8_UNORM:
412 case PIPE_FORMAT_R8_UNORM:
413 case PIPE_FORMAT_R8G8B8A8_SNORM:
414 case PIPE_FORMAT_R8G8B8_SNORM:
415 case PIPE_FORMAT_R8G8_SNORM:
416 case PIPE_FORMAT_R8_SNORM:
417 case PIPE_FORMAT_R8G8B8A8_USCALED:
418 case PIPE_FORMAT_R8G8B8_USCALED:
419 case PIPE_FORMAT_R8G8_USCALED:
420 case PIPE_FORMAT_R8_USCALED:
421 case PIPE_FORMAT_R8G8B8A8_SSCALED:
422 case PIPE_FORMAT_R8G8B8_SSCALED:
423 case PIPE_FORMAT_R8G8_SSCALED:
424 case PIPE_FORMAT_R8_SSCALED:
425 retval |= PIPE_BIND_VERTEX_BUFFER;
432 if ((usage & PIPE_BIND_RENDER_TARGET) &&
433 (sample_count == 0 || sample_count == VC4_MAX_SAMPLES) &&
434 vc4_rt_format_supported(format)) {
435 retval |= PIPE_BIND_RENDER_TARGET;
438 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
439 (sample_count == 0 || sample_count == VC4_MAX_SAMPLES) &&
440 (vc4_tex_format_supported(format))) {
441 retval |= PIPE_BIND_SAMPLER_VIEW;
444 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
445 (format == PIPE_FORMAT_S8_UINT_Z24_UNORM ||
446 format == PIPE_FORMAT_X8Z24_UNORM)) {
447 retval |= PIPE_BIND_DEPTH_STENCIL;
450 if ((usage & PIPE_BIND_INDEX_BUFFER) &&
451 (format == PIPE_FORMAT_I8_UINT ||
452 format == PIPE_FORMAT_I16_UINT)) {
453 retval |= PIPE_BIND_INDEX_BUFFER;
456 if (usage & PIPE_BIND_TRANSFER_READ)
457 retval |= PIPE_BIND_TRANSFER_READ;
458 if (usage & PIPE_BIND_TRANSFER_WRITE)
459 retval |= PIPE_BIND_TRANSFER_WRITE;
462 if (retval != usage) {
464 "not supported: format=%s, target=%d, sample_count=%d, "
465 "usage=0x%x, retval=0x%x\n", util_format_name(format),
466 target, sample_count, usage, retval);
470 return retval == usage;
474 vc4_screen_create(int fd)
476 struct vc4_screen *screen = rzalloc(NULL, struct vc4_screen);
477 struct pipe_screen *pscreen;
479 pscreen = &screen->base;
481 pscreen->destroy = vc4_screen_destroy;
482 pscreen->get_param = vc4_screen_get_param;
483 pscreen->get_paramf = vc4_screen_get_paramf;
484 pscreen->get_shader_param = vc4_screen_get_shader_param;
485 pscreen->context_create = vc4_context_create;
486 pscreen->is_format_supported = vc4_screen_is_format_supported;
489 list_inithead(&screen->bo_cache.time_list);
491 vc4_fence_init(screen);
493 vc4_debug = debug_get_option_vc4_debug();
494 if (vc4_debug & VC4_DEBUG_SHADERDB)
495 vc4_debug |= VC4_DEBUG_NORAST;
497 #if USE_VC4_SIMULATOR
498 vc4_simulator_init(screen);
501 vc4_resource_screen_init(pscreen);
503 pscreen->get_name = vc4_screen_get_name;
504 pscreen->get_vendor = vc4_screen_get_vendor;
505 pscreen->get_device_vendor = vc4_screen_get_vendor;
511 vc4_screen_bo_get_handle(struct pipe_screen *pscreen,
514 struct winsys_handle *whandle)
516 whandle->stride = stride;
518 /* If we're passing some reference to our BO out to some other part of
519 * the system, then we can't do any optimizations about only us being
520 * the ones seeing it (like BO caching or shadow update avoidance).
524 switch (whandle->type) {
525 case DRM_API_HANDLE_TYPE_SHARED:
526 return vc4_bo_flink(bo, &whandle->handle);
527 case DRM_API_HANDLE_TYPE_KMS:
528 whandle->handle = bo->handle;
530 case DRM_API_HANDLE_TYPE_FD:
531 whandle->handle = vc4_bo_get_dmabuf(bo);
532 return whandle->handle != -1;
539 vc4_screen_bo_from_handle(struct pipe_screen *pscreen,
540 struct winsys_handle *whandle)
542 struct vc4_screen *screen = vc4_screen(pscreen);
544 switch (whandle->type) {
545 case DRM_API_HANDLE_TYPE_SHARED:
546 return vc4_bo_open_name(screen, whandle->handle, whandle->stride);
547 case DRM_API_HANDLE_TYPE_FD:
548 return vc4_bo_open_dmabuf(screen, whandle->handle, whandle->stride);
551 "Attempt to import unsupported handle type %d\n",