src/gallium/drivers/vc4/vc4_state.c

   1 /*
   2  * Copyright © 2014 Broadcom
   3  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 #include "pipe/p_state.h"
  26 #include "util/u_inlines.h"
  27 #include "util/u_math.h"
  28 #include "util/u_memory.h"
  29 #include "util/u_helpers.h"
  30
  31 #include "vc4_context.h"
  32
  33 static void *
  34 vc4_generic_cso_state_create(const void *src, uint32_t size)
  35 {
  36         void *dst = calloc(1, size);
  37         if (!dst)
  38                 return NULL;
  39         memcpy(dst, src, size);
  40         return dst;
  41 }
  42
  43 static void
  44 vc4_generic_cso_state_delete(struct pipe_context *pctx, void *hwcso)
  45 {
  46         free(hwcso);
  47 }
  48
  49 static void
  50 vc4_set_blend_color(struct pipe_context *pctx,
  51                     const struct pipe_blend_color *blend_color)
  52 {
  53         struct vc4_context *vc4 = vc4_context(pctx);
  54         vc4->blend_color.f = *blend_color;
  55         for (int i = 0; i < 4; i++)
  56                 vc4->blend_color.ub[i] = float_to_ubyte(blend_color->color[i]);
  57         vc4->dirty |= VC4_DIRTY_BLEND_COLOR;
  58 }
  59
  60 static void
  61 vc4_set_stencil_ref(struct pipe_context *pctx,
  62                     const struct pipe_stencil_ref *stencil_ref)
  63 {
  64         struct vc4_context *vc4 = vc4_context(pctx);
  65         vc4->stencil_ref =* stencil_ref;
  66         vc4->dirty |= VC4_DIRTY_STENCIL_REF;
  67 }
  68
  69 static void
  70 vc4_set_clip_state(struct pipe_context *pctx,
  71                    const struct pipe_clip_state *clip)
  72 {
  73         struct vc4_context *vc4 = vc4_context(pctx);
  74         vc4->clip = *clip;
  75         vc4->dirty |= VC4_DIRTY_CLIP;
  76 }
  77
  78 static void
  79 vc4_set_sample_mask(struct pipe_context *pctx, unsigned sample_mask)
  80 {
  81         struct vc4_context *vc4 = vc4_context(pctx);
  82         vc4->sample_mask = (uint16_t)sample_mask;
  83         vc4->dirty |= VC4_DIRTY_SAMPLE_MASK;
  84 }
  85
  86 static uint16_t
  87 float_to_187_half(float f)
  88 {
  89         return fui(f) >> 16;
  90 }
  91
  92 static void *
  93 vc4_create_rasterizer_state(struct pipe_context *pctx,
  94                             const struct pipe_rasterizer_state *cso)
  95 {
  96         struct vc4_rasterizer_state *so;
  97
  98         so = CALLOC_STRUCT(vc4_rasterizer_state);
  99         if (!so)
 100                 return NULL;
 101
 102         so->base = *cso;
 103
 104         if (!(cso->cull_face & PIPE_FACE_FRONT))
 105                 so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_PRIM_FRONT;
 106         if (!(cso->cull_face & PIPE_FACE_BACK))
 107                 so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_PRIM_BACK;
 108
 109         /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
 110          * BCM21553).
 111          */
 112         so->point_size = MAX2(cso->point_size, .125f);
 113
 114         if (cso->front_ccw)
 115                 so->config_bits[0] |= VC4_CONFIG_BITS_CW_PRIMITIVES;
 116
 117         if (cso->offset_tri) {
 118                 so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_DEPTH_OFFSET;
 119
 120                 so->offset_units = float_to_187_half(cso->offset_units);
 121                 so->offset_factor = float_to_187_half(cso->offset_scale);
 122         }
 123
 124         return so;
 125 }
 126
 127 /* Blend state is baked into shaders. */
 128 static void *
 129 vc4_create_blend_state(struct pipe_context *pctx,
 130                        const struct pipe_blend_state *cso)
 131 {
 132         return vc4_generic_cso_state_create(cso, sizeof(*cso));
 133 }
 134
 135 /**
 136  * The TLB_STENCIL_SETUP data has a little bitfield for common writemask
 137  * values, so you don't have to do a separate writemask setup.
 138  */
 139 static uint8_t
 140 tlb_stencil_setup_writemask(uint8_t mask)
 141 {
 142         switch (mask) {
 143         case 0x1: return 0;
 144         case 0x3: return 1;
 145         case 0xf: return 2;
 146         case 0xff: return 3;
 147         default: return 0xff;
 148         }
 149 }
 150
 151 static uint32_t
 152 tlb_stencil_setup_bits(const struct pipe_stencil_state *state,
 153                        uint8_t writemask_bits)
 154 {
 155         static const uint8_t op_map[] = {
 156                 [PIPE_STENCIL_OP_ZERO] = 0,
 157                 [PIPE_STENCIL_OP_KEEP] = 1,
 158                 [PIPE_STENCIL_OP_REPLACE] = 2,
 159                 [PIPE_STENCIL_OP_INCR] = 3,
 160                 [PIPE_STENCIL_OP_DECR] = 4,
 161                 [PIPE_STENCIL_OP_INVERT] = 5,
 162                 [PIPE_STENCIL_OP_INCR_WRAP] = 6,
 163                 [PIPE_STENCIL_OP_DECR_WRAP] = 7,
 164         };
 165         uint32_t bits = 0;
 166
 167         if (writemask_bits != 0xff)
 168                 bits |= writemask_bits << 28;
 169         bits |= op_map[state->zfail_op] << 25;
 170         bits |= op_map[state->zpass_op] << 22;
 171         bits |= op_map[state->fail_op] << 19;
 172         bits |= state->func << 16;
 173         /* Ref is filled in at uniform upload time */
 174         bits |= state->valuemask << 0;
 175
 176         return bits;
 177 }
 178
 179 static void *
 180 vc4_create_depth_stencil_alpha_state(struct pipe_context *pctx,
 181                                      const struct pipe_depth_stencil_alpha_state *cso)
 182 {
 183         struct vc4_depth_stencil_alpha_state *so;
 184
 185         so = CALLOC_STRUCT(vc4_depth_stencil_alpha_state);
 186         if (!so)
 187                 return NULL;
 188
 189         so->base = *cso;
 190
 191         /* We always keep the early Z state correct, since a later state using
 192          * early Z may want it.
 193          */
 194         so->config_bits[2] |= VC4_CONFIG_BITS_EARLY_Z_UPDATE;
 195
 196         if (cso->depth.enabled) {
 197                 if (cso->depth.writemask) {
 198                         so->config_bits[1] |= VC4_CONFIG_BITS_Z_UPDATE;
 199                 }
 200                 so->config_bits[1] |= (cso->depth.func <<
 201                                        VC4_CONFIG_BITS_DEPTH_FUNC_SHIFT);
 202
 203                 /* We only handle early Z in the < direction because otherwise
 204                  * we'd have to runtime guess which direction to set in the
 205                  * render config.
 206                  */
 207                 if ((cso->depth.func == PIPE_FUNC_LESS ||
 208                      cso->depth.func == PIPE_FUNC_LEQUAL) &&
 209                     (!cso->stencil[0].enabled ||
 210                      (cso->stencil[0].zfail_op == PIPE_STENCIL_OP_KEEP &&
 211                       (!cso->stencil[1].enabled ||
 212                        cso->stencil[1].zfail_op == PIPE_STENCIL_OP_KEEP)))) {
 213                         so->config_bits[2] |= VC4_CONFIG_BITS_EARLY_Z;
 214                 }
 215         } else {
 216                 so->config_bits[1] |= (PIPE_FUNC_ALWAYS <<
 217                                        VC4_CONFIG_BITS_DEPTH_FUNC_SHIFT);
 218         }
 219
 220         if (cso->stencil[0].enabled) {
 221                 const struct pipe_stencil_state *front = &cso->stencil[0];
 222                 const struct pipe_stencil_state *back = &cso->stencil[1];
 223
 224                 uint8_t front_writemask_bits =
 225                         tlb_stencil_setup_writemask(front->writemask);
 226                 uint8_t back_writemask = front->writemask;
 227                 uint8_t back_writemask_bits = front_writemask_bits;
 228
 229                 so->stencil_uniforms[0] =
 230                         tlb_stencil_setup_bits(front, front_writemask_bits);
 231                 if (back->enabled) {
 232                         back_writemask = back->writemask;
 233                         back_writemask_bits =
 234                                 tlb_stencil_setup_writemask(back->writemask);
 235
 236                         so->stencil_uniforms[0] |= (1 << 30);
 237                         so->stencil_uniforms[1] =
 238                                 tlb_stencil_setup_bits(back, back_writemask_bits);
 239                         so->stencil_uniforms[1] |= (2 << 30);
 240                 } else {
 241                         so->stencil_uniforms[0] |= (3 << 30);
 242                 }
 243
 244                 if (front_writemask_bits == 0xff ||
 245                     back_writemask_bits == 0xff) {
 246                         so->stencil_uniforms[2] = (front->writemask |
 247                                                    (back_writemask << 8));
 248                 }
 249         }
 250
 251         return so;
 252 }
 253
 254 static void
 255 vc4_set_polygon_stipple(struct pipe_context *pctx,
 256                         const struct pipe_poly_stipple *stipple)
 257 {
 258         struct vc4_context *vc4 = vc4_context(pctx);
 259         vc4->stipple = *stipple;
 260         vc4->dirty |= VC4_DIRTY_STIPPLE;
 261 }
 262
 263 static void
 264 vc4_set_scissor_states(struct pipe_context *pctx,
 265                        unsigned start_slot,
 266                        unsigned num_scissors,
 267                        const struct pipe_scissor_state *scissor)
 268 {
 269         struct vc4_context *vc4 = vc4_context(pctx);
 270
 271         vc4->scissor = *scissor;
 272         vc4->dirty |= VC4_DIRTY_SCISSOR;
 273 }
 274
 275 static void
 276 vc4_set_viewport_states(struct pipe_context *pctx,
 277                         unsigned start_slot,
 278                         unsigned num_viewports,
 279                         const struct pipe_viewport_state *viewport)
 280 {
 281         struct vc4_context *vc4 = vc4_context(pctx);
 282         vc4->viewport = *viewport;
 283         vc4->dirty |= VC4_DIRTY_VIEWPORT;
 284 }
 285
 286 static void
 287 vc4_set_vertex_buffers(struct pipe_context *pctx,
 288                        unsigned start_slot, unsigned count,
 289                        const struct pipe_vertex_buffer *vb)
 290 {
 291         struct vc4_context *vc4 = vc4_context(pctx);
 292         struct vc4_vertexbuf_stateobj *so = &vc4->vertexbuf;
 293
 294         util_set_vertex_buffers_mask(so->vb, &so->enabled_mask, vb,
 295                                      start_slot, count);
 296         so->count = util_last_bit(so->enabled_mask);
 297
 298         vc4->dirty |= VC4_DIRTY_VTXBUF;
 299 }
 300
 301 static void
 302 vc4_set_index_buffer(struct pipe_context *pctx,
 303                      const struct pipe_index_buffer *ib)
 304 {
 305         struct vc4_context *vc4 = vc4_context(pctx);
 306
 307         if (ib) {
 308                 assert(!ib->user_buffer);
 309                 pipe_resource_reference(&vc4->indexbuf.buffer, ib->buffer);
 310                 vc4->indexbuf.index_size = ib->index_size;
 311                 vc4->indexbuf.offset = ib->offset;
 312         } else {
 313                 pipe_resource_reference(&vc4->indexbuf.buffer, NULL);
 314         }
 315
 316         vc4->dirty |= VC4_DIRTY_INDEXBUF;
 317 }
 318
 319 static void
 320 vc4_blend_state_bind(struct pipe_context *pctx, void *hwcso)
 321 {
 322         struct vc4_context *vc4 = vc4_context(pctx);
 323         vc4->blend = hwcso;
 324         vc4->dirty |= VC4_DIRTY_BLEND;
 325 }
 326
 327 static void
 328 vc4_rasterizer_state_bind(struct pipe_context *pctx, void *hwcso)
 329 {
 330         struct vc4_context *vc4 = vc4_context(pctx);
 331         struct vc4_rasterizer_state *rast = hwcso;
 332
 333         if (vc4->rasterizer && rast &&
 334             vc4->rasterizer->base.flatshade != rast->base.flatshade) {
 335                 vc4->dirty |= VC4_DIRTY_FLAT_SHADE_FLAGS;
 336         }
 337
 338         vc4->rasterizer = hwcso;
 339         vc4->dirty |= VC4_DIRTY_RASTERIZER;
 340 }
 341
 342 static void
 343 vc4_zsa_state_bind(struct pipe_context *pctx, void *hwcso)
 344 {
 345         struct vc4_context *vc4 = vc4_context(pctx);
 346         vc4->zsa = hwcso;
 347         vc4->dirty |= VC4_DIRTY_ZSA;
 348 }
 349
 350 static void *
 351 vc4_vertex_state_create(struct pipe_context *pctx, unsigned num_elements,
 352                         const struct pipe_vertex_element *elements)
 353 {
 354         struct vc4_vertex_stateobj *so = CALLOC_STRUCT(vc4_vertex_stateobj);
 355
 356         if (!so)
 357                 return NULL;
 358
 359         memcpy(so->pipe, elements, sizeof(*elements) * num_elements);
 360         so->num_elements = num_elements;
 361
 362         return so;
 363 }
 364
 365 static void
 366 vc4_vertex_state_bind(struct pipe_context *pctx, void *hwcso)
 367 {
 368         struct vc4_context *vc4 = vc4_context(pctx);
 369         vc4->vtx = hwcso;
 370         vc4->dirty |= VC4_DIRTY_VTXSTATE;
 371 }
 372
 373 static void
 374 vc4_set_constant_buffer(struct pipe_context *pctx, uint shader, uint index,
 375                         struct pipe_constant_buffer *cb)
 376 {
 377         struct vc4_context *vc4 = vc4_context(pctx);
 378         struct vc4_constbuf_stateobj *so = &vc4->constbuf[shader];
 379
 380         assert(index == 0);
 381
 382         /* Note that the state tracker can unbind constant buffers by
 383          * passing NULL here.
 384          */
 385         if (unlikely(!cb)) {
 386                 so->enabled_mask &= ~(1 << index);
 387                 so->dirty_mask &= ~(1 << index);
 388                 return;
 389         }
 390
 391         assert(!cb->buffer);
 392         so->cb[index].buffer_offset = cb->buffer_offset;
 393         so->cb[index].buffer_size   = cb->buffer_size;
 394         so->cb[index].user_buffer   = cb->user_buffer;
 395
 396         so->enabled_mask |= 1 << index;
 397         so->dirty_mask |= 1 << index;
 398         vc4->dirty |= VC4_DIRTY_CONSTBUF;
 399 }
 400
 401 static void
 402 vc4_set_framebuffer_state(struct pipe_context *pctx,
 403                           const struct pipe_framebuffer_state *framebuffer)
 404 {
 405         struct vc4_context *vc4 = vc4_context(pctx);
 406         struct pipe_framebuffer_state *cso = &vc4->framebuffer;
 407         unsigned i;
 408
 409         vc4_flush(pctx);
 410
 411         for (i = 0; i < framebuffer->nr_cbufs; i++)
 412                 pipe_surface_reference(&cso->cbufs[i], framebuffer->cbufs[i]);
 413         for (; i < vc4->framebuffer.nr_cbufs; i++)
 414                 pipe_surface_reference(&cso->cbufs[i], NULL);
 415
 416         cso->nr_cbufs = framebuffer->nr_cbufs;
 417
 418         pipe_surface_reference(&cso->zsbuf, framebuffer->zsbuf);
 419
 420         cso->width = framebuffer->width;
 421         cso->height = framebuffer->height;
 422
 423         /* Nonzero texture mipmap levels are laid out as if they were in
 424          * power-of-two-sized spaces.  The renderbuffer config infers its
 425          * stride from the width parameter, so we need to configure our
 426          * framebuffer.  Note that if the z/color buffers were mismatched
 427          * sizes, we wouldn't be able to do this.
 428          */
 429         if (cso->cbufs[0] && cso->cbufs[0]->u.tex.level) {
 430                 struct vc4_resource *rsc =
 431                         vc4_resource(cso->cbufs[0]->texture);
 432                 cso->width =
 433                         (rsc->slices[cso->cbufs[0]->u.tex.level].stride /
 434                          rsc->cpp);
 435         } else if (cso->zsbuf && cso->zsbuf->u.tex.level){
 436                 struct vc4_resource *rsc =
 437                         vc4_resource(cso->zsbuf->texture);
 438                 cso->width =
 439                         (rsc->slices[cso->zsbuf->u.tex.level].stride /
 440                          rsc->cpp);
 441         }
 442
 443         vc4->dirty |= VC4_DIRTY_FRAMEBUFFER;
 444 }
 445
 446 static struct vc4_texture_stateobj *
 447 vc4_get_stage_tex(struct vc4_context *vc4, unsigned shader)
 448 {
 449         vc4->dirty |= VC4_DIRTY_TEXSTATE;
 450
 451         switch (shader) {
 452         case PIPE_SHADER_FRAGMENT:
 453                 vc4->dirty |= VC4_DIRTY_FRAGTEX;
 454                 return &vc4->fragtex;
 455                 break;
 456         case PIPE_SHADER_VERTEX:
 457                 vc4->dirty |= VC4_DIRTY_VERTTEX;
 458                 return &vc4->verttex;
 459                 break;
 460         default:
 461                 fprintf(stderr, "Unknown shader target %d\n", shader);
 462                 abort();
 463         }
 464 }
 465
 466 static uint32_t translate_wrap(uint32_t p_wrap, bool using_nearest)
 467 {
 468         switch (p_wrap) {
 469         case PIPE_TEX_WRAP_REPEAT:
 470                 return 0;
 471         case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
 472                 return 1;
 473         case PIPE_TEX_WRAP_MIRROR_REPEAT:
 474                 return 2;
 475         case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
 476                 return 3;
 477         case PIPE_TEX_WRAP_CLAMP:
 478                 return (using_nearest ? 1 : 3);
 479         default:
 480                 fprintf(stderr, "Unknown wrap mode %d\n", p_wrap);
 481                 assert(!"not reached");
 482                 return 0;
 483         }
 484 }
 485
 486 static void *
 487 vc4_create_sampler_state(struct pipe_context *pctx,
 488                          const struct pipe_sampler_state *cso)
 489 {
 490         static const uint8_t minfilter_map[6] = {
 491                 VC4_TEX_P1_MINFILT_NEAR_MIP_NEAR,
 492                 VC4_TEX_P1_MINFILT_LIN_MIP_NEAR,
 493                 VC4_TEX_P1_MINFILT_NEAR_MIP_LIN,
 494                 VC4_TEX_P1_MINFILT_LIN_MIP_LIN,
 495                 VC4_TEX_P1_MINFILT_NEAREST,
 496                 VC4_TEX_P1_MINFILT_LINEAR,
 497         };
 498         static const uint32_t magfilter_map[] = {
 499                 [PIPE_TEX_FILTER_NEAREST] = VC4_TEX_P1_MAGFILT_NEAREST,
 500                 [PIPE_TEX_FILTER_LINEAR] = VC4_TEX_P1_MAGFILT_LINEAR,
 501         };
 502         bool either_nearest =
 503                 (cso->mag_img_filter == PIPE_TEX_MIPFILTER_NEAREST ||
 504                  cso->min_img_filter == PIPE_TEX_MIPFILTER_NEAREST);
 505         struct vc4_sampler_state *so = CALLOC_STRUCT(vc4_sampler_state);
 506
 507         if (!so)
 508                 return NULL;
 509
 510         memcpy(so, cso, sizeof(*cso));
 511
 512         so->texture_p1 =
 513                 (VC4_SET_FIELD(magfilter_map[cso->mag_img_filter],
 514                                VC4_TEX_P1_MAGFILT) |
 515                  VC4_SET_FIELD(minfilter_map[cso->min_mip_filter * 2 +
 516                                              cso->min_img_filter],
 517                                VC4_TEX_P1_MINFILT) |
 518                  VC4_SET_FIELD(translate_wrap(cso->wrap_s, either_nearest),
 519                                VC4_TEX_P1_WRAP_S) |
 520                  VC4_SET_FIELD(translate_wrap(cso->wrap_t, either_nearest),
 521                                VC4_TEX_P1_WRAP_T));
 522
 523         return so;
 524 }
 525
 526 static void
 527 vc4_sampler_states_bind(struct pipe_context *pctx,
 528                         unsigned shader, unsigned start,
 529                         unsigned nr, void **hwcso)
 530 {
 531         struct vc4_context *vc4 = vc4_context(pctx);
 532         struct vc4_texture_stateobj *stage_tex = vc4_get_stage_tex(vc4, shader);
 533
 534         assert(start == 0);
 535         unsigned i;
 536         unsigned new_nr = 0;
 537
 538         for (i = 0; i < nr; i++) {
 539                 if (hwcso[i])
 540                         new_nr = i + 1;
 541                 stage_tex->samplers[i] = hwcso[i];
 542                 stage_tex->dirty_samplers |= (1 << i);
 543         }
 544
 545         for (; i < stage_tex->num_samplers; i++) {
 546                 stage_tex->samplers[i] = NULL;
 547                 stage_tex->dirty_samplers |= (1 << i);
 548         }
 549
 550         stage_tex->num_samplers = new_nr;
 551 }
 552
 553 static struct pipe_sampler_view *
 554 vc4_create_sampler_view(struct pipe_context *pctx, struct pipe_resource *prsc,
 555                         const struct pipe_sampler_view *cso)
 556 {
 557         struct vc4_sampler_view *so = malloc(sizeof(*so));
 558         struct vc4_resource *rsc = vc4_resource(prsc);
 559
 560         if (!so)
 561                 return NULL;
 562
 563         so->base = *cso;
 564
 565         pipe_reference(NULL, &prsc->reference);
 566
 567         /* There is no hardware level clamping, and the start address of a
 568          * texture may be misaligned, so in that case we have to copy to a
 569          * temporary.
 570          *
 571          * Also, Raspberry Pi doesn't support sampling from raster textures,
 572          * so we also have to copy to a temporary then.
 573          */
 574         if (cso->u.tex.first_level ||
 575             rsc->vc4_format == VC4_TEXTURE_TYPE_RGBA32R) {
 576                 struct vc4_resource *shadow_parent = vc4_resource(prsc);
 577                 struct pipe_resource tmpl = shadow_parent->base.b;
 578                 struct vc4_resource *clone;
 579
 580                 tmpl.bind = PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_RENDER_TARGET;
 581                 tmpl.width0 = u_minify(tmpl.width0, cso->u.tex.first_level);
 582                 tmpl.height0 = u_minify(tmpl.height0, cso->u.tex.first_level);
 583                 tmpl.last_level = cso->u.tex.last_level - cso->u.tex.first_level;
 584
 585                 prsc = vc4_resource_create(pctx->screen, &tmpl);
 586                 rsc = vc4_resource(prsc);
 587                 clone = vc4_resource(prsc);
 588                 clone->shadow_parent = &shadow_parent->base.b;
 589                 /* Flag it as needing update of the contents from the parent. */
 590                 clone->writes = shadow_parent->writes - 1;
 591
 592                 assert(clone->vc4_format != VC4_TEXTURE_TYPE_RGBA32R);
 593         }
 594         so->base.texture = prsc;
 595         so->base.reference.count = 1;
 596         so->base.context = pctx;
 597
 598         so->texture_p0 =
 599                 (VC4_SET_FIELD(rsc->slices[0].offset >> 12, VC4_TEX_P0_OFFSET) |
 600                  VC4_SET_FIELD(rsc->vc4_format & 15, VC4_TEX_P0_TYPE) |
 601                  VC4_SET_FIELD(cso->u.tex.last_level -
 602                                cso->u.tex.first_level, VC4_TEX_P0_MIPLVLS) |
 603                  VC4_SET_FIELD(cso->target == PIPE_TEXTURE_CUBE,
 604                                VC4_TEX_P0_CMMODE));
 605         so->texture_p1 =
 606                 (VC4_SET_FIELD(rsc->vc4_format >> 4, VC4_TEX_P1_TYPE4) |
 607                  VC4_SET_FIELD(prsc->height0 & 2047, VC4_TEX_P1_HEIGHT) |
 608                  VC4_SET_FIELD(prsc->width0 & 2047, VC4_TEX_P1_WIDTH));
 609
 610         return &so->base;
 611 }
 612
 613 static void
 614 vc4_sampler_view_destroy(struct pipe_context *pctx,
 615                          struct pipe_sampler_view *view)
 616 {
 617         pipe_resource_reference(&view->texture, NULL);
 618         free(view);
 619 }
 620
 621 static void
 622 vc4_set_sampler_views(struct pipe_context *pctx, unsigned shader,
 623                       unsigned start, unsigned nr,
 624                       struct pipe_sampler_view **views)
 625 {
 626         struct vc4_context *vc4 = vc4_context(pctx);
 627         struct vc4_texture_stateobj *stage_tex = vc4_get_stage_tex(vc4, shader);
 628         unsigned i;
 629         unsigned new_nr = 0;
 630
 631         assert(start == 0);
 632
 633         vc4->dirty |= VC4_DIRTY_TEXSTATE;
 634
 635         for (i = 0; i < nr; i++) {
 636                 if (views[i])
 637                         new_nr = i + 1;
 638                 pipe_sampler_view_reference(&stage_tex->textures[i], views[i]);
 639                 stage_tex->dirty_samplers |= (1 << i);
 640         }
 641
 642         for (; i < stage_tex->num_textures; i++) {
 643                 pipe_sampler_view_reference(&stage_tex->textures[i], NULL);
 644                 stage_tex->dirty_samplers |= (1 << i);
 645         }
 646
 647         stage_tex->num_textures = new_nr;
 648 }
 649
 650 void
 651 vc4_state_init(struct pipe_context *pctx)
 652 {
 653         pctx->set_blend_color = vc4_set_blend_color;
 654         pctx->set_stencil_ref = vc4_set_stencil_ref;
 655         pctx->set_clip_state = vc4_set_clip_state;
 656         pctx->set_sample_mask = vc4_set_sample_mask;
 657         pctx->set_constant_buffer = vc4_set_constant_buffer;
 658         pctx->set_framebuffer_state = vc4_set_framebuffer_state;
 659         pctx->set_polygon_stipple = vc4_set_polygon_stipple;
 660         pctx->set_scissor_states = vc4_set_scissor_states;
 661         pctx->set_viewport_states = vc4_set_viewport_states;
 662
 663         pctx->set_vertex_buffers = vc4_set_vertex_buffers;
 664         pctx->set_index_buffer = vc4_set_index_buffer;
 665
 666         pctx->create_blend_state = vc4_create_blend_state;
 667         pctx->bind_blend_state = vc4_blend_state_bind;
 668         pctx->delete_blend_state = vc4_generic_cso_state_delete;
 669
 670         pctx->create_rasterizer_state = vc4_create_rasterizer_state;
 671         pctx->bind_rasterizer_state = vc4_rasterizer_state_bind;
 672         pctx->delete_rasterizer_state = vc4_generic_cso_state_delete;
 673
 674         pctx->create_depth_stencil_alpha_state = vc4_create_depth_stencil_alpha_state;
 675         pctx->bind_depth_stencil_alpha_state = vc4_zsa_state_bind;
 676         pctx->delete_depth_stencil_alpha_state = vc4_generic_cso_state_delete;
 677
 678         pctx->create_vertex_elements_state = vc4_vertex_state_create;
 679         pctx->delete_vertex_elements_state = vc4_generic_cso_state_delete;
 680         pctx->bind_vertex_elements_state = vc4_vertex_state_bind;
 681
 682         pctx->create_sampler_state = vc4_create_sampler_state;
 683         pctx->delete_sampler_state = vc4_generic_cso_state_delete;
 684         pctx->bind_sampler_states = vc4_sampler_states_bind;
 685
 686         pctx->create_sampler_view = vc4_create_sampler_view;
 687         pctx->sampler_view_destroy = vc4_sampler_view_destroy;
 688         pctx->set_sampler_views = vc4_set_sampler_views;
 689 }