src/gallium/winsys/r600/drm/evergreen_hw_context.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #include <errno.h>
  27 #include <stdint.h>
  28 #include <string.h>
  29 #include <stdlib.h>
  30 #include <assert.h>
  31 #include "xf86drm.h"
  32 #include "r600.h"
  33 #include "evergreend.h"
  34 #include "radeon_drm.h"
  35 #include "bof.h"
  36 #include "pipe/p_compiler.h"
  37 #include "util/u_inlines.h"
  38 #include "util/u_memory.h"
  39 #include "r600_priv.h"
  40
  41 #define GROUP_FORCE_NEW_BLOCK   0
  42
  43 static const struct r600_reg evergreen_config_reg_list[] = {
  44         {R_008958_VGT_PRIMITIVE_TYPE, 0, 0, 0},
  45         {R_008A14_PA_CL_ENHANCE, 0, 0, 0},
  46         {R_008C00_SQ_CONFIG, REG_FLAG_ENABLE_ALWAYS, 0, 0},
  47         {R_008C04_SQ_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS, 0, 0},
  48         {R_008C08_SQ_GPR_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS, 0, 0},
  49         {R_008C0C_SQ_THREAD_RESOURCE_MGMT, REG_FLAG_ENABLE_ALWAYS, 0, 0},
  50         {R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS, 0, 0},
  51         {R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS, 0, 0},
  52         {R_008C18_SQ_THREAD_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS, 0, 0},
  53         {R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS, 0, 0},
  54         {R_008C20_SQ_STACK_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS, 0, 0},
  55         {R_008C24_SQ_STACK_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS, 0, 0},
  56         {R_008C28_SQ_STACK_RESOURCE_MGMT_3, REG_FLAG_ENABLE_ALWAYS, 0, 0},
  57         {R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, REG_FLAG_ENABLE_ALWAYS, 0, 0},
  58         {R_009100_SPI_CONFIG_CNTL, REG_FLAG_ENABLE_ALWAYS, 0, 0},
  59         {R_00913C_SPI_CONFIG_CNTL_1, REG_FLAG_ENABLE_ALWAYS, 0, 0},
  60 };
  61
  62
  63 static const struct r600_reg cayman_config_reg_list[] = {
  64         {R_008958_VGT_PRIMITIVE_TYPE, 0, 0, 0},
  65         {R_008A14_PA_CL_ENHANCE, 0, 0, 0},
  66         {R_008C00_SQ_CONFIG, REG_FLAG_ENABLE_ALWAYS, 0, 0},
  67         {R_008C04_SQ_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS, 0, 0},
  68         {R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS, 0, 0},
  69         {R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS, 0, 0},
  70         {R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, REG_FLAG_ENABLE_ALWAYS, 0, 0},
  71         {R_009100_SPI_CONFIG_CNTL, REG_FLAG_ENABLE_ALWAYS, 0, 0},
  72         {R_00913C_SPI_CONFIG_CNTL_1, REG_FLAG_ENABLE_ALWAYS, 0, 0},
  73 };
  74
  75 static const struct r600_reg evergreen_ctl_const_list[] = {
  76         {R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0, 0},
  77         {R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0, 0},
  78 };
  79
  80 static const struct r600_reg evergreen_context_reg_list[] = {
  81         {R_028000_DB_RENDER_CONTROL, 0, 0, 0},
  82         {R_028004_DB_COUNT_CONTROL, 0, 0, 0},
  83         {R_028008_DB_DEPTH_VIEW, 0, 0, 0},
  84         {R_02800C_DB_RENDER_OVERRIDE, 0, 0, 0},
  85         {R_028010_DB_RENDER_OVERRIDE2, 0, 0, 0},
  86         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
  87         {R_028014_DB_HTILE_DATA_BASE, REG_FLAG_NEED_BO, 0, 0},
  88         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
  89         {R_028028_DB_STENCIL_CLEAR, 0, 0, 0},
  90         {R_02802C_DB_DEPTH_CLEAR, 0, 0, 0},
  91         {R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0, 0},
  92         {R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0, 0},
  93         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
  94         {R_028040_DB_Z_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
  95         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
  96         {R_028044_DB_STENCIL_INFO, 0, 0, 0},
  97         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
  98         {R_028048_DB_Z_READ_BASE, REG_FLAG_NEED_BO, 0, 0},
  99         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 100         {R_02804C_DB_STENCIL_READ_BASE, REG_FLAG_NEED_BO, 0, 0},
 101         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 102         {R_028050_DB_Z_WRITE_BASE, REG_FLAG_NEED_BO, 0, 0},
 103         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 104         {R_028054_DB_STENCIL_WRITE_BASE, REG_FLAG_NEED_BO, 0, 0},
 105         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 106         {R_028058_DB_DEPTH_SIZE, 0, 0, 0},
 107         {R_02805C_DB_DEPTH_SLICE, 0, 0, 0},
 108         {R_028140_ALU_CONST_BUFFER_SIZE_PS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0},
 109         {R_028180_ALU_CONST_BUFFER_SIZE_VS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0},
 110         {R_028200_PA_SC_WINDOW_OFFSET, 0, 0, 0},
 111         {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0, 0},
 112         {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0, 0},
 113         {R_02820C_PA_SC_CLIPRECT_RULE, 0, 0, 0},
 114         {R_028210_PA_SC_CLIPRECT_0_TL, 0, 0, 0},
 115         {R_028214_PA_SC_CLIPRECT_0_BR, 0, 0, 0},
 116         {R_028218_PA_SC_CLIPRECT_1_TL, 0, 0, 0},
 117         {R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0, 0},
 118         {R_028220_PA_SC_CLIPRECT_2_TL, 0, 0, 0},
 119         {R_028224_PA_SC_CLIPRECT_2_BR, 0, 0, 0},
 120         {R_028228_PA_SC_CLIPRECT_3_TL, 0, 0, 0},
 121         {R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0, 0},
 122         {R_028230_PA_SC_EDGERULE, 0, 0, 0},
 123         {R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0, 0},
 124         {R_028238_CB_TARGET_MASK, 0, 0, 0},
 125         {R_02823C_CB_SHADER_MASK, 0, 0, 0},
 126         {R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0, 0},
 127         {R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0, 0},
 128         {R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0, 0},
 129         {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0, 0},
 130         {R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0, 0},
 131         {R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0, 0},
 132         {R_028350_SX_MISC, 0, 0, 0},
 133         {R_028380_SQ_VTX_SEMANTIC_0, 0, 0, 0},
 134         {R_028384_SQ_VTX_SEMANTIC_1, 0, 0, 0},
 135         {R_028388_SQ_VTX_SEMANTIC_2, 0, 0, 0},
 136         {R_02838C_SQ_VTX_SEMANTIC_3, 0, 0, 0},
 137         {R_028390_SQ_VTX_SEMANTIC_4, 0, 0, 0},
 138         {R_028394_SQ_VTX_SEMANTIC_5, 0, 0, 0},
 139         {R_028398_SQ_VTX_SEMANTIC_6, 0, 0, 0},
 140         {R_02839C_SQ_VTX_SEMANTIC_7, 0, 0, 0},
 141         {R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0, 0},
 142         {R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0, 0},
 143         {R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0, 0},
 144         {R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0, 0},
 145         {R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0, 0},
 146         {R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0, 0},
 147         {R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0, 0},
 148         {R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0, 0},
 149         {R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0, 0},
 150         {R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0, 0},
 151         {R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0, 0},
 152         {R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0, 0},
 153         {R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0, 0},
 154         {R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0, 0},
 155         {R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0, 0},
 156         {R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0, 0},
 157         {R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0, 0},
 158         {R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0, 0},
 159         {R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0, 0},
 160         {R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0, 0},
 161         {R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0, 0},
 162         {R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0, 0},
 163         {R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0, 0},
 164         {R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0, 0},
 165         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 166         {R_028400_VGT_MAX_VTX_INDX, 0, 0, 0},
 167         {R_028404_VGT_MIN_VTX_INDX, 0, 0, 0},
 168         {R_028408_VGT_INDX_OFFSET, 0, 0, 0},
 169         {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0, 0},
 170         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 171         {R_028410_SX_ALPHA_TEST_CONTROL, 0, 0, 0},
 172         {R_028414_CB_BLEND_RED, 0, 0, 0},
 173         {R_028418_CB_BLEND_GREEN, 0, 0, 0},
 174         {R_02841C_CB_BLEND_BLUE, 0, 0, 0},
 175         {R_028420_CB_BLEND_ALPHA, 0, 0, 0},
 176         {R_028430_DB_STENCILREFMASK, 0, 0, 0},
 177         {R_028434_DB_STENCILREFMASK_BF, 0, 0, 0},
 178         {R_028438_SX_ALPHA_REF, 0, 0, 0},
 179         {R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0, 0},
 180         {R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0, 0},
 181         {R_028444_PA_CL_VPORT_YSCALE_0, 0, 0, 0},
 182         {R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0, 0},
 183         {R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0, 0},
 184         {R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0, 0},
 185         {R_0285BC_PA_CL_UCP0_X, 0, 0, 0},
 186         {R_0285C0_PA_CL_UCP0_Y, 0, 0, 0},
 187         {R_0285C4_PA_CL_UCP0_Z, 0, 0, 0},
 188         {R_0285C8_PA_CL_UCP0_W, 0, 0, 0},
 189         {R_0285CC_PA_CL_UCP1_X, 0, 0, 0},
 190         {R_0285D0_PA_CL_UCP1_Y, 0, 0, 0},
 191         {R_0285D4_PA_CL_UCP1_Z, 0, 0, 0},
 192         {R_0285D8_PA_CL_UCP1_W, 0, 0, 0},
 193         {R_0285DC_PA_CL_UCP2_X, 0, 0, 0},
 194         {R_0285E0_PA_CL_UCP2_Y, 0, 0, 0},
 195         {R_0285E4_PA_CL_UCP2_Z, 0, 0, 0},
 196         {R_0285E8_PA_CL_UCP2_W, 0, 0, 0},
 197         {R_0285EC_PA_CL_UCP3_X, 0, 0, 0},
 198         {R_0285F0_PA_CL_UCP3_Y, 0, 0, 0},
 199         {R_0285F4_PA_CL_UCP3_Z, 0, 0, 0},
 200         {R_0285F8_PA_CL_UCP3_W, 0, 0, 0},
 201         {R_0285FC_PA_CL_UCP4_X, 0, 0, 0},
 202         {R_028600_PA_CL_UCP4_Y, 0, 0, 0},
 203         {R_028604_PA_CL_UCP4_Z, 0, 0, 0},
 204         {R_028608_PA_CL_UCP4_W, 0, 0, 0},
 205         {R_02860C_PA_CL_UCP5_X, 0, 0, 0},
 206         {R_028610_PA_CL_UCP5_Y, 0, 0, 0},
 207         {R_028614_PA_CL_UCP5_Z, 0, 0, 0},
 208         {R_028618_PA_CL_UCP5_W, 0, 0, 0},
 209         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 210         {R_02861C_SPI_VS_OUT_ID_0, 0, 0, 0},
 211         {R_028620_SPI_VS_OUT_ID_1, 0, 0, 0},
 212         {R_028624_SPI_VS_OUT_ID_2, 0, 0, 0},
 213         {R_028628_SPI_VS_OUT_ID_3, 0, 0, 0},
 214         {R_02862C_SPI_VS_OUT_ID_4, 0, 0, 0},
 215         {R_028630_SPI_VS_OUT_ID_5, 0, 0, 0},
 216         {R_028634_SPI_VS_OUT_ID_6, 0, 0, 0},
 217         {R_028638_SPI_VS_OUT_ID_7, 0, 0, 0},
 218         {R_02863C_SPI_VS_OUT_ID_8, 0, 0, 0},
 219         {R_028640_SPI_VS_OUT_ID_9, 0, 0, 0},
 220         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 221         {R_028644_SPI_PS_INPUT_CNTL_0, 0, 0, 0},
 222         {R_028648_SPI_PS_INPUT_CNTL_1, 0, 0, 0},
 223         {R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0, 0},
 224         {R_028650_SPI_PS_INPUT_CNTL_3, 0, 0, 0},
 225         {R_028654_SPI_PS_INPUT_CNTL_4, 0, 0, 0},
 226         {R_028658_SPI_PS_INPUT_CNTL_5, 0, 0, 0},
 227         {R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0, 0},
 228         {R_028660_SPI_PS_INPUT_CNTL_7, 0, 0, 0},
 229         {R_028664_SPI_PS_INPUT_CNTL_8, 0, 0, 0},
 230         {R_028668_SPI_PS_INPUT_CNTL_9, 0, 0, 0},
 231         {R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0, 0},
 232         {R_028670_SPI_PS_INPUT_CNTL_11, 0, 0, 0},
 233         {R_028674_SPI_PS_INPUT_CNTL_12, 0, 0, 0},
 234         {R_028678_SPI_PS_INPUT_CNTL_13, 0, 0, 0},
 235         {R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0, 0},
 236         {R_028680_SPI_PS_INPUT_CNTL_15, 0, 0, 0},
 237         {R_028684_SPI_PS_INPUT_CNTL_16, 0, 0, 0},
 238         {R_028688_SPI_PS_INPUT_CNTL_17, 0, 0, 0},
 239         {R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0, 0},
 240         {R_028690_SPI_PS_INPUT_CNTL_19, 0, 0, 0},
 241         {R_028694_SPI_PS_INPUT_CNTL_20, 0, 0, 0},
 242         {R_028698_SPI_PS_INPUT_CNTL_21, 0, 0, 0},
 243         {R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0, 0},
 244         {R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0, 0},
 245         {R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0, 0},
 246         {R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0, 0},
 247         {R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0, 0},
 248         {R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0, 0},
 249         {R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0, 0},
 250         {R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0, 0},
 251         {R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0, 0},
 252         {R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0, 0},
 253         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 254         {R_0286C4_SPI_VS_OUT_CONFIG, 0, 0, 0},
 255         {R_0286C8_SPI_THREAD_GROUPING, 0, 0, 0},
 256         {R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0, 0},
 257         {R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0, 0},
 258         {R_0286D4_SPI_INTERP_CONTROL_0, 0, 0, 0},
 259         {R_0286D8_SPI_INPUT_Z, 0, 0, 0},
 260         {R_0286DC_SPI_FOG_CNTL, 0, 0, 0},
 261         {R_0286E0_SPI_BARYC_CNTL, 0, 0, 0},
 262         {R_0286E4_SPI_PS_IN_CONTROL_2, 0, 0, 0},
 263         {R_0286E8_SPI_COMPUTE_INPUT_CNTL, 0, 0, 0},
 264         {R_028780_CB_BLEND0_CONTROL, 0, 0, 0},
 265         {R_028784_CB_BLEND1_CONTROL, 0, 0, 0},
 266         {R_028788_CB_BLEND2_CONTROL, 0, 0, 0},
 267         {R_02878C_CB_BLEND3_CONTROL, 0, 0, 0},
 268         {R_028790_CB_BLEND4_CONTROL, 0, 0, 0},
 269         {R_028794_CB_BLEND5_CONTROL, 0, 0, 0},
 270         {R_028798_CB_BLEND6_CONTROL, 0, 0, 0},
 271         {R_02879C_CB_BLEND7_CONTROL, 0, 0, 0},
 272         {R_028800_DB_DEPTH_CONTROL, 0, 0, 0},
 273         {R_02880C_DB_SHADER_CONTROL, 0, 0, 0},
 274         {R_028808_CB_COLOR_CONTROL, 0, 0, 0},
 275         {R_028810_PA_CL_CLIP_CNTL, 0, 0, 0},
 276         {R_028814_PA_SU_SC_MODE_CNTL, 0, 0, 0},
 277         {R_028818_PA_CL_VTE_CNTL, 0, 0, 0},
 278         {R_02881C_PA_CL_VS_OUT_CNTL, 0, 0, 0},
 279         {R_028820_PA_CL_NANINF_CNTL, 0, 0, 0},
 280         {R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1, 0, 0, 0},
 281         {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
 282         {R_028844_SQ_PGM_RESOURCES_PS, 0, 0, 0},
 283         {R_028848_SQ_PGM_RESOURCES_2_PS, 0, 0, 0},
 284         {R_02884C_SQ_PGM_EXPORTS_PS, 0, 0, 0},
 285         {R_02885C_SQ_PGM_START_VS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
 286         {R_028860_SQ_PGM_RESOURCES_VS, 0, 0, 0},
 287         {R_028864_SQ_PGM_RESOURCES_2_VS, 0, 0, 0},
 288         {R_0288A4_SQ_PGM_START_FS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
 289         {R_0288A8_SQ_PGM_RESOURCES_FS, 0, 0, 0},
 290         {R_0288EC_SQ_LDS_ALLOC_PS, 0, 0, 0},
 291         {R_028900_SQ_ESGS_RING_ITEMSIZE, 0, 0, 0},
 292         {R_028904_SQ_GSVS_RING_ITEMSIZE, 0, 0, 0},
 293         {R_028908_SQ_ESTMP_RING_ITEMSIZE, 0, 0, 0},
 294         {R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0, 0, 0},
 295         {R_028910_SQ_VSTMP_RING_ITEMSIZE, 0, 0, 0},
 296         {R_028914_SQ_PSTMP_RING_ITEMSIZE, 0, 0, 0},
 297         {R_02891C_SQ_GS_VERT_ITEMSIZE, 0, 0, 0},
 298         {R_028920_SQ_GS_VERT_ITEMSIZE_1, 0, 0, 0},
 299         {R_028924_SQ_GS_VERT_ITEMSIZE_2, 0, 0, 0},
 300         {R_028928_SQ_GS_VERT_ITEMSIZE_3, 0, 0, 0},
 301         {R_028940_ALU_CONST_CACHE_PS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
 302         {R_028980_ALU_CONST_CACHE_VS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
 303         {R_028A00_PA_SU_POINT_SIZE, 0, 0, 0},
 304         {R_028A04_PA_SU_POINT_MINMAX, 0, 0, 0},
 305         {R_028A08_PA_SU_LINE_CNTL, 0, 0, 0},
 306         {R_028A10_VGT_OUTPUT_PATH_CNTL, 0, 0, 0},
 307         {R_028A14_VGT_HOS_CNTL, 0, 0, 0},
 308         {R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0, 0, 0},
 309         {R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0, 0, 0},
 310         {R_028A20_VGT_HOS_REUSE_DEPTH, 0, 0, 0},
 311         {R_028A24_VGT_GROUP_PRIM_TYPE, 0, 0, 0},
 312         {R_028A28_VGT_GROUP_FIRST_DECR, 0, 0, 0},
 313         {R_028A2C_VGT_GROUP_DECR, 0, 0, 0},
 314         {R_028A30_VGT_GROUP_VECT_0_CNTL, 0, 0, 0},
 315         {R_028A34_VGT_GROUP_VECT_1_CNTL, 0, 0, 0},
 316         {R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0, 0, 0},
 317         {R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0, 0, 0},
 318         {R_028A40_VGT_GS_MODE, 0, 0, 0},
 319         {R_028A48_PA_SC_MODE_CNTL_0, 0, 0, 0},
 320         {R_028A4C_PA_SC_MODE_CNTL_1, 0, 0, 0},
 321         {R_028AB4_VGT_REUSE_OFF, 0, 0, 0},
 322         {R_028AB8_VGT_VTX_CNT_EN, 0, 0, 0},
 323         {R_028ABC_DB_HTILE_SURFACE, 0, 0, 0},
 324         {R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0, 0, 0},
 325         {R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0, 0, 0},
 326         {R_028AC8_DB_PRELOAD_CONTROL, 0, 0, 0},
 327         {R_028B54_VGT_SHADER_STAGES_EN, 0, 0, 0},
 328         {R_028B70_DB_ALPHA_TO_MASK, 0, 0, 0},
 329         {R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0, 0},
 330         {R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0, 0, 0},
 331         {R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0, 0},
 332         {R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0, 0},
 333         {R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0, 0},
 334         {R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0, 0},
 335         {R_028B94_VGT_STRMOUT_CONFIG, 0, 0, 0},
 336         {R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0, 0, 0},
 337         {R_028C00_PA_SC_LINE_CNTL, 0, 0, 0},
 338         {R_028C04_PA_SC_AA_CONFIG, 0, 0, 0},
 339         {R_028C08_PA_SU_VTX_CNTL, 0, 0, 0},
 340         {R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0, 0, 0},
 341         {R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0, 0, 0},
 342         {R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0, 0},
 343         {R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0, 0, 0},
 344         {R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0, 0, 0},
 345         {R_028C3C_PA_SC_AA_MASK, 0, 0, 0},
 346         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 347         {R_028C60_CB_COLOR0_BASE, REG_FLAG_NEED_BO, 0, 0},
 348         {R_028C64_CB_COLOR0_PITCH, 0, 0, 0},
 349         {R_028C68_CB_COLOR0_SLICE, 0, 0, 0},
 350         {R_028C6C_CB_COLOR0_VIEW, 0, 0, 0},
 351         {R_028C70_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
 352         {R_028C74_CB_COLOR0_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
 353         {R_028C78_CB_COLOR0_DIM, 0, 0, 0},
 354         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 355         {R_028C9C_CB_COLOR1_BASE, REG_FLAG_NEED_BO, 0, 0},
 356         {R_028CA0_CB_COLOR1_PITCH, 0, 0, 0},
 357         {R_028CA4_CB_COLOR1_SLICE, 0, 0, 0},
 358         {R_028CA8_CB_COLOR1_VIEW, 0, 0, 0},
 359         {R_028CAC_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
 360         {R_028CB0_CB_COLOR1_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
 361         {R_028CB4_CB_COLOR1_DIM, 0, 0, 0},
 362         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 363         {R_028CD8_CB_COLOR2_BASE, REG_FLAG_NEED_BO, 0, 0},
 364         {R_028CDC_CB_COLOR2_PITCH, 0, 0, 0},
 365         {R_028CE0_CB_COLOR2_SLICE, 0, 0, 0},
 366         {R_028CE4_CB_COLOR2_VIEW, 0, 0, 0},
 367         {R_028CE8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
 368         {R_028CEC_CB_COLOR2_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
 369         {R_028CF0_CB_COLOR2_DIM, 0, 0, 0},
 370         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 371         {R_028D14_CB_COLOR3_BASE, REG_FLAG_NEED_BO, 0, 0},
 372         {R_028D18_CB_COLOR3_PITCH, 0, 0, 0},
 373         {R_028D1C_CB_COLOR3_SLICE, 0, 0, 0},
 374         {R_028D20_CB_COLOR3_VIEW, 0, 0, 0},
 375         {R_028D24_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
 376         {R_028D28_CB_COLOR3_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
 377         {R_028D2C_CB_COLOR3_DIM, 0, 0, 0},
 378         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 379         {R_028D50_CB_COLOR4_BASE, REG_FLAG_NEED_BO, 0, 0},
 380         {R_028D54_CB_COLOR4_PITCH, 0, 0, 0},
 381         {R_028D58_CB_COLOR4_SLICE, 0, 0, 0},
 382         {R_028D5C_CB_COLOR4_VIEW, 0, 0, 0},
 383         {R_028D60_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
 384         {R_028D64_CB_COLOR4_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
 385         {R_028D68_CB_COLOR4_DIM, 0, 0, 0},
 386         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 387         {R_028D8C_CB_COLOR5_BASE, REG_FLAG_NEED_BO, 0, 0},
 388         {R_028D90_CB_COLOR5_PITCH, 0, 0, 0},
 389         {R_028D94_CB_COLOR5_SLICE, 0, 0, 0},
 390         {R_028D98_CB_COLOR5_VIEW, 0, 0, 0},
 391         {R_028D9C_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
 392         {R_028DA0_CB_COLOR5_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
 393         {R_028DA4_CB_COLOR5_DIM, 0, 0, 0},
 394         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 395         {R_028DC8_CB_COLOR6_BASE, REG_FLAG_NEED_BO, 0, 0},
 396         {R_028DCC_CB_COLOR6_PITCH, 0, 0, 0},
 397         {R_028DD0_CB_COLOR6_SLICE, 0, 0, 0},
 398         {R_028DD4_CB_COLOR6_VIEW, 0, 0, 0},
 399         {R_028DD8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
 400         {R_028DDC_CB_COLOR6_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
 401         {R_028DE0_CB_COLOR6_DIM, 0, 0, 0},
 402         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 403         {R_028E04_CB_COLOR7_BASE, REG_FLAG_NEED_BO, 0, 0},
 404         {R_028E08_CB_COLOR7_PITCH, 0, 0, 0},
 405         {R_028E0C_CB_COLOR7_SLICE, 0, 0, 0},
 406         {R_028E10_CB_COLOR7_VIEW, 0, 0, 0},
 407         {R_028E14_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
 408         {R_028E18_CB_COLOR7_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
 409         {R_028E1C_CB_COLOR7_DIM, 0, 0, 0},
 410         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 411         {R_028E40_CB_COLOR8_BASE, REG_FLAG_NEED_BO, 0, 0},
 412         {R_028E44_CB_COLOR8_PITCH, 0, 0, 0},
 413         {R_028E48_CB_COLOR8_SLICE, 0, 0, 0},
 414         {R_028E4C_CB_COLOR8_VIEW, 0, 0, 0},
 415         {R_028E50_CB_COLOR8_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
 416         {R_028E54_CB_COLOR8_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
 417         {R_028E58_CB_COLOR8_DIM, 0, 0, 0},
 418         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 419         {R_028E5C_CB_COLOR9_BASE, REG_FLAG_NEED_BO, 0, 0},
 420         {R_028E60_CB_COLOR9_PITCH, 0, 0, 0},
 421         {R_028E64_CB_COLOR9_SLICE, 0, 0, 0},
 422         {R_028E68_CB_COLOR9_VIEW, 0, 0, 0},
 423         {R_028E6C_CB_COLOR9_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
 424         {R_028E70_CB_COLOR9_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
 425         {R_028E74_CB_COLOR9_DIM, 0, 0, 0},
 426         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 427         {R_028E78_CB_COLOR10_BASE, REG_FLAG_NEED_BO, 0, 0},
 428         {R_028E7C_CB_COLOR10_PITCH, 0, 0, 0},
 429         {R_028E80_CB_COLOR10_SLICE, 0, 0, 0},
 430         {R_028E84_CB_COLOR10_VIEW, 0, 0, 0},
 431         {R_028E88_CB_COLOR10_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
 432         {R_028E8C_CB_COLOR10_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
 433         {R_028E90_CB_COLOR10_DIM, 0, 0, 0},
 434         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 435         {R_028E94_CB_COLOR11_BASE, REG_FLAG_NEED_BO, 0, 0},
 436         {R_028E98_CB_COLOR11_PITCH, 0, 0, 0},
 437         {R_028E9C_CB_COLOR11_SLICE, 0, 0, 0},
 438         {R_028EA0_CB_COLOR11_VIEW, 0, 0, 0},
 439         {R_028EA4_CB_COLOR11_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
 440         {R_028EA8_CB_COLOR11_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
 441         {R_028EAC_CB_COLOR11_DIM, 0, 0, 0},
 442 };
 443
 444 static const struct r600_reg cayman_context_reg_list[] = {
 445         {R_028000_DB_RENDER_CONTROL, 0, 0, 0},
 446         {R_028004_DB_COUNT_CONTROL, 0, 0, 0},
 447         {R_028008_DB_DEPTH_VIEW, 0, 0, 0},
 448         {R_02800C_DB_RENDER_OVERRIDE, 0, 0, 0},
 449         {R_028010_DB_RENDER_OVERRIDE2, 0, 0, 0},
 450         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 451         {R_028014_DB_HTILE_DATA_BASE, REG_FLAG_NEED_BO, 0, 0},
 452         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 453         {R_028028_DB_STENCIL_CLEAR, 0, 0, 0},
 454         {R_02802C_DB_DEPTH_CLEAR, 0, 0, 0},
 455         {R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0, 0},
 456         {R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0, 0},
 457         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 458         {R_028040_DB_Z_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
 459         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 460         {R_028044_DB_STENCIL_INFO, 0, 0, 0},
 461         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 462         {R_028048_DB_Z_READ_BASE, REG_FLAG_NEED_BO, 0, 0},
 463         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 464         {R_02804C_DB_STENCIL_READ_BASE, REG_FLAG_NEED_BO, 0, 0},
 465         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 466         {R_028050_DB_Z_WRITE_BASE, REG_FLAG_NEED_BO, 0, 0},
 467         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 468         {R_028054_DB_STENCIL_WRITE_BASE, REG_FLAG_NEED_BO, 0, 0},
 469         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 470         {R_028058_DB_DEPTH_SIZE, 0, 0, 0},
 471         {R_02805C_DB_DEPTH_SLICE, 0, 0, 0},
 472         {R_028140_ALU_CONST_BUFFER_SIZE_PS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0},
 473         {R_028180_ALU_CONST_BUFFER_SIZE_VS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0},
 474         {R_028200_PA_SC_WINDOW_OFFSET, 0, 0, 0},
 475         {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0, 0},
 476         {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0, 0},
 477         {R_02820C_PA_SC_CLIPRECT_RULE, 0, 0, 0},
 478         {R_028210_PA_SC_CLIPRECT_0_TL, 0, 0, 0},
 479         {R_028214_PA_SC_CLIPRECT_0_BR, 0, 0, 0},
 480         {R_028218_PA_SC_CLIPRECT_1_TL, 0, 0, 0},
 481         {R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0, 0},
 482         {R_028220_PA_SC_CLIPRECT_2_TL, 0, 0, 0},
 483         {R_028224_PA_SC_CLIPRECT_2_BR, 0, 0, 0},
 484         {R_028228_PA_SC_CLIPRECT_3_TL, 0, 0, 0},
 485         {R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0, 0},
 486         {R_028230_PA_SC_EDGERULE, 0, 0, 0},
 487         {R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0, 0},
 488         {R_028238_CB_TARGET_MASK, 0, 0, 0},
 489         {R_02823C_CB_SHADER_MASK, 0, 0, 0},
 490         {R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0, 0},
 491         {R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0, 0},
 492         {R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0, 0},
 493         {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0, 0},
 494         {R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0, 0},
 495         {R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0, 0},
 496         {R_028350_SX_MISC, 0, 0, 0},
 497         {R_028380_SQ_VTX_SEMANTIC_0, 0, 0, 0},
 498         {R_028384_SQ_VTX_SEMANTIC_1, 0, 0, 0},
 499         {R_028388_SQ_VTX_SEMANTIC_2, 0, 0, 0},
 500         {R_02838C_SQ_VTX_SEMANTIC_3, 0, 0, 0},
 501         {R_028390_SQ_VTX_SEMANTIC_4, 0, 0, 0},
 502         {R_028394_SQ_VTX_SEMANTIC_5, 0, 0, 0},
 503         {R_028398_SQ_VTX_SEMANTIC_6, 0, 0, 0},
 504         {R_02839C_SQ_VTX_SEMANTIC_7, 0, 0, 0},
 505         {R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0, 0},
 506         {R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0, 0},
 507         {R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0, 0},
 508         {R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0, 0},
 509         {R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0, 0},
 510         {R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0, 0},
 511         {R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0, 0},
 512         {R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0, 0},
 513         {R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0, 0},
 514         {R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0, 0},
 515         {R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0, 0},
 516         {R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0, 0},
 517         {R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0, 0},
 518         {R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0, 0},
 519         {R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0, 0},
 520         {R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0, 0},
 521         {R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0, 0},
 522         {R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0, 0},
 523         {R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0, 0},
 524         {R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0, 0},
 525         {R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0, 0},
 526         {R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0, 0},
 527         {R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0, 0},
 528         {R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0, 0},
 529         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 530         {R_028400_VGT_MAX_VTX_INDX, 0, 0, 0},
 531         {R_028404_VGT_MIN_VTX_INDX, 0, 0, 0},
 532         {R_028408_VGT_INDX_OFFSET, 0, 0, 0},
 533         {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0, 0},
 534         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 535         {R_028410_SX_ALPHA_TEST_CONTROL, 0, 0, 0},
 536         {R_028414_CB_BLEND_RED, 0, 0, 0},
 537         {R_028418_CB_BLEND_GREEN, 0, 0, 0},
 538         {R_02841C_CB_BLEND_BLUE, 0, 0, 0},
 539         {R_028420_CB_BLEND_ALPHA, 0, 0, 0},
 540         {R_028430_DB_STENCILREFMASK, 0, 0, 0},
 541         {R_028434_DB_STENCILREFMASK_BF, 0, 0, 0},
 542         {R_028438_SX_ALPHA_REF, 0, 0, 0},
 543         {R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0, 0},
 544         {R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0, 0},
 545         {R_028444_PA_CL_VPORT_YSCALE_0, 0, 0, 0},
 546         {R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0, 0},
 547         {R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0, 0},
 548         {R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0, 0},
 549         {R_0285BC_PA_CL_UCP0_X, 0, 0, 0},
 550         {R_0285C0_PA_CL_UCP0_Y, 0, 0, 0},
 551         {R_0285C4_PA_CL_UCP0_Z, 0, 0, 0},
 552         {R_0285C8_PA_CL_UCP0_W, 0, 0, 0},
 553         {R_0285CC_PA_CL_UCP1_X, 0, 0, 0},
 554         {R_0285D0_PA_CL_UCP1_Y, 0, 0, 0},
 555         {R_0285D4_PA_CL_UCP1_Z, 0, 0, 0},
 556         {R_0285D8_PA_CL_UCP1_W, 0, 0, 0},
 557         {R_0285DC_PA_CL_UCP2_X, 0, 0, 0},
 558         {R_0285E0_PA_CL_UCP2_Y, 0, 0, 0},
 559         {R_0285E4_PA_CL_UCP2_Z, 0, 0, 0},
 560         {R_0285E8_PA_CL_UCP2_W, 0, 0, 0},
 561         {R_0285EC_PA_CL_UCP3_X, 0, 0, 0},
 562         {R_0285F0_PA_CL_UCP3_Y, 0, 0, 0},
 563         {R_0285F4_PA_CL_UCP3_Z, 0, 0, 0},
 564         {R_0285F8_PA_CL_UCP3_W, 0, 0, 0},
 565         {R_0285FC_PA_CL_UCP4_X, 0, 0, 0},
 566         {R_028600_PA_CL_UCP4_Y, 0, 0, 0},
 567         {R_028604_PA_CL_UCP4_Z, 0, 0, 0},
 568         {R_028608_PA_CL_UCP4_W, 0, 0, 0},
 569         {R_02860C_PA_CL_UCP5_X, 0, 0, 0},
 570         {R_028610_PA_CL_UCP5_Y, 0, 0, 0},
 571         {R_028614_PA_CL_UCP5_Z, 0, 0, 0},
 572         {R_028618_PA_CL_UCP5_W, 0, 0, 0},
 573         {R_02861C_SPI_VS_OUT_ID_0, 0, 0, 0},
 574         {R_028620_SPI_VS_OUT_ID_1, 0, 0, 0},
 575         {R_028624_SPI_VS_OUT_ID_2, 0, 0, 0},
 576         {R_028628_SPI_VS_OUT_ID_3, 0, 0, 0},
 577         {R_02862C_SPI_VS_OUT_ID_4, 0, 0, 0},
 578         {R_028630_SPI_VS_OUT_ID_5, 0, 0, 0},
 579         {R_028634_SPI_VS_OUT_ID_6, 0, 0, 0},
 580         {R_028638_SPI_VS_OUT_ID_7, 0, 0, 0},
 581         {R_02863C_SPI_VS_OUT_ID_8, 0, 0, 0},
 582         {R_028640_SPI_VS_OUT_ID_9, 0, 0, 0},
 583         {R_028644_SPI_PS_INPUT_CNTL_0, 0, 0, 0},
 584         {R_028648_SPI_PS_INPUT_CNTL_1, 0, 0, 0},
 585         {R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0, 0},
 586         {R_028650_SPI_PS_INPUT_CNTL_3, 0, 0, 0},
 587         {R_028654_SPI_PS_INPUT_CNTL_4, 0, 0, 0},
 588         {R_028658_SPI_PS_INPUT_CNTL_5, 0, 0, 0},
 589         {R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0, 0},
 590         {R_028660_SPI_PS_INPUT_CNTL_7, 0, 0, 0},
 591         {R_028664_SPI_PS_INPUT_CNTL_8, 0, 0, 0},
 592         {R_028668_SPI_PS_INPUT_CNTL_9, 0, 0, 0},
 593         {R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0, 0},
 594         {R_028670_SPI_PS_INPUT_CNTL_11, 0, 0, 0},
 595         {R_028674_SPI_PS_INPUT_CNTL_12, 0, 0, 0},
 596         {R_028678_SPI_PS_INPUT_CNTL_13, 0, 0, 0},
 597         {R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0, 0},
 598         {R_028680_SPI_PS_INPUT_CNTL_15, 0, 0, 0},
 599         {R_028684_SPI_PS_INPUT_CNTL_16, 0, 0, 0},
 600         {R_028688_SPI_PS_INPUT_CNTL_17, 0, 0, 0},
 601         {R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0, 0},
 602         {R_028690_SPI_PS_INPUT_CNTL_19, 0, 0, 0},
 603         {R_028694_SPI_PS_INPUT_CNTL_20, 0, 0, 0},
 604         {R_028698_SPI_PS_INPUT_CNTL_21, 0, 0, 0},
 605         {R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0, 0},
 606         {R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0, 0},
 607         {R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0, 0},
 608         {R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0, 0},
 609         {R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0, 0},
 610         {R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0, 0},
 611         {R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0, 0},
 612         {R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0, 0},
 613         {R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0, 0},
 614         {R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0, 0},
 615         {R_0286C4_SPI_VS_OUT_CONFIG, 0, 0, 0},
 616         {R_0286C8_SPI_THREAD_GROUPING, 0, 0, 0},
 617         {R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0, 0},
 618         {R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0, 0},
 619         {R_0286D4_SPI_INTERP_CONTROL_0, 0, 0, 0},
 620         {R_0286D8_SPI_INPUT_Z, 0, 0, 0},
 621         {R_0286DC_SPI_FOG_CNTL, 0, 0, 0},
 622         {R_0286E0_SPI_BARYC_CNTL, 0, 0, 0},
 623         {R_0286E4_SPI_PS_IN_CONTROL_2, 0, 0, 0},
 624         {R_0286E8_SPI_COMPUTE_INPUT_CNTL, 0, 0, 0},
 625         {R_028780_CB_BLEND0_CONTROL, 0, 0, 0},
 626         {R_028784_CB_BLEND1_CONTROL, 0, 0, 0},
 627         {R_028788_CB_BLEND2_CONTROL, 0, 0, 0},
 628         {R_02878C_CB_BLEND3_CONTROL, 0, 0, 0},
 629         {R_028790_CB_BLEND4_CONTROL, 0, 0, 0},
 630         {R_028794_CB_BLEND5_CONTROL, 0, 0, 0},
 631         {R_028798_CB_BLEND6_CONTROL, 0, 0, 0},
 632         {R_02879C_CB_BLEND7_CONTROL, 0, 0, 0},
 633         {R_028800_DB_DEPTH_CONTROL, 0, 0, 0},
 634         {CM_R_028804_DB_EQAA, 0, 0, 0},
 635         {R_028808_CB_COLOR_CONTROL, 0, 0, 0},
 636         {R_02880C_DB_SHADER_CONTROL, 0, 0, 0},
 637         {R_028810_PA_CL_CLIP_CNTL, 0, 0, 0},
 638         {R_028814_PA_SU_SC_MODE_CNTL, 0, 0, 0},
 639         {R_028818_PA_CL_VTE_CNTL, 0, 0, 0},
 640         {R_02881C_PA_CL_VS_OUT_CNTL, 0, 0, 0},
 641         {R_028820_PA_CL_NANINF_CNTL, 0, 0, 0},
 642         {R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1, 0, 0, 0},
 643         {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
 644         {R_028844_SQ_PGM_RESOURCES_PS, 0, 0, 0},
 645         {R_028848_SQ_PGM_RESOURCES_2_PS, 0, 0, 0},
 646         {R_02884C_SQ_PGM_EXPORTS_PS, 0, 0, 0},
 647         {R_02885C_SQ_PGM_START_VS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
 648         {R_028860_SQ_PGM_RESOURCES_VS, 0, 0, 0},
 649         {R_028864_SQ_PGM_RESOURCES_2_VS, 0, 0, 0},
 650         {R_0288A4_SQ_PGM_START_FS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
 651         {R_0288A8_SQ_PGM_RESOURCES_FS, 0, 0, 0},
 652         {CM_R_0288E8_SQ_LDS_ALLOC, 0, 0, 0},
 653         {R_0288EC_SQ_LDS_ALLOC_PS, 0, 0, 0},
 654         {R_028900_SQ_ESGS_RING_ITEMSIZE, 0, 0, 0},
 655         {R_028904_SQ_GSVS_RING_ITEMSIZE, 0, 0, 0},
 656         {R_028908_SQ_ESTMP_RING_ITEMSIZE, 0, 0, 0},
 657         {R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0, 0, 0},
 658         {R_028910_SQ_VSTMP_RING_ITEMSIZE, 0, 0, 0},
 659         {R_028914_SQ_PSTMP_RING_ITEMSIZE, 0, 0, 0},
 660         {R_02891C_SQ_GS_VERT_ITEMSIZE, 0, 0, 0},
 661         {R_028920_SQ_GS_VERT_ITEMSIZE_1, 0, 0, 0},
 662         {R_028924_SQ_GS_VERT_ITEMSIZE_2, 0, 0, 0},
 663         {R_028928_SQ_GS_VERT_ITEMSIZE_3, 0, 0, 0},
 664         {R_028940_ALU_CONST_CACHE_PS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
 665         {R_028980_ALU_CONST_CACHE_VS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
 666         {R_028A00_PA_SU_POINT_SIZE, 0, 0, 0},
 667         {R_028A04_PA_SU_POINT_MINMAX, 0, 0, 0},
 668         {R_028A08_PA_SU_LINE_CNTL, 0, 0, 0},
 669         {R_028A10_VGT_OUTPUT_PATH_CNTL, 0, 0, 0},
 670         {R_028A14_VGT_HOS_CNTL, 0, 0, 0},
 671         {R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0, 0, 0},
 672         {R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0, 0, 0},
 673         {R_028A20_VGT_HOS_REUSE_DEPTH, 0, 0, 0},
 674         {R_028A24_VGT_GROUP_PRIM_TYPE, 0, 0, 0},
 675         {R_028A28_VGT_GROUP_FIRST_DECR, 0, 0, 0},
 676         {R_028A2C_VGT_GROUP_DECR, 0, 0, 0},
 677         {R_028A30_VGT_GROUP_VECT_0_CNTL, 0, 0, 0},
 678         {R_028A34_VGT_GROUP_VECT_1_CNTL, 0, 0, 0},
 679         {R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0, 0, 0},
 680         {R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0, 0, 0},
 681         {R_028A40_VGT_GS_MODE, 0, 0, 0},
 682         {R_028A48_PA_SC_MODE_CNTL_0, 0, 0, 0},
 683         {R_028A4C_PA_SC_MODE_CNTL_1, 0, 0, 0},
 684         {R_028AB4_VGT_REUSE_OFF, 0, 0, 0},
 685         {R_028AB8_VGT_VTX_CNT_EN, 0, 0, 0},
 686         {R_028ABC_DB_HTILE_SURFACE, 0, 0, 0},
 687         {R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0, 0, 0},
 688         {R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0, 0, 0},
 689         {R_028AC8_DB_PRELOAD_CONTROL, 0, 0, 0},
 690         {R_028B54_VGT_SHADER_STAGES_EN, 0, 0, 0},
 691         {R_028B70_DB_ALPHA_TO_MASK, 0, 0, 0},
 692         {R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0, 0},
 693         {R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0, 0, 0},
 694         {R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0, 0},
 695         {R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0, 0},
 696         {R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0, 0},
 697         {R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0, 0},
 698         {R_028B94_VGT_STRMOUT_CONFIG, 0, 0, 0},
 699         {R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0, 0, 0},
 700         {CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0, 0, 0},
 701         {CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0, 0, 0},
 702         {CM_R_028BDC_PA_SC_LINE_CNTL, 0, 0, 0},
 703         {CM_R_028BE0_PA_SC_AA_CONFIG, 0, 0, 0},
 704         {CM_R_028BE4_PA_SU_VTX_CNTL, 0, 0, 0},
 705         {CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0, 0, 0},
 706         {CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0, 0, 0},
 707         {CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0, 0},
 708         {CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0, 0, 0},
 709         {CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0, 0, 0},
 710         {CM_R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, 0, 0, 0},
 711         {CM_R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, 0, 0, 0},
 712         {CM_R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, 0, 0, 0},
 713         {CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0, 0, 0},
 714         {CM_R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, 0, 0, 0},
 715         {CM_R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, 0, 0, 0},
 716         {CM_R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, 0, 0, 0},
 717         {CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0, 0, 0},
 718         {CM_R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, 0, 0, 0},
 719         {CM_R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, 0, 0, 0},
 720         {CM_R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, 0, 0, 0},
 721         {CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0, 0, 0},
 722         {CM_R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, 0, 0, 0},
 723         {CM_R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2, 0, 0, 0},
 724         {CM_R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3, 0, 0, 0},
 725         {CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 0, 0, 0},
 726         {CM_R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, 0, 0, 0},
 727         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 728         {R_028C60_CB_COLOR0_BASE, REG_FLAG_NEED_BO, 0, 0},
 729         {R_028C64_CB_COLOR0_PITCH, 0, 0, 0},
 730         {R_028C68_CB_COLOR0_SLICE, 0, 0, 0},
 731         {R_028C6C_CB_COLOR0_VIEW, 0, 0, 0},
 732         {R_028C70_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
 733         {R_028C74_CB_COLOR0_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
 734         {R_028C78_CB_COLOR0_DIM, 0, 0, 0},
 735         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 736         {R_028C9C_CB_COLOR1_BASE, REG_FLAG_NEED_BO, 0, 0},
 737         {R_028CA0_CB_COLOR1_PITCH, 0, 0, 0},
 738         {R_028CA4_CB_COLOR1_SLICE, 0, 0, 0},
 739         {R_028CA8_CB_COLOR1_VIEW, 0, 0, 0},
 740         {R_028CAC_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
 741         {R_028CB0_CB_COLOR1_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
 742         {R_028CB4_CB_COLOR1_DIM, 0, 0, 0},
 743         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 744         {R_028CD8_CB_COLOR2_BASE, REG_FLAG_NEED_BO, 0, 0},
 745         {R_028CDC_CB_COLOR2_PITCH, 0, 0, 0},
 746         {R_028CE0_CB_COLOR2_SLICE, 0, 0, 0},
 747         {R_028CE4_CB_COLOR2_VIEW, 0, 0, 0},
 748         {R_028CE8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
 749         {R_028CEC_CB_COLOR2_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
 750         {R_028CF0_CB_COLOR2_DIM, 0, 0, 0},
 751         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 752         {R_028D14_CB_COLOR3_BASE, REG_FLAG_NEED_BO, 0, 0},
 753         {R_028D18_CB_COLOR3_PITCH, 0, 0, 0},
 754         {R_028D1C_CB_COLOR3_SLICE, 0, 0, 0},
 755         {R_028D20_CB_COLOR3_VIEW, 0, 0, 0},
 756         {R_028D24_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
 757         {R_028D28_CB_COLOR3_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
 758         {R_028D2C_CB_COLOR3_DIM, 0, 0, 0},
 759         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 760         {R_028D50_CB_COLOR4_BASE, REG_FLAG_NEED_BO, 0, 0},
 761         {R_028D54_CB_COLOR4_PITCH, 0, 0, 0},
 762         {R_028D58_CB_COLOR4_SLICE, 0, 0, 0},
 763         {R_028D5C_CB_COLOR4_VIEW, 0, 0, 0},
 764         {R_028D60_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
 765         {R_028D64_CB_COLOR4_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
 766         {R_028D68_CB_COLOR4_DIM, 0, 0, 0},
 767         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 768         {R_028D8C_CB_COLOR5_BASE, REG_FLAG_NEED_BO, 0, 0},
 769         {R_028D90_CB_COLOR5_PITCH, 0, 0, 0},
 770         {R_028D94_CB_COLOR5_SLICE, 0, 0, 0},
 771         {R_028D98_CB_COLOR5_VIEW, 0, 0, 0},
 772         {R_028D9C_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
 773         {R_028DA0_CB_COLOR5_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
 774         {R_028DA4_CB_COLOR5_DIM, 0, 0, 0},
 775         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 776         {R_028DC8_CB_COLOR6_BASE, REG_FLAG_NEED_BO, 0, 0},
 777         {R_028DCC_CB_COLOR6_PITCH, 0, 0, 0},
 778         {R_028DD0_CB_COLOR6_SLICE, 0, 0, 0},
 779         {R_028DD4_CB_COLOR6_VIEW, 0, 0, 0},
 780         {R_028DD8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
 781         {R_028DDC_CB_COLOR6_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
 782         {R_028DE0_CB_COLOR6_DIM, 0, 0, 0},
 783         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 784         {R_028E04_CB_COLOR7_BASE, REG_FLAG_NEED_BO, 0, 0},
 785         {R_028E08_CB_COLOR7_PITCH, 0, 0, 0},
 786         {R_028E0C_CB_COLOR7_SLICE, 0, 0, 0},
 787         {R_028E10_CB_COLOR7_VIEW, 0, 0, 0},
 788         {R_028E14_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
 789         {R_028E18_CB_COLOR7_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
 790         {R_028E1C_CB_COLOR7_DIM, 0, 0, 0},
 791         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 792         {R_028E40_CB_COLOR8_BASE, REG_FLAG_NEED_BO, 0, 0},
 793         {R_028E44_CB_COLOR8_PITCH, 0, 0, 0},
 794         {R_028E48_CB_COLOR8_SLICE, 0, 0, 0},
 795         {R_028E4C_CB_COLOR8_VIEW, 0, 0, 0},
 796         {R_028E50_CB_COLOR8_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
 797         {R_028E54_CB_COLOR8_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
 798         {R_028E58_CB_COLOR8_DIM, 0, 0, 0},
 799         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 800         {R_028E5C_CB_COLOR9_BASE, REG_FLAG_NEED_BO, 0, 0},
 801         {R_028E60_CB_COLOR9_PITCH, 0, 0, 0},
 802         {R_028E64_CB_COLOR9_SLICE, 0, 0, 0},
 803         {R_028E68_CB_COLOR9_VIEW, 0, 0, 0},
 804         {R_028E6C_CB_COLOR9_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
 805         {R_028E70_CB_COLOR9_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
 806         {R_028E74_CB_COLOR9_DIM, 0, 0, 0},
 807         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 808         {R_028E78_CB_COLOR10_BASE, REG_FLAG_NEED_BO, 0, 0},
 809         {R_028E7C_CB_COLOR10_PITCH, 0, 0, 0},
 810         {R_028E80_CB_COLOR10_SLICE, 0, 0, 0},
 811         {R_028E84_CB_COLOR10_VIEW, 0, 0, 0},
 812         {R_028E88_CB_COLOR10_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
 813         {R_028E8C_CB_COLOR10_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
 814         {R_028E90_CB_COLOR10_DIM, 0, 0, 0},
 815         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 816         {R_028E94_CB_COLOR11_BASE, REG_FLAG_NEED_BO, 0, 0},
 817         {R_028E98_CB_COLOR11_PITCH, 0, 0, 0},
 818         {R_028E9C_CB_COLOR11_SLICE, 0, 0, 0},
 819         {R_028EA0_CB_COLOR11_VIEW, 0, 0, 0},
 820         {R_028EA4_CB_COLOR11_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
 821         {R_028EA8_CB_COLOR11_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
 822         {R_028EAC_CB_COLOR11_DIM, 0, 0, 0},
 823 };
 824
 825 /* SHADER RESOURCE R600/R700 */
 826 static int r600_resource_range_init(struct r600_context *ctx, struct r600_range *range, unsigned offset, unsigned nblocks, unsigned stride)
 827 {
 828         struct r600_reg r600_shader_resource[] = {
 829                 {R_030000_RESOURCE0_WORD0, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF},
 830                 {R_030004_RESOURCE0_WORD1, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF},
 831                 {R_030008_RESOURCE0_WORD2, 0, 0, 0},
 832                 {R_03000C_RESOURCE0_WORD3, 0, 0, 0},
 833                 {R_030010_RESOURCE0_WORD4, 0, 0, 0},
 834                 {R_030014_RESOURCE0_WORD5, 0, 0, 0},
 835                 {R_030018_RESOURCE0_WORD6, 0, 0, 0},
 836                 {R_03001C_RESOURCE0_WORD7, 0, 0, 0},
 837         };
 838         unsigned nreg = Elements(r600_shader_resource);
 839
 840         return r600_resource_init(ctx, range, offset, nblocks, stride, r600_shader_resource, nreg, EVERGREEN_RESOURCE_OFFSET);
 841 }
 842
 843 /* SHADER SAMPLER R600/R700 */
 844 static int r600_state_sampler_init(struct r600_context *ctx, u32 offset)
 845 {
 846         struct r600_reg r600_shader_sampler[] = {
 847                 {R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0, 0},
 848                 {R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0, 0},
 849                 {R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0, 0},
 850         };
 851         unsigned nreg = Elements(r600_shader_sampler);
 852
 853         for (int i = 0; i < nreg; i++) {
 854                 r600_shader_sampler[i].offset += offset;
 855         }
 856         return r600_context_add_block(ctx, r600_shader_sampler, nreg, PKT3_SET_SAMPLER, EVERGREEN_SAMPLER_OFFSET);
 857 }
 858
 859 /* SHADER SAMPLER BORDER R600/R700 */
 860 static int evergreen_state_sampler_border_init(struct r600_context *ctx, u32 offset, unsigned id)
 861 {
 862         struct r600_reg r600_shader_sampler_border[] = {
 863                 {R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, 0, 0, 0},
 864                 {R_00A404_TD_PS_SAMPLER0_BORDER_RED, 0, 0, 0},
 865                 {R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0, 0},
 866                 {R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0, 0},
 867                 {R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0, 0},
 868         };
 869         unsigned nreg = Elements(r600_shader_sampler_border);
 870         unsigned fake_offset = (offset - R_00A400_TD_PS_SAMPLER0_BORDER_INDEX) * 0x100 + 0x40000 + id * 0x1C;
 871         struct r600_range *range;
 872         struct r600_block *block;
 873         int r;
 874
 875         for (int i = 0; i < nreg; i++) {
 876                 r600_shader_sampler_border[i].offset -= R_00A400_TD_PS_SAMPLER0_BORDER_INDEX;
 877                 r600_shader_sampler_border[i].offset += fake_offset;
 878         }
 879         r = r600_context_add_block(ctx, r600_shader_sampler_border, nreg, PKT3_SET_CONFIG_REG, 0);
 880         if (r) {
 881                 return r;
 882         }
 883         /* set proper offset */
 884         range = &ctx->range[CTX_RANGE_ID(r600_shader_sampler_border[0].offset)];
 885         block = range->blocks[CTX_BLOCK_ID(r600_shader_sampler_border[0].offset)];
 886         block->pm4[1] = (offset - EVERGREEN_CONFIG_REG_OFFSET) >> 2;
 887         return 0;
 888 }
 889
 890 static int evergreen_loop_const_init(struct r600_context *ctx, u32 offset)
 891 {
 892         unsigned nreg = 32;
 893         struct r600_reg r600_loop_consts[32];
 894         int i;
 895
 896         for (i = 0; i < nreg; i++) {
 897                 r600_loop_consts[i].offset = EVERGREEN_LOOP_CONST_OFFSET + ((offset + i) * 4);
 898                 r600_loop_consts[i].flags = REG_FLAG_DIRTY_ALWAYS;
 899                 r600_loop_consts[i].flush_flags = 0;
 900                 r600_loop_consts[i].flush_mask = 0;
 901         }
 902         return r600_context_add_block(ctx, r600_loop_consts, nreg, PKT3_SET_LOOP_CONST, EVERGREEN_LOOP_CONST_OFFSET);
 903 }
 904
 905 int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon)
 906 {
 907         int r;
 908
 909         memset(ctx, 0, sizeof(struct r600_context));
 910         ctx->radeon = radeon;
 911         LIST_INITHEAD(&ctx->query_list);
 912
 913         /* init dirty list */
 914         LIST_INITHEAD(&ctx->dirty);
 915         LIST_INITHEAD(&ctx->resource_dirty);
 916         LIST_INITHEAD(&ctx->enable_list);
 917
 918         ctx->range = calloc(NUM_RANGES, sizeof(struct r600_range));
 919         if (!ctx->range) {
 920                 r = -ENOMEM;
 921                 goto out_err;
 922         }
 923
 924         /* add blocks */
 925         if (r600_get_family(radeon) == CHIP_CAYMAN)
 926                 r = r600_context_add_block(ctx, cayman_config_reg_list,
 927                                            Elements(cayman_config_reg_list), PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET);
 928         else
 929                 r = r600_context_add_block(ctx, evergreen_config_reg_list,
 930                                            Elements(evergreen_config_reg_list), PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET);
 931         if (r)
 932                 goto out_err;
 933         if (r600_get_family(radeon) == CHIP_CAYMAN)
 934                 r = r600_context_add_block(ctx, cayman_context_reg_list,
 935                                            Elements(cayman_context_reg_list), PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET);
 936         else
 937                 r = r600_context_add_block(ctx, evergreen_context_reg_list,
 938                                            Elements(evergreen_context_reg_list), PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET);
 939         if (r)
 940                 goto out_err;
 941         r = r600_context_add_block(ctx, evergreen_ctl_const_list,
 942                                    Elements(evergreen_ctl_const_list), PKT3_SET_CTL_CONST, EVERGREEN_CTL_CONST_OFFSET);
 943         if (r)
 944                 goto out_err;
 945
 946
 947         /* PS SAMPLER */
 948         for (int j = 0, offset = 0; j < 18; j++, offset += 0xC) {
 949                 r = r600_state_sampler_init(ctx, offset);
 950                 if (r)
 951                         goto out_err;
 952         }
 953         /* VS SAMPLER */
 954         for (int j = 0, offset = 0xD8; j < 18; j++, offset += 0xC) {
 955                 r = r600_state_sampler_init(ctx, offset);
 956                 if (r)
 957                         goto out_err;
 958         }
 959         /* PS SAMPLER BORDER */
 960         for (int j = 0; j < 18; j++) {
 961                 r = evergreen_state_sampler_border_init(ctx, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, j);
 962                 if (r)
 963                         goto out_err;
 964         }
 965         /* VS SAMPLER BORDER */
 966         for (int j = 0; j < 18; j++) {
 967                 r = evergreen_state_sampler_border_init(ctx, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, j);
 968                 if (r)
 969                         goto out_err;
 970         }
 971
 972         ctx->num_ps_resources = 176;
 973         ctx->num_vs_resources = 160;
 974         ctx->num_fs_resources = 16;
 975         r = r600_resource_range_init(ctx, &ctx->ps_resources, 0, 176, 0x20);
 976         if (r)
 977                 goto out_err;
 978         r = r600_resource_range_init(ctx, &ctx->vs_resources, 0x1600, 160, 0x20);
 979         if (r)
 980                 goto out_err;
 981         r = r600_resource_range_init(ctx, &ctx->fs_resources, 0x7C00, 16, 0x20);
 982         if (r)
 983                 goto out_err;
 984
 985         /* PS loop const */
 986         evergreen_loop_const_init(ctx, 0);
 987         /* VS loop const */
 988         evergreen_loop_const_init(ctx, 32);
 989
 990         r = r600_setup_block_table(ctx);
 991         if (r)
 992                 goto out_err;
 993
 994         /* allocate cs variables */
 995         ctx->nreloc = RADEON_CTX_MAX_PM4;
 996         ctx->reloc = calloc(ctx->nreloc, sizeof(struct r600_reloc));
 997         if (ctx->reloc == NULL) {
 998                 r = -ENOMEM;
 999                 goto out_err;
1000         }
1001         ctx->bo = calloc(ctx->nreloc, sizeof(void *));
1002         if (ctx->bo == NULL) {
1003                 r = -ENOMEM;
1004                 goto out_err;
1005         }
1006         ctx->pm4_ndwords = RADEON_CTX_MAX_PM4;
1007         ctx->pm4 = calloc(ctx->pm4_ndwords, 4);
1008         if (ctx->pm4 == NULL) {
1009                 r = -ENOMEM;
1010                 goto out_err;
1011         }
1012
1013         r600_init_cs(ctx);
1014         /* save 16dwords space for fence mecanism */
1015         ctx->pm4_ndwords -= 16;
1016
1017         ctx->max_db = 8;
1018
1019         LIST_INITHEAD(&ctx->fenced_bo);
1020
1021         return 0;
1022 out_err:
1023         r600_context_fini(ctx);
1024         return r;
1025 }
1026
1027 void evergreen_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
1028 {
1029         struct r600_block *block = ctx->ps_resources.blocks[rid];
1030
1031         r600_context_pipe_state_set_resource(ctx, state, block);
1032 }
1033
1034 void evergreen_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
1035 {
1036         struct r600_block *block = ctx->vs_resources.blocks[rid];
1037
1038         r600_context_pipe_state_set_resource(ctx, state, block);
1039 }
1040
1041 void evergreen_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
1042 {
1043         struct r600_block *block = ctx->fs_resources.blocks[rid];
1044
1045         r600_context_pipe_state_set_resource(ctx, state, block);
1046 }
1047
1048 static inline void evergreen_context_pipe_state_set_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
1049 {
1050         struct r600_range *range;
1051         struct r600_block *block;
1052         int i;
1053         int dirty;
1054
1055         range = &ctx->range[CTX_RANGE_ID(offset)];
1056         block = range->blocks[CTX_BLOCK_ID(offset)];
1057         if (state == NULL) {
1058                 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
1059                 LIST_DELINIT(&block->list);
1060                 LIST_DELINIT(&block->enable_list);
1061                 return;
1062         }
1063         dirty = block->status & R600_BLOCK_STATUS_DIRTY;
1064
1065         for (i = 0; i < 3; i++) {
1066                 if (block->reg[i] != state->regs[i].value) {
1067                         dirty |= R600_BLOCK_STATUS_DIRTY;
1068                         block->reg[i] = state->regs[i].value;
1069                 }
1070         }
1071         if (dirty)
1072                 r600_context_dirty_block(ctx, block, dirty, 2);
1073 }
1074
1075 static inline void evergreen_context_ps_partial_flush(struct r600_context *ctx)
1076 {
1077         if (!(ctx->flags & R600_CONTEXT_DRAW_PENDING))
1078                 return;
1079
1080         ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
1081         ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
1082
1083         ctx->flags &= ~R600_CONTEXT_DRAW_PENDING;
1084 }
1085
1086 static inline void evergreen_context_pipe_state_set_sampler_border(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset, unsigned id)
1087 {
1088         unsigned fake_offset = (offset - R_00A400_TD_PS_SAMPLER0_BORDER_INDEX) * 0x100 + 0x40000 + id * 0x1C;
1089         struct r600_range *range;
1090         struct r600_block *block;
1091         int i;
1092         int dirty;
1093
1094         range = &ctx->range[CTX_RANGE_ID(fake_offset)];
1095         block = range->blocks[CTX_BLOCK_ID(fake_offset)];
1096         if (state == NULL) {
1097                 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
1098                 LIST_DELINIT(&block->list);
1099                 LIST_DELINIT(&block->enable_list);
1100                 return;
1101         }
1102         if (state->nregs <= 3) {
1103                 return;
1104         }
1105
1106         dirty = block->status & R600_BLOCK_STATUS_DIRTY;
1107         if (block->reg[0] != id) {
1108                 block->reg[0] = id;
1109                 dirty |= R600_BLOCK_STATUS_DIRTY;
1110         }
1111
1112         for (i = 1; i < 5; i++) {
1113                 if (block->reg[i] != state->regs[i + 2].value) {
1114                         block->reg[i] = state->regs[i + 2].value;
1115                         dirty |= R600_BLOCK_STATUS_DIRTY;
1116                 }
1117         }
1118
1119         /* We have to flush the shaders before we change the border color
1120          * registers, or previous draw commands that haven't completed yet
1121          * will end up using the new border color. */
1122         if (dirty & R600_BLOCK_STATUS_DIRTY)
1123                 evergreen_context_ps_partial_flush(ctx);
1124
1125         if (dirty)
1126                 r600_context_dirty_block(ctx, block, dirty, 4);
1127 }
1128
1129 void evergreen_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
1130 {
1131         unsigned offset;
1132
1133         offset = 0x0003C000 + id * 0xc;
1134         evergreen_context_pipe_state_set_sampler(ctx, state, offset);
1135         evergreen_context_pipe_state_set_sampler_border(ctx, state, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, id);
1136 }
1137
1138 void evergreen_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
1139 {
1140         unsigned offset;
1141
1142         offset = 0x0003C0D8 + id * 0xc;
1143         evergreen_context_pipe_state_set_sampler(ctx, state, offset);
1144         evergreen_context_pipe_state_set_sampler_border(ctx, state, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, id);
1145 }
1146
1147
1148 void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *draw)
1149 {
1150         unsigned ndwords = 7;
1151         struct r600_block *dirty_block = NULL;
1152         struct r600_block *next_block;
1153         uint32_t *pm4;
1154
1155         if (draw->indices) {
1156                 ndwords = 11;
1157                 /* make sure there is enough relocation space before scheduling draw */
1158                 if (ctx->creloc >= (ctx->nreloc - 1)) {
1159                         r600_context_flush(ctx);
1160                 }
1161         }
1162
1163         /* queries need some special values */
1164         if (ctx->num_query_running) {
1165                 r600_context_reg(ctx,
1166                                 R_028004_DB_COUNT_CONTROL,
1167                                 S_028004_PERFECT_ZPASS_COUNTS(1),
1168                                 S_028004_PERFECT_ZPASS_COUNTS(1));
1169                 r600_context_reg(ctx,
1170                                 R_02800C_DB_RENDER_OVERRIDE,
1171                                 S_02800C_NOOP_CULL_DISABLE(1),
1172                                 S_02800C_NOOP_CULL_DISABLE(1));
1173         }
1174
1175         /* update the max dword count to make sure we have enough space
1176          * reserved for flushing the destination caches */
1177         ctx->pm4_ndwords = RADEON_CTX_MAX_PM4 - ctx->num_dest_buffers * 7 - 16;
1178
1179         if ((ctx->pm4_dirty_cdwords + ndwords + ctx->pm4_cdwords) > ctx->pm4_ndwords) {
1180                 /* need to flush */
1181                 r600_context_flush(ctx);
1182         }
1183         /* at that point everythings is flushed and ctx->pm4_cdwords = 0 */
1184         if ((ctx->pm4_dirty_cdwords + ndwords) > ctx->pm4_ndwords) {
1185                 R600_ERR("context is too big to be scheduled\n");
1186                 return;
1187         }
1188
1189         /* enough room to copy packet */
1190         LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &ctx->dirty,list) {
1191                 r600_context_block_emit_dirty(ctx, dirty_block);
1192         }
1193
1194         LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &ctx->resource_dirty,list) {
1195                 r600_context_block_resource_emit_dirty(ctx, dirty_block);
1196         }
1197
1198         /* draw packet */
1199         pm4 = &ctx->pm4[ctx->pm4_cdwords];
1200         pm4[0] = PKT3(PKT3_INDEX_TYPE, 0, ctx->predicate_drawing);
1201         pm4[1] = draw->vgt_index_type;
1202         pm4[2] = PKT3(PKT3_NUM_INSTANCES, 0, ctx->predicate_drawing);
1203         pm4[3] = draw->vgt_num_instances;
1204         if (draw->indices) {
1205                 pm4[4] = PKT3(PKT3_DRAW_INDEX, 3, ctx->predicate_drawing);
1206                 pm4[5] = draw->indices_bo_offset + r600_bo_offset(draw->indices);
1207                 pm4[6] = 0;
1208                 pm4[7] = draw->vgt_num_indices;
1209                 pm4[8] = draw->vgt_draw_initiator;
1210                 pm4[9] = PKT3(PKT3_NOP, 0, ctx->predicate_drawing);
1211                 pm4[10] = 0;
1212                 r600_context_bo_reloc(ctx, &pm4[10], draw->indices);
1213         } else {
1214                 pm4[4] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, ctx->predicate_drawing);
1215                 pm4[5] = draw->vgt_num_indices;
1216                 pm4[6] = draw->vgt_draw_initiator;
1217         }
1218         ctx->pm4_cdwords += ndwords;
1219
1220         ctx->flags |= (R600_CONTEXT_DRAW_PENDING | R600_CONTEXT_DST_CACHES_DIRTY);
1221
1222         /* all dirty state have been scheduled in current cs */
1223         ctx->pm4_dirty_cdwords = 0;
1224 }
1225
1226 void evergreen_context_flush_dest_caches(struct r600_context *ctx)
1227 {
1228         struct r600_bo *cb[12];
1229         struct r600_bo *db;
1230
1231         if (!(ctx->flags & R600_CONTEXT_DST_CACHES_DIRTY))
1232                 return;
1233
1234         /* find number of color buffer */
1235         db = r600_context_reg_bo(ctx, R_028048_DB_Z_READ_BASE);
1236         cb[0] = r600_context_reg_bo(ctx, R_028C60_CB_COLOR0_BASE);
1237         cb[1] = r600_context_reg_bo(ctx, R_028C9C_CB_COLOR1_BASE);
1238         cb[2] = r600_context_reg_bo(ctx, R_028CD8_CB_COLOR2_BASE);
1239         cb[3] = r600_context_reg_bo(ctx, R_028D14_CB_COLOR3_BASE);
1240         cb[4] = r600_context_reg_bo(ctx, R_028D50_CB_COLOR4_BASE);
1241         cb[5] = r600_context_reg_bo(ctx, R_028D8C_CB_COLOR5_BASE);
1242         cb[6] = r600_context_reg_bo(ctx, R_028DC8_CB_COLOR6_BASE);
1243         cb[7] = r600_context_reg_bo(ctx, R_028E04_CB_COLOR7_BASE);
1244         cb[8] = r600_context_reg_bo(ctx, R_028E40_CB_COLOR8_BASE);
1245         cb[9] = r600_context_reg_bo(ctx, R_028E5C_CB_COLOR9_BASE);
1246         cb[10] = r600_context_reg_bo(ctx, R_028E78_CB_COLOR10_BASE);
1247         cb[11] = r600_context_reg_bo(ctx, R_028E94_CB_COLOR11_BASE);
1248
1249         /* flush color buffer */
1250         for (int i = 0; i < 12; i++) {
1251                 if (cb[i]) {
1252                         unsigned flush;
1253
1254                         if (i > 7) {
1255                                 flush = (S_0085F0_CB8_DEST_BASE_ENA(1) << (i - 8)) |
1256                                         S_0085F0_CB_ACTION_ENA(1);
1257                         } else {
1258                                 flush = (S_0085F0_CB0_DEST_BASE_ENA(1) << i) |
1259                                         S_0085F0_CB_ACTION_ENA(1);
1260                         }
1261                         r600_context_bo_flush(ctx, flush, 0, cb[i]);
1262                 }
1263         }
1264         if (db) {
1265                 r600_context_bo_flush(ctx,
1266                                         S_0085F0_DB_ACTION_ENA(1) |
1267                                         S_0085F0_DB_DEST_BASE_ENA(1),
1268                                         0, db);
1269         }
1270
1271         ctx->flags &= ~R600_CONTEXT_DST_CACHES_DIRTY;
1272 }
1273