src/gallium/winsys/r600/drm/r600_hw_context.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #include <errno.h>
  27 #include <stdint.h>
  28 #include <string.h>
  29 #include <stdlib.h>
  30 #include <assert.h>
  31 #include <pipe/p_compiler.h>
  32 #include <util/u_inlines.h>
  33 #include <util/u_memory.h>
  34 #include <pipebuffer/pb_bufmgr.h>
  35 #include "xf86drm.h"
  36 #include "radeon_drm.h"
  37 #include "r600_priv.h"
  38 #include "bof.h"
  39 #include "r600d.h"
  40
  41 #define GROUP_FORCE_NEW_BLOCK   0
  42
  43 static inline void r600_context_ps_partial_flush(struct r600_context *ctx)
  44 {
  45         if (!(ctx->flags & R600_CONTEXT_DRAW_PENDING))
  46                 return;
  47
  48         ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
  49         ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
  50
  51         ctx->flags &= ~R600_CONTEXT_DRAW_PENDING;
  52 }
  53
  54 void r600_init_cs(struct r600_context *ctx)
  55 {
  56         /* R6xx requires this packet at the start of each command buffer */
  57         if (ctx->radeon->family < CHIP_RV770) {
  58                 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_START_3D_CMDBUF, 0, 0);
  59                 ctx->pm4[ctx->pm4_cdwords++] = 0x00000000;
  60         }
  61         /* All asics require this one */
  62         ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_CONTEXT_CONTROL, 1, 0);
  63         ctx->pm4[ctx->pm4_cdwords++] = 0x80000000;
  64         ctx->pm4[ctx->pm4_cdwords++] = 0x80000000;
  65 }
  66
  67 static void INLINE r600_context_update_fenced_list(struct r600_context *ctx)
  68 {
  69         for (int i = 0; i < ctx->creloc; i++) {
  70                 if (!LIST_IS_EMPTY(&ctx->bo[i]->fencedlist))
  71                         LIST_DELINIT(&ctx->bo[i]->fencedlist);
  72                 LIST_ADDTAIL(&ctx->bo[i]->fencedlist, &ctx->fenced_bo);
  73                 ctx->bo[i]->fence = ctx->radeon->fence;
  74                 ctx->bo[i]->ctx = ctx;
  75         }
  76 }
  77
  78 static void INLINE r600_context_fence_wraparound(struct r600_context *ctx, unsigned fence)
  79 {
  80         struct radeon_bo *bo = NULL;
  81         struct radeon_bo *tmp;
  82
  83         LIST_FOR_EACH_ENTRY_SAFE(bo, tmp, &ctx->fenced_bo, fencedlist) {
  84                 if (bo->fence <= *ctx->radeon->cfence) {
  85                         LIST_DELINIT(&bo->fencedlist);
  86                         bo->fence = 0;
  87                 } else {
  88                         bo->fence = fence;
  89                 }
  90         }
  91 }
  92
  93 static void r600_init_block(struct r600_context *ctx,
  94                             struct r600_block *block,
  95                             const struct r600_reg *reg, int index, int nreg,
  96                             unsigned opcode, unsigned offset_base)
  97 {
  98         int i = index;
  99         int j, n = nreg;
 100
 101         /* initialize block */
 102         if (opcode == PKT3_SET_RESOURCE) {
 103                 block->flags = BLOCK_FLAG_RESOURCE;
 104                 block->status |= R600_BLOCK_STATUS_RESOURCE_DIRTY; /* dirty all blocks at start */
 105         } else {
 106                 block->flags = 0;
 107                 block->status |= R600_BLOCK_STATUS_DIRTY; /* dirty all blocks at start */
 108         }
 109         block->start_offset = reg[i].offset;
 110         block->pm4[block->pm4_ndwords++] = PKT3(opcode, n, 0);
 111         block->pm4[block->pm4_ndwords++] = (block->start_offset - offset_base) >> 2;
 112         block->reg = &block->pm4[block->pm4_ndwords];
 113         block->pm4_ndwords += n;
 114         block->nreg = n;
 115         block->nreg_dirty = n;
 116         LIST_INITHEAD(&block->list);
 117         LIST_INITHEAD(&block->enable_list);
 118
 119         for (j = 0; j < n; j++) {
 120                 if (reg[i+j].flags & REG_FLAG_DIRTY_ALWAYS) {
 121                         block->flags |= REG_FLAG_DIRTY_ALWAYS;
 122                 }
 123                 if (reg[i+j].flags & REG_FLAG_ENABLE_ALWAYS) {
 124                         if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
 125                                 block->status |= R600_BLOCK_STATUS_ENABLED;
 126                                 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
 127                                 LIST_ADDTAIL(&block->list,&ctx->dirty);
 128                         }
 129                 }
 130                 if (reg[i+j].flags & REG_FLAG_FLUSH_CHANGE) {
 131                         block->flags |= REG_FLAG_FLUSH_CHANGE;
 132                 }
 133
 134                 if (reg[i+j].flags & REG_FLAG_NEED_BO) {
 135                         block->nbo++;
 136                         assert(block->nbo < R600_BLOCK_MAX_BO);
 137                         block->pm4_bo_index[j] = block->nbo;
 138                         block->pm4[block->pm4_ndwords++] = PKT3(PKT3_NOP, 0, 0);
 139                         block->pm4[block->pm4_ndwords++] = 0x00000000;
 140                         if (reg[i+j].flags & REG_FLAG_RV6XX_SBU) {
 141                                 block->reloc[block->nbo].flush_flags = 0;
 142                                 block->reloc[block->nbo].flush_mask = 0;
 143                         } else {
 144                                 block->reloc[block->nbo].flush_flags = reg[i+j].flush_flags;
 145                                 block->reloc[block->nbo].flush_mask = reg[i+j].flush_mask;
 146                         }
 147                         block->reloc[block->nbo].bo_pm4_index = block->pm4_ndwords - 1;
 148                 }
 149                 if ((ctx->radeon->family > CHIP_R600) &&
 150                     (ctx->radeon->family < CHIP_RV770) && reg[i+j].flags & REG_FLAG_RV6XX_SBU) {
 151                         block->pm4[block->pm4_ndwords++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0);
 152                         block->pm4[block->pm4_ndwords++] = reg[i+j].flush_flags;
 153                 }
 154         }
 155         for (j = 0; j < n; j++) {
 156                 if (reg[i+j].flush_flags) {
 157                         block->pm4_flush_ndwords += 7;
 158                 }
 159         }
 160         /* check that we stay in limit */
 161         assert(block->pm4_ndwords < R600_BLOCK_MAX_REG);
 162 }
 163
 164 int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg,
 165                            unsigned opcode, unsigned offset_base)
 166 {
 167         struct r600_block *block;
 168         struct r600_range *range;
 169         int offset;
 170
 171         for (unsigned i = 0, n = 0; i < nreg; i += n) {
 172                 /* ignore new block balise */
 173                 if (reg[i].offset == GROUP_FORCE_NEW_BLOCK) {
 174                         n = 1;
 175                         continue;
 176                 }
 177
 178                 /* ignore regs not on R600 on R600 */
 179                 if ((reg[i].flags & REG_FLAG_NOT_R600) && ctx->radeon->family == CHIP_R600) {
 180                         n = 1;
 181                         continue;
 182                 }
 183
 184                 /* register that need relocation are in their own group */
 185                 /* find number of consecutive registers */
 186                 n = 0;
 187                 offset = reg[i].offset;
 188                 while (reg[i + n].offset == offset) {
 189                         n++;
 190                         offset += 4;
 191                         if ((n + i) >= nreg)
 192                                 break;
 193                         if (n >= (R600_BLOCK_MAX_REG - 2))
 194                                 break;
 195                 }
 196
 197                 /* allocate new block */
 198                 block = calloc(1, sizeof(struct r600_block));
 199                 if (block == NULL) {
 200                         return -ENOMEM;
 201                 }
 202                 ctx->nblocks++;
 203                 for (int j = 0; j < n; j++) {
 204                         range = &ctx->range[CTX_RANGE_ID(reg[i + j].offset)];
 205                         /* create block table if it doesn't exist */
 206                         if (!range->blocks)
 207                                 range->blocks = calloc(1 << HASH_SHIFT, sizeof(void *));
 208                         if (!range->blocks)
 209                                 return -1;
 210
 211                         range->blocks[CTX_BLOCK_ID(reg[i + j].offset)] = block;
 212                 }
 213
 214                 r600_init_block(ctx, block, reg, i, n, opcode, offset_base);
 215
 216         }
 217         return 0;
 218 }
 219
 220 /* R600/R700 configuration */
 221 static const struct r600_reg r600_config_reg_list[] = {
 222         {R_008958_VGT_PRIMITIVE_TYPE, REG_FLAG_FLUSH_CHANGE, 0, 0},
 223         {R_008C00_SQ_CONFIG, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
 224         {R_008C04_SQ_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
 225         {R_008C08_SQ_GPR_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
 226         {R_008C0C_SQ_THREAD_RESOURCE_MGMT, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
 227         {R_008C10_SQ_STACK_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
 228         {R_008C14_SQ_STACK_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
 229         {R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
 230         {R_009508_TA_CNTL_AUX, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
 231         {R_009714_VC_ENHANCE, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
 232         {R_009830_DB_DEBUG, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
 233         {R_009838_DB_WATERMARKS, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
 234 };
 235
 236 static const struct r600_reg r600_ctl_const_list[] = {
 237         {R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0, 0},
 238         {R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0, 0},
 239 };
 240
 241 static const struct r600_reg r600_context_reg_list[] = {
 242         {R_028350_SX_MISC, 0, 0, 0},
 243         {R_0286C8_SPI_THREAD_GROUPING, 0, 0, 0},
 244         {R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0, 0, 0},
 245         {R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0, 0, 0},
 246         {R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0, 0, 0},
 247         {R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0, 0, 0},
 248         {R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0, 0, 0},
 249         {R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0, 0, 0},
 250         {R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0, 0, 0},
 251         {R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0, 0, 0},
 252         {R_0288C8_SQ_GS_VERT_ITEMSIZE, 0, 0, 0},
 253         {R_028A10_VGT_OUTPUT_PATH_CNTL, 0, 0, 0},
 254         {R_028A14_VGT_HOS_CNTL, 0, 0, 0},
 255         {R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0, 0, 0},
 256         {R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0, 0, 0},
 257         {R_028A20_VGT_HOS_REUSE_DEPTH, 0, 0, 0},
 258         {R_028A24_VGT_GROUP_PRIM_TYPE, 0, 0, 0},
 259         {R_028A28_VGT_GROUP_FIRST_DECR, 0, 0, 0},
 260         {R_028A2C_VGT_GROUP_DECR, 0, 0, 0},
 261         {R_028A30_VGT_GROUP_VECT_0_CNTL, 0, 0, 0},
 262         {R_028A34_VGT_GROUP_VECT_1_CNTL, 0, 0, 0},
 263         {R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0, 0, 0},
 264         {R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0, 0, 0},
 265         {R_028A40_VGT_GS_MODE, 0, 0, 0},
 266         {R_028A4C_PA_SC_MODE_CNTL, 0, 0, 0},
 267         {R_028AB0_VGT_STRMOUT_EN, 0, 0, 0},
 268         {R_028AB4_VGT_REUSE_OFF, 0, 0, 0},
 269         {R_028AB8_VGT_VTX_CNT_EN, 0, 0, 0},
 270         {R_028B20_VGT_STRMOUT_BUFFER_EN, 0, 0, 0},
 271         {R_028028_DB_STENCIL_CLEAR, 0, 0, 0},
 272         {R_02802C_DB_DEPTH_CLEAR, 0, 0, 0},
 273         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 274         {R_028040_CB_COLOR0_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(0), 0},
 275         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 276         {R_0280A0_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
 277         {R_028060_CB_COLOR0_SIZE, 0, 0, 0},
 278         {R_028080_CB_COLOR0_VIEW, 0, 0, 0},
 279         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 280         {R_0280E0_CB_COLOR0_FRAG, REG_FLAG_NEED_BO, 0, 0},
 281         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 282         {R_0280C0_CB_COLOR0_TILE, REG_FLAG_NEED_BO, 0, 0},
 283         {R_028100_CB_COLOR0_MASK, 0, 0, 0},
 284         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 285         {R_028044_CB_COLOR1_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(1), 0},
 286         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 287         {R_0280A4_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
 288         {R_028064_CB_COLOR1_SIZE, 0, 0, 0},
 289         {R_028084_CB_COLOR1_VIEW, 0, 0, 0},
 290         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 291         {R_0280E4_CB_COLOR1_FRAG, REG_FLAG_NEED_BO, 0, 0},
 292         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 293         {R_0280C4_CB_COLOR1_TILE, REG_FLAG_NEED_BO, 0, 0},
 294         {R_028104_CB_COLOR1_MASK, 0, 0, 0},
 295         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 296         {R_028048_CB_COLOR2_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(2), 0},
 297         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 298         {R_0280A8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
 299         {R_028068_CB_COLOR2_SIZE, 0, 0, 0},
 300         {R_028088_CB_COLOR2_VIEW, 0, 0, 0},
 301         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 302         {R_0280E8_CB_COLOR2_FRAG, REG_FLAG_NEED_BO, 0, 0},
 303         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 304         {R_0280C8_CB_COLOR2_TILE, REG_FLAG_NEED_BO, 0, 0},
 305         {R_028108_CB_COLOR2_MASK, 0, 0, 0},
 306         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 307         {R_02804C_CB_COLOR3_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(3), 0},
 308         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 309         {R_0280AC_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
 310         {R_02806C_CB_COLOR3_SIZE, 0, 0, 0},
 311         {R_02808C_CB_COLOR3_VIEW, 0, 0, 0},
 312         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 313         {R_0280EC_CB_COLOR3_FRAG, REG_FLAG_NEED_BO, 0, 0},
 314         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 315         {R_0280CC_CB_COLOR3_TILE, REG_FLAG_NEED_BO, 0, 0},
 316         {R_02810C_CB_COLOR3_MASK, 0, 0, 0},
 317         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 318         {R_028050_CB_COLOR4_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(4), 0},
 319         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 320         {R_0280B0_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
 321         {R_028070_CB_COLOR4_SIZE, 0, 0, 0},
 322         {R_028090_CB_COLOR4_VIEW, 0, 0, 0},
 323         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 324         {R_0280F0_CB_COLOR4_FRAG, REG_FLAG_NEED_BO, 0, 0},
 325         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 326         {R_0280D0_CB_COLOR4_TILE, REG_FLAG_NEED_BO, 0, 0},
 327         {R_028110_CB_COLOR4_MASK, 0, 0, 0},
 328         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 329         {R_028054_CB_COLOR5_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(5), 0},
 330         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 331         {R_0280B4_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
 332         {R_028074_CB_COLOR5_SIZE, 0, 0, 0},
 333         {R_028094_CB_COLOR5_VIEW, 0, 0, 0},
 334         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 335         {R_0280F4_CB_COLOR5_FRAG, REG_FLAG_NEED_BO, 0, 0},
 336         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 337         {R_0280D4_CB_COLOR5_TILE, REG_FLAG_NEED_BO, 0, 0},
 338         {R_028114_CB_COLOR5_MASK, 0, 0, 0},
 339         {R_028058_CB_COLOR6_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(6), 0},
 340         {R_0280B8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
 341         {R_028078_CB_COLOR6_SIZE, 0, 0, 0},
 342         {R_028098_CB_COLOR6_VIEW, 0, 0, 0},
 343         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 344         {R_0280F8_CB_COLOR6_FRAG, REG_FLAG_NEED_BO, 0, 0},
 345         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 346         {R_0280D8_CB_COLOR6_TILE, REG_FLAG_NEED_BO, 0, 0},
 347         {R_028118_CB_COLOR6_MASK, 0, 0, 0},
 348         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 349         {R_02805C_CB_COLOR7_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(7), 0},
 350         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 351         {R_0280BC_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
 352         {R_02807C_CB_COLOR7_SIZE, 0, 0, 0},
 353         {R_02809C_CB_COLOR7_VIEW, 0, 0, 0},
 354         {R_0280FC_CB_COLOR7_FRAG, REG_FLAG_NEED_BO, 0, 0},
 355         {R_0280DC_CB_COLOR7_TILE, REG_FLAG_NEED_BO, 0, 0},
 356         {R_02811C_CB_COLOR7_MASK, 0, 0, 0},
 357         {R_028120_CB_CLEAR_RED, 0, 0, 0},
 358         {R_028124_CB_CLEAR_GREEN, 0, 0, 0},
 359         {R_028128_CB_CLEAR_BLUE, 0, 0, 0},
 360         {R_02812C_CB_CLEAR_ALPHA, 0, 0, 0},
 361         {R_028140_ALU_CONST_BUFFER_SIZE_PS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0},
 362         {R_028180_ALU_CONST_BUFFER_SIZE_VS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0},
 363         {R_028940_ALU_CONST_CACHE_PS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
 364         {R_028980_ALU_CONST_CACHE_VS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
 365         {R_02823C_CB_SHADER_MASK, 0, 0, 0},
 366         {R_028238_CB_TARGET_MASK, 0, 0, 0},
 367         {R_028410_SX_ALPHA_TEST_CONTROL, 0, 0, 0},
 368         {R_028414_CB_BLEND_RED, 0, 0, 0},
 369         {R_028418_CB_BLEND_GREEN, 0, 0, 0},
 370         {R_02841C_CB_BLEND_BLUE, 0, 0, 0},
 371         {R_028420_CB_BLEND_ALPHA, 0, 0, 0},
 372         {R_028424_CB_FOG_RED, 0, 0, 0},
 373         {R_028428_CB_FOG_GREEN, 0, 0, 0},
 374         {R_02842C_CB_FOG_BLUE, 0, 0, 0},
 375         {R_028430_DB_STENCILREFMASK, 0, 0, 0},
 376         {R_028434_DB_STENCILREFMASK_BF, 0, 0, 0},
 377         {R_028438_SX_ALPHA_REF, 0, 0, 0},
 378         {R_0286DC_SPI_FOG_CNTL, 0, 0, 0},
 379         {R_0286E0_SPI_FOG_FUNC_SCALE, 0, 0, 0},
 380         {R_0286E4_SPI_FOG_FUNC_BIAS, 0, 0, 0},
 381         {R_028780_CB_BLEND0_CONTROL, REG_FLAG_NOT_R600, 0, 0},
 382         {R_028784_CB_BLEND1_CONTROL, REG_FLAG_NOT_R600, 0, 0},
 383         {R_028788_CB_BLEND2_CONTROL, REG_FLAG_NOT_R600, 0, 0},
 384         {R_02878C_CB_BLEND3_CONTROL, REG_FLAG_NOT_R600, 0, 0},
 385         {R_028790_CB_BLEND4_CONTROL, REG_FLAG_NOT_R600, 0, 0},
 386         {R_028794_CB_BLEND5_CONTROL, REG_FLAG_NOT_R600, 0, 0},
 387         {R_028798_CB_BLEND6_CONTROL, REG_FLAG_NOT_R600, 0, 0},
 388         {R_02879C_CB_BLEND7_CONTROL, REG_FLAG_NOT_R600, 0, 0},
 389         {R_0287A0_CB_SHADER_CONTROL, 0, 0, 0},
 390         {R_028800_DB_DEPTH_CONTROL, 0, 0, 0},
 391         {R_028804_CB_BLEND_CONTROL, 0, 0, 0},
 392         {R_028808_CB_COLOR_CONTROL, 0, 0, 0},
 393         {R_02880C_DB_SHADER_CONTROL, 0, 0, 0},
 394         {R_028C04_PA_SC_AA_CONFIG, 0, 0, 0},
 395         {R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0, 0, 0},
 396         {R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, 0, 0, 0},
 397         {R_028C30_CB_CLRCMP_CONTROL, 0, 0, 0},
 398         {R_028C34_CB_CLRCMP_SRC, 0, 0, 0},
 399         {R_028C38_CB_CLRCMP_DST, 0, 0, 0},
 400         {R_028C3C_CB_CLRCMP_MSK, 0, 0, 0},
 401         {R_028C48_PA_SC_AA_MASK, 0, 0, 0},
 402         {R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0, 0, 0},
 403         {R_028D44_DB_ALPHA_TO_MASK, 0, 0, 0},
 404         {R_02800C_DB_DEPTH_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_DEPTH, 0},
 405         {R_028000_DB_DEPTH_SIZE, 0, 0, 0},
 406         {R_028004_DB_DEPTH_VIEW, 0, 0, 0},
 407         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 408         {R_028010_DB_DEPTH_INFO, REG_FLAG_NEED_BO, 0, 0},
 409         {R_028D0C_DB_RENDER_CONTROL, 0, 0, 0},
 410         {R_028D10_DB_RENDER_OVERRIDE, 0, 0, 0},
 411         {R_028D24_DB_HTILE_SURFACE, 0, 0, 0},
 412         {R_028D30_DB_PRELOAD_CONTROL, 0, 0, 0},
 413         {R_028D34_DB_PREFETCH_LIMIT, 0, 0, 0},
 414         {R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0, 0},
 415         {R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0, 0},
 416         {R_028200_PA_SC_WINDOW_OFFSET, 0, 0, 0},
 417         {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0, 0},
 418         {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0, 0},
 419         {R_02820C_PA_SC_CLIPRECT_RULE, 0, 0, 0},
 420         {R_028210_PA_SC_CLIPRECT_0_TL, 0, 0, 0},
 421         {R_028214_PA_SC_CLIPRECT_0_BR, 0, 0, 0},
 422         {R_028218_PA_SC_CLIPRECT_1_TL, 0, 0, 0},
 423         {R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0, 0},
 424         {R_028220_PA_SC_CLIPRECT_2_TL, 0, 0, 0},
 425         {R_028224_PA_SC_CLIPRECT_2_BR, 0, 0, 0},
 426         {R_028228_PA_SC_CLIPRECT_3_TL, 0, 0, 0},
 427         {R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0, 0},
 428         {R_028230_PA_SC_EDGERULE, 0, 0, 0},
 429         {R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0, 0},
 430         {R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0, 0},
 431         {R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0, 0},
 432         {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0, 0},
 433         {R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0, 0},
 434         {R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0, 0},
 435         {R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0, 0},
 436         {R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0, 0},
 437         {R_028444_PA_CL_VPORT_YSCALE_0, 0, 0, 0},
 438         {R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0, 0},
 439         {R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0, 0},
 440         {R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0, 0},
 441         {R_0286D4_SPI_INTERP_CONTROL_0, 0, 0, 0},
 442         {R_028810_PA_CL_CLIP_CNTL, 0, 0, 0},
 443         {R_028814_PA_SU_SC_MODE_CNTL, 0, 0, 0},
 444         {R_028818_PA_CL_VTE_CNTL, 0, 0, 0},
 445         {R_02881C_PA_CL_VS_OUT_CNTL, 0, 0, 0},
 446         {R_028820_PA_CL_NANINF_CNTL, 0, 0, 0},
 447         {R_028A00_PA_SU_POINT_SIZE, 0, 0, 0},
 448         {R_028A04_PA_SU_POINT_MINMAX, 0, 0, 0},
 449         {R_028A08_PA_SU_LINE_CNTL, 0, 0, 0},
 450         {R_028A0C_PA_SC_LINE_STIPPLE, 0, 0, 0},
 451         {R_028A48_PA_SC_MPASS_PS_CNTL, 0, 0, 0},
 452         {R_028C00_PA_SC_LINE_CNTL, 0, 0, 0},
 453         {R_028C08_PA_SU_VTX_CNTL, 0, 0, 0},
 454         {R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0, 0, 0},
 455         {R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0, 0, 0},
 456         {R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0, 0},
 457         {R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0, 0, 0},
 458         {R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0, 0},
 459         {R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0, 0, 0},
 460         {R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0, 0},
 461         {R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0, 0},
 462         {R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0, 0},
 463         {R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0, 0},
 464         {R_028E20_PA_CL_UCP0_X, 0, 0, 0},
 465         {R_028E24_PA_CL_UCP0_Y, 0, 0, 0},
 466         {R_028E28_PA_CL_UCP0_Z, 0, 0, 0},
 467         {R_028E2C_PA_CL_UCP0_W, 0, 0, 0},
 468         {R_028E30_PA_CL_UCP1_X, 0, 0, 0},
 469         {R_028E34_PA_CL_UCP1_Y, 0, 0, 0},
 470         {R_028E38_PA_CL_UCP1_Z, 0, 0, 0},
 471         {R_028E3C_PA_CL_UCP1_W, 0, 0, 0},
 472         {R_028E40_PA_CL_UCP2_X, 0, 0, 0},
 473         {R_028E44_PA_CL_UCP2_Y, 0, 0, 0},
 474         {R_028E48_PA_CL_UCP2_Z, 0, 0, 0},
 475         {R_028E4C_PA_CL_UCP2_W, 0, 0, 0},
 476         {R_028E50_PA_CL_UCP3_X, 0, 0, 0},
 477         {R_028E54_PA_CL_UCP3_Y, 0, 0, 0},
 478         {R_028E58_PA_CL_UCP3_Z, 0, 0, 0},
 479         {R_028E5C_PA_CL_UCP3_W, 0, 0, 0},
 480         {R_028E60_PA_CL_UCP4_X, 0, 0, 0},
 481         {R_028E64_PA_CL_UCP4_Y, 0, 0, 0},
 482         {R_028E68_PA_CL_UCP4_Z, 0, 0, 0},
 483         {R_028E6C_PA_CL_UCP4_W, 0, 0, 0},
 484         {R_028E70_PA_CL_UCP5_X, 0, 0, 0},
 485         {R_028E74_PA_CL_UCP5_Y, 0, 0, 0},
 486         {R_028E78_PA_CL_UCP5_Z, 0, 0, 0},
 487         {R_028E7C_PA_CL_UCP5_W, 0, 0, 0},
 488         {R_028380_SQ_VTX_SEMANTIC_0, 0, 0, 0},
 489         {R_028384_SQ_VTX_SEMANTIC_1, 0, 0, 0},
 490         {R_028388_SQ_VTX_SEMANTIC_2, 0, 0, 0},
 491         {R_02838C_SQ_VTX_SEMANTIC_3, 0, 0, 0},
 492         {R_028390_SQ_VTX_SEMANTIC_4, 0, 0, 0},
 493         {R_028394_SQ_VTX_SEMANTIC_5, 0, 0, 0},
 494         {R_028398_SQ_VTX_SEMANTIC_6, 0, 0, 0},
 495         {R_02839C_SQ_VTX_SEMANTIC_7, 0, 0, 0},
 496         {R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0, 0},
 497         {R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0, 0},
 498         {R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0, 0},
 499         {R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0, 0},
 500         {R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0, 0},
 501         {R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0, 0},
 502         {R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0, 0},
 503         {R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0, 0},
 504         {R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0, 0},
 505         {R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0, 0},
 506         {R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0, 0},
 507         {R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0, 0},
 508         {R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0, 0},
 509         {R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0, 0},
 510         {R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0, 0},
 511         {R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0, 0},
 512         {R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0, 0},
 513         {R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0, 0},
 514         {R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0, 0},
 515         {R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0, 0},
 516         {R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0, 0},
 517         {R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0, 0},
 518         {R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0, 0},
 519         {R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0, 0},
 520         {R_028614_SPI_VS_OUT_ID_0, 0, 0, 0},
 521         {R_028618_SPI_VS_OUT_ID_1, 0, 0, 0},
 522         {R_02861C_SPI_VS_OUT_ID_2, 0, 0, 0},
 523         {R_028620_SPI_VS_OUT_ID_3, 0, 0, 0},
 524         {R_028624_SPI_VS_OUT_ID_4, 0, 0, 0},
 525         {R_028628_SPI_VS_OUT_ID_5, 0, 0, 0},
 526         {R_02862C_SPI_VS_OUT_ID_6, 0, 0, 0},
 527         {R_028630_SPI_VS_OUT_ID_7, 0, 0, 0},
 528         {R_028634_SPI_VS_OUT_ID_8, 0, 0, 0},
 529         {R_028638_SPI_VS_OUT_ID_9, 0, 0, 0},
 530         {R_0286C4_SPI_VS_OUT_CONFIG, 0, 0, 0},
 531         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 532         {R_028858_SQ_PGM_START_VS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
 533         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 534         {R_028868_SQ_PGM_RESOURCES_VS, 0, 0, 0},
 535         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 536         {R_028894_SQ_PGM_START_FS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
 537         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 538         {R_0288A4_SQ_PGM_RESOURCES_FS, 0, 0, 0},
 539         {R_0288D0_SQ_PGM_CF_OFFSET_VS, 0, 0, 0},
 540         {R_0288DC_SQ_PGM_CF_OFFSET_FS, 0, 0, 0},
 541         {R_028644_SPI_PS_INPUT_CNTL_0, 0, 0, 0},
 542         {R_028648_SPI_PS_INPUT_CNTL_1, 0, 0, 0},
 543         {R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0, 0},
 544         {R_028650_SPI_PS_INPUT_CNTL_3, 0, 0, 0},
 545         {R_028654_SPI_PS_INPUT_CNTL_4, 0, 0, 0},
 546         {R_028658_SPI_PS_INPUT_CNTL_5, 0, 0, 0},
 547         {R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0, 0},
 548         {R_028660_SPI_PS_INPUT_CNTL_7, 0, 0, 0},
 549         {R_028664_SPI_PS_INPUT_CNTL_8, 0, 0, 0},
 550         {R_028668_SPI_PS_INPUT_CNTL_9, 0, 0, 0},
 551         {R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0, 0},
 552         {R_028670_SPI_PS_INPUT_CNTL_11, 0, 0, 0},
 553         {R_028674_SPI_PS_INPUT_CNTL_12, 0, 0, 0},
 554         {R_028678_SPI_PS_INPUT_CNTL_13, 0, 0, 0},
 555         {R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0, 0},
 556         {R_028680_SPI_PS_INPUT_CNTL_15, 0, 0, 0},
 557         {R_028684_SPI_PS_INPUT_CNTL_16, 0, 0, 0},
 558         {R_028688_SPI_PS_INPUT_CNTL_17, 0, 0, 0},
 559         {R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0, 0},
 560         {R_028690_SPI_PS_INPUT_CNTL_19, 0, 0, 0},
 561         {R_028694_SPI_PS_INPUT_CNTL_20, 0, 0, 0},
 562         {R_028698_SPI_PS_INPUT_CNTL_21, 0, 0, 0},
 563         {R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0, 0},
 564         {R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0, 0},
 565         {R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0, 0},
 566         {R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0, 0},
 567         {R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0, 0},
 568         {R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0, 0},
 569         {R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0, 0},
 570         {R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0, 0},
 571         {R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0, 0},
 572         {R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0, 0},
 573         {R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0, 0},
 574         {R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0, 0},
 575         {R_0286D8_SPI_INPUT_Z, 0, 0, 0},
 576         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 577         {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
 578         {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 579         {R_028850_SQ_PGM_RESOURCES_PS, 0, 0, 0},
 580         {R_028854_SQ_PGM_EXPORTS_PS, 0, 0, 0},
 581         {R_0288CC_SQ_PGM_CF_OFFSET_PS, 0, 0, 0},
 582         {R_028400_VGT_MAX_VTX_INDX, 0, 0, 0},
 583         {R_028404_VGT_MIN_VTX_INDX, 0, 0, 0},
 584         {R_028408_VGT_INDX_OFFSET, 0, 0, 0},
 585         {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0, 0},
 586         {R_028A84_VGT_PRIMITIVEID_EN, 0, 0, 0},
 587         {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0, 0},
 588         {R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0, 0, 0},
 589         {R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0, 0, 0},
 590 };
 591
 592 /* SHADER RESOURCE R600/R700 */
 593 int r600_resource_init(struct r600_context *ctx, struct r600_range *range, unsigned offset, unsigned nblocks, unsigned stride, struct r600_reg *reg, int nreg, unsigned offset_base)
 594 {
 595         int i;
 596         struct r600_block *block;
 597         range->blocks = calloc(nblocks, sizeof(struct r600_block *));
 598         if (range->blocks == NULL)
 599                 return -ENOMEM;
 600
 601         reg[0].offset += offset;
 602         for (i = 0; i < nblocks; i++) {
 603                 block = calloc(1, sizeof(struct r600_block));
 604                 if (block == NULL) {
 605                         return -ENOMEM;
 606                 }
 607                 ctx->nblocks++;
 608                 range->blocks[i] = block;
 609                 r600_init_block(ctx, block, reg, 0, nreg, PKT3_SET_RESOURCE, offset_base);
 610
 611                 reg[0].offset += stride;
 612         }
 613         return 0;
 614 }
 615
 616
 617 static int r600_resource_range_init(struct r600_context *ctx, struct r600_range *range, unsigned offset, unsigned nblocks, unsigned stride)
 618 {
 619         struct r600_reg r600_shader_resource[] = {
 620                 {R_038000_RESOURCE0_WORD0, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF},
 621                 {R_038004_RESOURCE0_WORD1, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF},
 622                 {R_038008_RESOURCE0_WORD2, 0, 0, 0},
 623                 {R_03800C_RESOURCE0_WORD3, 0, 0, 0},
 624                 {R_038010_RESOURCE0_WORD4, 0, 0, 0},
 625                 {R_038014_RESOURCE0_WORD5, 0, 0, 0},
 626                 {R_038018_RESOURCE0_WORD6, 0, 0, 0},
 627         };
 628         unsigned nreg = Elements(r600_shader_resource);
 629
 630         return r600_resource_init(ctx, range, offset, nblocks, stride, r600_shader_resource, nreg, R600_RESOURCE_OFFSET);
 631 }
 632
 633 /* SHADER SAMPLER R600/R700 */
 634 static int r600_state_sampler_init(struct r600_context *ctx, u32 offset)
 635 {
 636         struct r600_reg r600_shader_sampler[] = {
 637                 {R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0, 0},
 638                 {R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0, 0},
 639                 {R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0, 0},
 640         };
 641         unsigned nreg = Elements(r600_shader_sampler);
 642
 643         for (int i = 0; i < nreg; i++) {
 644                 r600_shader_sampler[i].offset += offset;
 645         }
 646         return r600_context_add_block(ctx, r600_shader_sampler, nreg, PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET);
 647 }
 648
 649 /* SHADER SAMPLER BORDER R600/R700 */
 650 static int r600_state_sampler_border_init(struct r600_context *ctx, u32 offset)
 651 {
 652         struct r600_reg r600_shader_sampler_border[] = {
 653                 {R_00A400_TD_PS_SAMPLER0_BORDER_RED, 0, 0, 0},
 654                 {R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0, 0},
 655                 {R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0, 0},
 656                 {R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0, 0},
 657         };
 658         unsigned nreg = Elements(r600_shader_sampler_border);
 659
 660         for (int i = 0; i < nreg; i++) {
 661                 r600_shader_sampler_border[i].offset += offset;
 662         }
 663         return r600_context_add_block(ctx, r600_shader_sampler_border, nreg, PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET);
 664 }
 665
 666 static int r600_loop_const_init(struct r600_context *ctx, u32 offset)
 667 {
 668         unsigned nreg = 32;
 669         struct r600_reg r600_loop_consts[32];
 670         int i;
 671
 672         for (i = 0; i < nreg; i++) {
 673                 r600_loop_consts[i].offset = R600_LOOP_CONST_OFFSET + ((offset + i) * 4);
 674                 r600_loop_consts[i].flags = REG_FLAG_DIRTY_ALWAYS;
 675                 r600_loop_consts[i].flush_flags = 0;
 676                 r600_loop_consts[i].flush_mask = 0;
 677         }
 678         return r600_context_add_block(ctx, r600_loop_consts, nreg, PKT3_SET_LOOP_CONST, R600_LOOP_CONST_OFFSET);
 679 }
 680
 681 static void r600_context_clear_fenced_bo(struct r600_context *ctx)
 682 {
 683         struct radeon_bo *bo, *tmp;
 684
 685         LIST_FOR_EACH_ENTRY_SAFE(bo, tmp, &ctx->fenced_bo, fencedlist) {
 686                 LIST_DELINIT(&bo->fencedlist);
 687                 bo->fence = 0;
 688                 bo->ctx = NULL;
 689         }
 690 }
 691
 692 static void r600_free_resource_range(struct r600_context *ctx, struct r600_range *range, int nblocks)
 693 {
 694         struct r600_block *block;
 695         int i;
 696         for (i = 0; i < nblocks; i++) {
 697                 block = range->blocks[i];
 698                 if (block) {
 699                         for (int k = 1; k <= block->nbo; k++)
 700                                 r600_bo_reference(ctx->radeon, &block->reloc[k].bo, NULL);
 701                         free(block);
 702                 }
 703         }
 704         free(range->blocks);
 705
 706 }
 707
 708 /* initialize */
 709 void r600_context_fini(struct r600_context *ctx)
 710 {
 711         struct r600_block *block;
 712         struct r600_range *range;
 713
 714         for (int i = 0; i < NUM_RANGES; i++) {
 715                 if (!ctx->range[i].blocks)
 716                         continue;
 717                 for (int j = 0; j < (1 << HASH_SHIFT); j++) {
 718                         block = ctx->range[i].blocks[j];
 719                         if (block) {
 720                                 for (int k = 0, offset = block->start_offset; k < block->nreg; k++, offset += 4) {
 721                                         range = &ctx->range[CTX_RANGE_ID(offset)];
 722                                         range->blocks[CTX_BLOCK_ID(offset)] = NULL;
 723                                 }
 724                                 for (int k = 1; k <= block->nbo; k++) {
 725                                         r600_bo_reference(ctx->radeon, &block->reloc[k].bo, NULL);
 726                                 }
 727                                 free(block);
 728                         }
 729                 }
 730                 free(ctx->range[i].blocks);
 731         }
 732         r600_free_resource_range(ctx, &ctx->ps_resources, ctx->num_ps_resources);
 733         r600_free_resource_range(ctx, &ctx->vs_resources, ctx->num_vs_resources);
 734         r600_free_resource_range(ctx, &ctx->fs_resources, ctx->num_fs_resources);
 735         free(ctx->range);
 736         free(ctx->blocks);
 737         free(ctx->reloc);
 738         free(ctx->bo);
 739         free(ctx->pm4);
 740
 741         r600_context_clear_fenced_bo(ctx);
 742         memset(ctx, 0, sizeof(struct r600_context));
 743 }
 744
 745 static void r600_add_resource_block(struct r600_context *ctx, struct r600_range *range, int num_blocks, int *index)
 746 {
 747         int c = *index;
 748         for (int j = 0; j < num_blocks; j++) {
 749                 if (!range->blocks[j])
 750                         continue;
 751
 752                 ctx->blocks[c++] = range->blocks[j];
 753         }
 754         *index = c;
 755 }
 756
 757 int r600_setup_block_table(struct r600_context *ctx)
 758 {
 759         /* setup block table */
 760         int c = 0;
 761         ctx->blocks = calloc(ctx->nblocks, sizeof(void*));
 762         if (!ctx->blocks)
 763                 return -ENOMEM;
 764         for (int i = 0; i < NUM_RANGES; i++) {
 765                 if (!ctx->range[i].blocks)
 766                         continue;
 767                 for (int j = 0, add; j < (1 << HASH_SHIFT); j++) {
 768                         if (!ctx->range[i].blocks[j])
 769                                 continue;
 770
 771                         add = 1;
 772                         for (int k = 0; k < c; k++) {
 773                                 if (ctx->blocks[k] == ctx->range[i].blocks[j]) {
 774                                         add = 0;
 775                                         break;
 776                                 }
 777                         }
 778                         if (add) {
 779                                 assert(c < ctx->nblocks);
 780                                 ctx->blocks[c++] = ctx->range[i].blocks[j];
 781                                 j += (ctx->range[i].blocks[j]->nreg) - 1;
 782                         }
 783                 }
 784         }
 785
 786         r600_add_resource_block(ctx, &ctx->ps_resources, ctx->num_ps_resources, &c);
 787         r600_add_resource_block(ctx, &ctx->vs_resources, ctx->num_vs_resources, &c);
 788         r600_add_resource_block(ctx, &ctx->fs_resources, ctx->num_fs_resources, &c);
 789         return 0;
 790 }
 791
 792 int r600_context_init(struct r600_context *ctx, struct radeon *radeon)
 793 {
 794         int r;
 795
 796         memset(ctx, 0, sizeof(struct r600_context));
 797         ctx->radeon = radeon;
 798         LIST_INITHEAD(&ctx->query_list);
 799
 800         /* init dirty list */
 801         LIST_INITHEAD(&ctx->dirty);
 802         LIST_INITHEAD(&ctx->resource_dirty);
 803         LIST_INITHEAD(&ctx->enable_list);
 804
 805         ctx->range = calloc(NUM_RANGES, sizeof(struct r600_range));
 806         if (!ctx->range) {
 807                 r = -ENOMEM;
 808                 goto out_err;
 809         }
 810
 811         /* add blocks */
 812         r = r600_context_add_block(ctx, r600_config_reg_list,
 813                                    Elements(r600_config_reg_list), PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET);
 814         if (r)
 815                 goto out_err;
 816         r = r600_context_add_block(ctx, r600_context_reg_list,
 817                                    Elements(r600_context_reg_list), PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET);
 818         if (r)
 819                 goto out_err;
 820         r = r600_context_add_block(ctx, r600_ctl_const_list,
 821                                    Elements(r600_ctl_const_list), PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET);
 822         if (r)
 823                 goto out_err;
 824
 825         /* PS SAMPLER BORDER */
 826         for (int j = 0, offset = 0; j < 18; j++, offset += 0x10) {
 827                 r = r600_state_sampler_border_init(ctx, offset);
 828                 if (r)
 829                         goto out_err;
 830         }
 831
 832         /* VS SAMPLER BORDER */
 833         for (int j = 0, offset = 0x200; j < 18; j++, offset += 0x10) {
 834                 r = r600_state_sampler_border_init(ctx, offset);
 835                 if (r)
 836                         goto out_err;
 837         }
 838         /* PS SAMPLER */
 839         for (int j = 0, offset = 0; j < 18; j++, offset += 0xC) {
 840                 r = r600_state_sampler_init(ctx, offset);
 841                 if (r)
 842                         goto out_err;
 843         }
 844         /* VS SAMPLER */
 845         for (int j = 0, offset = 0xD8; j < 18; j++, offset += 0xC) {
 846                 r = r600_state_sampler_init(ctx, offset);
 847                 if (r)
 848                         goto out_err;
 849         }
 850
 851         ctx->num_ps_resources = 160;
 852         ctx->num_vs_resources = 160;
 853         ctx->num_fs_resources = 16;
 854         r = r600_resource_range_init(ctx, &ctx->ps_resources, 0, 160, 0x1c);
 855         if (r)
 856                 goto out_err;
 857         r = r600_resource_range_init(ctx, &ctx->vs_resources, 0x1180, 160, 0x1c);
 858         if (r)
 859                 goto out_err;
 860         r = r600_resource_range_init(ctx, &ctx->fs_resources, 0x2300, 16, 0x1c);
 861         if (r)
 862                 goto out_err;
 863
 864         /* PS loop const */
 865         r600_loop_const_init(ctx, 0);
 866         /* VS loop const */
 867         r600_loop_const_init(ctx, 32);
 868
 869         r = r600_setup_block_table(ctx);
 870         if (r)
 871                 goto out_err;
 872
 873         /* allocate cs variables */
 874         ctx->nreloc = RADEON_CTX_MAX_PM4;
 875         ctx->reloc = calloc(ctx->nreloc, sizeof(struct r600_reloc));
 876         if (ctx->reloc == NULL) {
 877                 r = -ENOMEM;
 878                 goto out_err;
 879         }
 880         ctx->bo = calloc(ctx->nreloc, sizeof(void *));
 881         if (ctx->bo == NULL) {
 882                 r = -ENOMEM;
 883                 goto out_err;
 884         }
 885         ctx->pm4_ndwords = RADEON_CTX_MAX_PM4;
 886         ctx->pm4 = calloc(ctx->pm4_ndwords, 4);
 887         if (ctx->pm4 == NULL) {
 888                 r = -ENOMEM;
 889                 goto out_err;
 890         }
 891
 892         r600_init_cs(ctx);
 893         /* save 16dwords space for fence mecanism */
 894         ctx->pm4_ndwords -= 16;
 895
 896         LIST_INITHEAD(&ctx->fenced_bo);
 897
 898         ctx->max_db = 4;
 899
 900         return 0;
 901 out_err:
 902         r600_context_fini(ctx);
 903         return r;
 904 }
 905
 906 /* Flushes all surfaces */
 907 void r600_context_flush_all(struct r600_context *ctx, unsigned flush_flags)
 908 {
 909         unsigned ndwords = 5;
 910
 911         if ((ctx->pm4_dirty_cdwords + ndwords + ctx->pm4_cdwords) > ctx->pm4_ndwords) {
 912                 /* need to flush */
 913                 r600_context_flush(ctx);
 914         }
 915
 916         ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, ctx->predicate_drawing);
 917         ctx->pm4[ctx->pm4_cdwords++] = flush_flags;     /* CP_COHER_CNTL */
 918         ctx->pm4[ctx->pm4_cdwords++] = 0xffffffff;      /* CP_COHER_SIZE */
 919         ctx->pm4[ctx->pm4_cdwords++] = 0;               /* CP_COHER_BASE */
 920         ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A;      /* POLL_INTERVAL */
 921 }
 922
 923 void r600_context_bo_flush(struct r600_context *ctx, unsigned flush_flags,
 924                                 unsigned flush_mask, struct r600_bo *rbo)
 925 {
 926         struct radeon_bo *bo;
 927
 928         bo = rbo->bo;
 929         /* if bo has already been flushed */
 930         if (!(~bo->last_flush & flush_flags)) {
 931                 bo->last_flush &= flush_mask;
 932                 return;
 933         }
 934
 935         if ((ctx->radeon->family < CHIP_RV770) &&
 936             (G_0085F0_CB_ACTION_ENA(flush_flags) ||
 937              G_0085F0_DB_ACTION_ENA(flush_flags))) {
 938                 if (ctx->flags & R600_CONTEXT_CHECK_EVENT_FLUSH) {
 939                         /* the rv670 seems to fail fbo-generatemipmap unless we flush the CB1 dest base ena */
 940                         if ((bo->binding & BO_BOUND_TEXTURE) &&
 941                             (flush_flags & S_0085F0_CB_ACTION_ENA(1))) {
 942                                 if ((ctx->radeon->family == CHIP_RV670) ||
 943                                     (ctx->radeon->family == CHIP_RS780) ||
 944                                     (ctx->radeon->family == CHIP_RS880)) {
 945                                         ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, ctx->predicate_drawing);
 946                                         ctx->pm4[ctx->pm4_cdwords++] = S_0085F0_CB1_DEST_BASE_ENA(1);     /* CP_COHER_CNTL */
 947                                         ctx->pm4[ctx->pm4_cdwords++] = 0xffffffff;      /* CP_COHER_SIZE */
 948                                         ctx->pm4[ctx->pm4_cdwords++] = 0;               /* CP_COHER_BASE */
 949                                         ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A;      /* POLL_INTERVAL */
 950                                 }
 951                         }
 952
 953                         ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, ctx->predicate_drawing);
 954                         ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
 955                         ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH;
 956                 }
 957         } else {
 958                 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, ctx->predicate_drawing);
 959                 ctx->pm4[ctx->pm4_cdwords++] = flush_flags;
 960                 ctx->pm4[ctx->pm4_cdwords++] = (bo->size + 255) >> 8;
 961                 ctx->pm4[ctx->pm4_cdwords++] = 0x00000000;
 962                 ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A;
 963                 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, ctx->predicate_drawing);
 964                 ctx->pm4[ctx->pm4_cdwords++] = bo->reloc_id;
 965         }
 966         bo->last_flush = (bo->last_flush | flush_flags) & flush_mask;
 967 }
 968
 969 void r600_context_get_reloc(struct r600_context *ctx, struct r600_bo *rbo)
 970 {
 971         struct radeon_bo *bo = rbo->bo;
 972         bo->reloc = &ctx->reloc[ctx->creloc];
 973         bo->reloc_id = ctx->creloc * sizeof(struct r600_reloc) / 4;
 974         ctx->reloc[ctx->creloc].handle = bo->handle;
 975         ctx->reloc[ctx->creloc].read_domain = rbo->domains & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM);
 976         ctx->reloc[ctx->creloc].write_domain = rbo->domains & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM);
 977         ctx->reloc[ctx->creloc].flags = 0;
 978         radeon_bo_reference(ctx->radeon, &ctx->bo[ctx->creloc], bo);
 979         rbo->fence = ctx->radeon->fence;
 980         ctx->creloc++;
 981 }
 982
 983 void r600_context_reg(struct r600_context *ctx,
 984                       unsigned offset, unsigned value,
 985                       unsigned mask)
 986 {
 987         struct r600_range *range;
 988         struct r600_block *block;
 989         unsigned id;
 990         unsigned new_val;
 991         int dirty;
 992
 993         range = &ctx->range[CTX_RANGE_ID(offset)];
 994         block = range->blocks[CTX_BLOCK_ID(offset)];
 995         id = (offset - block->start_offset) >> 2;
 996
 997         dirty = block->status & R600_BLOCK_STATUS_DIRTY;
 998
 999         new_val = block->reg[id];
1000         new_val &= ~mask;
1001         new_val |= value;
1002         if (new_val != block->reg[id]) {
1003                 dirty |= R600_BLOCK_STATUS_DIRTY;
1004                 block->reg[id] = new_val;
1005         }
1006         if (dirty)
1007                 r600_context_dirty_block(ctx, block, dirty, id);
1008 }
1009
1010 void r600_context_dirty_block(struct r600_context *ctx,
1011                               struct r600_block *block,
1012                               int dirty, int index)
1013 {
1014         if ((index + 1) > block->nreg_dirty)
1015                 block->nreg_dirty = index + 1;
1016
1017         if ((dirty != (block->status & R600_BLOCK_STATUS_DIRTY)) || !(block->status & R600_BLOCK_STATUS_ENABLED)) {
1018                 block->status |= R600_BLOCK_STATUS_DIRTY;
1019                 ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords;
1020                 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
1021                         block->status |= R600_BLOCK_STATUS_ENABLED;
1022                         LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
1023                 }
1024                 LIST_ADDTAIL(&block->list,&ctx->dirty);
1025
1026                 if (block->flags & REG_FLAG_FLUSH_CHANGE) {
1027                         r600_context_ps_partial_flush(ctx);
1028                 }
1029         }
1030 }
1031
1032 void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state)
1033 {
1034         struct r600_block *block;
1035         unsigned new_val;
1036         int dirty;
1037         for (int i = 0; i < state->nregs; i++) {
1038                 unsigned id, reloc_id;
1039                 struct r600_pipe_reg *reg = &state->regs[i];
1040
1041                 block = reg->block;
1042                 id = reg->id;
1043
1044                 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
1045
1046                 new_val = block->reg[id];
1047                 new_val &= ~reg->mask;
1048                 new_val |= reg->value;
1049                 if (new_val != block->reg[id]) {
1050                         block->reg[id] = new_val;
1051                         dirty |= R600_BLOCK_STATUS_DIRTY;
1052                 }
1053                 if (block->flags & REG_FLAG_DIRTY_ALWAYS)
1054                         dirty |= R600_BLOCK_STATUS_DIRTY;
1055                 if (block->pm4_bo_index[id]) {
1056                         /* find relocation */
1057                         reloc_id = block->pm4_bo_index[id];
1058                         r600_bo_reference(ctx->radeon, &block->reloc[reloc_id].bo, reg->bo);
1059                         reg->bo->fence = ctx->radeon->fence;
1060                         /* always force dirty for relocs for now */
1061                         dirty |= R600_BLOCK_STATUS_DIRTY;
1062                 }
1063
1064                 if (dirty)
1065                         r600_context_dirty_block(ctx, block, dirty, id);
1066         }
1067 }
1068
1069 static void r600_context_dirty_resource_block(struct r600_context *ctx,
1070                                               struct r600_block *block,
1071                                               int dirty, int index)
1072 {
1073         block->nreg_dirty = index + 1;
1074
1075         if ((dirty != (block->status & R600_BLOCK_STATUS_RESOURCE_DIRTY)) || !(block->status & R600_BLOCK_STATUS_ENABLED)) {
1076                 block->status |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
1077                 ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords;
1078                 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
1079                         block->status |= R600_BLOCK_STATUS_ENABLED;
1080                         LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
1081                 }
1082                 LIST_ADDTAIL(&block->list,&ctx->resource_dirty);
1083         }
1084 }
1085
1086 void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, struct r600_block *block)
1087 {
1088         int dirty;
1089         int num_regs = ctx->radeon->chip_class >= EVERGREEN ? 8 : 7;
1090         boolean is_vertex;
1091
1092         if (state == NULL) {
1093                 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_RESOURCE_DIRTY);
1094                 if (block->reloc[1].bo)
1095                         block->reloc[1].bo->bo->binding &= ~BO_BOUND_TEXTURE;
1096
1097                 r600_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL);
1098                 r600_bo_reference(ctx->radeon, &block->reloc[2].bo, NULL);
1099                 LIST_DELINIT(&block->list);
1100                 LIST_DELINIT(&block->enable_list);
1101                 return;
1102         }
1103
1104         is_vertex = ((state->val[num_regs-1] & 0xc0000000) == 0xc0000000);
1105         dirty = block->status & R600_BLOCK_STATUS_RESOURCE_DIRTY;
1106
1107         if (memcmp(block->reg, state->val, num_regs*4)) {
1108                 memcpy(block->reg, state->val, num_regs * 4);
1109                 dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
1110         }
1111
1112         /* if no BOs on block, force dirty */
1113         if (!block->reloc[1].bo || !block->reloc[2].bo)
1114                 dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
1115
1116         if (!dirty) {
1117                 if (is_vertex) {
1118                         if (block->reloc[1].bo->bo->handle != state->bo[0]->bo->handle)
1119                                 dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
1120                 } else {
1121                         if ((block->reloc[1].bo->bo->handle != state->bo[0]->bo->handle) ||
1122                             (block->reloc[2].bo->bo->handle != state->bo[1]->bo->handle))
1123                                 dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
1124                 }
1125         }
1126         if (!dirty) {
1127                 if (is_vertex)
1128                         state->bo[0]->fence = ctx->radeon->fence;
1129                 else {
1130                         state->bo[0]->fence = ctx->radeon->fence;
1131                         state->bo[1]->fence = ctx->radeon->fence;
1132                 }
1133         } else {
1134                 if (is_vertex) {
1135                         /* VERTEX RESOURCE, we preted there is 2 bo to relocate so
1136                          * we have single case btw VERTEX & TEXTURE resource
1137                          */
1138                         r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->bo[0]);
1139                         r600_bo_reference(ctx->radeon, &block->reloc[2].bo, NULL);
1140                         state->bo[0]->fence = ctx->radeon->fence;
1141                 } else {
1142                         /* TEXTURE RESOURCE */
1143                         r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->bo[0]);
1144                         r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->bo[1]);
1145                         state->bo[0]->fence = ctx->radeon->fence;
1146                         state->bo[1]->fence = ctx->radeon->fence;
1147                         state->bo[0]->bo->binding |= BO_BOUND_TEXTURE;
1148                 }
1149         }
1150         if (dirty) {
1151                 if (is_vertex)
1152                         block->status |= R600_BLOCK_STATUS_RESOURCE_VERTEX;
1153                 else
1154                         block->status &= ~R600_BLOCK_STATUS_RESOURCE_VERTEX;
1155
1156                 r600_context_dirty_resource_block(ctx, block, dirty, num_regs - 1);
1157         }
1158 }
1159
1160 void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
1161 {
1162         struct r600_block *block = ctx->ps_resources.blocks[rid];
1163
1164         r600_context_pipe_state_set_resource(ctx, state, block);
1165 }
1166
1167 void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
1168 {
1169         struct r600_block *block = ctx->vs_resources.blocks[rid];
1170
1171         r600_context_pipe_state_set_resource(ctx, state, block);
1172 }
1173
1174 void r600_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
1175 {
1176         struct r600_block *block = ctx->fs_resources.blocks[rid];
1177
1178         r600_context_pipe_state_set_resource(ctx, state, block);
1179 }
1180
1181 static inline void r600_context_pipe_state_set_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
1182 {
1183         struct r600_range *range;
1184         struct r600_block *block;
1185         int i;
1186         int dirty;
1187
1188         range = &ctx->range[CTX_RANGE_ID(offset)];
1189         block = range->blocks[CTX_BLOCK_ID(offset)];
1190         if (state == NULL) {
1191                 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
1192                 LIST_DELINIT(&block->list);
1193                 LIST_DELINIT(&block->enable_list);
1194                 return;
1195         }
1196         dirty = block->status & R600_BLOCK_STATUS_DIRTY;
1197         for (i = 0; i < 3; i++) {
1198                 if (block->reg[i] != state->regs[i].value) {
1199                         block->reg[i] = state->regs[i].value;
1200                         dirty |= R600_BLOCK_STATUS_DIRTY;
1201                 }
1202         }
1203
1204         if (dirty)
1205                 r600_context_dirty_block(ctx, block, dirty, 2);
1206 }
1207
1208
1209 static inline void r600_context_pipe_state_set_sampler_border(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
1210 {
1211         struct r600_range *range;
1212         struct r600_block *block;
1213         int i;
1214         int dirty;
1215
1216         range = &ctx->range[CTX_RANGE_ID(offset)];
1217         block = range->blocks[CTX_BLOCK_ID(offset)];
1218         if (state == NULL) {
1219                 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
1220                 LIST_DELINIT(&block->list);
1221                 LIST_DELINIT(&block->enable_list);
1222                 return;
1223         }
1224         if (state->nregs <= 3) {
1225                 return;
1226         }
1227         dirty = block->status & R600_BLOCK_STATUS_DIRTY;
1228         for (i = 0; i < 4; i++) {
1229                 if (block->reg[i] != state->regs[i + 3].value) {
1230                         block->reg[i] = state->regs[i + 3].value;
1231                         dirty |= R600_BLOCK_STATUS_DIRTY;
1232                 }
1233         }
1234
1235         /* We have to flush the shaders before we change the border color
1236          * registers, or previous draw commands that haven't completed yet
1237          * will end up using the new border color. */
1238         if (dirty & R600_BLOCK_STATUS_DIRTY)
1239                 r600_context_ps_partial_flush(ctx);
1240         if (dirty)
1241                 r600_context_dirty_block(ctx, block, dirty, 3);
1242 }
1243
1244 void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
1245 {
1246         unsigned offset;
1247
1248         offset = 0x0003C000 + id * 0xc;
1249         r600_context_pipe_state_set_sampler(ctx, state, offset);
1250         offset = 0x0000A400 + id * 0x10;
1251         r600_context_pipe_state_set_sampler_border(ctx, state, offset);
1252 }
1253
1254 void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
1255 {
1256         unsigned offset;
1257
1258         offset = 0x0003C0D8 + id * 0xc;
1259         r600_context_pipe_state_set_sampler(ctx, state, offset);
1260         offset = 0x0000A600 + id * 0x10;
1261         r600_context_pipe_state_set_sampler_border(ctx, state, offset);
1262 }
1263
1264 struct r600_bo *r600_context_reg_bo(struct r600_context *ctx, unsigned offset)
1265 {
1266         struct r600_range *range;
1267         struct r600_block *block;
1268         unsigned id;
1269
1270         range = &ctx->range[CTX_RANGE_ID(offset)];
1271         block = range->blocks[CTX_BLOCK_ID(offset)];
1272         offset -= block->start_offset;
1273         id = block->pm4_bo_index[offset >> 2];
1274         if (block->reloc[id].bo) {
1275                 return block->reloc[id].bo;
1276         }
1277         return NULL;
1278 }
1279
1280 void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block)
1281 {
1282         int id;
1283         int optional = block->nbo == 0 && !(block->flags & REG_FLAG_DIRTY_ALWAYS);
1284         int cp_dwords = block->pm4_ndwords, start_dword = 0;
1285         int new_dwords = 0;
1286         int nbo = block->nbo;
1287
1288         if (block->nreg_dirty == 0 && optional) {
1289                 goto out;
1290         }
1291
1292         if (nbo) {
1293                 ctx->flags |= R600_CONTEXT_CHECK_EVENT_FLUSH;
1294
1295                 for (int j = 0; j < block->nreg; j++) {
1296                         if (block->pm4_bo_index[j]) {
1297                                 /* find relocation */
1298                                 id = block->pm4_bo_index[j];
1299                                 r600_context_bo_reloc(ctx,
1300                                                       &block->pm4[block->reloc[id].bo_pm4_index],
1301                                                       block->reloc[id].bo);
1302                                 r600_context_bo_flush(ctx,
1303                                                       block->reloc[id].flush_flags,
1304                                                       block->reloc[id].flush_mask,
1305                                                       block->reloc[id].bo);
1306                                 nbo--;
1307                                 if (nbo == 0)
1308                                         break;
1309                         }
1310                 }
1311                 ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH;
1312         }
1313
1314         optional &= (block->nreg_dirty != block->nreg);
1315         if (optional) {
1316                 new_dwords = block->nreg_dirty;
1317                 start_dword = ctx->pm4_cdwords;
1318                 cp_dwords = new_dwords + 2;
1319         }
1320         memcpy(&ctx->pm4[ctx->pm4_cdwords], block->pm4, cp_dwords * 4);
1321         ctx->pm4_cdwords += cp_dwords;
1322
1323         if (optional) {
1324                 uint32_t newword;
1325
1326                 newword = ctx->pm4[start_dword];
1327                 newword &= PKT_COUNT_C;
1328                 newword |= PKT_COUNT_S(new_dwords);
1329                 ctx->pm4[start_dword] = newword;
1330         }
1331 out:
1332         block->status ^= R600_BLOCK_STATUS_DIRTY;
1333         block->nreg_dirty = 0;
1334         LIST_DELINIT(&block->list);
1335 }
1336
1337 void r600_context_block_resource_emit_dirty(struct r600_context *ctx, struct r600_block *block)
1338 {
1339         int id;
1340         int cp_dwords = block->pm4_ndwords;
1341         int nbo = block->nbo;
1342
1343         ctx->flags |= R600_CONTEXT_CHECK_EVENT_FLUSH;
1344
1345         if (block->status & R600_BLOCK_STATUS_RESOURCE_VERTEX) {
1346                 nbo = 1;
1347                 cp_dwords -= 2; /* don't copy the second NOP */
1348         }
1349
1350         for (int j = 0; j < nbo; j++) {
1351                 if (block->pm4_bo_index[j]) {
1352                         /* find relocation */
1353                         id = block->pm4_bo_index[j];
1354                         r600_context_bo_reloc(ctx,
1355                                               &block->pm4[block->reloc[id].bo_pm4_index],
1356                                               block->reloc[id].bo);
1357                         r600_context_bo_flush(ctx,
1358                                               block->reloc[id].flush_flags,
1359                                               block->reloc[id].flush_mask,
1360                                               block->reloc[id].bo);
1361                 }
1362         }
1363         ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH;
1364
1365         memcpy(&ctx->pm4[ctx->pm4_cdwords], block->pm4, cp_dwords * 4);
1366         ctx->pm4_cdwords += cp_dwords;
1367
1368         block->status ^= R600_BLOCK_STATUS_RESOURCE_DIRTY;
1369         block->nreg_dirty = 0;
1370         LIST_DELINIT(&block->list);
1371 }
1372
1373 void r600_context_flush_dest_caches(struct r600_context *ctx)
1374 {
1375         struct r600_bo *cb[8];
1376         struct r600_bo *db;
1377         int i;
1378
1379         if (!(ctx->flags & R600_CONTEXT_DST_CACHES_DIRTY))
1380                 return;
1381
1382         db = r600_context_reg_bo(ctx, R_02800C_DB_DEPTH_BASE);
1383         cb[0] = r600_context_reg_bo(ctx, R_028040_CB_COLOR0_BASE);
1384         cb[1] = r600_context_reg_bo(ctx, R_028044_CB_COLOR1_BASE);
1385         cb[2] = r600_context_reg_bo(ctx, R_028048_CB_COLOR2_BASE);
1386         cb[3] = r600_context_reg_bo(ctx, R_02804C_CB_COLOR3_BASE);
1387         cb[4] = r600_context_reg_bo(ctx, R_028050_CB_COLOR4_BASE);
1388         cb[5] = r600_context_reg_bo(ctx, R_028054_CB_COLOR5_BASE);
1389         cb[6] = r600_context_reg_bo(ctx, R_028058_CB_COLOR6_BASE);
1390         cb[7] = r600_context_reg_bo(ctx, R_02805C_CB_COLOR7_BASE);
1391
1392         ctx->flags |= R600_CONTEXT_CHECK_EVENT_FLUSH;
1393         /* flush the color buffers */
1394         for (i = 0; i < 8; i++) {
1395                 if (!cb[i])
1396                         continue;
1397
1398                 r600_context_bo_flush(ctx,
1399                                         (S_0085F0_CB0_DEST_BASE_ENA(1) << i) |
1400                                         S_0085F0_CB_ACTION_ENA(1),
1401                                         0, cb[i]);
1402         }
1403         if (db) {
1404                 r600_context_bo_flush(ctx, S_0085F0_DB_ACTION_ENA(1) | S_0085F0_DB_DEST_BASE_ENA(1), 0, db);
1405         }
1406         ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH;
1407         ctx->flags &= ~R600_CONTEXT_DST_CACHES_DIRTY;
1408 }
1409
1410 void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw)
1411 {
1412         unsigned ndwords = 7;
1413         struct r600_block *dirty_block = NULL;
1414         struct r600_block *next_block;
1415         uint32_t *pm4;
1416
1417         if (draw->indices) {
1418                 ndwords = 11;
1419                 /* make sure there is enough relocation space before scheduling draw */
1420                 if (ctx->creloc >= (ctx->nreloc - 1)) {
1421                         r600_context_flush(ctx);
1422                 }
1423         }
1424
1425         /* queries need some special values */
1426         if (ctx->num_query_running) {
1427                 if (ctx->radeon->family >= CHIP_RV770) {
1428                         r600_context_reg(ctx,
1429                                         R_028D0C_DB_RENDER_CONTROL,
1430                                         S_028D0C_R700_PERFECT_ZPASS_COUNTS(1),
1431                                         S_028D0C_R700_PERFECT_ZPASS_COUNTS(1));
1432                 }
1433                 r600_context_reg(ctx,
1434                                 R_028D10_DB_RENDER_OVERRIDE,
1435                                 S_028D10_NOOP_CULL_DISABLE(1),
1436                                 S_028D10_NOOP_CULL_DISABLE(1));
1437         }
1438
1439         /* update the max dword count to make sure we have enough space
1440          * reserved for flushing the destination caches */
1441         ctx->pm4_ndwords = RADEON_CTX_MAX_PM4 - ctx->num_dest_buffers * 7 - 16;
1442
1443         if ((ctx->pm4_dirty_cdwords + ndwords + ctx->pm4_cdwords) > ctx->pm4_ndwords) {
1444                 /* need to flush */
1445                 r600_context_flush(ctx);
1446         }
1447         /* at that point everythings is flushed and ctx->pm4_cdwords = 0 */
1448         if ((ctx->pm4_dirty_cdwords + ndwords) > ctx->pm4_ndwords) {
1449                 R600_ERR("context is too big to be scheduled\n");
1450                 return;
1451         }
1452         /* enough room to copy packet */
1453         LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &ctx->dirty, list) {
1454                 r600_context_block_emit_dirty(ctx, dirty_block);
1455         }
1456
1457         LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &ctx->resource_dirty, list) {
1458                 r600_context_block_resource_emit_dirty(ctx, dirty_block);
1459         }
1460
1461         /* draw packet */
1462         pm4 = &ctx->pm4[ctx->pm4_cdwords];
1463
1464         pm4[0] = PKT3(PKT3_INDEX_TYPE, 0, ctx->predicate_drawing);
1465         pm4[1] = draw->vgt_index_type;
1466         pm4[2] = PKT3(PKT3_NUM_INSTANCES, 0, ctx->predicate_drawing);
1467         pm4[3] = draw->vgt_num_instances;
1468         if (draw->indices) {
1469                 pm4[4] = PKT3(PKT3_DRAW_INDEX, 3, ctx->predicate_drawing);
1470                 pm4[5] = draw->indices_bo_offset + r600_bo_offset(draw->indices);
1471                 pm4[6] = 0;
1472                 pm4[7] = draw->vgt_num_indices;
1473                 pm4[8] = draw->vgt_draw_initiator;
1474                 pm4[9] = PKT3(PKT3_NOP, 0, ctx->predicate_drawing);
1475                 pm4[10] = 0;
1476                 r600_context_bo_reloc(ctx, &pm4[10], draw->indices);
1477         } else {
1478                 pm4[4] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, ctx->predicate_drawing);
1479                 pm4[5] = draw->vgt_num_indices;
1480                 pm4[6] = draw->vgt_draw_initiator;
1481         }
1482         ctx->pm4_cdwords += ndwords;
1483
1484         ctx->flags |= (R600_CONTEXT_DST_CACHES_DIRTY | R600_CONTEXT_DRAW_PENDING);
1485
1486         /* all dirty state have been scheduled in current cs */
1487         ctx->pm4_dirty_cdwords = 0;
1488 }
1489
1490 void r600_context_flush(struct r600_context *ctx)
1491 {
1492         struct drm_radeon_cs drmib = {};
1493         struct drm_radeon_cs_chunk chunks[2];
1494         uint64_t chunk_array[2];
1495         unsigned fence;
1496         int r;
1497         struct r600_block *enable_block = NULL;
1498
1499         if (!ctx->pm4_cdwords)
1500                 return;
1501
1502         /* suspend queries */
1503         r600_context_queries_suspend(ctx);
1504
1505         if (ctx->radeon->family >= CHIP_CEDAR)
1506                 evergreen_context_flush_dest_caches(ctx);
1507         else
1508                 r600_context_flush_dest_caches(ctx);
1509
1510         /* partial flush is needed to avoid lockups on some chips with user fences */
1511         ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
1512         ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
1513         /* emit fence */
1514         ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
1515         ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
1516         ctx->pm4[ctx->pm4_cdwords++] = 0;
1517         ctx->pm4[ctx->pm4_cdwords++] = (1 << 29) | (0 << 24);
1518         ctx->pm4[ctx->pm4_cdwords++] = ctx->radeon->fence;
1519         ctx->pm4[ctx->pm4_cdwords++] = 0;
1520         ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1521         ctx->pm4[ctx->pm4_cdwords++] = 0;
1522         r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], ctx->radeon->fence_bo);
1523
1524 #if 1
1525         /* emit cs */
1526         drmib.num_chunks = 2;
1527         drmib.chunks = (uint64_t)(uintptr_t)chunk_array;
1528         chunks[0].chunk_id = RADEON_CHUNK_ID_IB;
1529         chunks[0].length_dw = ctx->pm4_cdwords;
1530         chunks[0].chunk_data = (uint64_t)(uintptr_t)ctx->pm4;
1531         chunks[1].chunk_id = RADEON_CHUNK_ID_RELOCS;
1532         chunks[1].length_dw = ctx->creloc * sizeof(struct r600_reloc) / 4;
1533         chunks[1].chunk_data = (uint64_t)(uintptr_t)ctx->reloc;
1534         chunk_array[0] = (uint64_t)(uintptr_t)&chunks[0];
1535         chunk_array[1] = (uint64_t)(uintptr_t)&chunks[1];
1536         r = drmCommandWriteRead(ctx->radeon->fd, DRM_RADEON_CS, &drmib,
1537                                 sizeof(struct drm_radeon_cs));
1538 #else
1539         *ctx->radeon->cfence = ctx->radeon->fence;
1540 #endif
1541
1542         r600_context_update_fenced_list(ctx);
1543
1544         fence = ctx->radeon->fence + 1;
1545         if (fence < ctx->radeon->fence) {
1546                 /* wrap around */
1547                 fence = 1;
1548                 r600_context_fence_wraparound(ctx, fence);
1549         }
1550         ctx->radeon->fence = fence;
1551
1552         /* restart */
1553         for (int i = 0; i < ctx->creloc; i++) {
1554                 ctx->bo[i]->reloc = NULL;
1555                 ctx->bo[i]->last_flush = 0;
1556                 radeon_bo_reference(ctx->radeon, &ctx->bo[i], NULL);
1557         }
1558         ctx->creloc = 0;
1559         ctx->pm4_dirty_cdwords = 0;
1560         ctx->pm4_cdwords = 0;
1561         ctx->flags = 0;
1562
1563         r600_init_cs(ctx);
1564
1565         /* resume queries */
1566         r600_context_queries_resume(ctx);
1567
1568         /* set all valid group as dirty so they get reemited on
1569          * next draw command
1570          */
1571         LIST_FOR_EACH_ENTRY(enable_block, &ctx->enable_list, enable_list) {
1572                 if (!(enable_block->flags & BLOCK_FLAG_RESOURCE)) {
1573                         if(!(enable_block->status & R600_BLOCK_STATUS_DIRTY)) {
1574                                 LIST_ADDTAIL(&enable_block->list,&ctx->dirty);
1575                                 enable_block->status |= R600_BLOCK_STATUS_DIRTY;
1576                         }
1577                 } else {
1578                         if(!(enable_block->status & R600_BLOCK_STATUS_RESOURCE_DIRTY)) {
1579                                 LIST_ADDTAIL(&enable_block->list,&ctx->resource_dirty);
1580                                 enable_block->status |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
1581                         }
1582                 }
1583                 ctx->pm4_dirty_cdwords += enable_block->pm4_ndwords +
1584                         enable_block->pm4_flush_ndwords;
1585                 enable_block->nreg_dirty = enable_block->nreg;
1586         }
1587 }
1588
1589 void r600_context_emit_fence(struct r600_context *ctx, struct r600_bo *fence_bo, unsigned offset, unsigned value)
1590 {
1591         unsigned ndwords = 10;
1592
1593         if (((ctx->pm4_dirty_cdwords + ndwords + ctx->pm4_cdwords) > ctx->pm4_ndwords) ||
1594             (ctx->creloc >= (ctx->nreloc - 1))) {
1595                 /* need to flush */
1596                 r600_context_flush(ctx);
1597         }
1598
1599         ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
1600         ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
1601         ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
1602         ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
1603         ctx->pm4[ctx->pm4_cdwords++] = offset << 2;             /* ADDRESS_LO */
1604         ctx->pm4[ctx->pm4_cdwords++] = (1 << 29) | (0 << 24);   /* DATA_SEL | INT_EN | ADDRESS_HI */
1605         ctx->pm4[ctx->pm4_cdwords++] = value;                   /* DATA_LO */
1606         ctx->pm4[ctx->pm4_cdwords++] = 0;                       /* DATA_HI */
1607         ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1608         ctx->pm4[ctx->pm4_cdwords++] = 0;
1609         r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], fence_bo);
1610 }
1611
1612 void r600_context_dump_bof(struct r600_context *ctx, const char *file)
1613 {
1614         bof_t *bcs, *blob, *array, *bo, *size, *handle, *device_id, *root;
1615         unsigned i;
1616
1617         root = device_id = bcs = blob = array = bo = size = handle = NULL;
1618         root = bof_object();
1619         if (root == NULL)
1620                 goto out_err;
1621         device_id = bof_int32(ctx->radeon->device);
1622         if (device_id == NULL)
1623                 goto out_err;
1624         if (bof_object_set(root, "device_id", device_id))
1625                 goto out_err;
1626         bof_decref(device_id);
1627         device_id = NULL;
1628         /* dump relocs */
1629         blob = bof_blob(ctx->creloc * 16, ctx->reloc);
1630         if (blob == NULL)
1631                 goto out_err;
1632         if (bof_object_set(root, "reloc", blob))
1633                 goto out_err;
1634         bof_decref(blob);
1635         blob = NULL;
1636         /* dump cs */
1637         blob = bof_blob(ctx->pm4_cdwords * 4, ctx->pm4);
1638         if (blob == NULL)
1639                 goto out_err;
1640         if (bof_object_set(root, "pm4", blob))
1641                 goto out_err;
1642         bof_decref(blob);
1643         blob = NULL;
1644         /* dump bo */
1645         array = bof_array();
1646         if (array == NULL)
1647                 goto out_err;
1648         for (i = 0; i < ctx->creloc; i++) {
1649                 struct radeon_bo *rbo = ctx->bo[i];
1650                 bo = bof_object();
1651                 if (bo == NULL)
1652                         goto out_err;
1653                 size = bof_int32(rbo->size);
1654                 if (size == NULL)
1655                         goto out_err;
1656                 if (bof_object_set(bo, "size", size))
1657                         goto out_err;
1658                 bof_decref(size);
1659                 size = NULL;
1660                 handle = bof_int32(rbo->handle);
1661                 if (handle == NULL)
1662                         goto out_err;
1663                 if (bof_object_set(bo, "handle", handle))
1664                         goto out_err;
1665                 bof_decref(handle);
1666                 handle = NULL;
1667                 radeon_bo_map(ctx->radeon, rbo);
1668                 blob = bof_blob(rbo->size, rbo->data);
1669                 radeon_bo_unmap(ctx->radeon, rbo);
1670                 if (blob == NULL)
1671                         goto out_err;
1672                 if (bof_object_set(bo, "data", blob))
1673                         goto out_err;
1674                 bof_decref(blob);
1675                 blob = NULL;
1676                 if (bof_array_append(array, bo))
1677                         goto out_err;
1678                 bof_decref(bo);
1679                 bo = NULL;
1680         }
1681         if (bof_object_set(root, "bo", array))
1682                 goto out_err;
1683         bof_dump_file(root, file);
1684 out_err:
1685         bof_decref(blob);
1686         bof_decref(array);
1687         bof_decref(bo);
1688         bof_decref(size);
1689         bof_decref(handle);
1690         bof_decref(device_id);
1691         bof_decref(root);
1692 }
1693
1694 static boolean r600_query_result(struct r600_context *ctx, struct r600_query *query, boolean wait)
1695 {
1696         u64 start, end;
1697         u32 *results;
1698         int i;
1699         int size;
1700
1701         if (wait)
1702                 results = r600_bo_map(ctx->radeon, query->buffer, PB_USAGE_CPU_READ, NULL);
1703         else
1704                 results = r600_bo_map(ctx->radeon, query->buffer, PB_USAGE_DONTBLOCK | PB_USAGE_CPU_READ, NULL);
1705         if (!results)
1706                 return FALSE;
1707
1708         /* query->num_results contains how many dwords were used for the query */
1709         size = query->num_results;
1710         for (i = 0; i < size; i += 4) {
1711                 start = (u64)results[i] | (u64)results[i + 1] << 32;
1712                 end = (u64)results[i + 2] | (u64)results[i + 3] << 32;
1713                 if (((start & 0x8000000000000000UL) && (end & 0x8000000000000000UL))
1714                     || query->type == PIPE_QUERY_TIME_ELAPSED) {
1715                         query->result += end - start;
1716                 }
1717         }
1718         r600_bo_unmap(ctx->radeon, query->buffer);
1719         query->num_results = 0;
1720
1721         return TRUE;
1722 }
1723
1724 void r600_query_begin(struct r600_context *ctx, struct r600_query *query)
1725 {
1726         unsigned required_space;
1727         int num_backends = r600_get_num_backends(ctx->radeon);
1728
1729         /* query request needs 6/8 dwords for begin + 6/8 dwords for end */
1730         if (query->type == PIPE_QUERY_TIME_ELAPSED)
1731                 required_space = 16;
1732         else
1733                 required_space = 12;
1734
1735         if ((required_space + ctx->pm4_cdwords) > ctx->pm4_ndwords) {
1736                 /* need to flush */
1737                 r600_context_flush(ctx);
1738         }
1739
1740         /* if query buffer is full force a flush */
1741         if (query->num_results*4 >= query->buffer_size - 16) {
1742                 r600_context_flush(ctx);
1743                 r600_query_result(ctx, query, TRUE);
1744         }
1745
1746         if (query->type == PIPE_QUERY_OCCLUSION_COUNTER &&
1747             num_backends > 0) {
1748                 /* as per info on ZPASS the driver must set the unusued DB top bits */
1749                 u32 *results;
1750                 int i;
1751
1752                 results = r600_bo_map(ctx->radeon, query->buffer, PB_USAGE_DONTBLOCK | PB_USAGE_CPU_WRITE, NULL);
1753                 if (results) {
1754                         memset(results + (query->num_results * 4), 0, ctx->max_db * 4 * 4);
1755
1756                         for (i = num_backends; i < ctx->max_db; i++) {
1757                                 results[(i * 4)+1] = 0x80000000;
1758                                 results[(i * 4)+3] = 0x80000000;
1759                         }
1760                         r600_bo_unmap(ctx->radeon, query->buffer);
1761                 }
1762         }
1763
1764         /* emit begin query */
1765         if (query->type == PIPE_QUERY_TIME_ELAPSED) {
1766                 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
1767                 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
1768                 ctx->pm4[ctx->pm4_cdwords++] = query->num_results*4 + r600_bo_offset(query->buffer);
1769                 ctx->pm4[ctx->pm4_cdwords++] = (3 << 29);
1770                 ctx->pm4[ctx->pm4_cdwords++] = 0;
1771                 ctx->pm4[ctx->pm4_cdwords++] = 0;
1772         } else {
1773                 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
1774                 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
1775                 ctx->pm4[ctx->pm4_cdwords++] = query->num_results*4 + r600_bo_offset(query->buffer);
1776                 ctx->pm4[ctx->pm4_cdwords++] = 0;
1777         }
1778         ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1779         ctx->pm4[ctx->pm4_cdwords++] = 0;
1780         r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], query->buffer);
1781
1782         query->state |= R600_QUERY_STATE_STARTED;
1783         query->state ^= R600_QUERY_STATE_ENDED;
1784         ctx->num_query_running++;
1785 }
1786
1787 void r600_query_end(struct r600_context *ctx, struct r600_query *query)
1788 {
1789         /* emit begin query */
1790         if (query->type == PIPE_QUERY_TIME_ELAPSED) {
1791                 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
1792                 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
1793                 ctx->pm4[ctx->pm4_cdwords++] = query->num_results*4 + 8 + r600_bo_offset(query->buffer);
1794                 ctx->pm4[ctx->pm4_cdwords++] = (3 << 29);
1795                 ctx->pm4[ctx->pm4_cdwords++] = 0;
1796                 ctx->pm4[ctx->pm4_cdwords++] = 0;
1797         } else {
1798                 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
1799                 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
1800                 ctx->pm4[ctx->pm4_cdwords++] = query->num_results*4 + 8 + r600_bo_offset(query->buffer);
1801                 ctx->pm4[ctx->pm4_cdwords++] = 0;
1802         }
1803         ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1804         ctx->pm4[ctx->pm4_cdwords++] = 0;
1805         r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], query->buffer);
1806
1807         query->num_results += 4 * (query->type == PIPE_QUERY_OCCLUSION_COUNTER ? ctx->max_db : 1);
1808         query->state ^= R600_QUERY_STATE_STARTED;
1809         query->state |= R600_QUERY_STATE_ENDED;
1810         ctx->num_query_running--;
1811 }
1812
1813 void r600_query_predication(struct r600_context *ctx, struct r600_query *query, int operation,
1814                             int flag_wait)
1815 {
1816         ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SET_PREDICATION, 1, 0);
1817
1818         if (operation == PREDICATION_OP_CLEAR) {
1819                 ctx->pm4[ctx->pm4_cdwords++] = 0;
1820                 ctx->pm4[ctx->pm4_cdwords++] = PRED_OP(PREDICATION_OP_CLEAR);
1821         } else {
1822                 int results_base = query->num_results - (4 * ctx->max_db);
1823
1824                 if (results_base < 0)
1825                         results_base = 0;
1826
1827                 ctx->pm4[ctx->pm4_cdwords++] = results_base*4 + r600_bo_offset(query->buffer);
1828                 ctx->pm4[ctx->pm4_cdwords++] = PRED_OP(operation) | (flag_wait ? PREDICATION_HINT_WAIT : PREDICATION_HINT_NOWAIT_DRAW) | PREDICATION_DRAW_VISIBLE;
1829                 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1830                 ctx->pm4[ctx->pm4_cdwords++] = 0;
1831                 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], query->buffer);
1832         }
1833 }
1834
1835 struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type)
1836 {
1837         struct r600_query *query;
1838
1839         if (query_type != PIPE_QUERY_OCCLUSION_COUNTER && query_type != PIPE_QUERY_TIME_ELAPSED)
1840                 return NULL;
1841
1842         query = calloc(1, sizeof(struct r600_query));
1843         if (query == NULL)
1844                 return NULL;
1845
1846         query->type = query_type;
1847         query->buffer_size = 4096;
1848
1849         /* As of GL4, query buffers are normally read by the CPU after
1850          * being written by the gpu, hence staging is probably a good
1851          * usage pattern.
1852          */
1853         query->buffer = r600_bo(ctx->radeon, query->buffer_size, 1, 0,
1854                                 PIPE_USAGE_STAGING);
1855         if (!query->buffer) {
1856                 free(query);
1857                 return NULL;
1858         }
1859
1860         LIST_ADDTAIL(&query->list, &ctx->query_list);
1861
1862         return query;
1863 }
1864
1865 void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query)
1866 {
1867         r600_bo_reference(ctx->radeon, &query->buffer, NULL);
1868         LIST_DELINIT(&query->list);
1869         free(query);
1870 }
1871
1872 boolean r600_context_query_result(struct r600_context *ctx,
1873                                 struct r600_query *query,
1874                                 boolean wait, void *vresult)
1875 {
1876         uint64_t *result = (uint64_t*)vresult;
1877
1878         if (query->num_results) {
1879                 r600_context_flush(ctx);
1880         }
1881         if (!r600_query_result(ctx, query, wait))
1882                 return FALSE;
1883         if (query->type == PIPE_QUERY_TIME_ELAPSED)
1884                 *result = (1000000*query->result)/r600_get_clock_crystal_freq(ctx->radeon);
1885         else
1886                 *result = query->result;
1887         query->result = 0;
1888         return TRUE;
1889 }
1890
1891 void r600_context_queries_suspend(struct r600_context *ctx)
1892 {
1893         struct r600_query *query;
1894
1895         LIST_FOR_EACH_ENTRY(query, &ctx->query_list, list) {
1896                 if (query->state & R600_QUERY_STATE_STARTED) {
1897                         r600_query_end(ctx, query);
1898                         query->state |= R600_QUERY_STATE_SUSPENDED;
1899                 }
1900         }
1901 }
1902
1903 void r600_context_queries_resume(struct r600_context *ctx)
1904 {
1905         struct r600_query *query;
1906
1907         LIST_FOR_EACH_ENTRY(query, &ctx->query_list, list) {
1908                 if (query->state & R600_QUERY_STATE_SUSPENDED) {
1909                         r600_query_begin(ctx, query);
1910                         query->state ^= R600_QUERY_STATE_SUSPENDED;
1911                 }
1912         }
1913 }