2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <util/u_double_list.h>
34 #include <util/u_inlines.h>
35 #include "util/u_hash_table.h"
36 #include <os/os_thread.h>
39 #define PKT_COUNT_C 0xC000FFFF
40 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
50 enum chip_class chip_class;
51 struct r600_tiling_info tiling_info;
52 struct r600_bomgr *bomgr;
55 struct r600_bo *fence_bo;
56 unsigned clock_crystal_freq;
57 unsigned num_backends;
58 unsigned minor_version;
60 /* List of buffer handles and its mutex. */
61 struct util_hash_table *bo_handles;
62 pipe_mutex bo_handles_mutex;
65 #define REG_FLAG_NEED_BO 1
66 #define REG_FLAG_DIRTY_ALWAYS 2
67 #define REG_FLAG_RV6XX_SBU 4
68 #define REG_FLAG_NOT_R600 8
77 #define BO_BOUND_TEXTURE 1
79 struct pipe_reference reference;
85 struct list_head fencedlist;
87 struct r600_context *ctx;
89 struct r600_reloc *reloc;
97 struct pipe_reference reference;
99 unsigned tiling_flags;
100 unsigned kernel_pitch;
102 struct radeon_bo *bo;
105 struct list_head list;
114 struct radeon *radeon;
117 struct list_head delayed;
118 unsigned num_delayed;
124 struct radeon *r600_new(int fd, unsigned device);
125 void r600_delete(struct radeon *r600);
130 unsigned radeon_family_from_device(unsigned device);
135 struct radeon_bo *radeon_bo(struct radeon *radeon, unsigned handle,
136 unsigned size, unsigned alignment, unsigned initial_domain);
137 void radeon_bo_reference(struct radeon *radeon, struct radeon_bo **dst,
138 struct radeon_bo *src);
139 int radeon_bo_wait(struct radeon *radeon, struct radeon_bo *bo);
140 int radeon_bo_busy(struct radeon *radeon, struct radeon_bo *bo, uint32_t *domain);
141 int radeon_bo_fencelist(struct radeon *radeon, struct radeon_bo **bolist, uint32_t num_bo);
142 int radeon_bo_get_tiling_flags(struct radeon *radeon,
143 struct radeon_bo *bo,
144 uint32_t *tiling_flags,
146 int radeon_bo_get_name(struct radeon *radeon,
147 struct radeon_bo *bo,
149 int radeon_bo_fixed_map(struct radeon *radeon, struct radeon_bo *bo);
154 int r600_context_init_fence(struct r600_context *ctx);
155 void r600_context_bo_reloc(struct r600_context *ctx, u32 *pm4, struct r600_bo *rbo);
156 void r600_context_bo_flush(struct r600_context *ctx, unsigned flush_flags,
157 unsigned flush_mask, struct r600_bo *rbo);
158 struct r600_bo *r600_context_reg_bo(struct r600_context *ctx, unsigned offset);
159 int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg,
160 unsigned opcode, unsigned offset_base);
161 void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset);
162 void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block);
163 void r600_context_dirty_block(struct r600_context *ctx, struct r600_block *block,
164 int dirty, int index);
165 int r600_setup_block_table(struct r600_context *ctx);
166 void r600_context_reg(struct r600_context *ctx,
167 unsigned offset, unsigned value,
172 void r600_bo_destroy(struct radeon *radeon, struct r600_bo *bo);
177 struct r600_bomgr *r600_bomgr_create(struct radeon *radeon, unsigned usecs);
178 void r600_bomgr_destroy(struct r600_bomgr *mgr);
179 bool r600_bomgr_bo_destroy(struct r600_bomgr *mgr, struct r600_bo *bo);
180 void r600_bomgr_bo_init(struct r600_bomgr *mgr, struct r600_bo *bo);
181 struct r600_bo *r600_bomgr_bo_create(struct r600_bomgr *mgr,
191 /* each range covers 9 bits of dword space = 512 dwords = 2k bytes */
192 /* there is a block entry for each register so 512 blocks */
193 /* we have no registers to read/write below 0x8000 (0x2000 in dw space) */
194 /* we use some fake offsets at 0x40000 to do evergreen sampler borders so take 0x42000 as a max bound*/
195 #define RANGE_OFFSET_START 0x8000
197 #define NUM_RANGES (0x42000 - RANGE_OFFSET_START) / (4 << HASH_SHIFT) /* 128 << 9 = 64k */
199 #define CTX_RANGE_ID(ctx, offset) ((((offset - RANGE_OFFSET_START) >> 2) >> HASH_SHIFT) & 255)
200 #define CTX_BLOCK_ID(ctx, offset) (((offset - RANGE_OFFSET_START) >> 2) & ((1 << HASH_SHIFT) - 1))
205 static inline int radeon_bo_map(struct radeon *radeon, struct radeon_bo *bo)
207 if (bo->map_count == 0 && !bo->data)
208 return radeon_bo_fixed_map(radeon, bo);
213 static inline void radeon_bo_unmap(struct radeon *radeon, struct radeon_bo *bo)
216 assert(bo->map_count >= 0);
222 static inline bool fence_is_after(unsigned fence, unsigned ofence)
224 /* handle wrap around */
225 if (fence < 0x80000000 && ofence > 0x80000000)