2 * Copyright © 2009 Corbin Simpson
3 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
29 * Corbin Simpson <MostAwesomeDude@gmail.com>
30 * Joakim Sindholt <opensource@zhasha.com>
31 * Marek Olšák <maraeo@gmail.com>
34 #include "radeon_drm_bo.h"
35 #include "radeon_drm_cs.h"
36 #include "radeon_drm_public.h"
38 #include "pipebuffer/pb_bufmgr.h"
39 #include "util/u_memory.h"
45 * this are copy from radeon_drm, once an updated libdrm is released
46 * we should bump configure.ac requirement for it and remove the following
49 #ifndef RADEON_INFO_TILING_CONFIG
50 #define RADEON_INFO_TILING_CONFIG 6
53 #ifndef RADEON_INFO_WANT_HYPERZ
54 #define RADEON_INFO_WANT_HYPERZ 7
57 #ifndef RADEON_INFO_WANT_CMASK
58 #define RADEON_INFO_WANT_CMASK 8
61 #ifndef RADEON_INFO_CLOCK_CRYSTAL_FREQ
62 #define RADEON_INFO_CLOCK_CRYSTAL_FREQ 9
65 #ifndef RADEON_INFO_NUM_BACKENDS
66 #define RADEON_INFO_NUM_BACKENDS 0xa
69 #ifndef RADEON_INFO_NUM_TILE_PIPES
70 #define RADEON_INFO_NUM_TILE_PIPES 0xb
73 #ifndef RADEON_INFO_BACKEND_MAP
74 #define RADEON_INFO_BACKEND_MAP 0xd
77 #ifndef RADEON_INFO_VA_START
78 /* virtual address start, va < start are reserved by the kernel */
79 #define RADEON_INFO_VA_START 0x0e
80 /* maximum size of ib using the virtual memory cs */
81 #define RADEON_INFO_IB_VM_MAX_SIZE 0x0f
85 /* Enable/disable feature access for one command stream.
86 * If enable == TRUE, return TRUE on success.
87 * Otherwise, return FALSE.
89 * We basically do the same thing kernel does, because we have to deal
90 * with multiple contexts (here command streams) backed by one winsys. */
91 static boolean radeon_set_fd_access(struct radeon_drm_cs *applier,
92 struct radeon_drm_cs **owner,
94 unsigned request, boolean enable)
96 struct drm_radeon_info info;
97 unsigned value = enable ? 1 : 0;
99 memset(&info, 0, sizeof(info));
101 pipe_mutex_lock(*mutex);
103 /* Early exit if we are sure the request will fail. */
106 pipe_mutex_unlock(*mutex);
110 if (*owner != applier) {
111 pipe_mutex_unlock(*mutex);
116 /* Pass through the request to the kernel. */
117 info.value = (unsigned long)&value;
118 info.request = request;
119 if (drmCommandWriteRead(applier->ws->fd, DRM_RADEON_INFO,
120 &info, sizeof(info)) != 0) {
121 pipe_mutex_unlock(*mutex);
125 /* Update the rights in the winsys. */
129 fprintf(stderr, "radeon: Acquired Hyper-Z.\n");
130 pipe_mutex_unlock(*mutex);
135 fprintf(stderr, "radeon: Released Hyper-Z.\n");
138 pipe_mutex_unlock(*mutex);
142 static boolean radeon_get_drm_value(int fd, unsigned request,
143 const char *errname, uint32_t *out)
145 struct drm_radeon_info info;
148 memset(&info, 0, sizeof(info));
150 info.value = (unsigned long)out;
151 info.request = request;
153 retval = drmCommandWriteRead(fd, DRM_RADEON_INFO, &info, sizeof(info));
156 fprintf(stderr, "radeon: Failed to get %s, error number %d\n",
164 /* Helper function to do the ioctls needed for setup and init. */
165 static boolean do_winsys_init(struct radeon_drm_winsys *ws)
167 struct drm_radeon_gem_info gem_info;
169 drmVersionPtr version;
171 memset(&gem_info, 0, sizeof(gem_info));
173 /* We do things in a specific order here.
175 * DRM version first. We need to be sure we're running on a KMS chipset.
176 * This is also for some features.
178 * Then, the PCI ID. This is essential and should return usable numbers
179 * for all Radeons. If this fails, we probably got handed an FD for some
182 * The GEM info is actually bogus on the kernel side, as well as our side
183 * (see radeon_gem_info_ioctl in radeon_gem.c) but that's alright because
184 * we don't actually use the info for anything yet.
186 * The GB and Z pipe requests should always succeed, but they might not
187 * return sensical values for all chipsets, but that's alright because
188 * the pipe drivers already know that.
191 /* Get DRM version. */
192 version = drmGetVersion(ws->fd);
193 if (version->version_major != 2 ||
194 version->version_minor < 3) {
195 fprintf(stderr, "%s: DRM version is %d.%d.%d but this driver is "
196 "only compatible with 2.3.x (kernel 2.6.34) or later.\n",
198 version->version_major,
199 version->version_minor,
200 version->version_patchlevel);
201 drmFreeVersion(version);
205 ws->info.drm_major = version->version_major;
206 ws->info.drm_minor = version->version_minor;
207 ws->info.drm_patchlevel = version->version_patchlevel;
208 drmFreeVersion(version);
211 if (!radeon_get_drm_value(ws->fd, RADEON_INFO_DEVICE_ID, "PCI ID",
216 switch (ws->info.pci_id) {
217 #define CHIPSET(pci_id, name, family) case pci_id:
218 #include "pci_ids/r300_pci_ids.h"
223 #define CHIPSET(pci_id, name, family) case pci_id:
224 #include "pci_ids/r600_pci_ids.h"
229 #define CHIPSET(pci_id, name, family) case pci_id:
230 #include "pci_ids/radeonsi_pci_ids.h"
236 fprintf(stderr, "radeon: Invalid PCI ID.\n");
241 retval = drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_INFO,
242 &gem_info, sizeof(gem_info));
244 fprintf(stderr, "radeon: Failed to get MM info, error number %d\n",
248 ws->info.gart_size = gem_info.gart_size;
249 ws->info.vram_size = gem_info.vram_size;
251 ws->num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
253 /* Generation-specific queries. */
254 if (ws->gen == R300) {
255 if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_GB_PIPES,
257 &ws->info.r300_num_gb_pipes))
260 if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_Z_PIPES,
262 &ws->info.r300_num_z_pipes))
265 else if (ws->gen >= R600) {
266 if (ws->info.drm_minor >= 9 &&
267 !radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BACKENDS,
269 &ws->info.r600_num_backends))
272 /* get the GPU counter frequency, failure is not fatal */
273 radeon_get_drm_value(ws->fd, RADEON_INFO_CLOCK_CRYSTAL_FREQ, NULL,
274 &ws->info.r600_clock_crystal_freq);
276 radeon_get_drm_value(ws->fd, RADEON_INFO_TILING_CONFIG, NULL,
277 &ws->info.r600_tiling_config);
279 if (ws->info.drm_minor >= 11) {
280 radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_TILE_PIPES, NULL,
281 &ws->info.r600_num_tile_pipes);
283 if (radeon_get_drm_value(ws->fd, RADEON_INFO_BACKEND_MAP, NULL,
284 &ws->info.r600_backend_map))
285 ws->info.r600_backend_map_valid = TRUE;
288 ws->info.r600_virtual_address = FALSE;
289 if (ws->info.drm_minor >= 13) {
290 ws->info.r600_virtual_address = TRUE;
291 if (!radeon_get_drm_value(ws->fd, RADEON_INFO_VA_START, NULL,
292 &ws->info.r600_va_start))
293 ws->info.r600_virtual_address = FALSE;
294 if (!radeon_get_drm_value(ws->fd, RADEON_INFO_IB_VM_MAX_SIZE, NULL,
295 &ws->info.r600_ib_vm_max_size))
296 ws->info.r600_virtual_address = FALSE;
299 ws->info.r600_has_streamout = ws->info.drm_minor >= 13;
305 static void radeon_winsys_destroy(struct radeon_winsys *rws)
307 struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
309 pipe_mutex_destroy(ws->hyperz_owner_mutex);
310 pipe_mutex_destroy(ws->cmask_owner_mutex);
312 ws->cman->destroy(ws->cman);
313 ws->kman->destroy(ws->kman);
314 if (ws->gen == R600) {
315 radeon_surface_manager_free(ws->surf_man);
320 static void radeon_query_info(struct radeon_winsys *rws,
321 struct radeon_info *info)
323 *info = ((struct radeon_drm_winsys *)rws)->info;
326 static boolean radeon_cs_request_feature(struct radeon_winsys_cs *rcs,
327 enum radeon_feature_id fid,
330 struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
333 case RADEON_FID_R300_HYPERZ_ACCESS:
334 if (debug_get_bool_option("RADEON_HYPERZ", FALSE)) {
335 return radeon_set_fd_access(cs, &cs->ws->hyperz_owner,
336 &cs->ws->hyperz_owner_mutex,
337 RADEON_INFO_WANT_HYPERZ, enable);
342 case RADEON_FID_R300_CMASK_ACCESS:
343 if (debug_get_bool_option("RADEON_CMASK", FALSE)) {
344 return radeon_set_fd_access(cs, &cs->ws->cmask_owner,
345 &cs->ws->cmask_owner_mutex,
346 RADEON_INFO_WANT_CMASK, enable);
354 static int radeon_drm_winsys_surface_init(struct radeon_winsys *rws,
355 struct radeon_surface *surf)
357 struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
359 return radeon_surface_init(ws->surf_man, surf);
362 static int radeon_drm_winsys_surface_best(struct radeon_winsys *rws,
363 struct radeon_surface *surf)
365 struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
367 return radeon_surface_best(ws->surf_man, surf);
370 struct radeon_winsys *radeon_drm_winsys_create(int fd)
372 struct radeon_drm_winsys *ws = CALLOC_STRUCT(radeon_drm_winsys);
379 if (!do_winsys_init(ws))
382 /* Create managers. */
383 ws->kman = radeon_bomgr_create(ws);
386 ws->cman = pb_cache_manager_create(ws->kman, 1000000);
390 /* FIXME check for libdrm version ?? */
391 if (ws->gen == R600) {
392 ws->surf_man = radeon_surface_manager_new(fd);
398 ws->base.destroy = radeon_winsys_destroy;
399 ws->base.query_info = radeon_query_info;
400 ws->base.cs_request_feature = radeon_cs_request_feature;
401 ws->base.surface_init = radeon_drm_winsys_surface_init;
402 ws->base.surface_best = radeon_drm_winsys_surface_best;
404 radeon_bomgr_init_functions(ws);
405 radeon_drm_cs_init_functions(ws);
407 pipe_mutex_init(ws->hyperz_owner_mutex);
408 pipe_mutex_init(ws->cmask_owner_mutex);
414 ws->cman->destroy(ws->cman);
416 ws->kman->destroy(ws->kman);
418 radeon_surface_manager_free(ws->surf_man);