2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Peng Chen <peng.c.chen@intel.com>
30 #ifndef GEN10_HCP_COMMON_H
31 #define GEN10_HCP_COMMON_H
33 #define GEN10_MMIO_HCP_ENC_BITSTREAM_BYTECOUNT_FRAME_OFFSET 0x1E9A0
34 #define GEN10_MMIO_HCP_ENC_BITSTREAM_BYTECOUNT_FRAME_NO_HEADER_OFFSET 0x1E9A4
35 #define GEN10_MMIO_HCP_ENC_BITSTREAM_SE_BITCOUNT_FRAME_OFFSET 0x1E9A8
36 #define GEN10_MMIO_HCP_ENC_IMAGE_STATUS_MASK_OFFSET 0x1E9B8
37 #define GEn10_MMIO_HCP_ENC_IMAGE_STATUS_CTRL_OFFSET 0x1E9BC
38 #define GEN10_MMIO_HCP_ENC_QP_STATE_OFFSET 0x1E9C0
40 #define GEN10_HCP_ENCODE 1
41 #define GEN10_HCP_DECODE 0
43 #define GEN10_HCP_HEVC_CODEC 0
44 #define GEN10_HCP_VP9_CODEC 1
46 typedef struct _gen10_hcp_pipe_mode_select_param {
48 uint32_t codec_select : 1;
49 uint32_t deblocker_stream_enabled : 1;
50 uint32_t pak_streamout_enabled : 1;
51 uint32_t pic_error_stat_enabled : 1;
52 uint32_t reserved0 : 1;
53 uint32_t codec_standard_select : 3;
54 uint32_t sao_first_pass : 1;
55 uint32_t advanced_brc_enabled : 1;
56 uint32_t vdenc_mode : 1;
57 uint32_t rdoq_enabled : 1;
58 uint32_t pak_frame_level_streamout_enabled : 1;
59 uint32_t reserved1 : 2;
60 uint32_t pipe_work_mode : 2;
61 uint32_t reserved2 : 15;
64 uint32_t media_reset_counter;
65 uint32_t pic_error_report_id;
67 } gen10_hcp_pipe_mode_select_param;
69 #define GEN10_HCP_DECODE_SURFACE_ID 0
70 #define GEN10_HCP_INPUT_SURFACE_ID 1
71 #define GEN10_HCP_PREV_SURFACE_ID 2
72 #define GEN10_HCP_GOLD_SURFACE_ID 3
73 #define GEN10_HCP_ALT_SURFACE_ID 4
74 #define GEN10_HCP_REF_SURFACE_ID 5
76 typedef struct _gen10_hcp_surface_state_param {
78 uint32_t surface_pitch : 17;
79 uint32_t reserved : 11;
80 uint32_t surface_id : 4;
84 uint32_t y_cb_offset : 15;
85 uint32_t reserved : 13;
86 uint32_t surface_format : 4;
90 uint32_t default_alpha : 16;
91 uint32_t y_cr_offset : 16;
95 uint32_t auxilary_index : 11;
96 uint32_t reserved0 : 1;
97 uint32_t memory_compression : 1;
98 uint32_t reserved1 : 18;
100 } gen10_hcp_surface_state_param;
102 typedef struct _gen10_hcp_pipe_buf_addr_state_param {
103 struct i965_gpe_resource *reconstructed;
104 struct i965_gpe_resource *deblocking_filter_line;
105 struct i965_gpe_resource *deblocking_filter_tile_line;
106 struct i965_gpe_resource *deblocking_filter_tile_column;
107 struct i965_gpe_resource *metadata_line;
108 struct i965_gpe_resource *metadata_tile_line;
109 struct i965_gpe_resource *metadata_tile_column;
110 struct i965_gpe_resource *sao_line;
111 struct i965_gpe_resource *sao_tile_line;
112 struct i965_gpe_resource *sao_tile_column;
113 struct i965_gpe_resource *current_motion_vector_temporal;
114 struct i965_gpe_resource *reference_picture[8];
115 struct i965_gpe_resource *uncompressed_picture;
116 struct i965_gpe_resource *streamout_data_destination;
117 struct i965_gpe_resource *picture_status;
118 struct i965_gpe_resource *ildb_streamout;
119 struct i965_gpe_resource *collocated_motion_vector_temporal[8];
120 struct i965_gpe_resource *vp9_probability;
121 struct i965_gpe_resource *vp9_segmentid;
122 struct i965_gpe_resource *vp9_hvd_line_rowstore;
123 struct i965_gpe_resource *vp9_hvd_time_rowstore;
124 struct i965_gpe_resource *sao_streamout_data_destination;
125 struct i965_gpe_resource *frame_statics_streamout_data_destination;
126 struct i965_gpe_resource *sse_source_pixel_rowstore;
127 } gen10_hcp_pipe_buf_addr_state_param;
129 typedef struct _gen10_hcp_ind_obj_base_addr_state_param {
130 struct i965_gpe_resource *ind_cu_obj_bse;
132 uint32_t ind_cu_obj_bse_offset;
134 struct i965_gpe_resource *ind_pak_bse;
136 uint32_t ind_pak_bse_offset;
137 uint32_t ind_pak_bse_upper;
138 } gen10_hcp_ind_obj_base_addr_state_param;
140 typedef struct _gen10_hcp_pic_state_param {
142 uint32_t frame_width_in_cu_minus1 : 11;
143 uint32_t reserved0 : 4;
144 uint32_t pak_transform_skip : 1;
145 uint32_t frame_height_in_cu_minus1 : 11;
146 uint32_t reserved1 : 5;
150 uint32_t min_cu_size : 2;
151 uint32_t lcu_size : 2;
152 uint32_t min_tu_size : 2;
153 uint32_t max_tu_size : 2;
154 uint32_t min_pcm_size : 2;
155 uint32_t max_pcm_size : 2;
156 uint32_t reserved : 20;
160 uint32_t col_pic_i_only : 1;
161 uint32_t curr_pic_i_only : 1;
162 uint32_t insert_test_flag : 1;
163 uint32_t reserved : 29;
167 uint32_t reserved0 : 3;
168 uint32_t sao_enabled_flag : 1;
169 uint32_t pcm_enabled_flag : 1;
170 uint32_t cu_qp_delta_enabled_flag : 1;
171 uint32_t diff_cu_qp_delta_depth : 2;
173 uint32_t pcm_loop_filter_disable_flag : 1;
174 uint32_t constrained_intra_pred_flag : 1;
175 uint32_t log2_parallel_merge_level_minus2 : 3;
176 uint32_t sign_data_hiding_flag : 1;
177 uint32_t reserved1 : 1;
178 uint32_t loop_filter_across_tiles_enabled_flag : 1;
180 uint32_t entropy_coding_sync_enabled_flag : 1;
181 uint32_t tiles_enabled_flag : 1;
182 uint32_t weighted_bipred_flag : 1;
183 uint32_t weighted_pred_flag : 1;
184 uint32_t field_pic : 1;
185 uint32_t bottom_field : 1;
186 uint32_t transform_skip_enabled_flag : 1;
187 uint32_t amp_enabled_flag : 1;
189 uint32_t reserved2 : 1;
190 uint32_t transquant_bypass_enabled_flag : 1;
191 uint32_t strong_intra_smoothing_enabled_flag : 1;
192 uint32_t cu_pak_structure : 1;
193 uint32_t reserved3 : 4;
197 uint32_t pic_cb_qp_offset : 5;
198 uint32_t pic_cr_qp_offset : 5;
199 uint32_t max_transform_hierarchy_depth_intra : 3;
200 uint32_t max_transform_hierarchy_depth_inter : 3;
202 uint32_t pcm_sample_bit_depth_chroma_minus1 : 4;
203 uint32_t pcm_sample_bit_depth_luma_minus1 : 4;
204 uint32_t bit_depth_chroma_minus8 : 3;
205 uint32_t bit_depth_luma_minus8 : 3;
206 uint32_t reserved : 2;
210 uint32_t lcu_max_bits_allowed : 16;
211 uint32_t non_first_pass_flag : 1;
212 uint32_t reserved0 : 7;
213 uint32_t lcu_max_bits_stats_en : 1;
214 uint32_t frame_sz_over_status_en : 1;
215 uint32_t frame_sz_under_status_en : 1;
216 uint32_t reserved1 : 2;
217 uint32_t load_slice_ptr_flag : 1;
218 uint32_t reserved2 : 2;
222 uint32_t frame_bit_rate_max : 14;
223 uint32_t reserved : 17;
224 uint32_t frame_bit_rate_unit : 1;
228 uint32_t frame_bit_rate_min : 14;
229 uint32_t reserved : 17;
230 uint32_t frame_bit_rate_unit : 1;
234 uint32_t frame_bit_rate_delta_min : 15;
235 uint32_t reserved0 : 1;
236 uint32_t frame_bit_rate_delta_max : 15;
237 uint32_t reserved1 : 1;
241 uint32_t frame_max_delta_qp0 : 8;
242 uint32_t frame_max_delta_qp1 : 8;
243 uint32_t frame_max_delta_qp2 : 8;
244 uint32_t frame_max_delta_qp3 : 8;
248 uint32_t frame_max_delta_qp4 : 8;
249 uint32_t frame_max_delta_qp5 : 8;
250 uint32_t frame_max_delta_qp6 : 8;
251 uint32_t frame_max_delta_qp7 : 8;
255 uint32_t frame_min_delta_qp0 : 8;
256 uint32_t frame_min_delta_qp1 : 8;
257 uint32_t frame_min_delta_qp2 : 8;
258 uint32_t frame_min_delta_qp3 : 8;
262 uint32_t frame_min_delta_qp4 : 8;
263 uint32_t frame_min_delta_qp5 : 8;
264 uint32_t frame_min_delta_qp6 : 8;
265 uint32_t frame_min_delta_qp7 : 8;
269 uint32_t frame_max_range_delta_qp0 : 8;
270 uint32_t frame_max_range_delta_qp1 : 8;
271 uint32_t frame_max_range_delta_qp2 : 8;
272 uint32_t frame_max_range_delta_qp3 : 8;
276 uint32_t frame_max_range_delta_qp4 : 8;
277 uint32_t frame_max_range_delta_qp5 : 8;
278 uint32_t frame_max_range_delta_qp6 : 8;
279 uint32_t frame_max_range_delta_qp7 : 8;
283 uint32_t frame_min_range_delta_qp0 : 8;
284 uint32_t frame_min_range_delta_qp1 : 8;
285 uint32_t frame_min_range_delta_qp2 : 8;
286 uint32_t frame_min_range_delta_qp3 : 8;
290 uint32_t frame_min_range_delta_qp4 : 8;
291 uint32_t frame_min_range_delta_qp5 : 8;
292 uint32_t frame_min_range_delta_qp6 : 8;
293 uint32_t frame_min_range_delta_qp7 : 8;
297 uint32_t min_frame_size : 16;
298 uint32_t reserved : 14;
299 uint32_t min_frame_size_unit : 2;
303 uint32_t fraction_qp_input : 3;
304 uint32_t fraction_qp_offset : 3;
305 uint32_t rho_domain_rc_enabled : 1;
306 uint32_t fraction_qp_adj_enabled : 1;
308 uint32_t rho_domain_frame_qp : 6;
309 uint32_t pak_dyna_slice_mode_enabled : 1;
310 uint32_t no_output_of_prior_pics_flag : 1;
312 uint32_t first_slice_segment_in_pic_flag : 1;
313 uint32_t nal_unit_type_flag : 1;
314 uint32_t slice_pic_parameter_set_id : 6;
316 uint32_t sse_enabled : 1;
317 uint32_t rhoq_enabled : 1;
318 uint32_t lcu_num_in_ssc_mode : 2;
319 uint32_t reserved : 2;
320 uint32_t partial_frame_update : 1;
321 uint32_t temporal_mv_disable : 1;
329 uint32_t slice_size_thr_in_bytes;
333 uint32_t target_slice_size_in_bytes;
337 uint32_t class0_sse_threshold_0 : 16;
338 uint32_t class0_sse_threshold_1 : 16;
342 uint32_t class1_sse_threshold_0 : 16;
343 uint32_t class1_sse_threshold_1 : 16;
347 uint32_t class2_sse_threshold_0 : 16;
348 uint32_t class2_sse_threshold_1 : 16;
352 uint32_t class3_sse_threshold_0 : 16;
353 uint32_t class3_sse_threshold_1 : 16;
357 uint32_t class4_sse_threshold_0 : 16;
358 uint32_t class4_sse_threshold_1 : 16;
362 uint32_t class5_sse_threshold_0 : 16;
363 uint32_t class5_sse_threshold_1 : 16;
367 uint32_t class6_sse_threshold_0 : 16;
368 uint32_t class6_sse_threshold_1 : 16;
372 uint32_t class7_sse_threshold_0 : 16;
373 uint32_t class7_sse_threshold_1 : 16;
375 } gen10_hcp_pic_state_param;
377 typedef struct _gen10_hcp_vp9_pic_state_param {
379 uint32_t frame_width_in_pixels_minus1: 14;
380 uint32_t reserved0: 2;
381 uint32_t frame_height_in_pixels_minus1: 14;
382 uint32_t reserved1: 2;
386 uint32_t frame_type: 1;
387 uint32_t adapt_probabilities_flag: 1;
388 uint32_t intra_only_flag: 1;
389 uint32_t allow_high_precision_mv: 1;
390 uint32_t motion_comp_filter_type: 3;
391 uint32_t ref_frame_sign_bias_last: 1;
392 uint32_t ref_frame_sign_bias_golden: 1;
393 uint32_t ref_frame_sign_bias_altref: 1;
394 uint32_t use_prev_in_find_mv_references: 1;
395 uint32_t hybrid_prediction_mode: 1;
396 uint32_t selectable_tx_mode: 1;
397 uint32_t last_frame_type: 1;
398 uint32_t refresh_frame_context: 1;
399 uint32_t error_resilient_mode: 1;
400 uint32_t frame_parallel_decoding_mode: 1;
401 uint32_t filter_level: 6;
402 uint32_t sharpness_level: 3;
403 uint32_t segmentation_enabled: 1;
404 uint32_t segmentation_update_map: 1;
405 uint32_t segmentation_temporal_update: 1;
406 uint32_t lossless_mode: 1;
407 uint32_t segment_id_streamout_enable: 1;
408 uint32_t segment_id_streamin_enable: 1;
412 uint32_t log2_tile_column: 4;
414 uint32_t log2_tile_row: 2;
416 uint32_t sse_enable: 1;
417 uint32_t chroma_sampling_format: 2;
418 uint32_t bit_depth_minus8: 4;
419 uint32_t profile_level: 4;
423 uint32_t vertical_scale_factor_for_last: 16;
424 uint32_t horizontal_scale_factor_for_last: 16;
428 uint32_t vertical_scale_factor_for_golden: 16;
429 uint32_t horizontal_scale_factor_for_golden: 16;
433 uint32_t vertical_scale_factor_for_altref: 16;
434 uint32_t horizontal_scale_factor_for_altref: 16;
438 uint32_t last_frame_width_in_pixels_minus1: 14;
440 uint32_t last_frame_height_in_pixels_minus1: 14;
445 uint32_t golden_frame_width_in_pixels_minus1: 14;
447 uint32_t golden_frame_height_in_pixels_minus1: 14;
452 uint32_t altref_frame_width_in_pixels_minus1: 14;
454 uint32_t altref_frame_height_in_pixels_minus1: 14;
459 uint32_t uncompressed_header_length_in_bytes: 8;
461 uint32_t first_partition_size_in_bytes: 16;
466 uint32_t motion_comp_scaling: 1;
467 uint32_t mv_clamp_disable: 1;
468 uint32_t chroma_fractional_calculation_modified: 1;
477 uint32_t compressed_header_buffer_bin_count: 16;
478 uint32_t base_qindex: 8;
479 uint32_t tail_insertion_enable: 1;
480 uint32_t header_insertion_enable: 1;
485 uint32_t chroma_ac_qindex_delta: 5;
487 uint32_t chroma_dc_qindex_delta: 5;
489 uint32_t luma_dc_qindex_delta: 5;
494 uint32_t lf_ref_delta0: 7;
496 uint32_t lf_ref_delta1: 7;
498 uint32_t lf_ref_delta2: 7;
500 uint32_t lf_ref_delta3: 7;
505 uint32_t lf_mode_delta0: 7;
507 uint32_t lf_mode_delta1: 7;
512 uint32_t bit_offset_for_lf_ref_delta: 16;
513 uint32_t bit_offset_for_mode_delta: 16;
517 uint32_t bit_offset_for_qindex: 16;
518 uint32_t bit_offset_for_lf_level: 16;
523 uint32_t non_first_pass_flag: 1;
524 uint32_t vdenc_pak_only_pass: 1;
526 uint32_t frame_bitrate_max_report_mask: 1;
527 uint32_t frame_bitrate_min_report_mask: 1;
532 uint32_t frame_bitrate_max: 14;
534 uint32_t frame_bitrate_max_unit: 1;
538 uint32_t frame_bitrate_min: 14;
540 uint32_t frame_bitrate_min_unit: 1;
544 uint32_t frame_delta_qindex_max_low;
545 uint32_t frame_delta_qindex_max_high;
549 uint32_t frame_delta_qindex_min;
553 uint32_t frame_delta_lf_max_low;
554 uint32_t frame_delta_lf_max_high;
558 uint32_t frame_delta_lf_min;
562 uint32_t frame_delta_qindex_lf_max_range_low;
563 uint32_t frame_delta_qindex_lf_max_range_high;
567 uint32_t frame_delta_qindex_lf_min_range;
571 uint32_t min_fram_size: 16;
573 uint32_t min_frame_size_units: 2;
577 uint32_t bit_offset_for_first_partition_size: 16;
582 uint32_t class0_sse_threshold_0: 16;
583 uint32_t class0_sse_threshold_1: 16;
587 uint32_t class1_sse_threshold_0: 16;
588 uint32_t class1_sse_threshold_1: 16;
592 uint32_t class2_sse_threshold_0: 16;
593 uint32_t class2_sse_threshold_1: 16;
597 uint32_t class3_sse_threshold_0: 16;
598 uint32_t class3_sse_threshold_1: 16;
602 uint32_t class4_sse_threshold_0: 16;
603 uint32_t class4_sse_threshold_1: 16;
607 uint32_t class5_sse_threshold_0: 16;
608 uint32_t class5_sse_threshold_1: 16;
612 uint32_t class6_sse_threshold_0: 16;
613 uint32_t class6_sse_threshold_1: 16;
617 uint32_t class7_sse_threshold_0: 16;
618 uint32_t class7_sse_threshold_1: 16;
622 uint32_t class8_sse_threshold_0: 16;
623 uint32_t class8_sse_threshold_1: 16;
625 } gen10_hcp_vp9_pic_state_param;
627 typedef struct _gen10_hcp_qm_state_param {
629 uint32_t prediction_type : 1;
630 uint32_t size_id : 2;
631 uint32_t color_component : 2;
632 uint32_t dc_coefficient : 8;
633 uint32_t reserved : 19;
636 uint32_t quant_matrix[16];
637 } gen10_hcp_qm_state_param;
639 typedef struct _gen10_hcp_fqm_state_param {
641 uint32_t prediction_type : 1;
642 uint32_t size_id : 2;
643 uint32_t color_component : 2;
644 uint32_t reserved : 11;
645 uint32_t forward_dc_coeff : 16;
648 uint32_t forward_quant_matrix[32];
649 } gen10_hcp_fqm_state_param;
651 typedef struct _gen10_hcp_rdoq_state_param {
653 uint32_t reserved : 30;
654 uint32_t disable_htq_fix1 : 1;
655 uint32_t disable_htq_fix0 : 1;
658 uint16_t lambda_intra_luma[64];
659 uint16_t lambda_intra_chroma[64];
660 uint16_t lambda_inter_luma[64];
661 uint16_t lambda_inter_chroma[64];
662 } gen10_hcp_rdoq_state_param;
664 typedef struct _gen10_hcp_weightoffset_state_param {
666 uint32_t ref_pic_list_num : 1;
667 uint32_t reserved : 31;
671 uint32_t delta_luma_weight : 8;
672 uint32_t luma_offset : 8;
673 uint32_t reserved : 16;
677 uint32_t delta_chroma_weight_0 : 8;
678 uint32_t chroma_offset_0 : 8;
679 uint32_t delta_chroma_weight_1 : 8;
680 uint32_t chroma_offset_1 : 8;
682 } gen10_hcp_weightoffset_state_param;
684 #define GEN10_HCP_B_SLICE 0
685 #define GEN10_HCP_P_SLICE 1
686 #define GEN10_HCP_I_SLICE 2
688 typedef struct _gen10_hcp_slice_state_param {
690 uint32_t slice_start_ctu_x : 10;
691 uint32_t reserved0 : 6;
692 uint32_t slice_start_ctu_y : 10;
693 uint32_t reserved1 : 6;
697 uint32_t next_slice_start_ctu_x : 10;
698 uint32_t reserved0 : 6;
699 uint32_t next_slice_start_ctu_y : 10;
700 uint32_t reserved1 : 6;
704 uint32_t slice_type : 2;
705 uint32_t last_slice_flag : 1;
706 uint32_t slice_qp_sign_flag : 1;
707 uint32_t reserved0 : 1;
708 uint32_t slice_temporal_mvp_enabled : 1;
709 uint32_t slice_qp : 6;
710 uint32_t slice_cb_qp_offset : 5;
711 uint32_t slice_cr_qp_offset : 5;
712 uint32_t intra_ref_fetch_disable : 1;
713 uint32_t cu_chroma_qu_offset_enabled : 1;
714 uint32_t reserved1 : 8;
718 uint32_t deblocking_filter_disable : 1;
719 uint32_t tc_offset_div2 : 4;
720 uint32_t beta_offset_div2 : 4;
721 uint32_t reserved0 : 1;
722 uint32_t loop_filter_across_slices_enabled : 1;
723 uint32_t sao_chroma_flag : 1;
724 uint32_t sao_luma_flag : 1;
725 uint32_t mvd_l1_zero_flag : 1;
726 uint32_t is_low_delay : 1;
727 uint32_t collocated_from_l0_flag : 1;
728 uint32_t chroma_log2_weight_denom : 3;
729 uint32_t luma_log2_weight_denom : 3;
730 uint32_t cabac_init_flag : 1;
731 uint32_t max_merge_idx : 3;
732 uint32_t collocated_ref_idx : 3;
733 uint32_t reserved1 : 3;
741 uint32_t reserved0 : 20;
742 uint32_t round_intra : 4;
743 uint32_t reserved1 : 2;
744 uint32_t round_inter : 4;
745 uint32_t reserved2 : 2;
749 uint32_t reserved0 : 1;
750 uint32_t cabac_zero_word_insertion_enabled : 1;
751 uint32_t emulation_byte_insert_enabled : 1;
752 uint32_t reserved1 : 5;
753 uint32_t tail_insertion_enabled : 1;
754 uint32_t slice_data_enabled : 1;
755 uint32_t header_insertion_enabled : 1;
756 uint32_t reserved2 : 21;
764 uint32_t transform_skip_lambda : 16;
765 uint32_t reserved : 16;
769 uint32_t transform_skip_zero_factor0 : 8;
770 uint32_t transform_skip_nonezero_factor0 : 8;
771 uint32_t transform_skip_zero_factor1 : 8;
772 uint32_t transform_skip_nonezero_factor1 : 8;
774 } gen10_hcp_slice_state_param;
776 typedef struct _gen10_hcp_ref_idx_state_param {
778 uint32_t ref_pic_list_num : 1;
779 uint32_t num_ref_idx_active_minus1 : 4;
780 uint32_t reserved : 27;
784 uint32_t ref_pic_tb_value : 8;
785 uint32_t ref_pic_frame_id : 3;
786 uint32_t chroma_weight_flag : 1;
787 uint32_t luma_weight_flag : 1;
788 uint32_t long_term_ref_flag : 1;
789 uint32_t field_pic_flag : 1;
790 uint32_t bottom_field_flag : 1;
791 uint32_t reserved : 16;
792 } ref_list_entry[16];
793 } gen10_hcp_ref_idx_state_param;
795 typedef struct _gen10_hcp_pak_insert_object_param {
798 uint32_t reserved0 : 1;
799 uint32_t end_of_slice_flag : 1;
800 uint32_t last_header_flag : 1;
801 uint32_t emulation_flag : 1;
802 uint32_t skip_emulation_bytes : 4;
803 uint32_t data_bits_in_last_dw : 6;
804 uint32_t reserved1 : 18;
809 uint8_t *inline_payload_ptr;
810 uint32_t inline_payload_bits;
811 } gen10_hcp_pak_insert_object_param;
813 typedef struct gen10_hcp_vp9_segment_state_param {
815 uint32_t segment_id: 3;
820 uint32_t segment_skipped: 1;
821 uint32_t segment_reference: 2;
822 uint32_t segment_reference_enabled: 1;
827 uint32_t pad0; /* decoder only */
831 uint32_t pad0; /* decoder only */
835 uint32_t pad0; /* decoder only */
839 uint32_t pad0; /* decoder only */
843 uint32_t segment_qindex_delta: 9;
845 uint32_t segment_lf_level_delta: 7;
848 } gen10_hcp_vp9_segment_state_param;
851 gen10_hcp_pipe_mode_select(VADriverContextP ctx,
852 struct intel_batchbuffer *batch,
853 gen10_hcp_pipe_mode_select_param *param);
855 gen10_hcp_surface_state(VADriverContextP ctx,
856 struct intel_batchbuffer *batch,
857 gen10_hcp_surface_state_param *param);
859 gen10_hcp_pipe_buf_addr_state(VADriverContextP ctx,
860 struct intel_batchbuffer *batch,
861 gen10_hcp_pipe_buf_addr_state_param *param);
863 gen10_hcp_ind_obj_base_addr_state(VADriverContextP ctx,
864 struct intel_batchbuffer *batch,
865 gen10_hcp_ind_obj_base_addr_state_param *param);
867 gen10_hcp_pic_state(VADriverContextP ctx,
868 struct intel_batchbuffer *batch,
869 gen10_hcp_pic_state_param *param);
872 gen10_hcp_vp9_pic_state(VADriverContextP ctx,
873 struct intel_batchbuffer *batch,
874 gen10_hcp_vp9_pic_state_param *param);
877 gen10_hcp_qm_state(VADriverContextP ctx,
878 struct intel_batchbuffer *batch,
879 gen10_hcp_qm_state_param *param);
881 gen10_hcp_fqm_state(VADriverContextP ctx,
882 struct intel_batchbuffer *batch,
883 gen10_hcp_fqm_state_param *param);
885 gen10_hcp_rdoq_state(VADriverContextP ctx,
886 struct intel_batchbuffer *batch,
887 gen10_hcp_rdoq_state_param *param);
889 gen10_hcp_weightoffset_state(VADriverContextP ctx,
890 struct intel_batchbuffer *batch,
891 gen10_hcp_weightoffset_state_param *param);
893 gen10_hcp_slice_state(VADriverContextP ctx,
894 struct intel_batchbuffer *batch,
895 gen10_hcp_slice_state_param *param);
897 gen10_hcp_ref_idx_state(VADriverContextP ctx,
898 struct intel_batchbuffer *batch,
899 gen10_hcp_ref_idx_state_param *param);
901 gen10_hcp_pak_insert_object(VADriverContextP ctx,
902 struct intel_batchbuffer *batch,
903 gen10_hcp_pak_insert_object_param *param);
906 gen10_hcp_vp9_segment_state(VADriverContextP ctx,
907 struct intel_batchbuffer *batch,
908 gen10_hcp_vp9_segment_state_param *param);