2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Peng Chen <peng.c.chen@intel.com>
29 #ifndef GEN10_HEVC_ENC_UTILS_H
30 #define GEN10_HEVC_ENC_UTILS_H
32 #define GEN10_MAX_REF_SURFACES 8
33 #define GEN10_HEVC_NUM_MAX_REF_L0 3
34 #define GEN10_HEVC_NUM_MAX_REF_L1 1
36 #define GEN10_MAX_COLLOCATED_REF_IDX 2
38 #define GEN10_HEVC_ENC_MIN_LCU_SIZE 16
39 #define GEN10_HEVC_ENC_MAX_LCU_SIZE 64
41 #define GEN10_HEVC_ENC_PAK_OBJ_SIZE ((5 + 3) * 4)
42 #define GEN10_HEVC_ENC_PAK_CU_RECORD_SIZE (8 * 4)
44 #define GEN10_HEVC_ENC_ROLLING_I_COLUMN 1
45 #define GEN10_HEVC_ENC_ROLLING_I_ROW 2
46 #define GEN10_HEVC_ENC_ROLLING_I_SQUARE 3
48 enum GEN10_HEVC_BRC_METHOD {
58 struct gen10_hevc_enc_frame_info {
61 uint32_t picture_coding_type;
62 uint32_t bit_depth_luma_minus8;
63 uint32_t bit_depth_chroma_minus8;
68 int32_t height_in_lcu;
74 uint32_t ctu_max_bitsize_allowed;
76 int32_t arbitrary_num_mb_in_slice;
78 uint8_t qm_matrix[4][3][2][64];
79 uint8_t qm_dc_matrix[2][3][2];
81 uint16_t fqm_matrix[4][2][64];
82 uint16_t fqm_dc_matrix[2][2];
86 int mapped_ref_idx_list0[8];
87 int mapped_ref_idx_list1[8];
90 uint32_t gop_ref_dist;
92 uint32_t gop_num_b[3];
94 uint32_t reallocate_flag : 1;
95 uint32_t is_same_ref_list : 1;
96 uint32_t reserved : 31;
98 VAEncSequenceParameterBufferHEVC last_seq_param;
101 struct gen10_hevc_enc_status {
102 uint32_t image_status_mask;
103 uint32_t image_status_ctrl;
104 uint32_t bytes_per_frame;
105 uint32_t pass_number;
106 uint32_t media_state;
108 uint32_t bs_se_bitcount;
111 struct gen10_hevc_enc_status_buffer {
112 struct i965_gpe_resource gpe_res;
113 uint32_t status_size;
115 uint32_t status_bytes_per_frame_offset;
116 uint32_t status_image_mask_offset;
117 uint32_t status_image_ctrl_offset;
118 uint32_t status_pass_num_offset;
119 uint32_t status_media_state_offset;
120 uint32_t status_qp_status_offset;
121 uint32_t status_bs_se_bitcount_offset;
123 uint32_t mmio_bytes_per_frame_offset;
124 uint32_t mmio_bs_frame_no_header_offset;
125 uint32_t mmio_image_mask_offset;
126 uint32_t mmio_image_ctrl_offset;
127 uint32_t mmio_qp_status_offset;
128 uint32_t mmio_bs_se_bitcount_offset;
131 struct gen10_hevc_enc_common_res {
133 struct i965_gpe_resource gpe_res;
136 } compressed_bitstream;
139 struct object_surface *obj_surface;
140 VASurfaceID surface_id;
141 struct i965_gpe_resource gpe_res;
145 struct object_surface *obj_surface;
146 VASurfaceID surface_id;
147 struct i965_gpe_resource gpe_res;
151 struct object_surface *obj_surface;
152 VASurfaceID surface_id;
153 struct i965_gpe_resource gpe_res;
154 } reference_pics[16];
156 struct i965_gpe_resource deblocking_filter_line_buffer;
157 struct i965_gpe_resource deblocking_filter_tile_line_buffer;
158 struct i965_gpe_resource deblocking_filter_tile_column_buffer;
159 struct i965_gpe_resource metadata_line_buffer;
160 struct i965_gpe_resource metadata_tile_line_buffer;
161 struct i965_gpe_resource metadata_tile_column_buffer;
162 struct i965_gpe_resource sao_line_buffer;
163 struct i965_gpe_resource sao_tile_line_buffer;
164 struct i965_gpe_resource sao_tile_column_buffer;
165 struct i965_gpe_resource streamout_data_destination_buffer;
166 struct i965_gpe_resource picture_status_buffer;
167 struct i965_gpe_resource ildb_streamout_buffer;
168 struct i965_gpe_resource sao_streamout_data_destination_buffer;
169 struct i965_gpe_resource frame_statics_streamout_data_destination_buffer;
170 struct i965_gpe_resource sse_source_pixel_rowstore_buffer;
173 struct gen10_hevc_enc_lambda_param {
174 uint16_t lambda_intra[2][64];
175 uint16_t lambda_inter[2][64];
179 gen10_hevc_enc_init_frame_info(VADriverContextP ctx,
180 struct encode_state *encode_state,
181 struct intel_encoder_context *encoder_context,
182 struct gen10_hevc_enc_frame_info *frame_info);
185 gen10_hevc_enc_insert_packed_header(VADriverContextP ctx,
186 struct encode_state *encode_state,
187 struct intel_encoder_context *encoder_context,
188 struct intel_batchbuffer *batch);
191 gen10_hevc_enc_insert_slice_header(VADriverContextP ctx,
192 struct encode_state *encode_state,
193 struct intel_encoder_context *encoder_context,
194 struct intel_batchbuffer *batch,
198 gen10_hevc_enc_init_common_resource(VADriverContextP ctx,
199 struct encode_state *encode_state,
200 struct intel_encoder_context *encoder_context,
201 struct gen10_hevc_enc_common_res *common_res,
202 struct gen10_hevc_enc_frame_info *frame_info,
207 gen10_hevc_enc_free_common_resource(struct gen10_hevc_enc_common_res *common_resource);
210 gen10_hevc_enc_init_status_buffer(VADriverContextP ctx,
211 struct encode_state *encode_state,
212 struct intel_encoder_context *encoder_context,
213 struct gen10_hevc_enc_status_buffer *status_buffer);
216 gen10_hevc_enc_init_lambda_param(struct gen10_hevc_enc_lambda_param *param,
217 int bit_depth_luma_minus8,
218 int bit_depth_chroma_minus8);
221 gen10_hevc_enc_hcp_set_qm_fqm_states(VADriverContextP ctx,
222 struct intel_batchbuffer *batch,
223 struct gen10_hevc_enc_frame_info *frame_info);
226 gen10_hevc_enc_hcp_set_ref_idx_lists(VADriverContextP ctx,
227 struct intel_batchbuffer *batch,
228 VAEncPictureParameterBufferHEVC *pic_param,
229 VAEncSliceParameterBufferHEVC *slice_param);
232 gen10_hevc_enc_hcp_set_weight_offsets(VADriverContextP ctx,
233 struct intel_batchbuffer *batch,
234 VAEncPictureParameterBufferHEVC *pic_param,
235 VAEncSliceParameterBufferHEVC *slice_param);
238 gen10_hevc_enc_ensure_surface(VADriverContextP ctx,
239 struct object_surface *obj_surface,
240 int bit_depth_minus8,
241 int reallocate_flag);
244 gen10_hevc_enc_get_profile_level_max_frame(VAEncSequenceParameterBufferHEVC *seq_param,
245 uint32_t user_max_frame_size,
246 uint32_t frame_rate);
249 gen10_hevc_enc_get_max_num_slices(VAEncSequenceParameterBufferHEVC *seq_param);
252 gen10_hevc_enc_get_pic_header_size(struct encode_state *encode_state);