2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Zhao, Yakui <yakui.zhao@intel.com>
26 * Chen, Peng <peng.c.chen@intel.com>
30 #ifndef _GEN10_HEVC_ENC_KERNEL_H
31 #define _GEN10_HEVC_ENC_KERNEL_H
33 typedef struct _gen10_hevc_concurrent_tg_data_ {
34 uint16_t curr_tg_start_lcu_index;
35 uint16_t curr_tg_end_luc_index;
36 uint16_t curr_tg_index;
38 uint16_t curr_wf_lcu_idx_x;
39 uint16_t curr_wf_lcu_idx_y;
40 uint16_t curr_wf_lcu_idx1_y;
41 uint16_t next_wf_lcu_idx_x;
42 uint16_t curr_wf_yoffset;
43 uint16_t reserved1[23];
44 } gen10_hevc_concurrent_tg_data;
46 typedef struct _gen10_hevc_lcu_level_data_ {
47 int16_t slice_start_lcu_idx;
48 int16_t slice_end_lcu_idx;
52 } gen10_hevc_lcu_level_data;
54 typedef struct _gen10_hevc_pak_stats_info_ {
55 uint32_t hcp_bs_frame;
56 uint32_t hcp_bs_frame_noheader;
57 uint32_t hcp_image_status_control;
59 uint32_t hcp_image_status_ctl_last_pass;
60 uint32_t reserved1[3];
61 } gen10_hevc_pak_stats_info;
63 typedef struct _gen10_hevc_brc_init_curbe_data {
65 uint32_t profile_level_max_frame;
69 uint32_t init_buf_full;
77 uint32_t target_bit_rate;
81 uint32_t maximum_bit_rate;
85 uint32_t minimum_bit_rate;
97 uint32_t brc_flag : 16;
98 uint32_t brc_gopp : 16;
102 uint32_t brc_gopb : 16;
103 uint32_t frame_width : 16;
107 uint32_t frame_height : 16;
108 uint32_t avbr_accuracy : 16;
112 uint32_t avbr_convergence : 16;
113 uint32_t minimum_qp : 16;
117 uint32_t maximum_qp : 16;
118 uint32_t number_slice : 16;
122 uint32_t reserved : 16;
123 uint32_t brc_gopb1 : 16;
127 uint32_t brc_gopb2 : 16;
128 uint32_t max_brc_level : 16;
132 uint32_t long_term_interval : 16;
133 uint32_t reserved : 16;
137 uint32_t instant_rate_thr0_pframe : 8;
138 uint32_t instant_rate_thr1_pframe : 8;
139 uint32_t instant_rate_thr2_pframe : 8;
140 uint32_t instant_rate_thr3_pframe : 8;
144 uint32_t instant_rate_thr0_bframe : 8;
145 uint32_t instant_rate_thr1_bframe : 8;
146 uint32_t instant_rate_thr2_bframe : 8;
147 uint32_t instant_rate_thr3_bframe : 8;
151 uint32_t instant_rate_thr0_iframe : 8;
152 uint32_t instant_rate_thr1_iframe : 8;
153 uint32_t instant_rate_thr2_iframe : 8;
154 uint32_t instant_rate_thr3_iframe : 8;
158 uint32_t deviation_thr0_pbframe : 8;
159 uint32_t deviation_thr1_pbframe : 8;
160 uint32_t deviation_thr2_pbframe : 8;
161 uint32_t deviation_thr3_pbframe : 8;
165 uint32_t deviation_thr4_pbframe : 8;
166 uint32_t deviation_thr5_pbframe : 8;
167 uint32_t deviation_thr6_pbframe : 8;
168 uint32_t deviation_thr7_pbframe : 8;
172 uint32_t deviation_thr0_vbrctrl : 8;
173 uint32_t deviation_thr1_vbrctrl : 8;
174 uint32_t deviation_thr2_vbrctrl : 8;
175 uint32_t deviation_thr3_vbrctrl : 8;
179 uint32_t deviation_thr4_vbrctrl : 8;
180 uint32_t deviation_thr5_vbrctrl : 8;
181 uint32_t deviation_thr6_vbrctrl : 8;
182 uint32_t deviation_thr7_vbrctrl : 8;
186 uint32_t deviation_thr0_iframe : 8;
187 uint32_t deviation_thr1_iframe : 8;
188 uint32_t deviation_thr2_iframe : 8;
189 uint32_t deviation_thr3_iframe : 8;
193 uint32_t deviation_thr4_iframe : 8;
194 uint32_t deviation_thr5_iframe : 8;
195 uint32_t deviation_thr6_iframe : 8;
196 uint32_t deviation_thr7_iframe : 8;
200 uint32_t ac_qp_buffer : 8;
201 uint32_t intra_sad_tr : 8;
202 uint32_t log2_max_cu_size : 8;
203 uint32_t sliding_wind_size : 8;
229 } gen10_hevc_brc_init_curbe_data;
231 typedef struct _gen10_hevc_brc_update_curbe_data {
233 uint32_t target_size;
241 uint32_t picture_header_size;
245 uint32_t start_gadj_frame0 : 16;
246 uint32_t start_gadj_frame1 : 16;
250 uint32_t start_gadj_frame2 : 16;
251 uint32_t start_gadj_frame3 : 16;
255 uint32_t target_size_flag : 8;
256 uint32_t reserved : 8;
257 uint32_t max_num_paks : 8;
258 uint32_t curr_frame_brclevel : 8;
262 uint32_t num_skipped_frames : 8;
263 uint32_t cqp_value : 8;
264 uint32_t new_feature_flag : 8;
265 uint32_t roi_ratio : 8;
273 uint32_t start_gadj_mult0 : 8;
274 uint32_t start_gadj_mult1 : 8;
275 uint32_t start_gadj_mult2 : 8;
276 uint32_t start_gadj_mult3 : 8;
280 uint32_t start_gadj_mult4 : 8;
281 uint32_t start_gadj_divd0 : 8;
282 uint32_t start_gadj_divd1 : 8;
283 uint32_t start_gadj_divd2 : 8;
287 uint32_t start_gadj_divd3 : 8;
288 uint32_t start_gadj_divd4 : 8;
289 uint32_t qp_threshold0 : 8;
290 uint32_t qp_threshold1 : 8;
294 uint32_t qp_threshold2 : 8;
295 uint32_t qp_threshold3 : 8;
296 uint32_t grate_ratio_thr0 : 8;
297 uint32_t grate_ratio_thr1 : 8;
301 uint32_t grate_ratio_thr2 : 8;
302 uint32_t grate_ratio_thr3 : 8;
303 uint32_t grate_ratio_thr4 : 8;
304 uint32_t grate_ratio_thr5 : 8;
308 uint32_t grate_ratio_thr6 : 8;
309 uint32_t grate_ratio_thr7 : 8;
310 uint32_t grate_ratio_thr8 : 8;
311 uint32_t grate_ratio_thr9 : 8;
315 uint32_t grate_ratio_thr10 : 8;
316 uint32_t grate_ratio_thr11 : 8;
317 uint32_t grate_ratio_thr12 : 8;
318 uint32_t parallel_mode : 8;
322 uint32_t size_of_skipped_frames;
324 } gen10_hevc_brc_update_curbe_data;
326 typedef struct _gen10_hevc_scaling_curbe_data_ {
328 uint32_t input_bit_depth_for_chroma : 8;
329 uint32_t input_bit_depth_for_luma : 8;
330 uint32_t output_bit_depth_for_chroma: 8;
331 uint32_t output_bit_depth_for_luma : 7;
332 uint32_t rounding_enabled : 1;
336 uint32_t picture_format : 8;
337 uint32_t convert_flag : 1;
338 uint32_t downscale_stage : 3;
339 uint32_t mb_statistics_dump_flag : 1;
340 uint32_t reserved0 : 2;
341 uint32_t lcu_size : 1;
342 uint32_t job_queue_size : 16;
346 uint32_t orig_pic_width_in_pixel : 16;
347 uint32_t orig_pic_height_in_pixel : 16;
351 uint32_t bti_input_conversion_surface;
355 uint32_t bti_output_conversion_surface;
356 uint32_t bti_input_ds_surface;
360 uint32_t bti_4x_ds_surface;
364 uint32_t bti_mbstat_surface;
368 uint32_t bti_2x_ds_surface;
372 uint32_t bti_mb_split_surface;
376 uint32_t bti_lcu32_jobqueue_buffer_surface;
380 uint32_t bti_lcu64_lcu32_jobqueue_buffer_surface;
384 uint32_t bti_lcu64_cu32_distortion_surface;
386 } gen10_hevc_scaling_curbe_data;
388 typedef struct _gen10_hevc_me_curbe_data_ {
390 uint32_t rounded_frame_width_in_mv_for4x : 16;
391 uint32_t rounded_frame_height_in_mv_for4x : 16;
395 uint32_t reserved0 : 16;
396 uint32_t mv_cost_scale_factor : 2;
397 uint32_t reserved1 : 14;
401 uint32_t reserved0 : 16;
402 uint32_t sub_pel_mode : 2;
403 uint32_t bme_disable_fbr : 1;
404 uint32_t reserved1 : 1;
405 uint32_t inter_sad_adj : 2;
406 uint32_t reserved2 : 10;
410 uint32_t reserved0 : 1;
411 uint32_t adaptive_search_en : 1;
412 uint32_t reserved1 : 14;
413 uint32_t ime_ref_window_size : 2;
414 uint32_t reserved2 : 14;
418 uint32_t reserved0 : 8;
419 uint32_t quarter_quad_tree_cand : 5;
420 uint32_t reserved1 : 3;
421 uint32_t bi_weight : 6;
422 uint32_t reserved2 : 10;
427 uint32_t max_num_su : 8;
428 uint32_t start_center0_x : 4;
429 uint32_t start_center0_y : 4;
430 uint32_t reserved : 8;
434 uint32_t reserved0 : 1;
435 uint32_t slice_type : 1;
436 uint32_t hme_stage : 2;
437 uint32_t num_ref_l0 : 2;
438 uint32_t num_ref_l1 : 2;
439 uint32_t reserved1 : 24;
443 uint32_t rounded_frame_width_in_mv_for16x : 16;
444 uint32_t rounded_frame_height_in_mv_for16x : 16;
447 uint32_t ime_search_path_03;
448 uint32_t ime_search_path_47;
449 uint32_t ime_search_path_811;
450 uint32_t ime_search_path_1215;
451 uint32_t ime_search_path_1619;
452 uint32_t ime_search_path_2023;
453 uint32_t ime_search_path_2427;
454 uint32_t ime_search_path_2831;
455 uint32_t ime_search_path_3235;
456 uint32_t ime_search_path_3639;
457 uint32_t ime_search_path_4043;
458 uint32_t ime_search_path_4447;
459 uint32_t ime_search_path_4851;
460 uint32_t ime_search_path_5255;
461 uint32_t ime_search_path_5659;
462 uint32_t ime_search_path_6063;
465 uint32_t reserved0 : 6;
466 uint32_t coding_unit_size : 2;
467 uint32_t reserved1 : 4;
468 uint32_t coding_unit_partition_mode : 3;
469 uint32_t coding_unit_prediction_mode: 1;
470 uint32_t reserved2 : 16;
474 uint32_t frame_width_in_pixel_cs : 16;
475 uint32_t frame_height_in_pixel_cs : 16;
479 uint32_t intra8x8_mode_mask : 10;
480 uint32_t reserved0 : 6;
481 uint32_t intra16x16_mode_mask : 9;
482 uint32_t reserved1 : 7;
486 uint32_t intra32x32_mode_mask : 4;
487 uint32_t intra_chroma_mode_mask : 5;
488 uint32_t intra_compute_type : 2;
489 uint32_t reserved0 : 21;
493 uint32_t reserved0 : 8;
494 uint32_t penalty_intra32x32_nondc : 8;
495 uint32_t penalty_intra16x16_nondc : 8;
496 uint32_t penalty_intra8x8_nondc : 8;
500 uint32_t mode0_cost : 8;
501 uint32_t mode1_cost : 8;
502 uint32_t mode2_cost : 8;
503 uint32_t mode3_cost : 8;
507 uint32_t mode4_cost : 8;
508 uint32_t mode5_cost : 8;
509 uint32_t mode6_cost : 8;
510 uint32_t mode7_cost : 8;
514 uint32_t mode8_cost : 8;
515 uint32_t mode9_cost : 8;
516 uint32_t reserved0 : 8;
517 uint32_t chroma_intra_mode_cost : 8;
521 uint32_t reserved0 : 8;
522 uint32_t sicintra_neighbor_avail_flag : 6;
523 uint32_t reserved1 : 6;
525 uint32_t sic_inter_sad_measure : 2;
526 uint32_t sic_intra_sad_measure : 2;
527 uint32_t reserved2 : 8;
531 uint32_t sic_log2_min_cu_size : 8;
532 uint32_t reserved0 : 12;
533 uint32_t sic_only_harr : 1;
534 uint32_t reserved1 : 3;
535 uint32_t sic_hevc_quarter_quadtree : 5;
536 uint32_t reserved2 : 3;
540 uint32_t bti_hme_output_mv_data_surface;
544 uint32_t bti_16xinput_mv_data_surface;
548 uint32_t bti_4x_output_distortion_surface;
552 uint32_t bti_vme_input_surface;
556 uint32_t bti_4xds_surface;
560 uint32_t bti_brc_distortion_surface;
564 uint32_t bti_mv_and_distortion_sum_surface;
566 } gen10_hevc_me_curbe_data;
568 typedef struct _gen10_hevc_mbenc_intra_curbe_data {
570 uint32_t frame_width_in_pixel : 16;
571 uint32_t frame_height_in_pixel : 16;
575 uint32_t reserved0 : 8;
576 uint32_t penalty_intra32x32_nondc_pred : 8;
577 uint32_t penalty_intra16x16_nondc_pred : 8;
578 uint32_t penalty_intra8x8_nondc_pred : 8;
582 uint32_t reserved0 : 6;
583 uint32_t intra_sad_measure_adj : 2;
584 uint32_t intra_prediction : 3;
585 uint32_t reserved1 : 21;
589 uint32_t mode0_cost : 8;
590 uint32_t mode1_cost : 8;
591 uint32_t mode2_cost : 8;
592 uint32_t mode3_cost : 8;
596 uint32_t mode4_cost : 8;
597 uint32_t mode5_cost : 8;
598 uint32_t mode6_cost : 8;
599 uint32_t mode7_cost : 8;
603 uint32_t mode8_cost : 8;
604 uint32_t mode9_cost : 8;
605 uint32_t ref_id_cost : 8;
606 uint32_t chroma_intra_mode_cost : 8;
610 uint32_t log2_max_cu_size : 4;
611 uint32_t log2_min_cu_size : 4;
612 uint32_t log2_max_tu_size : 4;
613 uint32_t log2_min_tu_size : 4;
614 uint32_t max_tr_depth_intra : 4;
615 uint32_t tu_split_flag : 1;
616 uint32_t tu_based_cost_setting : 3;
617 uint32_t reserved0 : 8;
621 uint32_t concurrent_group_num : 8;
622 uint32_t enc_tu_decision_mode : 2;
623 uint32_t reserved0 : 14;
624 uint32_t slice_qp : 8;
632 uint32_t lambda_md : 16;
633 uint32_t reserved0 : 16;
637 uint32_t intra_tusad_thr;
641 uint32_t slice_type : 2;
642 uint32_t qp_type : 2;
643 uint32_t check_pcm_mode_flag : 1;
644 uint32_t enable_intra4x4_pu : 1;
645 uint32_t enc_qt_decision_mode : 1;
646 uint32_t reserved0 : 25;
650 uint32_t pcm_8x8_sad_threshold : 16;
651 uint32_t reserved0 : 16;
667 uint32_t bti_vme_intra_pred_surface;
671 uint32_t bti_curr_picture_y;
675 uint32_t bti_enc_curecord_surface;
679 uint32_t bti_pak_obj_cmd_surface;
683 uint32_t bti_cu_packet_for_pak_surface;
687 uint32_t bti_internal_scratch_surface;
691 uint32_t bti_cu_based_qp_surface;
695 uint32_t bti_const_data_lut_surface;
699 uint32_t bti_lcu_level_data_input_surface;
703 uint32_t bti_concurrent_tg_data_surface;
707 uint32_t bti_brc_combined_enc_param_surface;
711 uint32_t bti_cu_split_surface;
715 uint32_t bti_debug_surface;
717 } gen10_hevc_mbenc_intra_curbe_data;
719 typedef struct _gen10_hevc_mbenc_inter_curbe_data {
721 uint32_t frame_width_in_pixel : 16;
722 uint32_t frame_height_in_pixel : 16;
726 uint32_t log2_max_cu_size : 4;
727 uint32_t log2_min_cu_size : 4;
728 uint32_t log2_max_tu_size : 4;
729 uint32_t log2_min_tu_size : 4;
730 uint32_t max_tr_depth_inter : 4;
731 uint32_t max_tr_depth_intra : 4;
732 uint32_t log2_para_merge_level : 4;
733 uint32_t max_num_ime_search_center : 4;
737 uint32_t transquant_bypass_enable : 1;
738 uint32_t cu_qpdelta_enable : 1;
739 uint32_t pcm_enable : 1;
740 uint32_t enable_cu64_check : 1;
741 uint32_t enable_intra4x4_pu : 1;
742 uint32_t chroma_skip_check : 1;
743 uint32_t enc_trans_simplify : 2;
744 uint32_t hme_flag : 2;
745 uint32_t hme_coarse_stage : 2;
746 uint32_t hme_subpel_mode : 2;
747 uint32_t super_hme_enable : 1;
748 uint32_t regions_in_slice_splits_enable : 1;
749 uint32_t enc_tu_dec_mode : 2;
750 uint32_t enc_tu_dec_for_all_qt : 1;
751 uint32_t coef_bit_est_mode : 1;
752 uint32_t enc_skip_dec_mode : 2;
753 uint32_t enc_qt_dec_mode : 1;
754 uint32_t lcu32_enc_rd_dec_mode_for_all_qt : 1;
755 uint32_t qp_type : 2;
756 uint32_t lcu64_cu64_skip_check_only : 1;
757 uint32_t sic_dys_run_path_mode : 2;
758 uint32_t reserved0 : 3;
762 uint32_t active_num_child_threads_cu64 : 4;
763 uint32_t active_num_child_threads_cu32_0 : 4;
764 uint32_t active_num_child_threads_cu32_1 : 4;
765 uint32_t active_num_child_threads_cu32_2 : 4;
766 uint32_t active_num_child_threads_cu32_3 : 4;
767 uint32_t reserved0 : 4;
768 uint32_t slice_qp : 8;
772 uint32_t skip_mode_enable : 1;
773 uint32_t adaptive_enable : 1;
774 uint32_t reserved0 : 1;
775 uint32_t hevc_min_cu_ctrl : 2;
776 uint32_t early_ime_succ_enable : 1;
777 uint32_t reserved1 : 1;
778 uint32_t ime_cost_center_sel : 1;
779 uint32_t ref_pixel_offset : 8;
780 uint32_t ime_ref_window_size : 2;
781 uint32_t residual_pred_data_type_ctrl : 1;
782 uint32_t residual_pred_inter_chroma_ctrl : 1;
783 uint32_t residual_pred16x16_sel_ctrl : 2;
784 uint32_t reserved2 : 2;
785 uint32_t early_ime_stop : 8;
789 uint32_t subpel_mode : 2;
790 uint32_t reserved0 : 2;
791 uint32_t inter_sad_measure : 2;
792 uint32_t intra_sad_measure : 2;
794 uint32_t max_num_su : 8;
795 uint32_t intra_pred_mask : 3;
796 uint32_t refid_cost_mode : 1;
797 uint32_t disable_pintra : 1;
798 uint32_t tu_based_cost_setting : 3;
806 uint32_t slice_type : 2;
807 uint32_t temporal_mvp_enable : 1;
808 uint32_t mvp_collocated_from_l0 : 1;
809 uint32_t same_ref_list : 1;
810 uint32_t is_low_delay : 1;
811 uint32_t reserved0 : 2;
812 uint32_t max_num_merge_cand : 8;
813 uint32_t num_ref_idx_l0 : 8;
814 uint32_t num_ref_idx_l1 : 8;
818 uint32_t fwd_poc_num_l0_mtb_0 : 8;
819 uint32_t bwd_poc_num_l1_mtb_0 : 8;
820 uint32_t fwd_poc_num_l0_mtb_1 : 8;
821 uint32_t bwd_poc_num_l1_mtb_1 : 8;
825 uint32_t fwd_poc_num_l0_mtb_2 : 8;
826 uint32_t bwd_poc_num_l1_mtb_2 : 8;
827 uint32_t fwd_poc_num_l0_mtb_3 : 8;
828 uint32_t bwd_poc_num_l1_mtb_3 : 8;
832 uint32_t fwd_poc_num_l0_mtb_4 : 8;
833 uint32_t bwd_poc_num_l1_mtb_4 : 8;
834 uint32_t fwd_poc_num_l0_mtb_5 : 8;
835 uint32_t bwd_poc_num_l1_mtb_5 : 8;
839 uint32_t fwd_poc_num_l0_mtb_6 : 8;
840 uint32_t bwd_poc_num_l1_mtb_6 : 8;
841 uint32_t fwd_poc_num_l0_mtb_7 : 8;
842 uint32_t bwd_poc_num_l1_mtb_7 : 8;
846 uint32_t long_term_ref_flags_l0 : 16;
847 uint32_t long_term_ref_flags_l1 : 16;
851 uint32_t ref_frame_hor_size : 16;
852 uint32_t ref_frame_ver_size : 16;
856 uint32_t kernel_debug;
860 uint32_t concurrent_gop_num : 8;
861 uint32_t total_thread_num_per_lcu : 8;
862 uint32_t regions_in_slice_split_count : 8;
863 uint32_t reserved0 : 8;
867 uint32_t bti_curr_picture_y;
871 uint32_t bti_enc_curecord_surface;
875 uint32_t bti_lcu32_pak_objcmd_surface;
876 uint32_t bti_lcu64_enc_curecord2_surface;
880 uint32_t bti_lcu32_pak_curecord_surface;
881 uint32_t bti_lcu64_pak_objcmd_surface;
885 uint32_t bti_lcu32_vme_intra_inter_pred_surface;
886 uint32_t bti_lcu64_pak_curecord_surface;
890 uint32_t bti_lcu32_cu16_qpdata_input_surface;
891 uint32_t bti_lcu64_vme_intra_inter_pred_surface;
895 uint32_t bti_lcu32_enc_const_table_surface;
896 uint32_t bti_lcu64_cu16_qpdata_input_surface;
900 uint32_t bti_lcu32_colocated_mvdata_surface;
901 uint32_t bti_lcu64_cu32_enc_const_table_surface;
905 uint32_t bti_lcu32_hme_pred_data_surface;
906 uint32_t bti_lcu64_colocated_mvdata_surface;
910 uint32_t bti_lcu32_lculevel_data_input_surface;
911 uint32_t bti_lcu64_hme_pred_surface;
915 uint32_t bti_lcu32_enc_scratch_surface;
916 uint32_t bti_lcu64_lculevel_data_input_surface;
920 uint32_t bti_lcu32_concurrent_tg_data_surface;
921 uint32_t bti_lcu64_cu32_enc_scratch_surface;
925 uint32_t bti_lcu32_brc_combined_enc_param_surface;
926 uint32_t bti_lcu64_64x64_dist_surface;
930 uint32_t bti_lcu32_jbq_scratch_surface;
931 uint32_t bti_lcu64_concurrent_tg_data_surface;
935 uint32_t bti_lcu32_cusplit_data_surface;
936 uint32_t bti_lcu64_brc_combined_enc_param_surface;
940 uint32_t bti_lcu32_residual_scratch_surface;
941 uint32_t bti_lcu64_cu32_jbq1d_buf_surface;
945 uint32_t bti_lcu32_debug_surface;
946 uint32_t bti_lcu64_cu32_jbq2d_buf_surface;
951 uint32_t bti_lcu64_cu32_residual_scratch_surface;
956 uint32_t bti_lcu64_cusplit_surface;
961 uint32_t bti_lcu64_curr_picture_y_2xds;
966 uint32_t bti_lcu64_intermediate_curecord_surface;
971 uint32_t bti_lcu64_const_data_lut_surface;
976 uint32_t bti_lcu64_lcu_storage_surface;
981 uint32_t bti_lcu64_vme_inter_pred_2xds_surface;
986 uint32_t bti_lcu64_cu64_jbq1d_surface;
991 uint32_t bti_lcu64_cu64_jbq2d_surface;
996 uint32_t bti_lcu64_cu64_residual_scratch_surface;
1001 uint32_t bti_lcu64_debug_surface;
1003 } gen10_hevc_mbenc_inter_curbe_data;
1005 typedef struct _gen10_intel_kernel_header_ {
1006 uint32_t reserved : 6;
1007 uint32_t kernel_start_pointer : 26;
1008 } gen10_intel_kernel_header;
1010 typedef struct _gen10_hevc_kernel_header_ {
1012 gen10_intel_kernel_header hevc_intra;
1013 gen10_intel_kernel_header hevc_enc;
1014 gen10_intel_kernel_header hevc_ds_convert;
1015 gen10_intel_kernel_header hevc_hme;
1016 gen10_intel_kernel_header hevc_enc_lcu64;
1017 gen10_intel_kernel_header hevc_brc_init;
1018 gen10_intel_kernel_header hevc_brc_lcuqp;
1019 gen10_intel_kernel_header hevc_brc_reset;
1020 gen10_intel_kernel_header hevc_brc_update;
1021 gen10_intel_kernel_header hevc_last;
1022 } gen10_hevc_kernel_header;
1024 typedef enum _GEN10_HEVC_ENC_OPERATION_ {
1025 GEN10_HEVC_ENC_SCALING_CONVERSION = 0,
1028 GEN10_HEVC_ENC_MBENC,
1029 } GEN10_HEVC_ENC_OPERATION;