src/gen10_hevc_encoder.h

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Zhao, Yakui <yakui.zhao@intel.com>
  26  *    Chen, Peng  <peng.c.chen@intel.com>
  27  *
  28  */
  29
  30 #ifndef GEN10_HEVC_ENCODER_H
  31 #define GEN10_HEVC_ENCODER_H
  32
  33 #include <drm.h>
  34 #include <i915_drm.h>
  35 #include <intel_bufmgr.h>
  36
  37 #include <va/va.h>
  38 #include "i965_gpe_utils.h"
  39
  40 #define GEN10_HEVC_REGION_START_Y_OFFSET    32
  41
  42 #define GEN10_HEVC_LOG2_MAX_HEVC_LCU        6
  43 #define GEN10_HEVC_LOG2_MIN_HEVC_LCU        4
  44
  45 #define GEN10_MAX_REF_SURFACES              8
  46
  47 #define GEN10_HEVC_NUM_MAX_REF_L0           3
  48 #define GEN10_HEVC_NUM_MAX_REF_L1           1
  49
  50 #define GEN10_HEVC_VME_REF_WIN              64
  51
  52 #define GEN10_HEVC_MAX_LCU_SIZE             64
  53
  54 #define BYTES2UINT32(a)      (a / sizeof(uint32_t))
  55
  56 enum GEN10_HEVC_MEDIA_STATE_TYPE {
  57     GEN10_HEVC_MEDIA_STATE_BRC_INIT_RESET = 0,
  58     GEN10_HEVC_MEDIA_STATE_BRC_UPDATE     = 1,
  59     GEN10_HEVC_MEDIA_STATE_BRC_LCU_UPDATE = 2,
  60     GEN10_HEVC_MEDIA_STATE_MBENC_INTRA    = 3,
  61     GEN10_HEVC_MEDIA_STATE_MBENC_LCU32    = 4,
  62     GEN10_HEVC_MEDIA_STATE_MBENC_LCU64    = 5,
  63     GEN10_HEVC_MEDIA_STATE_4XME           = 6,
  64     GEN10_HEVC_MEDIA_STATE_16XME          = 7,
  65     GEN10_HEVC_MEDIA_STATE_NO_SCALING     = 8,
  66     GEN10_HEVC_MEDIA_STATE_2X_SCALING     = 9,
  67     GEN10_HEVC_MEDIA_STATE_4X_SCALING     = 10,
  68     GEN10_HEVC_MEDIA_STATE_2X_4X_SCALING  = 11,
  69     GEN10_HEVC_MEDIA_STATE_16X_SCALING    = 12
  70 };
  71
  72 struct gen10_hevc_enc_kernel_walker_parameter {
  73     unsigned int use_scoreboard;
  74     unsigned int no_dependency;
  75     unsigned int use_vertical_scan;
  76     unsigned int use_custom_walker;
  77     unsigned int walker_degree;
  78     unsigned int resolution_x;
  79     unsigned int resolution_y;
  80 };
  81
  82 struct gen10_hevc_enc_kernel_parameter {
  83     uint32_t curbe_size;
  84     uint32_t inline_data_size;
  85     uint32_t sampler_size;
  86 };
  87
  88 struct gen10_hevc_enc_scoreboard_parameter {
  89     uint32_t mask;
  90     uint32_t type;
  91     uint32_t enable;
  92     uint32_t no_dependency;
  93 };
  94
  95 struct gen10_hevc_scaling_conversion_param {
  96     struct object_surface *input_surface;
  97     struct object_surface *converted_output_surface;
  98     struct object_surface *scaled_2x_surface;
  99     struct object_surface *scaled_4x_surface;
 100     uint32_t input_width;
 101     uint32_t input_height;
 102     uint32_t output_2x_width;
 103     uint32_t output_2x_height;
 104     uint32_t output_4x_width;
 105     uint32_t output_4x_height;
 106     struct {
 107         uint32_t  ds_type       : 4;
 108         uint32_t  reserved0     : 12;
 109         uint32_t  conv_enable   : 1;
 110         uint32_t  dump_enable   : 1;
 111         uint32_t  is_64lcu      : 1;
 112         uint32_t  reserved1     : 13;
 113     } scale_flag;
 114 };
 115
 116 #define    GEN10_NONE_DS         0
 117 #define    GEN10_2X_DS           1
 118 #define    GEN10_4X_DS           2
 119 #define    GEN10_16X_DS          3
 120 #define    GEN10_2X_4X_DS        4
 121 #define    GEN10_DS_MASK         0x000F
 122
 123 #define    GEN10_DEPTH_CONV_ENABLE    1
 124 #define    GEN10_DEPTH_CONV_DISABLE   0
 125
 126 enum GEN10_HEVC_SCALING_BTI {
 127     GEN10_HEVC_SCALING_10BIT_Y = 0,
 128     GEN10_HEVC_SCALING_10BIT_UV,
 129     GEN10_HEVC_SCALING_8BIT_Y,
 130     GEN10_HEVC_SCALING_8BIT_UV,
 131     GEN10_HEVC_SCALING_4xDS,
 132     GEN10_HEVC_SCALING_MB_STATS,
 133     GEN10_HEVC_SCALING_2xDS,
 134     GEN10_HEVC_SCALING_MB_SPLIT_SURFACE,
 135     GEN10_HEVC_SCALING_LCU32_JOB_QUEUE_SCRATCH_SURFACE,
 136     GEN10_HEVC_SCALING_LCU64_JOB_QUEUE_SCRATCH_SURFACE,
 137     GEN10_HEVC_SCALING_LCU64_64x64_DISTORTION_SURFACE
 138 };
 139
 140 enum GEN10_HEVC_HME_BTI {
 141     GEN10_HEVC_HME_OUTPUT_MV_DATA = 0,
 142     GEN10_HEVC_HME_16xINPUT_MV_DATA,
 143     GEN10_HEVC_HME_4xOUTPUT_DISTORTION,
 144     GEN10_HEVC_HME_VME_PRED_CURR_PIC_IDX0,
 145     GEN10_HEVC_HME_VME_PRED_FWD_PIC_IDX0,
 146     GEN10_HEVC_HME_VME_PRED_BWD_PIC_IDX0,
 147     GEN10_HEVC_HME_VME_PRED_FWD_PIC_IDX1,
 148     GEN10_HEVC_HME_VME_PRED_BWD_PIC_IDX1,
 149     GEN10_HEVC_HME_VME_PRED_FWD_PIC_IDX2,
 150     GEN10_HEVC_HME_VME_PRED_BWD_PIC_IDX2,
 151     GEN10_HEVC_HME_VME_PRED_FWD_PIC_IDX3,
 152     GEN10_HEVC_HME_VME_PRED_BWD_PIC_IDX3,
 153     GEN10_HEVC_HME_4xDS_INPUT,
 154     GEN10_HEVC_HME_BRC_DISTORTION,
 155     GEN10_HEVC_HME_MV_AND_DISTORTION_SUM
 156 };
 157
 158 enum GEN10_HEVC_MBENC_INTRA_BTI {
 159     GEN10_HEVC_MBENC_INTRA_VME_PRED_CURR_PIC_IDX0 = 0,
 160     GEN10_HEVC_MBENC_INTRA_VME_PRED_FWD_PIC_IDX0,
 161     GEN10_HEVC_MBENC_INTRA_VME_PRED_BWD_PIC_IDX0,
 162     GEN10_HEVC_MBENC_INTRA_VME_PRED_FWD_PIC_IDX1,
 163     GEN10_HEVC_MBENC_INTRA_VME_PRED_BWD_PIC_IDX1,
 164     GEN10_HEVC_MBENC_INTRA_VME_PRED_FWD_PIC_IDX2,
 165     GEN10_HEVC_MBENC_INTRA_VME_PRED_BWD_PIC_IDX2,
 166     GEN10_HEVC_MBENC_INTRA_VME_PRED_FWD_PIC_IDX3,
 167     GEN10_HEVC_MBENC_INTRA_VME_PRED_BWD_PIC_IDX3,
 168     GEN10_HEVC_MBENC_INTRA_CURR_Y,
 169     GEN10_HEVC_MBENC_INTRA_CURR_UV,
 170     GEN10_HEVC_MBENC_INTRA_INTERMEDIATE_CU_RECORD,
 171     GEN10_HEVC_MBENC_INTRA_PAK_OBJ0,
 172     GEN10_HEVC_MBENC_INTRA_PAK_CU_RECORD,
 173     GEN10_HEVC_MBENC_INTRA_SCRATCH_SURFACE,
 174     GEN10_HEVC_MBENC_INTRA_CU_QP_DATA,
 175     GEN10_HEVC_MBENC_INTRA_CONST_DATA_LUT,
 176     GEN10_HEVC_MBENC_INTRA_LCU_LEVEL_DATA_INPUT,
 177     GEN10_HEVC_MBENC_INTRA_CONCURRENT_TG_DATA,
 178     GEN10_HEVC_MBENC_INTRA_BRC_COMBINED_ENC_PARAMETER_SURFACE,
 179     GEN10_HEVC_MBENC_INTRA_CU_SPLIT_SURFACE,
 180     GEN10_HEVC_MBENC_INTRA_DEBUG_DUMP
 181 };
 182
 183 enum GEN10_HEVC_MBENC_INTER_LCU32_BTI {
 184     GEN10_HEVC_MBENC_INTER_LCU32_CURR_Y = 0,
 185     GEN10_HEVC_MBENC_INTER_LCU32_CURR_UV,
 186     GEN10_HEVC_MBENC_INTER_LCU32_ENC_CU_RECORD,
 187     GEN10_HEVC_MBENC_INTER_LCU32_PAK_OBJ0,
 188     GEN10_HEVC_MBENC_INTER_LCU32_PAK_CU_RECORD,
 189     GEN10_HEVC_MBENC_INTER_LCU32_VME_PRED_CURR_PIC_IDX0,
 190     GEN10_HEVC_MBENC_INTER_LCU32_VME_PRED_FWD_PIC_IDX0,
 191     GEN10_HEVC_MBENC_INTER_LCU32_VME_PRED_BWD_PIC_IDX0,
 192     GEN10_HEVC_MBENC_INTER_LCU32_VME_PRED_FWD_PIC_IDX1,
 193     GEN10_HEVC_MBENC_INTER_LCU32_VME_PRED_BWD_PIC_IDX1,
 194     GEN10_HEVC_MBENC_INTER_LCU32_VME_PRED_FWD_PIC_IDX2,
 195     GEN10_HEVC_MBENC_INTER_LCU32_VME_PRED_BWD_PIC_IDX2,
 196     GEN10_HEVC_MBENC_INTER_LCU32_VME_PRED_FWD_PIC_IDX3,
 197     GEN10_HEVC_MBENC_INTER_LCU32_VME_PRED_BWD_PIC_IDX3,
 198     GEN10_HEVC_MBENC_INTER_LCU32_CU16x16_QP_DATA,
 199     GEN10_HEVC_MBENC_INTER_LCU32_ENC_CONST_TABLE,
 200     GEN10_HEVC_MBENC_INTER_LCU32_COLOCATED_CU_MV_DATA,
 201     GEN10_HEVC_MBENC_INTER_LCU32_HME_MOTION_PREDICTOR_DATA,
 202     GEN10_HEVC_MBENC_INTER_LCU32_LCU_LEVEL_DATA_INPUT,
 203     GEN10_HEVC_MBENC_INTER_LCU32_LCU_ENC_SCRATCH_SURFACE,
 204     GEN10_HEVC_MBENC_INTER_LCU32_CONCURRENT_TG_DATA,
 205     GEN10_HEVC_MBENC_INTER_LCU32_BRC_COMBINED_ENC_PARAMETER_SURFACE,
 206     GEN10_HEVC_MBENC_INTER_LCU32_JOB_QUEUE_SCRATCH_SURFACE,
 207     GEN10_HEVC_MBENC_INTER_LCU32_CU_SPLIT_DATA_SURFACE,
 208     GEN10_HEVC_MBENC_INTER_LCU32_RESIDUAL_DATA_SCRATCH_SURFACE,
 209     GEN10_HEVC_MBENC_INTER_LCU32_DEBUG_SURFACE
 210 };
 211
 212 enum GEN10_HEVC_MBENC_INTER_LCU64_BTI {
 213     GEN10_HEVC_MBENC_INTER_LCU64_CURR_Y = 0,
 214     GEN10_HEVC_MBENC_INTER_LCU64_CURR_UV,
 215     GEN10_HEVC_MBENC_INTER_LCU64_CU32_ENC_CU_RECORD,
 216     GEN10_HEVC_MBENC_INTER_LCU64_SECOND_CU32_ENC_CU_RECORD,
 217     GEN10_HEVC_MBENC_INTER_LCU64_PAK_OBJ0,
 218     GEN10_HEVC_MBENC_INTER_LCU64_PAK_CU_RECORD,
 219     GEN10_HEVC_MBENC_INTER_LCU64_VME_PRED_CURR_PIC_IDX0,
 220     GEN10_HEVC_MBENC_INTER_LCU64_VME_PRED_FWD_PIC_IDX0,
 221     GEN10_HEVC_MBENC_INTER_LCU64_VME_PRED_BWD_PIC_IDX0,
 222     GEN10_HEVC_MBENC_INTER_LCU64_VME_PRED_FWD_PIC_IDX1,
 223     GEN10_HEVC_MBENC_INTER_LCU64_VME_PRED_BWD_PIC_IDX1,
 224     GEN10_HEVC_MBENC_INTER_LCU64_VME_PRED_FWD_PIC_IDX2,
 225     GEN10_HEVC_MBENC_INTER_LCU64_VME_PRED_BWD_PIC_IDX2,
 226     GEN10_HEVC_MBENC_INTER_LCU64_VME_PRED_FWD_PIC_IDX3,
 227     GEN10_HEVC_MBENC_INTER_LCU64_VME_PRED_BWD_PIC_IDX3,
 228     GEN10_HEVC_MBENC_INTER_LCU64_CU16x16_QP_DATA,
 229     GEN10_HEVC_MBENC_INTER_LCU64_CU32_ENC_CONST_TABLE,
 230     GEN10_HEVC_MBENC_INTER_LCU64_COLOCATED_CU_MV_DATA,
 231     GEN10_HEVC_MBENC_INTER_LCU64_HME_MOTION_PREDICTOR_DATA,
 232     GEN10_HEVC_MBENC_INTER_LCU64_LCU_LEVEL_DATA_INPUT,
 233     GEN10_HEVC_MBENC_INTER_LCU64_CU32_LCU_ENC_SCRATCH_SURFACE,
 234     GEN10_HEVC_MBENC_INTER_LCU64_64X64_DISTORTION_SURFACE,
 235     GEN10_HEVC_MBENC_INTER_LCU64_CONCURRENT_TG_DATA,
 236     GEN10_HEVC_MBENC_INTER_LCU64_BRC_COMBINED_ENC_PARAMETER_SURFACE,
 237     GEN10_HEVC_MBENC_INTER_LCU64_CU32_JOB_QUEUE_1D_SURFACE,
 238     GEN10_HEVC_MBENC_INTER_LCU64_CU32_JOB_QUEUE_2D_SURFACE,
 239     GEN10_HEVC_MBENC_INTER_LCU64_CU32_RESIDUAL_DATA_SCRATCH_SURFACE,
 240     GEN10_HEVC_MBENC_INTER_LCU64_CU_SPLIT_DATA_SURFACE,
 241     GEN10_HEVC_MBENC_INTER_LCU64_CURR_Y_2xDS,
 242     GEN10_HEVC_MBENC_INTER_LCU64_INTERMEDIATE_CU_RECORD,
 243     GEN10_HEVC_MBENC_INTER_LCU64_CONST64_DATA_LUT,
 244     GEN10_HEVC_MBENC_INTER_LCU64_LCU_STORAGE_SURFACE,
 245     GEN10_HEVC_MBENC_INTER_LCU64_VME_PRED_CURR_PIC_2xDS_IDX0,
 246     GEN10_HEVC_MBENC_INTER_LCU64_VME_PRED_FWD_PIC_2xDS_IDX0,
 247     GEN10_HEVC_MBENC_INTER_LCU64_VME_PRED_BWD_PIC_2xDS_IDX0,
 248     GEN10_HEVC_MBENC_INTER_LCU64_VME_PRED_FWD_PIC_2xDS_IDX1,
 249     GEN10_HEVC_MBENC_INTER_LCU64_VME_PRED_BWD_PIC_2xDS_IDX1,
 250     GEN10_HEVC_MBENC_INTER_LCU64_VME_PRED_FWD_PIC_2xDS_IDX2,
 251     GEN10_HEVC_MBENC_INTER_LCU64_VME_PRED_BWD_PIC_2xDS_IDX2,
 252     GEN10_HEVC_MBENC_INTER_LCU64_VME_PRED_FWD_PIC_2xDS_IDX3,
 253     GEN10_HEVC_MBENC_INTER_LCU64_VME_PRED_BWD_PIC_2xDS_IDX3,
 254     GEN10_HEVC_MBENC_INTER_LCU64_JOB_QUEUE_1D_SURFACE,
 255     GEN10_HEVC_MBENC_INTER_LCU64_JOB_QUEUE_2D_SURFACE,
 256     GEN10_HEVC_MBENC_INTER_LCU64_RESIDUAL_DATA_SCRATCH_SURFACE,
 257     GEN10_HEVC_MBENC_INTER_LCU64_DEBUG_SURFACE
 258 };
 259
 260 struct gen10_scaling_context {
 261     struct i965_gpe_context gpe_context;
 262 };
 263
 264 #define GEN10_HEVC_ME_DIST_TYPE_INTER_BRC    2
 265 #define GEN10_HEVC_ME_DIST_TYPE_INTRA        0
 266 #define GEN10_HEVC_ME_DIST_TYPE_INTRA_BRC    1
 267
 268 #define GEN10_HEVC_HME_LEVEL_4X              1
 269 #define GEN10_HEVC_HME_LEVEL_16X             2
 270
 271 struct gen10_me_context {
 272     struct i965_gpe_context gpe_context;
 273 };
 274
 275 #define GEN10_HEVC_MBENC_INTRA              0
 276 #define GEN10_HEVC_MBENC_INTER_LCU32        1
 277 #define GEN10_HEVC_MBENC_INTER_LCU64        2
 278
 279 #define GEN10_HEVC_MBENC_I_KRNIDX_G10           0
 280 #define GEN10_HEVC_MBENC_INTER_LCU32_KRNIDX_G10 1
 281 #define GEN10_HEVC_MBENC_INTER_LCU64_KRNIDX_G10 2
 282 #define GEN10_HEVC_MBENC_NUM                    3
 283
 284 #define GEN10_HEVC_MBENC_INTRA              0
 285 #define GEN10_HEVC_MBENC_INTER_LCU32        1
 286 #define GEN10_HEVC_MBENC_INTER_LCU64        2
 287
 288 struct gen10_mbenc_context {
 289     struct i965_gpe_context gpe_contexts[GEN10_HEVC_MBENC_NUM];
 290 };
 291
 292 #define GEN10_HEVC_BRC_HISTORY_BUFFER_SIZE        832
 293 #define GEN10_HEVC_BRC_IMG_STATE_SIZE_PER_PASS    128
 294
 295 #define GEN10_HEVC_BRC_CONST_SURFACE_WIDTH        64
 296 #define GEN10_HEVC_BRC_CONST_SURFACE_HEIGHT       35
 297
 298 #define GEN10_HEVC_BRC_INIT         0
 299 #define GEN10_HEVC_BRC_RESET        1
 300 #define GEN10_HEVC_BRC_FRAME_UPDATE 2
 301 #define GEN10_HEVC_BRC_LCU_UPDATE   3
 302 #define GEN10_HEVC_BRC_NUM          4
 303
 304 struct gen10_brc_context {
 305     struct i965_gpe_context gpe_contexts[GEN10_HEVC_BRC_NUM];
 306 };
 307
 308 struct gen10_hevc_surface_priv {
 309     VADriverContextP ctx;
 310
 311     VASurfaceID scaled_4x_surface_id;
 312     struct object_surface *scaled_4x_surface;
 313     struct i965_gpe_resource gpe_scaled_4x_surface;
 314
 315     VASurfaceID scaled_16x_surface_id;
 316     struct object_surface *scaled_16x_surface;
 317     struct i965_gpe_resource gpe_scaled_16x_surface;
 318
 319     VASurfaceID scaled_2x_surface_id;
 320     struct object_surface *scaled_2x_surface;
 321     struct i965_gpe_resource gpe_scaled_2x_surface;
 322
 323     VASurfaceID converted_surface_id;
 324     struct object_surface *converted_surface;
 325     struct i965_gpe_resource gpe_converted_surface;
 326
 327     struct i965_gpe_resource motion_vector_temporal;
 328
 329     int frame_width;
 330     int frame_height;
 331
 332     int width_ctb;
 333     int height_ctb;
 334
 335     uint32_t is_10bit                  : 1;
 336     uint32_t is_64lcu                  : 1;
 337     uint32_t hme_enabled               : 1;
 338     uint32_t conv_scaling_done         : 1;
 339     uint32_t reserved                  : 28;
 340 };
 341
 342 struct gen10_hevc_gpe_scoreboard {
 343     struct {
 344         uint32_t mask: 8;
 345         uint32_t pad: 22;
 346         uint32_t type: 1;
 347         uint32_t enable: 1;
 348     } scoreboard0;
 349
 350     union {
 351         uint32_t value;
 352         struct {
 353             int32_t delta_x0: 4;
 354             int32_t delta_y0: 4;
 355             int32_t delta_x1: 4;
 356             int32_t delta_y1: 4;
 357             int32_t delta_x2: 4;
 358             int32_t delta_y2: 4;
 359             int32_t delta_x3: 4;
 360             int32_t delta_y3: 4;
 361         } scoreboard1;
 362     } dw1;
 363
 364     union {
 365         uint32_t value;
 366         struct {
 367             int32_t delta_x4: 4;
 368             int32_t delta_y4: 4;
 369             int32_t delta_x5: 4;
 370             int32_t delta_y5: 4;
 371             int32_t delta_x6: 4;
 372             int32_t delta_y6: 4;
 373             int32_t delta_x7: 4;
 374             int32_t delta_y7: 4;
 375         } scoreboard2;
 376     } dw2;
 377 };
 378
 379 struct gen10_hevc_enc_state {
 380     uint32_t frame_width;
 381     uint32_t frame_height;
 382     uint32_t frame_width_2x;
 383     uint32_t frame_height_2x;
 384     uint32_t frame_width_4x;
 385     uint32_t frame_height_4x;
 386     uint32_t frame_width_16x;
 387     uint32_t frame_height_16x;
 388
 389     uint32_t use_hw_scoreboard                        : 1;
 390     uint32_t use_hw_non_stalling_scoreboard           : 1;
 391     uint32_t hme_supported                            : 1;
 392     uint32_t b16xme_supported                         : 1;
 393     uint32_t hme_enabled                              : 1;
 394     uint32_t b16xme_enabled                           : 1;
 395     uint32_t is_10bit                                 : 1;
 396     uint32_t is_64lcu                                 : 1;
 397     uint32_t is_same_ref_list                         : 1;
 398     uint32_t is_col_mvp_enabled                       : 1;
 399     uint32_t sao_2nd_needed                           : 1;
 400     uint32_t sao_first_pass_flag                      : 1;
 401     uint32_t lambda_init                              : 1;
 402     uint32_t rdoq_enabled                             : 1;
 403     uint32_t low_delay                                : 1;
 404     uint32_t reserved                                 : 17;
 405
 406     uint32_t curr_pak_stat_index;
 407     uint32_t frame_number;
 408     uint32_t cu_records_offset;
 409
 410     int thread_num_per_ctb;
 411     int num_regions_in_slice;
 412
 413     int num_pak_passes;
 414     int num_sao_passes;
 415     int curr_pak_idx;
 416
 417     uint32_t profile_level_max_frame;
 418
 419     struct {
 420         int offset_y;
 421         int offset_delta;
 422         uint32_t num_regions;
 423         uint32_t max_height_in_region;
 424         uint32_t num_unit_in_wf;
 425     } hevc_wf_param;
 426
 427     struct {
 428         uint32_t target_usage;
 429
 430         double brc_init_current_target_buf_full_in_bits;
 431         double brc_init_reset_input_bits_per_frame;
 432         double brc_init_reset_buf_size_in_bits;
 433
 434         uint32_t init_vbv_buffer_fullness_in_bit;
 435         uint32_t vbv_buffer_size_in_bit;
 436         int window_size;
 437
 438         uint32_t target_percentage;
 439         uint32_t target_bit_rate;
 440         uint32_t max_bit_rate;
 441         uint32_t min_bit_rate;
 442
 443         int frame_rate_m;
 444         int frame_rate_d;
 445
 446         uint32_t gop_size;
 447         uint32_t gop_p;
 448         uint32_t gop_b;
 449
 450         uint32_t lcu_brc_enabled : 1;
 451         uint32_t brc_inited      : 1;
 452         uint32_t brc_reset       : 1;
 453         uint32_t brc_enabled     : 1;
 454         uint32_t brc_method      : 8;
 455         uint32_t reserved        : 20;
 456     } brc;
 457 };
 458
 459 struct gen10_hevc_enc_context {
 460     void *enc_priv_state;
 461
 462     struct gen10_scaling_context scaling_context;
 463     struct gen10_me_context me_context;
 464     struct gen10_mbenc_context mbenc_context;
 465     struct gen10_brc_context brc_context;
 466
 467     struct i965_gpe_resource res_mb_code_surface;
 468
 469     struct i965_gpe_resource res_16x16_qp_data_surface;
 470     struct i965_gpe_resource res_lculevel_input_data_buffer;
 471     struct i965_gpe_resource res_concurrent_tg_data;
 472     struct i965_gpe_resource res_cu_split_surface;
 473     struct i965_gpe_resource res_kernel_trace_data;
 474     struct i965_gpe_resource res_temp_curecord_lcu32_surface;
 475     struct i965_gpe_resource res_temp2_curecord_lcu32_surface;
 476     struct i965_gpe_resource res_temp_curecord_surface_lcu64;
 477     struct i965_gpe_resource res_enc_scratch_buffer;
 478     struct i965_gpe_resource res_enc_scratch_lcu64_buffer;
 479     struct i965_gpe_resource res_enc_const_table_inter;
 480     struct i965_gpe_resource res_enc_const_table_inter_lcu64;
 481     struct i965_gpe_resource res_enc_const_table_intra;
 482     struct i965_gpe_resource res_scratch_surface;
 483     struct i965_gpe_resource res_jbq_header_buffer;
 484     struct i965_gpe_resource res_jbq_header_lcu64_buffer;
 485     struct i965_gpe_resource res_jbq_data_lcu32_surface;
 486     struct i965_gpe_resource res_jbq_data_lcu64_surface;
 487     struct i965_gpe_resource res_residual_scratch_lcu32_surface;
 488     struct i965_gpe_resource res_residual_scratch_lcu64_surface;
 489     struct i965_gpe_resource res_64x64_dist_buffer;
 490     struct i965_gpe_resource res_mb_stat_surface;
 491     struct i965_gpe_resource res_mb_split_surface;
 492
 493     struct i965_gpe_resource res_s4x_memv_data_surface;
 494     struct i965_gpe_resource res_s4x_me_dist_surface;
 495     struct i965_gpe_resource res_s16x_memv_data_surface;
 496     struct i965_gpe_resource res_mv_dist_sum_buffer;
 497
 498     struct i965_gpe_resource res_brc_history_buffer;
 499     struct i965_gpe_resource res_brc_intra_dist_surface;
 500     struct i965_gpe_resource res_brc_pak_statistics_buffer[2];
 501     struct i965_gpe_resource res_brc_pic_image_state_write_buffer;
 502     struct i965_gpe_resource res_brc_pic_image_state_read_buffer;
 503     struct i965_gpe_resource res_brc_const_data_surface;
 504     struct i965_gpe_resource res_brc_lcu_const_data_buffer;
 505     struct i965_gpe_resource res_brc_mb_qp_surface;
 506     struct i965_gpe_resource res_brc_input_enc_kernel_buffer;
 507     struct i965_gpe_resource res_brc_me_dist_surface;
 508
 509     struct gen10_hevc_enc_lambda_param lambda_param;
 510     struct gen10_hevc_enc_frame_info frame_info;
 511     struct gen10_hevc_enc_common_res common_res;
 512     struct gen10_hevc_enc_status_buffer status_buffer;
 513 };
 514
 515 #endif