src/gen10_huc_common.c

   1 /*
   2  * Copyright © 2018 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Xiang Haihao <haihao.xiang@intel.com>
  26  *
  27  */
  28
  29 #include <assert.h>
  30
  31 #include "intel_batchbuffer.h"
  32 #include "i965_defines.h"
  33 #include "i965_drv_video.h"
  34 #include "gen10_huc_common.h"
  35
  36 #define OUT_BUFFER_2DW(batch, bo, is_target, delta)  do {               \
  37         if (bo) {                                                       \
  38             OUT_BCS_RELOC64(batch,                                      \
  39                             bo,                                         \
  40                             I915_GEM_DOMAIN_RENDER,                     \
  41                             is_target ? I915_GEM_DOMAIN_RENDER : 0,     \
  42                             delta);                                     \
  43         } else {                                                        \
  44             OUT_BCS_BATCH(batch, 0);                                    \
  45             OUT_BCS_BATCH(batch, 0);                                    \
  46         }                                                               \
  47     } while (0)
  48
  49 #define OUT_BUFFER_3DW(batch, bo, is_target, delta)        do { \
  50         OUT_BUFFER_2DW(batch, bo, is_target, delta);            \
  51         if (bo)                                                 \
  52             OUT_BCS_BATCH(batch, i965->intel.mocs_state);       \
  53         else                                                    \
  54             OUT_BCS_BATCH(batch, 0);                            \
  55     } while (0)
  56
  57 void
  58 gen10_huc_pipe_mode_select(VADriverContextP ctx,
  59                            struct intel_batchbuffer *batch,
  60                            struct gen10_huc_pipe_mode_select_parameter *params)
  61 {
  62     BEGIN_BCS_BATCH(batch, 3);
  63
  64     OUT_BCS_BATCH(batch, HUC_PIPE_MODE_SELECT | (3 - 2));
  65     OUT_BCS_BATCH(batch,
  66                   (!!params->huc_stream_object_enabled << 10) |
  67                   (!!params->indirect_stream_out_enabled << 4));
  68     OUT_BCS_BATCH(batch,
  69                   params->media_soft_reset_counter);
  70
  71     ADVANCE_BCS_BATCH(batch);
  72 }
  73
  74 void
  75 gen10_huc_imem_state(VADriverContextP ctx,
  76                      struct intel_batchbuffer *batch,
  77                      struct gen10_huc_imem_state_parameter *params)
  78 {
  79     assert(params->huc_firmware_descriptor >= 1 &&
  80            params->huc_firmware_descriptor <= 255);
  81
  82     BEGIN_BCS_BATCH(batch, 5);
  83
  84     OUT_BCS_BATCH(batch, HUC_IMEM_STATE | (5 - 2));
  85     OUT_BCS_BATCH(batch, 0);
  86     OUT_BCS_BATCH(batch, 0);
  87     OUT_BCS_BATCH(batch, 0);
  88     OUT_BCS_BATCH(batch, params->huc_firmware_descriptor);
  89
  90     ADVANCE_BCS_BATCH(batch);
  91 }
  92
  93 void
  94 gen10_huc_dmem_state(VADriverContextP ctx,
  95                      struct intel_batchbuffer *batch,
  96                      struct gen10_huc_dmem_state_parameter *params)
  97 {
  98     struct i965_driver_data *i965 = i965_driver_data(ctx);
  99
 100     BEGIN_BCS_BATCH(batch, 6);
 101
 102     OUT_BCS_BATCH(batch, HUC_DMEM_STATE | (6 - 2));
 103     OUT_BUFFER_3DW(batch, params->huc_data_source_res->bo, 0, 0);
 104     OUT_BCS_BATCH(batch, params->huc_data_destination_base_address);
 105     OUT_BCS_BATCH(batch, params->huc_data_length);
 106
 107     ADVANCE_BCS_BATCH(batch);
 108 }
 109
 110 void
 111 gen10_huc_virtual_addr_state(VADriverContextP ctx,
 112                              struct intel_batchbuffer *batch,
 113                              struct gen10_huc_virtual_addr_parameter *params)
 114 {
 115     struct i965_driver_data *i965 = i965_driver_data(ctx);
 116     int i;
 117
 118     BEGIN_BCS_BATCH(batch, 49);
 119
 120     OUT_BCS_BATCH(batch, HUC_VIRTUAL_ADDR_STATE | (49 - 2));
 121
 122     for (i = 0; i < 16; i++) {
 123         if (params->regions[i].huc_surface_res && params->regions[i].huc_surface_res->bo)
 124             OUT_BUFFER_3DW(batch,
 125                            params->regions[i].huc_surface_res->bo,
 126                            !!params->regions[i].is_target,
 127                            params->regions[i].offset);
 128         else
 129             OUT_BUFFER_3DW(batch, NULL, 0, 0);
 130     }
 131
 132     ADVANCE_BCS_BATCH(batch);
 133 }
 134
 135 void
 136 gen10_huc_ind_obj_base_addr_state(VADriverContextP ctx,
 137                                   struct intel_batchbuffer *batch,
 138                                   struct gen10_huc_ind_obj_base_addr_parameter *params)
 139 {
 140     struct i965_driver_data *i965 = i965_driver_data(ctx);
 141
 142     BEGIN_BCS_BATCH(batch, 11);
 143
 144     OUT_BCS_BATCH(batch, HUC_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
 145
 146     if (params->huc_indirect_stream_in_object_res)
 147         OUT_BUFFER_3DW(batch,
 148                        params->huc_indirect_stream_in_object_res->bo,
 149                        0,
 150                        0);
 151     else
 152         OUT_BUFFER_3DW(batch, NULL, 0, 0);
 153
 154     OUT_BUFFER_2DW(batch, NULL, 0, 0); /* ignore access upper bound */
 155
 156     if (params->huc_indirect_stream_out_object_res)
 157         OUT_BUFFER_3DW(batch,
 158                        params->huc_indirect_stream_out_object_res->bo,
 159                        1,
 160                        0);
 161     else
 162         OUT_BUFFER_3DW(batch, NULL, 0, 0);
 163
 164     OUT_BUFFER_2DW(batch, NULL, 0, 0); /* ignore access upper bound */
 165
 166     ADVANCE_BCS_BATCH(batch);
 167 }
 168
 169 void
 170 gen10_huc_stream_object(VADriverContextP ctx,
 171                         struct intel_batchbuffer *batch,
 172                         struct gen10_huc_stream_object_parameter *params)
 173 {
 174     BEGIN_BCS_BATCH(batch, 5);
 175
 176     OUT_BCS_BATCH(batch, HUC_STREAM_OBJECT | (5 - 2));
 177     OUT_BCS_BATCH(batch, params->indirect_stream_in_data_length);
 178     OUT_BCS_BATCH(batch,
 179                   (1 << 31) |   /* Must be 1 */
 180                   params->indirect_stream_in_start_address);
 181     OUT_BCS_BATCH(batch, params->indirect_stream_out_start_address);
 182     OUT_BCS_BATCH(batch,
 183                   (!!params->huc_bitstream_enabled << 29) |
 184                   (params->length_mode << 27) |
 185                   (!!params->stream_out << 26) |
 186                   (!!params->emulation_prevention_byte_removal << 25) |
 187                   (!!params->start_code_search_engine << 24) |
 188                   (params->start_code_byte2 << 16) |
 189                   (params->start_code_byte1 << 8) |
 190                   params->start_code_byte0);
 191
 192     ADVANCE_BCS_BATCH(batch);
 193 }
 194
 195 void
 196 gen10_huc_start(VADriverContextP ctx,
 197                 struct intel_batchbuffer *batch,
 198                 struct gen10_huc_start_parameter *params)
 199 {
 200     BEGIN_BCS_BATCH(batch, 2);
 201
 202     OUT_BCS_BATCH(batch, HUC_START | (2 - 2));
 203     OUT_BCS_BATCH(batch, !!params->last_stream_object);
 204
 205     ADVANCE_BCS_BATCH(batch);
 206 }