src/gen10_vdenc_common.h

   1 /*
   2  * Copyright © 2018 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Peng Chen <peng.c.chen@intel.com>
  26  *
  27  */
  28
  29 #ifndef GEN10_VDENC_COMMON_H
  30 #define GEN10_VDENC_COMMON_H
  31
  32 typedef struct _gen10_vdenc_vd_pipeline_flush_param {
  33     struct {
  34         uint32_t hevc_pipeline_done                     : 1;
  35         uint32_t vdenc_pipeline_done                    : 1;
  36         uint32_t mfl_pipeline_done                      : 1;
  37         uint32_t mfx_pipeline_done                      : 1;
  38         uint32_t vd_cmd_msg_parser_done                 : 1;
  39         uint32_t reserved0                              : 11;
  40         uint32_t hevc_pipeline_flush                    : 1;
  41         uint32_t vdenc_pipeline_flush                   : 1;
  42         uint32_t mfl_pipeline_flush                     : 1;
  43         uint32_t mfx_pipeline_flush                     : 1;
  44         uint32_t reserved1                              : 12;
  45     } dw1;
  46 } gen10_vdenc_vd_pipeline_flush_param;
  47
  48 #define GEN10_VDENC_HEVC_CODEC      0
  49 #define GEN10_VDENC_VP9_CODEC       1
  50 #define GEN10_VDENC_AVC_CODEC       2
  51
  52 #define GEN10_VDENC_CHROMA_420      1
  53 #define GEN10_VDENC_CHROMA_422      2
  54 #define GEN10_VDENC_CHROMA_444      3
  55
  56 typedef struct _gen10_vdenc_pipe_mode_select_param {
  57     struct {
  58         uint32_t codec_type                             : 4;
  59         uint32_t reserved0                              : 1;
  60         uint32_t frame_statics_streamout_enabled        : 1;
  61         uint32_t vdenc_pak_obj_cmd_streamout_enabled    : 1;
  62         uint32_t tlb_prefetch_enabled                   : 1;
  63         uint32_t pak_threshold_check_enabled            : 1;
  64         uint32_t vdenc_streamin_enabled                 : 1;
  65         uint32_t downscaled_8x_write_disable            : 1;
  66         uint32_t downscaled_4x_write_disable            : 1;
  67         uint32_t bit_depth                              : 3;
  68         uint32_t pak_chroma_subsampling_type            : 2;
  69         uint32_t reserved1                              : 14;
  70         uint32_t speed_mode_fetch_optimation_enabled    : 1;
  71     } dw1;
  72 } gen10_vdenc_pipe_mode_select_param;
  73
  74
  75 enum GEN10_VDENC_SURFACE_TYPE {
  76     GEN10_VDENC_SRC_SURFACE = 0,
  77     GEN10_VDENC_REF_SURFACE = 1,
  78     GEN10_VDENC_DS_REF_SURFACE = 2
  79 };
  80
  81 #define GEN10_VDENC_COLOR_SPACE_BT601 0
  82 #define GEN10_VDENC_COLOR_SPACE_BT709 1
  83
  84 #define GEN10_VDENC_TILEWALK_XMAJOR   0
  85 #define GEN10_VDENC_TILEWALK_YMAJOR   1
  86
  87 typedef struct _gen10_vdenc_surface_state_param {
  88     struct {
  89         uint32_t crcb_offset_vdirection                 : 2;
  90         uint32_t surface_format_byte_swizzle            : 1;
  91         uint32_t color_space_conversion                 : 1;
  92         uint32_t width                                  : 14;
  93         uint32_t height                                 : 14;
  94     } dw0;
  95
  96     struct {
  97         uint32_t tile_walk                              : 1;
  98         uint32_t tiled_surface_enabled                  : 1;
  99         uint32_t half_pitch_for_chroma_enabled          : 1;
 100         uint32_t pitch_in_bytes                         : 17;
 101         uint32_t chroma_downsample_filter_control       : 3;
 102         uint32_t reserved                               : 4;
 103         uint32_t interleave_chroma                      : 1;
 104         uint32_t format                                 : 4;
 105     } dw1;
 106
 107     struct {
 108         uint32_t y_offset_for_cb                        : 15;
 109         uint32_t reserved0                              : 1;
 110         uint32_t x_offset_for_cb                        : 15;
 111         uint32_t reserved1                              : 1;
 112     } dw2;
 113
 114     struct {
 115         uint32_t y_offset_for_cr                        : 16;
 116         uint32_t x_offset_for_cr                        : 13;
 117         uint32_t reserved1                              : 3;
 118     } dw3;
 119 } gen10_vdenc_surface_state_param;
 120
 121 typedef struct _gen10_vdenc_pipe_buf_addr_state_param {
 122     struct i965_gpe_resource *downscaled_fwd_ref[2];
 123     struct i965_gpe_resource *downscaled_bwd_ref[1];
 124     struct i965_gpe_resource *uncompressed_picture;
 125     struct i965_gpe_resource *stream_data_picture;
 126     struct i965_gpe_resource *row_store_scratch_buf;
 127     struct i965_gpe_resource *collocated_mv_buf;
 128     struct i965_gpe_resource *fwd_ref[3];
 129     struct i965_gpe_resource *bwd_ref[1];
 130     struct i965_gpe_resource *statictics_streamout_buf;
 131     struct i965_gpe_resource *downscaled_fwd_ref_4x[2];
 132     struct i965_gpe_resource *lcu_pak_obj_cmd_buf;
 133     struct i965_gpe_resource *scaled_ref_8x;
 134     struct i965_gpe_resource *scaled_ref_4x;
 135     struct i965_gpe_resource *vp9_segmentation_map_streamin_buf;
 136     struct i965_gpe_resource *vp9_segmentation_map_streamout_buf;
 137
 138     struct {
 139         uint32_t weights_histogram_streamout_offset;
 140     } dw61;
 141 } gen10_vdenc_pipe_buf_addr_state_param;
 142
 143 typedef struct _gen10_vdenc_costs_state_param {
 144     struct {
 145         uint32_t hme_mvcost0                            : 8;
 146         uint32_t hme_mvcost1                            : 8;
 147         uint32_t hme_mvcost2                            : 8;
 148         uint32_t hme_mvcost3                            : 8;
 149     } dw1;
 150
 151     struct {
 152         uint32_t hme_mvcost4                            : 8;
 153         uint32_t hme_mvcost5                            : 8;
 154         uint32_t hme_mvcost6                            : 8;
 155         uint32_t hme_mvcost7                            : 8;
 156     } dw2;
 157
 158     struct {
 159         uint32_t sad_mvcost0                            : 8;
 160         uint32_t sad_mvcost1                            : 8;
 161         uint32_t sad_mvcost2                            : 8;
 162         uint32_t sad_mvcost3                            : 8;
 163     } dw3;
 164
 165     struct {
 166         uint32_t sad_mvcost4                            : 8;
 167         uint32_t sad_mvcost5                            : 8;
 168         uint32_t sad_mvcost6                            : 8;
 169         uint32_t sad_mvcost7                            : 8;
 170     } dw4;
 171
 172     struct {
 173         uint32_t sad_mvcost8                            : 8;
 174         uint32_t sad_mvcost9                            : 8;
 175         uint32_t sad_mvcost10                           : 8;
 176         uint32_t sad_mvcost11                           : 8;
 177     } dw5;
 178
 179     struct {
 180         uint32_t rd_mvcost0                            : 8;
 181         uint32_t rd_mvcost1                            : 8;
 182         uint32_t rd_mvcost2                            : 8;
 183         uint32_t rd_mvcost3                            : 8;
 184     } dw6;
 185
 186     struct {
 187         uint32_t rd_mvcost4                            : 8;
 188         uint32_t rd_mvcost5                            : 8;
 189         uint32_t rd_mvcost6                            : 8;
 190         uint32_t rd_mvcost7                            : 8;
 191     } dw7;
 192
 193     struct {
 194         uint32_t rd_mvcost8                            : 8;
 195         uint32_t rd_mvcost9                            : 8;
 196         uint32_t rd_mvcost10                           : 8;
 197         uint32_t rd_mvcost11                           : 8;
 198     } dw8;
 199
 200     struct {
 201         uint32_t vp9_near_mv_cost                      : 8;
 202         uint32_t vp9_nearest_mv_cost                   : 8;
 203         uint32_t vp9_zero_mv_cost                      : 8;
 204         uint32_t reserved                              : 8;
 205     } dw9;
 206
 207     struct {
 208         uint32_t skip_8x8_cost                         : 8;
 209         uint32_t merge_8x8_cost                        : 8;
 210         uint32_t skip_16x16_cost                       : 8;
 211         uint32_t merge_16x16_cost                      : 8;
 212     } dw10;
 213
 214     struct {
 215         uint32_t skip_32x32_cost                       : 8;
 216         uint32_t merge_32x32_cost                      : 8;
 217         uint32_t skip_64x64_cost                       : 8;
 218         uint32_t merge_64x64_cost                      : 8;
 219     } dw11;
 220
 221     struct {
 222         uint32_t mode_inter_32x16                      : 8;
 223         uint32_t mode_inter_16x16                      : 8;
 224         uint32_t mode_inter_16x8                       : 8;
 225         uint32_t mode_inter_8x8                        : 8;
 226     } dw12;
 227
 228     struct {
 229         uint32_t mode_inter_32x32                      : 8;
 230         uint32_t mode_inter_bidir                      : 8;
 231         uint32_t ref_id_cost                           : 8;
 232         uint32_t chroma_intra_mode_cost                : 8;
 233     } dw13;
 234
 235     struct {
 236         uint32_t sad_penalty_for_intra_dc_32x32_pred_mode      : 8;
 237         uint32_t sad_penalty_for_intra_dc_8x8_pred_mode        : 8;
 238         uint32_t sad_penalty_for_intra_nondc_32x32_pred_mode   : 8;
 239         uint32_t sad_penalty_for_intra_nondc_8x8_pred_mode     : 8;
 240     } dw14;
 241
 242     struct {
 243         uint32_t rd_penalty_for_intra_dc_32x32_pred_mode       : 8;
 244         uint32_t rd_penalty_for_intra_dc_8x8_pred_mode         : 8;
 245         uint32_t rd_penalty_for_intra_nondc_32x32_pred_mode    : 8;
 246         uint32_t rd_penalty_for_intra_nondc_8x8_pred_mode      : 8;
 247     } dw15;
 248
 249     struct {
 250         uint32_t sad_penalty_for_intra_left_boundary_cu        : 8;
 251         uint32_t sad_penalty_for_intra_top_boundary_cu         : 8;
 252         uint32_t sad_intra_nonpred_mode_cost                   : 8;
 253         uint32_t ibc_ref_id_cost                               : 8;
 254     } dw16;
 255
 256     struct {
 257         uint32_t rd_mode_intra_nonpred                         : 8;
 258         uint32_t mode_intra_32x32                              : 8;
 259         uint32_t mode_intra_16x16                              : 8;
 260         uint32_t mode_intra_8x8                                : 8;
 261     } dw17;
 262
 263     struct {
 264         uint32_t intra_NxN_cost                                : 8;
 265         uint32_t intra_64x64_cost                              : 8;
 266         uint32_t mode_intra_2NxN_32x32CU                       : 8;
 267         uint32_t mode_intra_2NxN_16x16CU                       : 8;
 268     } dw18;
 269
 270     struct {
 271         uint32_t reserved                                      : 8;
 272         uint32_t tu_depth_cost0                                : 8;
 273         uint32_t tu_depth_cost1                                : 8;
 274         uint32_t tu_depth_cost2                                : 8;
 275     } dw19;
 276
 277     struct {
 278         uint32_t intra_tu_4x4_cbf_cost                         : 8;
 279         uint32_t intra_tu_8x8_cbf_cost                         : 8;
 280         uint32_t intra_tu_16x16_cbf_cost                       : 8;
 281         uint32_t intra_tu_32x32_cbf_cost                       : 8;
 282     } dw20;
 283
 284     struct {
 285         uint32_t inter_tu_4x4_cbf_cost                         : 8;
 286         uint32_t inter_tu_8x8_cbf_cost                         : 8;
 287         uint32_t inter_tu_16x16_cbf_cost                       : 8;
 288         uint32_t inter_tu_32x32_cbf_cost                       : 8;
 289     } dw21;
 290
 291     struct {
 292         uint32_t intra_tu_4x4_nzc                              : 8;
 293         uint32_t intra_tu_8x8_nzc                              : 8;
 294         uint32_t intra_tu_16x16_nzc                            : 8;
 295         uint32_t intra_tu_32x32_nzc                            : 8;
 296     } dw22;
 297
 298     struct {
 299         uint32_t intra_tu_4x4_nsigc                            : 8;
 300         uint32_t intra_tu_8x8_nsigc                            : 8;
 301         uint32_t intra_tu_16x16_nsigc                          : 8;
 302         uint32_t intra_tu_32x32_nsigc                          : 8;
 303     } dw23;
 304
 305     struct {
 306         uint32_t intra_tu_4x4_nsubsetc                         : 8;
 307         uint32_t intra_tu_8x8_nsubsetc                         : 8;
 308         uint32_t intra_tu_16x16_nsubsetc                       : 8;
 309         uint32_t intra_tu_32x32_nsubsetc                       : 8;
 310     } dw24;
 311
 312     struct {
 313         uint32_t intra_tu_4x4_nlevelc                          : 8;
 314         uint32_t intra_tu_8x8_nlevelc                          : 8;
 315         uint32_t intra_tu_16x16_nlevelc                        : 8;
 316         uint32_t intra_tu_32x32_nlevelc                        : 8;
 317     } dw25;
 318
 319     struct {
 320         uint32_t inter_tu_4x4_nzc                              : 8;
 321         uint32_t inter_tu_8x8_nzc                              : 8;
 322         uint32_t inter_tu_16x16_nzc                            : 8;
 323         uint32_t inter_tu_32x32_nzc                            : 8;
 324     } dw26;
 325
 326     struct {
 327         uint32_t inter_tu_4x4_nsigc                            : 8;
 328         uint32_t inter_tu_8x8_nsigc                            : 8;
 329         uint32_t inter_tu_16x16_nsigc                          : 8;
 330         uint32_t inter_tu_32x32_nsigc                          : 8;
 331     } dw27;
 332
 333     struct {
 334         uint32_t inter_tu_4x4_nsubsetc                         : 8;
 335         uint32_t inter_tu_8x8_nsubsetc                         : 8;
 336         uint32_t inter_tu_16x16_nsubsetc                       : 8;
 337         uint32_t inter_tu_32x32_nsubsetc                       : 8;
 338     } dw28;
 339
 340     struct {
 341         uint32_t inter_tu_4x4_nlevelc                          : 8;
 342         uint32_t inter_tu_8x8_nlevelc                          : 8;
 343         uint32_t inter_tu_16x16_nlevelc                        : 8;
 344         uint32_t inter_tu_32x32_nlevelc                        : 8;
 345     } dw29;
 346 } gen10_vdenc_costs_state_param;
 347
 348 #define GEN10_PICTURE_TYPE_I        0
 349 #define GEN10_PICTURE_TYPE_P        1
 350 #define GEN10_PICTURE_TYPE_B        2
 351 #define GEN10_PICTURE_TYPE_GPB      3
 352
 353 typedef struct _gen10_vdenc_hevc_vp9_img_state_param {
 354     struct {
 355         uint32_t frame_width_in_pixels_minus_one               : 16;
 356         uint32_t frame_height_in_pixels_minus_one              : 16;
 357     } dw1;
 358
 359     struct {
 360         uint32_t max_cu_size                                   : 2;
 361         uint32_t min_cu_size                                   : 2;
 362         uint32_t max_tu_size_cu64x64_inter                     : 2;
 363         uint32_t max_tu_size_cu64x64_intra                     : 2;
 364         uint32_t max_tu_size_cu32x32_inter                     : 2;
 365         uint32_t max_tu_size_cu32x32_intra                     : 2;
 366         uint32_t max_tu_size_cu16x16_inter                     : 2;
 367         uint32_t max_tu_size_cu16x16_intra                     : 2;
 368         uint32_t max_tu_size_cu8x8_inter                       : 2;
 369         uint32_t max_tu_size_cu8x8_intra                       : 2;
 370         uint32_t picture_type                                  : 2;
 371         uint32_t temporal_mvp_enabled                          : 1;
 372         uint32_t collocated_from_l0_flag                       : 1;
 373         uint32_t long_term_reference_flag_l0                   : 3;
 374         uint32_t long_term_reference_flag_l1                   : 1;
 375         uint32_t lcu_size_control                              : 1;
 376         uint32_t tu_4x4_disable                                : 1;
 377         uint32_t transform_skip                                : 1;
 378         uint32_t costrained_intra_pred_flag                    : 1;
 379     } dw2;
 380
 381     struct {
 382         uint32_t poc_number_for_ref_id0_in_l0                  : 8;
 383         uint32_t poc_number_for_ref_id0_in_l1                  : 8;
 384         uint32_t poc_number_for_ref_id1_in_l0                  : 8;
 385         uint32_t poc_number_for_ref_id1_in_l1                  : 8;
 386     } dw3;
 387
 388     struct {
 389         uint32_t poc_number_for_ref_id2_in_l0                  : 8;
 390         uint32_t poc_number_for_ref_id2_in_l1                  : 8;
 391         uint32_t poc_number_for_ref_id3_in_l0                  : 8;
 392         uint32_t poc_number_for_ref_id3_in_l1                  : 8;
 393     } dw4;
 394
 395     struct {
 396         uint32_t intra_chroma_sad_wt                           : 3;
 397         uint32_t intra_chroma_mode_mask                        : 5;
 398         uint32_t streamin_roi_enabled                          : 1;
 399         uint32_t streamin_panic_enabled                        : 1;
 400         uint32_t sub_pel_mode                                  : 2;
 401         uint32_t intra_sad_measure_adjustment                  : 2;
 402         uint32_t inter_sad_measure_adjustment                  : 2;
 403         uint32_t bme_disable_for_fbr                           : 1;
 404         uint32_t bilinear_filter_enabled                       : 1;
 405         uint32_t luma_intra_partition_mask                     : 5;
 406         uint32_t ref_id_cost_mode_select                       : 1;
 407         uint32_t num_refidx_l0_minus1                          : 4;
 408         uint32_t num_refidx_l1_minus1                          : 4;
 409     } dw5;
 410
 411     struct {
 412         uint32_t intra_8x8_mode_mask                           : 10;
 413         uint32_t intra_16x16_mode_mask                         : 10;
 414         uint32_t intra_32x32_mode_mask                         : 10;
 415         uint32_t vp9_intra_2NxN_NX2n_partition_masks           : 2;
 416     } dw6;
 417
 418     struct {
 419         uint32_t max_dqp_depth                                 : 4;
 420         uint32_t segmentation_enabled                          : 1;
 421         uint32_t segmentation_map_temporal_prediction_enabled  : 1;
 422         uint32_t reserved                                      : 1;
 423         uint32_t tiling_enabled                                : 1;
 424         uint32_t speed_mode                                    : 1;
 425         uint32_t vdenc_streamin_enabled                        : 1;
 426         uint32_t use_left_recon_pix_rollingI                   : 1;
 427         uint32_t use_left_recon_pix                            : 1;
 428         uint32_t stage3_mv_threshold                           : 4;
 429         uint32_t pak_only_multi_pass_enabled                   : 1;
 430         uint32_t pak_prefetch_enabled                          : 1;
 431         uint32_t cre_prefetch_enabled                          : 1;
 432         uint32_t hme_ref1_disable                              : 1;
 433         uint32_t time_budget_overflow_check_enabled            : 1;
 434         uint32_t stage1_dual_list_winner_en                    : 1;
 435         uint32_t stage2_hme_disable                            : 1;
 436         uint32_t stage1_hme_disable                            : 1;
 437         uint32_t inter_shape_mask                              : 8;
 438     } dw7;
 439
 440     struct {
 441         uint32_t stage3_stream0_predictor_list_priority        : 2;
 442         uint32_t stage3_stream1_predictor_list_priority        : 2;
 443         uint32_t stage3_stream2_predictor_list_priority        : 2;
 444         uint32_t stage3_stream3_predictor_list_priority        : 2;
 445         uint32_t stage3_zmv_l0_predictor_list_priority         : 2;
 446         uint32_t stage3_temp_mv_predictor_list_priority        : 2;
 447         uint32_t stage3_hme0_predictor_list_priority           : 2;
 448         uint32_t stage3_hme1_predictor_list_priority           : 2;
 449         uint32_t stage3_cc0123_list0_predictor_list_priority   : 8;
 450         uint32_t stage3_cc0123_list1_predictor_list_priority   : 8;
 451     } dw8;
 452
 453     struct {
 454         uint32_t stage3_shmd0123_predictor_list_priorty        : 8;
 455         uint32_t stage3_zmv_l1_predictor_list_priority         : 2;
 456         uint32_t reserved                                      : 6;
 457         uint32_t num_beta_predictors                           : 4;
 458         uint32_t num_ime_predictors                            : 4;
 459         uint32_t num_merge_candidate_cu_32x32                  : 4;
 460         uint32_t num_merge_candidate_cu_64x64                  : 4;
 461     } dw9;
 462
 463     struct {
 464         uint32_t hme0_x_offset                                 : 8;
 465         uint32_t hme0_y_offset                                 : 8;
 466         uint32_t hme1_x_offset                                 : 8;
 467         uint32_t hme1_y_offset                                 : 8;
 468     } dw10;
 469
 470     struct {
 471         uint32_t vdenc_cache_priority;
 472     } dw11;
 473
 474     struct {
 475         uint32_t lcu_budget                                    : 16;
 476         uint32_t initial_time                                  : 16;
 477     } dw12;
 478
 479     struct {
 480         uint32_t roi_qp_adjustment_for_zone0                   : 4;
 481         uint32_t roi_qp_adjustment_for_zone1                   : 4;
 482         uint32_t roi_qp_adjustment_for_zone2                   : 4;
 483         uint32_t roi_qp_adjustment_for_zone3                   : 4;
 484         uint32_t qp_adjustment_for_current_cu_with_tu_4x4      : 4;
 485         uint32_t qp_adjustment_for_current_cu_with_tu_8x8      : 4;
 486         uint32_t qp_adjustment_for_current_cu_with_tu_16x16    : 4;
 487         uint32_t qp_adjustment_for_current_cu_with_tu_32x32    : 4;
 488     } dw13;
 489
 490     struct {
 491         uint32_t best_distortion_qp_adjustment_for_zone0       : 4;
 492         uint32_t best_distortion_qp_adjustment_for_zone1       : 4;
 493         uint32_t best_distortion_qp_adjustment_for_zone2       : 4;
 494         uint32_t best_distortion_qp_adjustment_for_zone3       : 4;
 495         uint32_t sad_har_threshold0                            : 16;
 496     } dw14;
 497
 498     struct {
 499         uint32_t sad_har_threshold1                            : 16;
 500         uint32_t sad_har_threshold2                            : 16;
 501     } dw15;
 502
 503     struct {
 504         uint32_t min_qp                                        : 8;
 505         uint32_t max_qp                                        : 8;
 506         uint32_t delta_qp_for_non_angintra                     : 4;
 507         uint32_t delta_qp_for_angintra                         : 4;
 508         uint32_t max_delta_qp                                  : 4;
 509         uint32_t mv_length_qp_adjustment_for_zero_mv           : 4;
 510     } dw16;
 511
 512     struct {
 513         uint32_t mid_point_sad_haar                            : 20;
 514         uint32_t reserved                                      : 12;
 515     } dw17;
 516
 517     struct {
 518         uint32_t mv_length_qp_adjustment_for_zone0             : 4;
 519         uint32_t mv_length_qp_adjustment_for_zone1             : 4;
 520         uint32_t mv_length_qp_adjustment_for_zone2             : 4;
 521         uint32_t reserved                                      : 4;
 522         uint32_t mv_length_threshold0                          : 16;
 523     } dw18;
 524
 525     struct {
 526         uint32_t mv_length_threshold1                          : 16;
 527         uint32_t lcu_estimated_size_adjustment                 : 8;
 528         uint32_t num_bits_multiplier                           : 7;
 529         uint32_t reserved                                      : 1;
 530     } dw19;
 531
 532     struct {
 533         uint32_t panic_initial_size_in_dw                      : 16;
 534         uint32_t panic_enabled                                 : 1;
 535         uint32_t reserved                                      : 15;
 536     } dw20;
 537
 538     struct {
 539         uint32_t widi_intra_refresh_pos                        : 9;
 540         uint32_t reserved0                                     : 7;
 541         uint32_t widi_intra_refresh_mb_size_minus_one          : 8;
 542         uint32_t widi_intra_refresh_mode                       : 1;
 543         uint32_t widi_intra_refresh_eable                      : 1;
 544         uint32_t reserved1                                     : 2;
 545         uint32_t qp_ajustment_for_rolling_I                    : 4;
 546     } dw21;
 547
 548     struct {
 549         uint32_t low_luma_intra_quarter_block_flatness_threshold_minus_one  : 5;
 550         uint32_t low_luma_intra_total_block_sad_threshold                   : 3;
 551         uint32_t high_luma_intra_quarter_block_flatness_threshold_minus_one : 5;
 552         uint32_t high_luma_intra_total_block_sad_threshold                  : 3;
 553         uint32_t low_inter_quarter_block_flatness_threshold_minus_one       : 5;
 554         uint32_t low_inter_total_block_sad_threshold                        : 3;
 555         uint32_t high_inter_quarter_block_flatness_threshold_minus_one      : 5;
 556         uint32_t high_inter_total_block_sad_threshold                       : 3;
 557     } dw22;
 558
 559     struct {
 560         uint32_t low_chroma_intra_quarter_block_flatness_threshold_minus_one  : 5;
 561         uint32_t low_chroma_intra_total_block_sad_threshold                   : 3;
 562         uint32_t high_chroma_intra_quarter_block_flatness_threshold_minus_one : 5;
 563         uint32_t high_chroma_intra_total_block_sad_threshold                  : 3;
 564         uint32_t intra_cu_depth_control                                       : 8;
 565         uint32_t inter_cu_depth_control                                       : 8;
 566     } dw23;
 567
 568     struct {
 569         uint32_t qp_for_segment0                                : 8;
 570         uint32_t qp_for_segment1                                : 8;
 571         uint32_t qp_for_segment2                                : 8;
 572         uint32_t qp_for_segment3                                : 8;
 573     } dw24;
 574
 575     struct {
 576         uint32_t qp_for_segment4                                : 8;
 577         uint32_t qp_for_segment5                                : 8;
 578         uint32_t qp_for_segment6                                : 8;
 579         uint32_t qp_for_segment7                                : 8;
 580     } dw25;
 581
 582     struct {
 583         uint32_t rd_qp_lambda                                   : 16;
 584         uint32_t sad_qp_lambda                                  : 9;
 585         uint32_t vp9_dynamic_slice_enabled                      : 1;
 586         uint32_t reserved                                       : 2;
 587         uint32_t delata_qp_for_second_pass                      : 4;
 588     } dw26;
 589
 590     struct {
 591         uint32_t qp_prime_Y_DC                                  : 8;
 592         uint32_t qp_prime_Y_AC                                  : 8;
 593         uint32_t panic_mode_lcu_threshold                       : 16;
 594     } dw27;
 595
 596     struct {
 597         uint32_t rounding_threshold_intra_cu_32x32              : 16;
 598         uint32_t rounding_threshold_merge_cu_32x32              : 16;
 599     } dw28;
 600
 601     struct {
 602         uint32_t rounding_threshold_inter_cu_32x32              : 16;
 603         uint32_t rounding_threshold_merge_cu_16x16              : 16;
 604     } dw29;
 605
 606     struct {
 607         uint32_t rounding_threshold_intra_cu_16x16              : 16;
 608         uint32_t rounding_threshold_inter_cu_16x16              : 16;
 609     } dw30;
 610
 611     struct {
 612         uint32_t rounding_threshold_merge_cu_8x8                : 16;
 613         uint32_t rounding_threshold_intra_cu_8x8                : 16;
 614     } dw31;
 615
 616     struct {
 617         uint32_t rounding_threshold_inter_cu_8x8                : 16;
 618         uint32_t rounding_select0_merge_cu_32x32                : 4;
 619         uint32_t rounding_select1_merge_cu_32x32                : 4;
 620         uint32_t rounding_select0_intra_cu_32x32                : 4;
 621         uint32_t rounding_select1_intra_cu_32x32                : 4;
 622     } dw32;
 623
 624     struct {
 625         uint32_t rounding_select0_inter_cu_32x32                : 4;
 626         uint32_t rounding_select1_inter_cu_32x32                : 4;
 627         uint32_t rounding_select0_merge_cu_16x16                : 4;
 628         uint32_t rounding_select1_merge_cu_16x16                : 4;
 629         uint32_t rounding_select0_intra_cu_16x16                : 4;
 630         uint32_t rounding_select1_intra_cu_16x16                : 4;
 631         uint32_t rounding_select0_inter_cu_16x16                : 4;
 632         uint32_t rounding_select1_inter_cu_16x16                : 4;
 633     } dw33;
 634
 635     struct {
 636         uint32_t rounding_select0_merge_cu_8x8                  : 4;
 637         uint32_t rounding_select1_merge_cu_8x8                  : 4;
 638         uint32_t rounding_select0_intra_cu_8x8                  : 4;
 639         uint32_t rounding_select1_intra_cu_8x8                  : 4;
 640         uint32_t rounding_select0_inter_cu_8x8                  : 4;
 641         uint32_t rounding_select1_inter_cu_8x8                  : 4;
 642         uint32_t num_merge_candidate_cu_8x8                     : 4;
 643         uint32_t num_merge_candidate_cu_16x16                   : 4;
 644     } dw34;
 645
 646     struct {
 647         uint32_t delta_lcu_byte_cost                            : 8;
 648         uint32_t num_32x32_in_flight                            : 4;
 649         uint32_t performance_stats_streamout_enabled            : 1;
 650         uint32_t perf_opt_I4x4                                  : 3;
 651         uint32_t time_budget_check_disable_lcu_num              : 16;
 652     } dw35;
 653
 654     struct {
 655         uint32_t widi_intra_refresh_boundary_ref0               : 9;
 656         uint32_t reserved0                                      : 1;
 657         uint32_t widi_intra_refresh_boundary_ref1               : 9;
 658         uint32_t reserved1                                      : 1;
 659         uint32_t widi_intra_refresh_boundary_ref2               : 9;
 660         uint32_t reserved2                                      : 3;
 661     } dw36;
 662 } gen10_vdenc_hevc_vp9_img_state_param;
 663
 664 typedef struct _gen10_vdenc_walker_state_param {
 665     struct {
 666         uint32_t lcu_start_y_position                           : 9;
 667         uint32_t reserved0                                      : 7;
 668         uint32_t lcu_start_x_position                           : 9;
 669         uint32_t reserved1                                      : 3;
 670         uint32_t first_super_slice                              : 1;
 671         uint32_t reserved2                                      : 3;
 672     } dw1;
 673
 674     struct {
 675         uint32_t next_slice_lcu_start_y_position                : 10;
 676         uint32_t reserved0                                      : 6;
 677         uint32_t next_slice_lcu_start_x_position                : 10;
 678         uint32_t reserved1                                      : 6;
 679     } dw2;
 680
 681     struct {
 682         uint32_t log2_weight_denom_luma                         : 3;
 683         uint32_t reserved                                       : 29;
 684     } dw3;
 685
 686     struct {
 687         uint32_t tile_start_ctu_y                               : 16;
 688         uint32_t tile_start_ctu_x                               : 16;
 689     } dw4;
 690
 691     struct {
 692         uint32_t tile_width                                     : 16;
 693         uint32_t tile_height                                    : 16;
 694     } dw5;
 695 } gen10_vdenc_walker_state_param;
 696
 697 typedef struct _gen10_vdenc_weightsoffsets_state_param {
 698     struct {
 699         uint32_t weights_forward_reference0                     : 8;
 700         uint32_t offset_forward_reference0                      : 8;
 701         uint32_t weights_forward_reference1                     : 8;
 702         uint32_t offset_forward_reference1                      : 8;
 703     } dw1;
 704
 705     struct {
 706         uint32_t weights_forward_reference2                     : 8;
 707         uint32_t offset_forward_reference2                      : 8;
 708         uint32_t reserved                                       : 16;
 709     } dw2;
 710
 711     struct {
 712         uint32_t hevc_vp9_weights_forward_reference0            : 8;
 713         uint32_t hevc_vp9_offset_forward_reference0             : 8;
 714         uint32_t hevc_vp9_weights_forward_reference1            : 8;
 715         uint32_t hevc_vp9_offset_forward_reference1             : 8;
 716     } dw3;
 717
 718     struct {
 719         uint32_t hevc_vp9_weights_backward_reference2           : 8;
 720         uint32_t hevc_vp9_offset_backward_reference2            : 8;
 721         uint32_t hevc_vp9_weights_backward_reference0           : 8;
 722         uint32_t hevc_vp9_offset_backward_reference0            : 8;
 723     } dw4;
 724 } gen10_vdenc_weightsoffsets_state_param;
 725
 726 void
 727 gen10_vdenc_vd_pipeline_flush(VADriverContextP ctx,
 728                               struct intel_batchbuffer *batch,
 729                               gen10_vdenc_vd_pipeline_flush_param *param);
 730 void
 731 gen10_vdenc_pipe_mode_select(VADriverContextP ctx,
 732                              struct intel_batchbuffer *batch,
 733                              gen10_vdenc_pipe_mode_select_param *param);
 734
 735 void
 736 gen10_vdenc_surface_state(VADriverContextP ctx,
 737                           struct intel_batchbuffer *batch,
 738                           enum GEN10_VDENC_SURFACE_TYPE type,
 739                           gen10_vdenc_surface_state_param *surface0,
 740                           gen10_vdenc_surface_state_param *surface1);
 741
 742 void
 743 gen10_vdenc_walker_state(VADriverContextP ctx,
 744                          struct intel_batchbuffer *batch,
 745                          gen10_vdenc_walker_state_param *param);
 746 void
 747 gen10_vdenc_weightsoffsets_state(VADriverContextP ctx,
 748                                  struct intel_batchbuffer *batch,
 749                                  gen10_vdenc_weightsoffsets_state_param *param);
 750 void
 751 gen10_vdenc_pipe_buf_addr_state(VADriverContextP ctx,
 752                                 struct intel_batchbuffer *batch,
 753                                 gen10_vdenc_pipe_buf_addr_state_param *param);
 754 #endif