2 * Copyright © 2018 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Xiang Haihao <haihao.xiang@intel.com>
29 #ifndef GEN10_VDENC_VP9_H
30 #define GEN10_VDENC_VP9_H
34 #include <intel_bufmgr.h>
36 #include "i965_gpe_utils.h"
37 #include "i965_encoder.h"
38 #include "vp9_probs.h"
45 #define VP9_REF_NONE 0x00
46 #define VP9_REF_LAST 0x01
47 #define VP9_REF_GOLDEN 0x02
48 #define VP9_REF_ALT 0x04
50 #define VP9_SUPER_BLOCK_WIDTH 64
51 #define VP9_SUPER_BLOCK_HEIGHT 64
53 #define VP9_MAX_SEGMENTS 8
55 #define VDENC_VP9_HUC_BRC_INIT_RESET 11
56 #define VDENC_VP9_HUC_BRC_UPDATE 12
57 #define VDENC_VP9_HUC_PROB 13
58 #define VDENC_VP9_HUC_INITIALIZER 14
60 #define VDENC_VP9_HUC_DMEM_DATA_OFFSET 0x2000
61 #define VDENC_VP9_HUC_SUPERFRAME_PASS 2
63 #define VDENC_VP9_BRC_STATS_BUF_SIZE (48 * sizeof(unsigned int))
64 #define VDENC_VP9_BRC_PAK_STATS_BUF_SIZE (64 * sizeof(unsigned int))
65 #define VDENC_VP9_BRC_HISTORY_BUFFER_SIZE 1152
67 #define VDENC_VP9_BRC_MAX_NUM_OF_PASSES 3
68 #define VDENC_VP9_BRC_CONSTANT_DATA_SIZE 1664
70 #define VDENC_VP9_BRC_BITSTREAM_SIZE_BUFFER_SIZE 64
71 #define VDENC_VP9_BRC_BITSTREAM_BYTE_COUNT_OFFSET 0
73 #define VDENC_VP9_BRC_HUC_DATA_BUFFER_SIZE 64
75 #define VDENC_VP9_HUC_DATA_EXTENSION_SIZE 32
77 #define VDENC_HCP_VP9_PIC_STATE_SIZE 168
78 #define VDENC_HCP_VP9_SEGMENT_STATE_SIZE 32
79 #define VDENC_VDENC_CMD0_STATE_SIZE 120
80 #define VDENC_VDENC_CMD1_STATE_SIZE 148
81 #define VDENC_BATCHBUFFER_END_SIZE 4 /* END */
83 #define VDENC_HCP_VP9_PIC_STATE_SIZE_IN_DWS (VDENC_HCP_VP9_PIC_STATE_SIZE >> 2)
84 #define VDENC_HCP_VP9_SEGMENT_STATE_SIZE_IN_DWS (VDENC_HCP_VP9_SEGMENT_STATE_SIZE >> 2)
85 #define VDENC_VDENC_CMD0_STATE_SIZE_IN_DWS (VDENC_VDENC_CMD0_STATE_SIZE >> 2)
86 #define VDENC_VDENC_CMD1_STATE_SIZE_IN_DWS (VDENC_VDENC_CMD1_STATE_SIZE >> 2)
88 enum gen10_vdenc_vp9_walker_degree {
94 #define NUM_KERNELS_PER_GPE_CONTEXT 1
95 #define MAX_VP9_VDENC_SURFACES 128
97 struct gen10_vdenc_vp9_kernel_parameters {
98 unsigned int curbe_size;
99 unsigned int inline_data_size;
100 unsigned int external_data_size;
101 unsigned int sampler_size;
104 struct gen10_vdenc_vp9_kernel_scoreboard_parameters {
108 unsigned int walk_pattern_flag;
111 struct gen10_vdenc_vp9_dys_curbe_data {
113 uint32_t input_frame_width: 16;
114 uint32_t input_frame_height: 16;
118 uint32_t output_frame_width: 16;
119 uint32_t output_frame_height: 16;
130 uint32_t reserved[12];
133 uint32_t input_frame_nv12_bti;
137 uint32_t output_frame_y_bti;
141 uint32_t avs_sample_bti;
145 struct gen10_vdenc_vp9_dys_curbe_parameters {
146 uint32_t input_width;
147 uint32_t input_height;
148 uint32_t output_width;
149 uint32_t output_height;
152 struct gen10_vdenc_vp9_dys_surface_parameters {
153 struct object_surface *input_frame;
154 struct object_surface *output_frame;
155 uint32_t vert_line_stride;
156 uint32_t vert_line_stride_offset;
159 struct gen10_vdenc_vp9_dys_kernel_parameters {
160 uint32_t input_width;
161 uint32_t input_height;
162 uint32_t output_width;
163 uint32_t output_height;
164 struct object_surface *input_surface;
165 struct object_surface *output_surface;
168 enum gen10_vdenc_vp9_dys_binding_table_offset {
169 VP9_BTI_DYS_INPUT_NV12 = 0,
170 VP9_BTI_DYS_OUTPUT_Y = 1,
171 VP9_BTI_DYS_OUTPUT_UV = 2,
172 VP9_BTI_DYS_NUM_SURFACES = 3
175 struct gen10_vdenc_vp9_dys_context {
176 struct i965_gpe_context gpe_context;
179 struct gen10_vdenc_vp9_search_path_delta {
184 struct gen10_vdenc_vp9_streamin_curbe_data {
186 uint32_t skip_mode_enabled: 1;
187 uint32_t adaptive_enabled: 1;
188 uint32_t bi_mix_dis: 1;
189 uint32_t reserved0: 2;
190 uint32_t early_ime_success_enabled: 1;
191 uint32_t reserved1: 1;
192 uint32_t t8x8_flag_for_inter_enabled: 1;
193 uint32_t reserved2: 16;
194 uint32_t early_ime_stop: 8;
198 uint32_t max_num_mvs: 6;
199 uint32_t reserved0: 10;
200 uint32_t bi_weight: 6;
201 uint32_t reserved1: 6;
202 uint32_t uni_mix_disable: 1;
203 uint32_t reserved2: 3;
207 uint32_t max_len_sp: 8;
208 uint32_t max_num_su: 8;
209 uint32_t reserved: 16;
213 uint32_t src_size: 2;
214 uint32_t reserved0: 2;
215 uint32_t mb_type_remap: 2;
216 uint32_t src_access: 1;
217 uint32_t ref_access: 1;
218 uint32_t search_ctrl: 3;
219 uint32_t dual_search_path_option: 1;
220 uint32_t sub_pel_mode: 2;
221 uint32_t skip_type: 1;
222 uint32_t disable_field_cache_alloc: 1;
223 uint32_t inter_chroma_mode: 1;
224 uint32_t ft_enable: 1;
225 uint32_t bme_disable_fbr: 1;
226 uint32_t block_based_skip_enable: 1;
227 uint32_t inter_sad: 2;
228 uint32_t intra_sad: 2;
229 uint32_t sub_mb_part_mask: 7;
230 uint32_t reserved1: 1;
234 uint32_t reserved0: 8;
235 uint32_t picture_height_minus1: 8;
236 uint32_t picture_width: 8;
237 uint32_t reserved1: 8;
241 uint32_t reserved: 8;
242 uint32_t qp_prime_y: 8;
243 uint32_t ref_width: 8;
244 uint32_t ref_height: 8;
248 uint32_t reserved0: 1;
249 uint32_t input_streamin_enabled: 1;
250 uint32_t lcu_size: 1;
251 uint32_t write_distortions: 1;
252 uint32_t use_mv_from_prev_step: 1;
253 uint32_t reserved1: 3;
254 uint32_t super_combine_dist: 8;
255 uint32_t max_vmv_r: 16;
259 uint32_t reserved0: 16;
260 uint32_t mv_ct_scale_factor: 2;
261 uint32_t bilinear_enable: 1;
262 uint32_t src_field_polarity: 1;
263 uint32_t weighted_sad_haar: 1;
264 uint32_t ac_only_haar: 1;
265 uint32_t ref_id_ct_mode: 1;
266 uint32_t reserved1: 1;
267 uint32_t skip_center_mask: 8;
271 uint32_t mode0_ct: 8;
272 uint32_t mode1_ct: 8;
273 uint32_t mode2_ct: 8;
274 uint32_t mode3_ct: 8;
278 uint32_t mode4_ct: 8;
279 uint32_t mode5_ct: 8;
280 uint32_t mode6_ct: 8;
281 uint32_t mode7_ct: 8;
285 uint32_t mode8_ct: 8;
286 uint32_t mode9_ct: 8;
287 uint32_t ref_id_ct: 8;
288 uint32_t chroma_intra_mode_ct: 8;
306 uint32_t num_ref_idx_l0_minus_one: 8;
307 uint32_t num_ref_idx_l1_minus_one: 8;
308 uint32_t ref_streamin_ct: 8;
309 uint32_t roi_enable: 3;
310 uint32_t reserved: 5;
314 uint32_t list0_ref_id0_field_parity: 1;
315 uint32_t list0_ref_id1_field_parity: 1;
316 uint32_t list0_ref_id2_field_parity: 1;
317 uint32_t list0_ref_id3_field_parity: 1;
318 uint32_t list0_ref_id4_field_parity: 1;
319 uint32_t list0_ref_id5_field_parity: 1;
320 uint32_t list0_ref_id6_field_parity: 1;
321 uint32_t list0_ref_id7_field_parity: 1;
322 uint32_t list1_ref_id0_field_parity: 1;
323 uint32_t list1_ref_id1_field_parity: 1;
324 uint32_t reserved: 22;
328 uint32_t prev_mv_read_pos_factor: 8;
329 uint32_t mv_shift_factor: 8;
330 uint32_t reserved: 16;
334 struct gen10_vdenc_vp9_search_path_delta sp_delta_0;
335 struct gen10_vdenc_vp9_search_path_delta sp_delta_1;
336 struct gen10_vdenc_vp9_search_path_delta sp_delta_2;
337 struct gen10_vdenc_vp9_search_path_delta sp_delta_3;
341 struct gen10_vdenc_vp9_search_path_delta sp_delta_4;
342 struct gen10_vdenc_vp9_search_path_delta sp_delta_5;
343 struct gen10_vdenc_vp9_search_path_delta sp_delta_6;
344 struct gen10_vdenc_vp9_search_path_delta sp_delta_7;
348 struct gen10_vdenc_vp9_search_path_delta sp_delta_8;
349 struct gen10_vdenc_vp9_search_path_delta sp_delta_9;
350 struct gen10_vdenc_vp9_search_path_delta sp_delta_10;
351 struct gen10_vdenc_vp9_search_path_delta sp_delta_11;
355 struct gen10_vdenc_vp9_search_path_delta sp_delta_12;
356 struct gen10_vdenc_vp9_search_path_delta sp_delta_13;
357 struct gen10_vdenc_vp9_search_path_delta sp_delta_14;
358 struct gen10_vdenc_vp9_search_path_delta sp_delta_15;
362 struct gen10_vdenc_vp9_search_path_delta sp_delta_16;
363 struct gen10_vdenc_vp9_search_path_delta sp_delta_17;
364 struct gen10_vdenc_vp9_search_path_delta sp_delta_18;
365 struct gen10_vdenc_vp9_search_path_delta sp_delta_19;
369 struct gen10_vdenc_vp9_search_path_delta sp_delta_20;
370 struct gen10_vdenc_vp9_search_path_delta sp_delta_21;
371 struct gen10_vdenc_vp9_search_path_delta sp_delta_22;
372 struct gen10_vdenc_vp9_search_path_delta sp_delta_23;
376 struct gen10_vdenc_vp9_search_path_delta sp_delta_24;
377 struct gen10_vdenc_vp9_search_path_delta sp_delta_25;
378 struct gen10_vdenc_vp9_search_path_delta sp_delta_26;
379 struct gen10_vdenc_vp9_search_path_delta sp_delta_27;
383 struct gen10_vdenc_vp9_search_path_delta sp_delta_28;
384 struct gen10_vdenc_vp9_search_path_delta sp_delta_29;
385 struct gen10_vdenc_vp9_search_path_delta sp_delta_30;
386 struct gen10_vdenc_vp9_search_path_delta sp_delta_31;
390 struct gen10_vdenc_vp9_search_path_delta sp_delta_32;
391 struct gen10_vdenc_vp9_search_path_delta sp_delta_33;
392 struct gen10_vdenc_vp9_search_path_delta sp_delta_34;
393 struct gen10_vdenc_vp9_search_path_delta sp_delta_35;
397 struct gen10_vdenc_vp9_search_path_delta sp_delta_36;
398 struct gen10_vdenc_vp9_search_path_delta sp_delta_37;
399 struct gen10_vdenc_vp9_search_path_delta sp_delta_38;
400 struct gen10_vdenc_vp9_search_path_delta sp_delta_39;
404 struct gen10_vdenc_vp9_search_path_delta sp_delta_40;
405 struct gen10_vdenc_vp9_search_path_delta sp_delta_41;
406 struct gen10_vdenc_vp9_search_path_delta sp_delta_42;
407 struct gen10_vdenc_vp9_search_path_delta sp_delta_43;
411 struct gen10_vdenc_vp9_search_path_delta sp_delta_44;
412 struct gen10_vdenc_vp9_search_path_delta sp_delta_45;
413 struct gen10_vdenc_vp9_search_path_delta sp_delta_46;
414 struct gen10_vdenc_vp9_search_path_delta sp_delta_47;
418 struct gen10_vdenc_vp9_search_path_delta sp_delta_48;
419 struct gen10_vdenc_vp9_search_path_delta sp_delta_49;
420 struct gen10_vdenc_vp9_search_path_delta sp_delta_50;
421 struct gen10_vdenc_vp9_search_path_delta sp_delta_51;
425 struct gen10_vdenc_vp9_search_path_delta sp_delta_52;
426 struct gen10_vdenc_vp9_search_path_delta sp_delta_53;
427 struct gen10_vdenc_vp9_search_path_delta sp_delta_54;
428 struct gen10_vdenc_vp9_search_path_delta sp_delta_55;
432 uint32_t actual_mb_width: 16;
433 uint32_t actual_mb_height: 16;
437 uint32_t roi_ctrl: 8;
438 uint32_t max_tu_size: 2;
439 uint32_t max_cu_size: 2;
440 uint32_t num_ime_predictors: 4;
441 uint32_t reserved: 8;
442 uint32_t pu_type_ctrl: 8;
446 uint32_t force_mvx0: 16;
447 uint32_t force_mvy0: 16;
451 uint32_t force_mvx1: 16;
452 uint32_t force_mvy1: 16;
456 uint32_t force_mvx2: 16;
457 uint32_t force_mvy2: 16;
461 uint32_t force_mvx3: 16;
462 uint32_t force_mvy3: 16;
466 uint32_t force_ref_idx0: 4;
467 uint32_t force_ref_idx1: 4;
468 uint32_t force_ref_idx2: 4;
469 uint32_t force_ref_idx3: 4;
470 uint32_t num_merge_cand_cu8x8: 4;
471 uint32_t num_merge_cand_cu16x16: 4;
472 uint32_t num_merge_cand_cu32x32: 4;
473 uint32_t num_merge_cand_cu64x64: 4;
478 uint32_t qp_enable: 4;
479 uint32_t seg_id_enable: 1;
480 uint32_t reserved0: 2;
481 uint32_t force_ref_id_enable: 1;
482 uint32_t reserved1: 8;
486 uint32_t force_qp0: 8;
487 uint32_t force_qp1: 8;
488 uint32_t force_qp2: 8;
489 uint32_t force_qp3: 8;
497 uint32_t surf_index_4x_me_mv_output_data;
501 uint32_t surf_index_16x_or_32x_me_mv_input_data;
505 uint32_t surf_index_4x_me_output_dist;
509 uint32_t surf_index_4x_me_output_brc_dist;
513 uint32_t surf_index_vme_fwd_inter_prediction;
517 uint32_t surf_index_vme_bwd_inter_prediction;
521 uint32_t surf_index_vdenc_streamin_output;
525 uint32_t surf_index_vdenc_streamin_input;
529 struct gen10_vdenc_vp9_streamin_curbe_parameters {
530 uint32_t input_width;
531 uint32_t input_height;
532 uint32_t output_width;
533 uint32_t output_height;
536 struct gen10_vdenc_vp9_streamin_surface_parameters {
537 struct object_surface *input_frame;
538 struct object_surface *output_frame;
539 uint32_t vert_line_stride;
540 uint32_t vert_line_stride_offset;
543 struct gen10_vdenc_vp9_streamin_kernel_parameters {
544 uint32_t input_width;
545 uint32_t input_height;
546 uint32_t output_width;
547 uint32_t output_height;
548 struct object_surface *input_surface;
549 struct object_surface *output_surface;
552 enum gen10_vdenc_vp9_streamin_binding_table_offset {
553 VP9_BTI_STREAMIN_INPUT_NV12 = 0,
554 VP9_BTI_STREAMIN_OUTPUT_Y = 1,
555 VP9_BTI_STREAMIN_OUTPUT_UV = 2,
556 VP9_BTI_STREAMIN_NUM_SURFACES = 3
559 struct gen10_vdenc_vp9_streamin_context {
560 struct i965_gpe_context gpe_context;
579 struct gen10_vdenc_vp9_igs {
582 uint32_t dword_length: 12;
584 uint32_t sub_opcode_b: 5;
585 uint32_t sub_opcode_a: 2;
586 uint32_t command_opcode: 4;
587 uint32_t pipeline: 2;
588 uint32_t command_type: 3;
596 uint32_t bidirectional_mix_disable: 1;
598 uint32_t time_budget_overflow_check: 1;
600 uint32_t extended_pak_obj_cmd_enable: 1;
601 uint32_t transform_8x8_flag: 1;
602 uint32_t vdenc_l1_cache_priority: 2;
608 uint32_t bidirectional_weight: 6;
610 uint32_t unidirection_mix_disable: 1;
616 uint32_t picture_width: 16;
621 uint32_t subpel_mode: 2;
623 uint32_t forward_transform_skip_check_enable: 1;
624 uint32_t bme_disable_for_fbr_message: 1;
625 uint32_t block_based_skip_enabled: 1;
626 uint32_t inter_sad_measure_adjustment: 2;
627 uint32_t intra_sad_measure_adjustment: 2;
628 uint32_t sub_macroblock_sub_partition_mask: 7;
629 uint32_t block_based_skip_type: 1;
633 uint32_t picture_height_minus1: 16;
634 uint32_t cre_prefetch_enable: 1;
635 uint32_t hme_ref1_disable: 1;
636 uint32_t mb_slice_threshold_value: 4;
638 uint32_t constrained_intra_prediction_flag: 1;
640 uint32_t picture_type: 2;
645 uint32_t slice_macroblock_height_minus1: 16;
654 uint32_t luma_intra_partition_mask: 5;
655 uint32_t non_skip_zero_mv_const_added: 1;
656 uint32_t non_skip_mb_mode_const_added: 1;
658 uint32_t mv_ct_scaling_factor: 2;
659 uint32_t bilinear_filter_enable: 1;
661 uint32_t ref_id_ct_mode_select: 1;
666 uint32_t mode0_ct: 8;
667 uint32_t mode1_ct: 8;
668 uint32_t mode2_ct: 8;
669 uint32_t mode3_ct: 8;
673 uint32_t mode4_ct: 8;
674 uint32_t mode5_ct: 8;
675 uint32_t mode6_ct: 8;
676 uint32_t mode7_ct: 8;
680 uint32_t mode8_ct: 8;
681 uint32_t mode9_ct: 8;
682 uint32_t ref_id_ct: 8;
683 uint32_t chroma_intra_mode_ct: 8;
687 struct gen10_is_ct mv_ct;
691 uint32_t qp_prime_y: 8;
693 uint32_t target_size_in_word: 8;
705 uint32_t avc_intra_4x4_mode_mask: 9;
707 uint32_t avc_intra_8x8_mode_mask: 9;
712 uint32_t avc_intra_16x16_mode_mask: 4;
713 uint32_t avc_intra_chroma_mode_mask: 4;
714 uint32_t intra_compute_type_intra_compute_type: 2;
723 uint32_t penalty_for_intra_16x16_non_dc_prediction: 8;
724 uint32_t penalty_for_intra_8x8_non_dc_prediction: 8;
725 uint32_t penalty_for_intra_4x4_non_dc_prediction: 8;
734 uint32_t panic_mode_mb_threadhold: 16;
735 uint32_t small_mb_size_in_word: 8;
736 uint32_t large_mb_size_in_word: 8;
740 uint32_t l0_number_of_reference_minus1: 8;
742 uint32_t l1_number_of_reference_minus1: 8;
756 uint32_t hme_ref_windows_combining_threshold: 8;
761 uint32_t max_hmv_r: 16;
762 uint32_t max_vmv_r: 16;
766 struct gen10_is_ct hme_mv_ct;
770 uint32_t roi_qp_adjustment_for_zone0: 4;
771 uint32_t roi_qp_adjustment_for_zone1: 4;
772 uint32_t roi_qp_adjustment_for_zone2: 4;
773 uint32_t roi_qp_adjustment_for_zone3: 4;
774 uint32_t qp_adjustment_for_shape_best_intra_4x4_winner: 4;
775 uint32_t qp_adjustment_for_shape_best_intra_8x8_winner: 4;
776 uint32_t qp_adjustment_for_shape_best_intra_16x16_winner: 4;
781 uint32_t best_distortion_qp_adjustment_for_zone0: 4;
782 uint32_t best_distortion_qp_adjustment_for_zone1: 4;
783 uint32_t best_distortion_qp_adjustment_for_zone2: 4;
784 uint32_t best_distortion_qp_adjustment_for_zone3: 4;
785 uint32_t offset0_for_zone0_neg_zone1_boundary: 16;
789 uint32_t offset1_for_zone1_neg_zone2_boundary: 16;
790 uint32_t offset2_for_zone2_neg_zone3_boundary: 16;
794 uint32_t qp_range_check_upper_bound: 8;
795 uint32_t qp_range_check_lower_bound: 8;
797 uint32_t qp_range_check_value: 4;
802 uint32_t roi_enable: 1;
803 uint32_t fwd_predictor0_mv_enable: 1;
804 uint32_t bdw_predictor1_mv_enable: 1;
805 uint32_t mb_level_qp_enable: 1;
806 uint32_t target_size_in_words_mb_max_size_in_words_mb_enable: 1;
808 uint32_t ppmv_disable: 1;
809 uint32_t coefficient_clamp_enable: 1;
810 uint32_t long_term_reference_frame_bwd_ref0_indicator: 1;
811 uint32_t long_term_reference_frame_fwd_ref2_indicator: 1;
812 uint32_t long_term_reference_frame_fwd_ref1_indicator: 1;
813 uint32_t long_term_reference_frame_fwd_ref0_indicator: 1;
814 uint32_t is_qp_override: 1;
816 uint32_t midpoint_distortion: 16;
820 struct gen10_vdenc_vp9_streamin_state {
822 uint32_t roi_32x32_0_16x16_03: 8;
823 uint32_t max_tu_size: 2;
824 uint32_t max_cu_size: 2;
825 uint32_t num_ime_predictors: 4;
827 uint32_t pu_type_32x32_0_16x16_03: 8;
831 uint32_t force_mv_x_32x32_0_16x16_0: 16;
832 uint32_t force_mv_y_32x32_0_16x16_0: 16;
836 uint32_t force_mv_x_32x32_0_16x16_1: 16;
837 uint32_t force_mv_y_32x32_0_16x16_1: 16;
841 uint32_t force_mv_x_32x32_0_16x16_2: 16;
842 uint32_t force_mv_y_32x32_0_16x16_2: 16;
846 uint32_t force_mv_x_32x32_0_16x16_3: 16;
847 uint32_t force_mv_y_32x32_0_16x16_3: 16;
855 uint32_t force_mv_ref_idx_32x32_0_16x16_0: 4;
856 uint32_t force_mv_ref_idx_32x32_0_16x16_1: 4;
857 uint32_t force_mv_ref_idx_32x32_0_16x16_2: 4;
858 uint32_t force_mv_ref_idx_32x32_0_16x16_3: 4;
859 uint32_t num_merge_candidate_cu_8x8: 4;
860 uint32_t num_merge_candidate_cu_16x16: 4;
861 uint32_t num_merge_candidate_cu_32x32: 4;
862 uint32_t num_merge_candidate_cu_64x64: 4;
866 uint32_t segid_32x32_0_16x16_03_vp9_only: 16;
867 uint32_t qp_en_32x32_0_16x16_03: 4;
868 uint32_t segid_enable: 1;
870 uint32_t force_refid_enable_32x32_0: 4;
871 uint32_t ime_predictor_refid_select_03_32x32_0: 8;
875 uint32_t ime_predictor_0_x_32x32_0: 16;
876 uint32_t ime_predictor_0_y_32x32_0: 16;
880 uint32_t ime_predictor_0_x_32x32_1: 16;
881 uint32_t ime_predictor_0_y_32x32_1: 16;
885 uint32_t ime_predictor_0_x_32x32_2: 16;
886 uint32_t ime_predictor_0_y_32x32_2: 16;
890 uint32_t ime_predictor_0_x_32x32_3: 16;
891 uint32_t ime_predictor_0_y_32x32_3: 16;
895 uint32_t ime_predictor_0_refidx32x32_0: 4;
896 uint32_t ime_predictor_1_refidx32x32_1: 4;
897 uint32_t ime_predictor_2_refidx32x32_2: 4;
898 uint32_t ime_predictor_3_refidx32x32_3: 4;
903 uint32_t panic_model_cu_threshold: 16;
908 uint32_t force_qp_value_16x16_0: 8;
909 uint32_t force_qp_value_16x16_1: 8;
910 uint32_t force_qp_value_16x16_2: 8;
911 uint32_t force_qp_value_16x16_3: 8;
919 struct huc_brc_update_constant_data {
920 uint8_t global_rate_qp_adj_tab_i[64];
921 uint8_t global_rate_qp_adj_tab_p[64];
922 uint8_t global_rate_qp_adj_tab_b[64];
923 uint8_t dist_threshld_i[10];
924 uint8_t dist_threshld_p[10];
925 uint8_t dist_threshld_b[10];
926 uint8_t dist_qp_adj_tab_i[81];
927 uint8_t dist_qp_adj_tab_p[81];
928 uint8_t dist_qp_adj_tab_b[81];
929 int8_t buf_rate_adj_tab_i[72];
930 int8_t buf_rate_adj_tab_p[72];
931 int8_t buf_rate_adj_tab_b[72];
932 uint8_t frame_size_min_tab_p[9];
933 uint8_t frame_size_min_tab_b[9];
934 uint8_t frame_size_min_tab_i[9];
935 uint8_t frame_size_max_tab_p[9];
936 uint8_t frame_size_max_tab_b[9];
937 uint8_t frame_size_max_tab_i[9];
938 uint8_t frame_size_scg_tab_p[9];
939 uint8_t frame_size_scg_tab_b[9];
940 uint8_t frame_size_scg_tab_i[9];
942 uint8_t i_intra_non_pred[42];
943 uint8_t i_intra_16x16[42];
944 uint8_t i_intra_8x8[42];
945 uint8_t i_intra_4x4[42];
946 uint8_t i_intra_chroma[42];
947 uint8_t p_intra_non_pred[42];
948 uint8_t p_intra_16x16[42];
949 uint8_t p_intra_8x8[42];
950 uint8_t p_intra_4x4[42];
951 uint8_t p_intra_chroma[42];
952 uint8_t p_inter_16x8[42];
953 uint8_t p_inter_8x8[42];
954 uint8_t p_inter_16x16[42];
955 uint8_t p_ref_id[42];
956 uint8_t hme_mv_ct[8][42];
960 struct vdenc_vp9_huc_brc_init_dmem {
962 uint32_t profile_level_max_frame;
963 uint32_t init_buffer_fullness;
964 uint32_t buffer_size;
965 uint32_t target_bitrate;
968 uint32_t frame_rate_m;
969 uint32_t frame_rate_d;
973 uint16_t num_p_in_gop;
975 uint16_t frame_width;
976 uint16_t frame_height;
980 uint16_t golden_frame_interval;
981 uint16_t enable_scaling;
982 uint16_t overshoot_cbr;
985 int8_t inst_rate_thresh_p0[4];
987 int8_t inst_rate_thresh_i0[4];
988 int8_t dev_thresh_pb0[8];
989 int8_t dev_thresh_vbr0[8];
990 int8_t dev_thresh_i0[8];
996 uint8_t max_level_ratio[16];
997 uint8_t sliding_window_enable;
998 uint8_t sliding_window_size;
1002 struct vdenc_vp9_huc_brc_update_dmem {
1003 int32_t target_buf_fullness;
1005 int32_t hrd_buffer_fullness_upper;
1006 int32_t hrd_buffer_fullness_lower;
1009 uint16_t start_global_adjust_frame[4] ;
1011 uint16_t cur_height;
1013 uint16_t vdenc_igs_offset;
1014 uint16_t second_level_batchbuffer_size;
1015 uint16_t pic_state_offset;
1018 uint8_t overflow_flag;
1020 uint8_t max_num_paks;
1021 int8_t current_frame_type;
1022 uint8_t qp_threshold[4];
1023 uint8_t global_rate_ratio_threshold[6];
1024 int8_t start_global_adjust_mult[5];
1025 int8_t start_global_adjust_div[5];
1026 int8_t global_rate_ratio_threshold_qp[7];
1027 uint8_t distion_threshld_i[9];
1028 uint8_t distion_threshld_p[9];
1029 uint8_t distion_threshld_b[9];
1030 int8_t max_frame_thresh_i[5];
1031 int8_t max_frame_thresh_p[5];
1032 int8_t max_frame_thresh_b[5];
1033 uint8_t current_pak_pass;
1035 int8_t delta_qp_for_sad_zone0;
1036 int8_t delta_qp_for_sad_zone1;
1037 int8_t delta_qp_for_sad_zone2;
1038 int8_t delta_qp_for_sad_zone3;
1039 int8_t delta_qp_for_mv_zero;
1040 int8_t delta_qp_for_mv_zone0;
1041 int8_t delta_qp_for_mv_zone1;
1042 int8_t delta_qp_for_mv_zone2;
1043 uint8_t temporal_level;
1044 uint8_t segment_map_generating;
1049 struct gen10_vdenc_vp9_status {
1050 uint32_t bytes_per_frame;
1053 struct vdenc_vp9_huc_frame_ctrl {
1054 uint32_t frame_type;
1055 uint32_t show_frame;
1056 uint32_t error_resilient_mode;
1057 uint32_t intra_only;
1058 uint32_t context_reset;
1059 uint32_t last_ref_frame_bias;
1060 uint32_t golden_ref_frame_bias;
1061 uint32_t alt_ref_frame_bias;
1062 uint32_t allow_high_precision_mv;
1063 uint32_t mcomp_filter_mode;
1065 uint32_t refresh_frame_context;
1066 uint32_t frame_parallel_decode;
1067 uint32_t comp_pred_mode;
1068 uint32_t frame_context_idx;
1069 uint32_t sharpness_level;
1071 uint32_t seg_map_update;
1072 uint32_t seg_update_data;
1074 uint8_t log2tile_cols;
1075 uint8_t log2tile_rows;
1079 struct vdenc_vp9_huc_prev_frame_info {
1080 uint32_t intra_only;
1081 uint32_t frame_width;
1082 uint32_t frame_height;
1084 uint32_t show_frame;
1087 struct vdenc_vp9_huc_prob_dmem {
1088 uint32_t huc_pass_num;
1089 uint32_t frame_width;
1090 uint32_t frame_height;
1092 char segment_ref[VP9_MAX_SEGMENTS];
1093 uint8_t segment_skip[VP9_MAX_SEGMENTS];
1094 uint8_t seg_code_abs;
1095 uint8_t seg_temporal_update;
1096 uint8_t last_ref_index;
1097 uint8_t golden_ref_index;
1098 uint8_t alt_ref_index;
1099 uint8_t refresh_frame_flags;
1100 uint8_t ref_frame_flags;
1101 uint8_t context_frame_types;
1102 struct vdenc_vp9_huc_frame_ctrl frame_ctrl;
1103 struct vdenc_vp9_huc_prev_frame_info prev_frame_info;
1105 uint8_t frame_to_show;
1106 uint8_t load_key_framede_fault_probs;
1107 uint32_t frame_size;
1110 uint16_t loop_filter_level_bit_offset;
1111 uint16_t qindex_bit_offset;
1112 uint16_t seg_bit_offset;
1113 uint16_t seg_length_in_bits;
1114 uint16_t uncomp_hdr_total_length_in_bits;
1115 uint16_t seg_update_disable;
1116 int32_t repak_threshold[256];
1117 uint16_t pic_state_offset;
1118 uint16_t slb_block_size;
1119 uint8_t streamin_enable;
1120 uint8_t streamin_segenable;
1121 uint8_t disable_dma;
1122 uint8_t ivf_header_size;
1126 struct vp9_huc_prob_dmem {
1127 uint32_t huc_pass_num; // dw0
1128 uint32_t frame_width; // dw1
1129 uint32_t frame_height; // dw2
1130 uint32_t max_num_pak_passes; // dw3
1131 int32_t repak_saving_thr; // dw4
1132 uint8_t frame_qp[VP9_MAX_SEGMENTS]; // dw5,6
1133 uint8_t loop_filter_level[VP9_MAX_SEGMENTS]; // dw7,8
1134 uint8_t segment_ref[VP9_MAX_SEGMENTS]; // dw9,10
1135 uint8_t segment_skip[VP9_MAX_SEGMENTS]; // dw11,12
1136 uint8_t seg_code_abs; // dw13
1137 uint8_t seg_temporal_update;
1138 uint8_t last_ref_index;
1139 uint8_t golden_ref_index;
1140 uint8_t alt_ref_index; // dw14
1141 uint8_t refresh_frame_flags;
1142 uint8_t ref_frame_flags;
1143 uint8_t context_frame_types;
1144 struct vdenc_vp9_huc_frame_ctrl frame_ctrl; // dw15 - 38
1145 struct vdenc_vp9_huc_prev_frame_info prev_frame_info; // dw39 - 43
1146 uint8_t brc_enable; // dw44
1148 uint8_t frame_to_show;
1149 uint8_t load_key_frame_default_probs;
1150 uint32_t frame_size; // dw45
1151 uint32_t hcp_is_control; // dw46
1152 uint32_t repak; // dw47
1153 uint16_t loop_filter_level_bit_offset; // dw48
1154 uint16_t qindex_bit_offset;
1155 uint16_t seg_bit_offset; // dw49
1156 uint16_t seg_length_in_bits;
1157 uint16_t uncomp_hdr_total_length_in_bits; // dw50
1158 uint16_t seg_update_disable;
1159 uint32_t repak_threshold[256]; // dw51 - 306
1160 uint8_t pad0[52]; // dw307 - 319
1163 struct vdenc_vp9_cu_data {
1165 uint32_t cu_size: 2;
1167 uint32_t cu_part_mode: 2;
1169 uint32_t intra_chroma_mode0: 4;
1171 uint32_t intra_chroma_mode1: 4;
1172 uint32_t cu_pred_mode0: 1;
1173 uint32_t cu_pred_mode1: 1;
1175 uint32_t interpred_comp0: 1;
1176 uint32_t interpred_comp1: 1;
1181 uint32_t intra_mode0: 4;
1183 uint32_t intra_mode1: 4;
1185 uint32_t intra_mode2: 4;
1187 uint32_t intra_mode3: 4;
1232 uint32_t refframe_part0_l0: 2; // 0=intra,1=last,2=golden,3=altref
1234 uint32_t refframe_part1_l0: 2; // 0=intra,1=last,2=golden,3=altref
1236 uint32_t refframe_part0_l1: 2; // 0=intra,1=last,2=golden,3=altref
1238 uint32_t refframe_part1_l1: 2; // 0=intra,1=last,2=golden,3=altref
1240 uint32_t round_part0: 3;
1242 uint32_t round_part1: 3;
1247 uint32_t tu_size0: 2;
1248 uint32_t tu_size1: 2;
1250 uint32_t segidx_pred0: 1;
1251 uint32_t segidx_pred1: 1;
1252 uint32_t segidx_part0: 3;
1253 uint32_t segidx_part1: 3;
1254 uint32_t mc_filtertype_part0: 2;
1255 uint32_t mc_filtertype_part1: 2;
1268 struct vdenc_vp9_last_frame_status {
1269 uint16_t frame_width;
1270 uint16_t frame_height;
1271 uint8_t is_key_frame;
1273 uint8_t refresh_frame_context;
1274 uint8_t frame_context_idx;
1276 uint8_t segment_enabled;
1279 struct huc_initializer_dmem {
1280 uint32_t output_size;
1281 uint32_t total_output_commands;
1282 uint8_t target_usage;
1285 uint8_t reserved[37];
1287 uint16_t start_in_bytes;
1290 uint32_t batch_buffer_end;
1291 } output_command[50];
1294 struct huc_initializer_data {
1295 uint32_t total_commands;
1298 uint16_t size_of_data;
1300 } input_command[50];
1303 struct huc_initializer_input_command1 {
1304 uint32_t frame_width_in_min_cb_minus1;
1305 uint32_t frame_height_in_min_cb_minus1;
1306 uint32_t log2_min_coding_block_size_minus3;
1307 uint8_t vdenc_streamin_enabled;
1308 uint8_t pak_only_multi_pass_enabled;
1309 uint16_t num_ref_idx_l0_active_minus1;
1310 uint16_t sad_qp_lambda;
1311 uint16_t rd_qp_lambda;
1313 uint16_t num_ref_idx_l1_active_minus1;
1315 uint8_t roi_streamin_enabled;
1316 int8_t roi_delta_qp[8];
1317 uint8_t fwd_poc_num_for_ref_id0_in_l0;
1318 uint8_t fwd_poc_num_for_ref_id0_in_l1;
1319 uint8_t fwd_poc_num_for_ref_id1_in_l0;
1320 uint8_t fwd_poc_num_for_ref_id1_in_l1;
1321 uint8_t fwd_poc_num_for_ref_id2_in_l0;
1322 uint8_t fwd_poc_num_for_ref_id2_in_l1;
1323 uint8_t fwd_poc_num_for_ref_id3_in_l0;
1324 uint8_t fwd_poc_num_for_ref_id3_in_l1;
1325 uint8_t enable_rolling_intra_refresh;
1326 int8_t qp_delta_for_inserted_intra;
1327 uint16_t intra_insertion_size;
1328 uint16_t intra_insertion_location;
1330 uint8_t rounding_enabled;
1331 uint8_t use_default_qp_deltas;
1332 uint8_t panic_enabled;
1333 uint8_t reserved1[2];
1335 uint16_t dst_frame_width_minus1;
1336 uint16_t dst_frame_height_minus1;
1337 uint8_t segment_enabled;
1338 uint8_t prev_frame_segment_enabled;
1339 uint8_t segment_map_streamin_enabled;
1340 uint8_t luma_ac_qindex;
1341 int8_t luma_dc_qindex_delta;
1342 uint8_t reserved2[3];
1343 int16_t segment_qindex_delta[8];
1346 struct gen10_vdenc_vp9_context {
1347 struct i965_gpe_table *gpe_table;
1349 struct gen10_vdenc_vp9_dys_context dys_context;
1350 struct gen10_vdenc_vp9_streamin_context streamin_context;
1352 struct intel_fraction framerate;
1355 uint32_t res_height;
1356 uint32_t frame_width;
1357 uint32_t frame_height;
1358 uint32_t max_frame_width;
1359 uint32_t max_frame_height;
1360 uint32_t frame_width_in_mbs;
1361 uint32_t frame_height_in_mbs;
1362 uint32_t frame_width_in_mi_units;
1363 uint32_t frame_height_in_mi_units;
1364 uint32_t frame_width_in_sbs; /* in super blocks */
1365 uint32_t frame_height_in_sbs; /* in super blocks */
1366 uint32_t down_scaled_width_in_mb4x;
1367 uint32_t down_scaled_height_in_mb4x;
1368 uint32_t down_scaled_width_4x;
1369 uint32_t down_scaled_height_4x;
1370 uint32_t down_scaled_width_in_mb16x;
1371 uint32_t down_scaled_height_in_mb16x;
1372 uint32_t down_scaled_width_16x;
1373 uint32_t down_scaled_height_16x;
1374 uint32_t target_bit_rate; /* in kbps */
1375 uint32_t max_bit_rate; /* in kbps */
1376 uint32_t min_bit_rate; /* in kbps */
1377 uint64_t init_vbv_buffer_fullness_in_bit;
1378 uint64_t vbv_buffer_size_in_bit;
1379 uint16_t sad_qp_lambda;
1380 uint16_t rd_qp_lambda;
1381 uint8_t ref_frame_flag;
1382 uint8_t num_ref_frames;
1383 uint8_t dys_ref_frame_flag;
1384 double current_target_buf_full_in_bits;
1385 double input_bits_per_frame;
1387 uint32_t brc_initted: 1;
1388 uint32_t brc_need_reset: 1;
1389 uint32_t brc_enabled: 1;
1390 uint32_t internal_rate_mode: 4;
1391 uint32_t current_pass: 4;
1392 uint32_t num_passes: 4;
1393 uint32_t is_first_pass: 1;
1394 uint32_t is_last_pass: 1;
1396 uint32_t vdenc_pak_threshold_check_enable: 1;
1397 uint32_t is_key_frame: 1;
1398 uint32_t frame_intra_only: 1;
1399 uint32_t vp9_frame_type: 2; // 0: key frame or intra only, 1: others
1401 uint32_t dys_enabled: 1;
1402 uint32_t dys_in_use: 1;
1403 uint32_t is_first_frame: 1;
1404 uint32_t has_hme: 1;
1405 uint32_t need_hme: 1;
1406 uint32_t hme_enabled: 1;
1407 uint32_t has_hme_16x: 1;
1408 uint32_t hme_16x_enabled: 1;
1409 uint32_t allocate_once_done: 1;
1410 uint32_t is_8bit: 1;
1411 uint32_t multiple_pass_brc_enabled: 1;
1412 uint32_t dys_multiple_pass_enbaled: 1;
1413 uint32_t pak_only_pass_enabled: 1;
1414 uint32_t is_super_frame_huc_pass: 1;
1415 uint32_t has_adaptive_repak: 1;
1416 uint32_t vdenc_pak_object_streamout_enable: 1;
1417 uint32_t use_huc: 1;
1418 uint32_t use_hw_scoreboard: 1;
1419 uint32_t use_hw_non_stalling_scoreborad: 1;
1420 uint32_t submit_batchbuffer: 1;
1422 VAEncSequenceParameterBufferVP9 *seq_param;
1423 VAEncSequenceParameterBufferVP9 bogus_seq_param;
1424 VAEncPictureParameterBufferVP9 *pic_param;
1425 VAEncMiscParameterTypeVP9PerSegmantParam *segment_param;
1427 struct i965_gpe_resource brc_history_buffer_res;
1428 struct i965_gpe_resource brc_constant_data_buffer_res;
1429 struct i965_gpe_resource brc_bitstream_size_buffer_res;
1430 struct i965_gpe_resource brc_huc_data_buffer_res;
1432 struct i965_gpe_resource s4x_memv_data_buffer_res;
1433 struct i965_gpe_resource s4x_memv_distortion_buffer_res;
1434 struct i965_gpe_resource s16x_memv_data_buffer_res;
1435 struct i965_gpe_resource output_16x16_inter_modes_buffer_res;
1436 struct i965_gpe_resource mode_decision_buffer_res[2];
1437 struct i965_gpe_resource mv_temporal_buffer_res[2];
1438 struct i965_gpe_resource mb_code_buffer_res;
1439 struct i965_gpe_resource mb_segment_map_buffer_res;
1442 struct i965_gpe_resource hvd_line_buffer_res;
1443 struct i965_gpe_resource hvd_tile_line_buffer_res;
1444 struct i965_gpe_resource deblocking_filter_line_buffer_res;
1445 struct i965_gpe_resource deblocking_filter_tile_line_buffer_res;
1446 struct i965_gpe_resource deblocking_filter_tile_col_buffer_res;
1448 struct i965_gpe_resource metadata_line_buffer_res;
1449 struct i965_gpe_resource metadata_tile_line_buffer_res;
1450 struct i965_gpe_resource metadata_tile_col_buffer_res;
1452 struct i965_gpe_resource segmentid_buffer_res;
1453 struct i965_gpe_resource prob_buffer_res[4];
1454 struct i965_gpe_resource prob_delta_buffer_res;
1455 struct i965_gpe_resource prob_counter_buffer_res;
1457 struct i965_gpe_resource compressed_header_buffer_res;
1458 struct i965_gpe_resource tile_record_streamout_buffer_res;
1459 struct i965_gpe_resource cu_stat_streamout_buffer_res;
1462 struct i965_gpe_resource huc_prob_dmem_buffer_res[2];
1463 struct i965_gpe_resource huc_default_prob_buffer_res;
1464 struct i965_gpe_resource huc_prob_output_buffer_res;
1465 struct i965_gpe_resource huc_pak_insert_uncompressed_header_input_2nd_batchbuffer_res;
1466 struct i965_gpe_resource huc_pak_insert_uncompressed_header_output_2nd_batchbuffer_res;
1469 struct i965_gpe_resource vdenc_row_store_scratch_res;
1470 struct i965_gpe_resource vdenc_brc_stat_buffer_res;
1471 struct i965_gpe_resource vdenc_pic_state_input_2nd_batchbuffer_res[4];
1472 struct i965_gpe_resource vdenc_pic_state_output_2nd_batchbuffer_res[4];
1473 struct i965_gpe_resource vdenc_dys_pic_state_2nd_batchbuffer_res;
1474 struct i965_gpe_resource vdenc_brc_init_reset_dmem_buffer_res;
1475 struct i965_gpe_resource vdenc_brc_update_dmem_buffer_res[VDENC_VP9_BRC_MAX_NUM_OF_PASSES];
1476 struct i965_gpe_resource vdenc_segment_map_stream_out_buffer_res;
1477 struct i965_gpe_resource vdenc_brc_pak_stat_buffer_res;
1478 struct i965_gpe_resource vdenc_sse_src_pixel_row_store_buffer_res;
1479 struct i965_gpe_resource vdenc_data_extension_buffer_res;
1480 struct i965_gpe_resource vdenc_streamin_buffer_res;
1481 struct i965_gpe_resource huc_status2_buffer_res;
1482 struct i965_gpe_resource huc_status_buffer_res;
1484 /* Reconstructed picture */
1485 struct i965_gpe_resource recon_surface_res;
1486 struct i965_gpe_resource scaled_4x_recon_surface_res;
1487 struct i965_gpe_resource scaled_8x_recon_surface_res;
1488 struct i965_gpe_resource scaled_16x_recon_surface_res;
1490 /* HuC CMD initializer */
1491 struct i965_gpe_resource huc_initializer_dmem_buffer_res[VDENC_VP9_BRC_MAX_NUM_OF_PASSES];
1492 struct i965_gpe_resource huc_initializer_data_buffer_res[VDENC_VP9_BRC_MAX_NUM_OF_PASSES];
1493 struct i965_gpe_resource huc_initializer_dys_dmem_buffer_res;
1494 struct i965_gpe_resource huc_initializer_dys_data_buffer_res;
1497 struct object_surface *last_ref_obj;
1498 struct object_surface *golden_ref_obj;
1499 struct object_surface *alt_ref_obj;
1501 struct i965_gpe_resource last_ref_res;
1502 struct i965_gpe_resource golden_ref_res;
1503 struct i965_gpe_resource alt_ref_res;
1506 struct i965_gpe_resource uncompressed_input_yuv_surface_res; // Input
1509 struct i965_gpe_resource res; // Output
1510 uint32_t start_offset;
1511 uint32_t end_offset;
1512 } compressed_bitstream;
1515 struct i965_gpe_resource res;
1516 uint32_t base_offset;
1518 uint32_t bytes_per_frame_offset;
1521 uint32_t coding_unit_offset;
1522 uint32_t mb_code_buffer_size;
1523 char *alias_insert_data;
1524 char *frame_header_data;
1525 int32_t frame_header_length;
1526 vp9_header_bitoffset frame_header;
1527 int32_t vdenc_pic_state_2nd_batchbuffer_index;
1529 struct vdenc_vp9_last_frame_status last_frame_status;
1530 uint32_t frame_number;
1531 uint32_t curr_mv_temporal_index;
1533 uint32_t huc_2nd_batchbuffer_size;
1534 uint32_t cmd1_state_offset_in_2nd_batchbuffer;
1535 uint32_t pic_state_offset_in_2nd_batchbuffer;
1536 uint8_t context_frame_types[4];
1539 #endif /* GEN10_VDENC_VP9_H */