2 * Copyright © 2010-2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Zhou Chang <chang.zhou@intel.com>
35 #include "intel_batchbuffer.h"
36 #include "i965_defines.h"
37 #include "i965_structs.h"
38 #include "i965_drv_video.h"
39 #include "i965_encoder.h"
40 #include "i965_encoder_utils.h"
43 #include "intel_media.h"
45 #define SURFACE_STATE_PADDED_SIZE MAX(SURFACE_STATE_PADDED_SIZE_GEN6, SURFACE_STATE_PADDED_SIZE_GEN7)
46 #define SURFACE_STATE_OFFSET(index) (SURFACE_STATE_PADDED_SIZE * index)
47 #define BINDING_TABLE_OFFSET(index) (SURFACE_STATE_OFFSET(MAX_MEDIA_SURFACES_GEN6) + sizeof(unsigned int) * index)
49 static const uint32_t gen6_mfc_batchbuffer_avc_intra[][4] = {
50 #include "shaders/utils/mfc_batchbuffer_avc_intra.g6b"
53 static const uint32_t gen6_mfc_batchbuffer_avc_inter[][4] = {
54 #include "shaders/utils/mfc_batchbuffer_avc_inter.g6b"
57 static struct i965_kernel gen6_mfc_kernels[] = {
59 "MFC AVC INTRA BATCHBUFFER ",
60 MFC_BATCHBUFFER_AVC_INTRA,
61 gen6_mfc_batchbuffer_avc_intra,
62 sizeof(gen6_mfc_batchbuffer_avc_intra),
67 "MFC AVC INTER BATCHBUFFER ",
68 MFC_BATCHBUFFER_AVC_INTER,
69 gen6_mfc_batchbuffer_avc_inter,
70 sizeof(gen6_mfc_batchbuffer_avc_inter),
76 gen6_mfc_pipe_mode_select(VADriverContextP ctx,
78 struct intel_encoder_context *encoder_context)
80 struct intel_batchbuffer *batch = encoder_context->base.batch;
81 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
83 assert(standard_select == MFX_FORMAT_AVC);
85 BEGIN_BCS_BATCH(batch, 4);
87 OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (4 - 2));
89 (1 << 10) | /* disable Stream-Out , advanced QP/bitrate control need enable it*/
90 ((!!mfc_context->post_deblocking_output.bo) << 9) | /* Post Deblocking Output */
91 ((!!mfc_context->pre_deblocking_output.bo) << 8) | /* Pre Deblocking Output */
92 (0 << 7) | /* disable TLB prefectch */
93 (0 << 5) | /* not in stitch mode */
94 (1 << 4) | /* encoding mode */
95 (2 << 0)); /* Standard Select: AVC */
97 (0 << 20) | /* round flag in PB slice */
98 (0 << 19) | /* round flag in Intra8x8 */
99 (0 << 7) | /* expand NOA bus flag */
100 (1 << 6) | /* must be 1 */
101 (0 << 5) | /* disable clock gating for NOA */
102 (0 << 4) | /* terminate if AVC motion and POC table error occurs */
103 (0 << 3) | /* terminate if AVC mbdata error occurs */
104 (0 << 2) | /* terminate if AVC CABAC/CAVLC decode error occurs */
105 (0 << 1) | /* AVC long field motion vector */
106 (0 << 0)); /* always calculate AVC ILDB boundary strength */
107 OUT_BCS_BATCH(batch, 0);
109 ADVANCE_BCS_BATCH(batch);
113 gen6_mfc_surface_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
115 struct intel_batchbuffer *batch = encoder_context->base.batch;
116 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
118 BEGIN_BCS_BATCH(batch, 6);
120 OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
121 OUT_BCS_BATCH(batch, 0);
123 ((mfc_context->surface_state.height - 1) << 19) |
124 ((mfc_context->surface_state.width - 1) << 6));
126 (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
127 (1 << 27) | /* must be 1 for interleave U/V, hardware requirement */
128 (0 << 22) | /* surface object control state, FIXME??? */
129 ((mfc_context->surface_state.w_pitch - 1) << 3) | /* pitch */
130 (0 << 2) | /* must be 0 for interleave U/V */
131 (1 << 1) | /* must be y-tiled */
132 (I965_TILEWALK_YMAJOR << 0)); /* tile walk, TILEWALK_YMAJOR */
134 (0 << 16) | /* must be 0 for interleave U/V */
135 (mfc_context->surface_state.h_pitch)); /* y offset for U(cb) */
136 OUT_BCS_BATCH(batch, 0);
137 ADVANCE_BCS_BATCH(batch);
141 gen6_mfc_pipe_buf_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
143 struct intel_batchbuffer *batch = encoder_context->base.batch;
144 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
147 BEGIN_BCS_BATCH(batch, 24);
149 OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
151 if (mfc_context->pre_deblocking_output.bo)
152 OUT_BCS_RELOC(batch, mfc_context->pre_deblocking_output.bo,
153 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
156 OUT_BCS_BATCH(batch, 0); /* pre output addr */
158 if (mfc_context->post_deblocking_output.bo)
159 OUT_BCS_RELOC(batch, mfc_context->post_deblocking_output.bo,
160 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
161 0); /* post output addr */
163 OUT_BCS_BATCH(batch, 0);
165 OUT_BCS_RELOC(batch, mfc_context->uncompressed_picture_source.bo,
166 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
167 0); /* uncompressed data */
168 OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo,
169 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
170 0); /* StreamOut data*/
171 OUT_BCS_RELOC(batch, mfc_context->intra_row_store_scratch_buffer.bo,
172 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
174 OUT_BCS_RELOC(batch, mfc_context->deblocking_filter_row_store_scratch_buffer.bo,
175 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
177 /* 7..22 Reference pictures*/
178 for (i = 0; i < ARRAY_ELEMS(mfc_context->reference_surfaces); i++) {
179 if ( mfc_context->reference_surfaces[i].bo != NULL) {
180 OUT_BCS_RELOC(batch, mfc_context->reference_surfaces[i].bo,
181 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
184 OUT_BCS_BATCH(batch, 0);
187 OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo,
188 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
189 0); /* Macroblock status buffer*/
191 ADVANCE_BCS_BATCH(batch);
195 gen6_mfc_ind_obj_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
197 struct intel_batchbuffer *batch = encoder_context->base.batch;
198 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
199 struct gen6_vme_context *vme_context = encoder_context->vme_context;
201 BEGIN_BCS_BATCH(batch, 11);
203 OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
204 OUT_BCS_BATCH(batch, 0);
205 OUT_BCS_BATCH(batch, 0);
206 /* MFX Indirect MV Object Base Address */
207 OUT_BCS_RELOC(batch, vme_context->vme_output.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
208 OUT_BCS_BATCH(batch, 0);
209 OUT_BCS_BATCH(batch, 0);
210 OUT_BCS_BATCH(batch, 0);
211 OUT_BCS_BATCH(batch, 0);
212 OUT_BCS_BATCH(batch, 0);
213 /*MFC Indirect PAK-BSE Object Base Address for Encoder*/
215 mfc_context->mfc_indirect_pak_bse_object.bo,
216 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
219 mfc_context->mfc_indirect_pak_bse_object.bo,
220 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
221 mfc_context->mfc_indirect_pak_bse_object.end_offset);
223 ADVANCE_BCS_BATCH(batch);
227 gen6_mfc_bsp_buf_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
229 struct intel_batchbuffer *batch = encoder_context->base.batch;
230 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
232 BEGIN_BCS_BATCH(batch, 4);
234 OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
235 OUT_BCS_RELOC(batch, mfc_context->bsd_mpc_row_store_scratch_buffer.bo,
236 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
238 OUT_BCS_BATCH(batch, 0);
239 OUT_BCS_BATCH(batch, 0);
241 ADVANCE_BCS_BATCH(batch);
245 gen6_mfc_avc_img_state(VADriverContextP ctx,struct encode_state *encode_state,
246 struct intel_encoder_context *encoder_context)
248 struct intel_batchbuffer *batch = encoder_context->base.batch;
249 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
250 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
251 VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
252 int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
253 int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
255 BEGIN_BCS_BATCH(batch, 13);
256 OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (13 - 2));
258 ((width_in_mbs * height_in_mbs) & 0xFFFF));
260 (height_in_mbs << 16) |
261 (width_in_mbs << 0));
263 (0 << 24) | /*Second Chroma QP Offset*/
264 (0 << 16) | /*Chroma QP Offset*/
265 (0 << 14) | /*Max-bit conformance Intra flag*/
266 (0 << 13) | /*Max Macroblock size conformance Inter flag*/
267 (1 << 12) | /*Should always be written as "1" */
268 (0 << 10) | /*QM Preset FLag */
269 (0 << 8) | /*Image Structure*/
270 (0 << 0) ); /*Current Decoed Image Frame Store ID, reserved in Encode mode*/
272 (400 << 16) | /*Mininum Frame size*/
273 (0 << 15) | /*Disable reading of Macroblock Status Buffer*/
274 (0 << 14) | /*Load BitStream Pointer only once, 1 slic 1 frame*/
275 (0 << 13) | /*CABAC 0 word insertion test enable*/
276 (1 << 12) | /*MVUnpackedEnable,compliant to DXVA*/
277 (1 << 10) | /*Chroma Format IDC, 4:2:0*/
278 (pPicParameter->pic_fields.bits.entropy_coding_mode_flag << 7) | /*0:CAVLC encoding mode,1:CABAC*/
279 (0 << 6) | /*Only valid for VLD decoding mode*/
280 (0 << 5) | /*Constrained Intra Predition Flag, from PPS*/
281 (pSequenceParameter->seq_fields.bits.direct_8x8_inference_flag << 4) | /*Direct 8x8 inference flag*/
282 (pPicParameter->pic_fields.bits.transform_8x8_mode_flag << 3) | /*8x8 or 4x4 IDCT Transform Mode Flag*/
283 (1 << 2) | /*Frame MB only flag*/
284 (0 << 1) | /*MBAFF mode is in active*/
285 (0 << 0) ); /*Field picture flag*/
287 (1<<16) | /*Frame Size Rate Control Flag*/
289 (1<<9) | /*MB level Rate Control Enabling Flag*/
290 (1 << 3) | /*FrameBitRateMinReportMask*/
291 (1 << 2) | /*FrameBitRateMaxReportMask*/
292 (1 << 1) | /*InterMBMaxSizeReportMask*/
293 (1 << 0) ); /*IntraMBMaxSizeReportMask*/
294 OUT_BCS_BATCH(batch, /*Inter and Intra Conformance Max size limit*/
295 (0x0600 << 16) | /*InterMbMaxSz 192 Byte*/
296 (0x0800) ); /*IntraMbMaxSz 256 Byte*/
297 OUT_BCS_BATCH(batch, 0x00000000); /*Reserved : MBZReserved*/
298 OUT_BCS_BATCH(batch, 0x01020304); /*Slice QP Delta for bitrate control*/
299 OUT_BCS_BATCH(batch, 0xFEFDFCFB);
300 OUT_BCS_BATCH(batch, 0x80601004); /*MAX = 128KB, MIN = 64KB*/
301 OUT_BCS_BATCH(batch, 0x00800001);
302 OUT_BCS_BATCH(batch, 0);
304 ADVANCE_BCS_BATCH(batch);
308 gen6_mfc_avc_directmode_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
310 struct intel_batchbuffer *batch = encoder_context->base.batch;
311 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
315 BEGIN_BCS_BATCH(batch, 69);
317 OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
319 /* Reference frames and Current frames */
320 for(i = 0; i < NUM_MFC_DMV_BUFFERS; i++) {
321 if ( mfc_context->direct_mv_buffers[i].bo != NULL) {
322 OUT_BCS_RELOC(batch, mfc_context->direct_mv_buffers[i].bo,
323 I915_GEM_DOMAIN_INSTRUCTION, 0,
326 OUT_BCS_BATCH(batch, 0);
331 for(i = 0; i < 32; i++) {
332 OUT_BCS_BATCH(batch, i/2);
334 OUT_BCS_BATCH(batch, 0);
335 OUT_BCS_BATCH(batch, 0);
337 ADVANCE_BCS_BATCH(batch);
341 gen6_mfc_avc_slice_state(VADriverContextP ctx,
342 VAEncPictureParameterBufferH264 *pic_param,
343 VAEncSliceParameterBufferH264 *slice_param,
344 struct encode_state *encode_state,
345 struct intel_encoder_context *encoder_context,
346 int rate_control_enable,
348 struct intel_batchbuffer *batch)
350 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
351 int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
352 int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
353 int beginmb = slice_param->macroblock_address;
354 int endmb = beginmb + slice_param->num_macroblocks;
355 int beginx = beginmb % width_in_mbs;
356 int beginy = beginmb / width_in_mbs;
357 int nextx = endmb % width_in_mbs;
358 int nexty = endmb / width_in_mbs;
359 int slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type);
360 int last_slice = (endmb == (width_in_mbs * height_in_mbs));
362 unsigned char correct[6], grow, shrink;
364 int weighted_pred_idc = 0;
365 unsigned int luma_log2_weight_denom = slice_param->luma_log2_weight_denom;
366 unsigned int chroma_log2_weight_denom = slice_param->chroma_log2_weight_denom;
367 int num_ref_l0 = 0, num_ref_l1 = 0;
370 batch = encoder_context->base.batch;
372 if (slice_type == SLICE_TYPE_I) {
373 luma_log2_weight_denom = 0;
374 chroma_log2_weight_denom = 0;
375 } else if (slice_type == SLICE_TYPE_P) {
376 weighted_pred_idc = pic_param->pic_fields.bits.weighted_pred_flag;
377 num_ref_l0 = pic_param->num_ref_idx_l0_active_minus1 + 1;
379 if (slice_param->num_ref_idx_active_override_flag)
380 num_ref_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
381 } else if (slice_type == SLICE_TYPE_B) {
382 weighted_pred_idc = pic_param->pic_fields.bits.weighted_bipred_idc;
383 num_ref_l0 = pic_param->num_ref_idx_l0_active_minus1 + 1;
384 num_ref_l1 = pic_param->num_ref_idx_l1_active_minus1 + 1;
386 if (slice_param->num_ref_idx_active_override_flag) {
387 num_ref_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
388 num_ref_l1 = slice_param->num_ref_idx_l1_active_minus1 + 1;
391 if (weighted_pred_idc == 2) {
392 /* 8.4.3 - Derivation process for prediction weights (8-279) */
393 luma_log2_weight_denom = 5;
394 chroma_log2_weight_denom = 5;
398 maxQpN = mfc_context->bit_rate_control_context[slice_type].MaxQpNegModifier;
399 maxQpP = mfc_context->bit_rate_control_context[slice_type].MaxQpPosModifier;
401 for (i = 0; i < 6; i++)
402 correct[i] = mfc_context->bit_rate_control_context[slice_type].Correct[i];
404 grow = mfc_context->bit_rate_control_context[slice_type].GrowInit +
405 (mfc_context->bit_rate_control_context[slice_type].GrowResistance << 4);
406 shrink = mfc_context->bit_rate_control_context[slice_type].ShrinkInit +
407 (mfc_context->bit_rate_control_context[slice_type].ShrinkResistance << 4);
409 BEGIN_BCS_BATCH(batch, 11);;
411 OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2) );
412 OUT_BCS_BATCH(batch, slice_type); /*Slice Type: I:P:B Slice*/
417 (chroma_log2_weight_denom << 8) |
418 (luma_log2_weight_denom << 0));
421 (weighted_pred_idc << 30) |
422 (slice_param->direct_spatial_mv_pred_flag<<29) | /*Direct Prediction Type*/
423 (slice_param->disable_deblocking_filter_idc << 27) |
424 (slice_param->cabac_init_idc << 24) |
425 (qp<<16) | /*Slice Quantization Parameter*/
426 ((slice_param->slice_beta_offset_div2 & 0xf) << 8) |
427 ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0));
429 (beginy << 24) | /*First MB X&Y , the begin postion of current slice*/
431 slice_param->macroblock_address );
432 OUT_BCS_BATCH(batch, (nexty << 16) | nextx); /*Next slice first MB X&Y*/
434 (0/*rate_control_enable*/ << 31) | /*in CBR mode RateControlCounterEnable = enable*/
435 (1 << 30) | /*ResetRateControlCounter*/
436 (0 << 28) | /*RC Triggle Mode = Always Rate Control*/
437 (4 << 24) | /*RC Stable Tolerance, middle level*/
438 (0/*rate_control_enable*/ << 23) | /*RC Panic Enable*/
439 (0 << 22) | /*QP mode, don't modfiy CBP*/
440 (0 << 21) | /*MB Type Direct Conversion Enabled*/
441 (0 << 20) | /*MB Type Skip Conversion Enabled*/
442 (last_slice << 19) | /*IsLastSlice*/
443 (0 << 18) | /*BitstreamOutputFlag Compressed BitStream Output Disable Flag 0:enable 1:disable*/
444 (1 << 17) | /*HeaderPresentFlag*/
445 (1 << 16) | /*SliceData PresentFlag*/
446 (1 << 15) | /*TailPresentFlag*/
447 (1 << 13) | /*RBSP NAL TYPE*/
448 (0 << 12) ); /*CabacZeroWordInsertionEnable*/
449 OUT_BCS_BATCH(batch, mfc_context->mfc_indirect_pak_bse_object.offset);
451 (maxQpN << 24) | /*Target QP - 24 is lowest QP*/
452 (maxQpP << 16) | /*Target QP + 20 is highest QP*/
462 OUT_BCS_BATCH(batch, 0);
464 ADVANCE_BCS_BATCH(batch);
467 static void gen6_mfc_avc_qm_state(VADriverContextP ctx,
468 struct encode_state *encode_state,
469 struct intel_encoder_context *encoder_context)
471 struct intel_batchbuffer *batch = encoder_context->base.batch;
474 BEGIN_BCS_BATCH(batch, 58);
476 OUT_BCS_BATCH(batch, MFX_AVC_QM_STATE | 56);
477 OUT_BCS_BATCH(batch, 0xFF ) ;
478 for( i = 0; i < 56; i++) {
479 OUT_BCS_BATCH(batch, 0x10101010);
482 ADVANCE_BCS_BATCH(batch);
485 static void gen6_mfc_avc_fqm_state(VADriverContextP ctx,
486 struct encode_state *encode_state,
487 struct intel_encoder_context *encoder_context)
489 struct intel_batchbuffer *batch = encoder_context->base.batch;
492 BEGIN_BCS_BATCH(batch, 113);
493 OUT_BCS_BATCH(batch, MFC_AVC_FQM_STATE | (113 - 2));
495 for(i = 0; i < 112;i++) {
496 OUT_BCS_BATCH(batch, 0x10001000);
499 ADVANCE_BCS_BATCH(batch);
503 gen6_mfc_avc_insert_object(VADriverContextP ctx, struct intel_encoder_context *encoder_context,
504 unsigned int *insert_data, int lenght_in_dws, int data_bits_in_last_dw,
505 int skip_emul_byte_count, int is_last_header, int is_end_of_slice, int emulation_flag,
506 struct intel_batchbuffer *batch)
509 batch = encoder_context->base.batch;
511 BEGIN_BCS_BATCH(batch, lenght_in_dws + 2);
513 OUT_BCS_BATCH(batch, MFC_AVC_INSERT_OBJECT | (lenght_in_dws + 2 - 2));
516 (0 << 16) | /* always start at offset 0 */
517 (data_bits_in_last_dw << 8) |
518 (skip_emul_byte_count << 4) |
519 (!!emulation_flag << 3) |
520 ((!!is_last_header) << 2) |
521 ((!!is_end_of_slice) << 1) |
522 (0 << 0)); /* FIXME: ??? */
524 intel_batchbuffer_data(batch, insert_data, lenght_in_dws * 4);
525 ADVANCE_BCS_BATCH(batch);
529 gen6_mfc_init(VADriverContextP ctx,
530 struct encode_state *encode_state,
531 struct intel_encoder_context *encoder_context)
533 struct i965_driver_data *i965 = i965_driver_data(ctx);
534 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
537 int width_in_mbs = 0;
538 int height_in_mbs = 0;
539 int slice_batchbuffer_size;
541 if (encoder_context->codec == CODEC_H264) {
542 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
543 width_in_mbs = pSequenceParameter->picture_width_in_mbs;
544 height_in_mbs = pSequenceParameter->picture_height_in_mbs;
546 VAEncSequenceParameterBufferMPEG2 *pSequenceParameter = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer;
548 assert(encoder_context->codec == CODEC_MPEG2);
550 width_in_mbs = ALIGN(pSequenceParameter->picture_width, 16) / 16;
551 height_in_mbs = ALIGN(pSequenceParameter->picture_height, 16) / 16;
554 slice_batchbuffer_size = 64 * width_in_mbs * height_in_mbs + 4096 +
555 (SLICE_HEADER + SLICE_TAIL) * encode_state->num_slice_params_ext;
557 /*Encode common setup for MFC*/
558 dri_bo_unreference(mfc_context->post_deblocking_output.bo);
559 mfc_context->post_deblocking_output.bo = NULL;
561 dri_bo_unreference(mfc_context->pre_deblocking_output.bo);
562 mfc_context->pre_deblocking_output.bo = NULL;
564 dri_bo_unreference(mfc_context->uncompressed_picture_source.bo);
565 mfc_context->uncompressed_picture_source.bo = NULL;
567 dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo);
568 mfc_context->mfc_indirect_pak_bse_object.bo = NULL;
570 for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){
571 if (mfc_context->direct_mv_buffers[i].bo != NULL)
572 dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
573 mfc_context->direct_mv_buffers[i].bo = NULL;
576 for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){
577 if (mfc_context->reference_surfaces[i].bo != NULL)
578 dri_bo_unreference(mfc_context->reference_surfaces[i].bo);
579 mfc_context->reference_surfaces[i].bo = NULL;
582 dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
583 bo = dri_bo_alloc(i965->intel.bufmgr,
588 mfc_context->intra_row_store_scratch_buffer.bo = bo;
590 dri_bo_unreference(mfc_context->macroblock_status_buffer.bo);
591 bo = dri_bo_alloc(i965->intel.bufmgr,
593 width_in_mbs * height_in_mbs * 16,
596 mfc_context->macroblock_status_buffer.bo = bo;
598 dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
599 bo = dri_bo_alloc(i965->intel.bufmgr,
601 4 * width_in_mbs * 64, /* 4 * width_in_mbs * 64 */
604 mfc_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
606 dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
607 bo = dri_bo_alloc(i965->intel.bufmgr,
609 128 * width_in_mbs, /* 2 * widht_in_mbs * 64 */
612 mfc_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
614 dri_bo_unreference(mfc_context->mfc_batchbuffer_surface.bo);
615 mfc_context->mfc_batchbuffer_surface.bo = NULL;
617 dri_bo_unreference(mfc_context->aux_batchbuffer_surface.bo);
618 mfc_context->aux_batchbuffer_surface.bo = NULL;
620 if (mfc_context->aux_batchbuffer)
621 intel_batchbuffer_free(mfc_context->aux_batchbuffer);
623 mfc_context->aux_batchbuffer = intel_batchbuffer_new(&i965->intel, I915_EXEC_BSD,
624 slice_batchbuffer_size);
625 mfc_context->aux_batchbuffer_surface.bo = mfc_context->aux_batchbuffer->buffer;
626 dri_bo_reference(mfc_context->aux_batchbuffer_surface.bo);
627 mfc_context->aux_batchbuffer_surface.pitch = 16;
628 mfc_context->aux_batchbuffer_surface.num_blocks = mfc_context->aux_batchbuffer->size / 16;
629 mfc_context->aux_batchbuffer_surface.size_block = 16;
631 i965_gpe_context_init(ctx, &mfc_context->gpe_context);
634 static void gen6_mfc_avc_pipeline_picture_programing( VADriverContextP ctx,
635 struct encode_state *encode_state,
636 struct intel_encoder_context *encoder_context)
638 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
640 mfc_context->pipe_mode_select(ctx, MFX_FORMAT_AVC, encoder_context);
641 mfc_context->set_surface_state(ctx, encoder_context);
642 mfc_context->ind_obj_base_addr_state(ctx, encoder_context);
643 gen6_mfc_pipe_buf_addr_state(ctx, encoder_context);
644 gen6_mfc_bsp_buf_base_addr_state(ctx, encoder_context);
645 mfc_context->avc_img_state(ctx, encode_state, encoder_context);
646 mfc_context->avc_qm_state(ctx, encode_state, encoder_context);
647 mfc_context->avc_fqm_state(ctx, encode_state, encoder_context);
648 gen6_mfc_avc_directmode_state(ctx, encoder_context);
649 intel_mfc_avc_ref_idx_state(ctx, encode_state, encoder_context);
654 gen6_mfc_run(VADriverContextP ctx,
655 struct encode_state *encode_state,
656 struct intel_encoder_context *encoder_context)
658 struct intel_batchbuffer *batch = encoder_context->base.batch;
660 intel_batchbuffer_flush(batch); //run the pipeline
662 return VA_STATUS_SUCCESS;
666 gen6_mfc_stop(VADriverContextP ctx,
667 struct encode_state *encode_state,
668 struct intel_encoder_context *encoder_context,
669 int *encoded_bits_size)
671 VAStatus vaStatus = VA_STATUS_ERROR_UNKNOWN;
672 VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
673 VACodedBufferSegment *coded_buffer_segment;
675 vaStatus = i965_MapBuffer(ctx, pPicParameter->coded_buf, (void **)&coded_buffer_segment);
676 assert(vaStatus == VA_STATUS_SUCCESS);
677 *encoded_bits_size = coded_buffer_segment->size * 8;
678 i965_UnmapBuffer(ctx, pPicParameter->coded_buf);
680 return VA_STATUS_SUCCESS;
685 gen6_mfc_avc_pak_object_intra(VADriverContextP ctx, int x, int y, int end_mb, int qp,unsigned int *msg,
686 struct intel_encoder_context *encoder_context,
687 unsigned char target_mb_size, unsigned char max_mb_size,
688 struct intel_batchbuffer *batch)
690 int len_in_dwords = 11;
693 batch = encoder_context->base.batch;
695 BEGIN_BCS_BATCH(batch, len_in_dwords);
697 OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
698 OUT_BCS_BATCH(batch, 0);
699 OUT_BCS_BATCH(batch, 0);
701 (0 << 24) | /* PackedMvNum, Debug*/
702 (0 << 20) | /* No motion vector */
703 (1 << 19) | /* CbpDcY */
704 (1 << 18) | /* CbpDcU */
705 (1 << 17) | /* CbpDcV */
708 OUT_BCS_BATCH(batch, (0xFFFF << 16) | (y << 8) | x); /* Code Block Pattern for Y*/
709 OUT_BCS_BATCH(batch, 0x000F000F); /* Code Block Pattern */
710 OUT_BCS_BATCH(batch, (0 << 27) | (end_mb << 26) | qp); /* Last MB */
712 /*Stuff for Intra MB*/
713 OUT_BCS_BATCH(batch, msg[1]); /* We using Intra16x16 no 4x4 predmode*/
714 OUT_BCS_BATCH(batch, msg[2]);
715 OUT_BCS_BATCH(batch, msg[3]&0xFC);
717 /*MaxSizeInWord and TargetSzieInWord*/
718 OUT_BCS_BATCH(batch, (max_mb_size << 24) |
719 (target_mb_size << 16) );
721 ADVANCE_BCS_BATCH(batch);
723 return len_in_dwords;
727 gen6_mfc_avc_pak_object_inter(VADriverContextP ctx, int x, int y, int end_mb, int qp,
728 unsigned int *msg, unsigned int offset,
729 struct intel_encoder_context *encoder_context,
730 unsigned char target_mb_size,unsigned char max_mb_size, int slice_type,
731 struct intel_batchbuffer *batch)
733 struct gen6_vme_context *vme_context = encoder_context->vme_context;
734 int len_in_dwords = 11;
737 batch = encoder_context->base.batch;
739 BEGIN_BCS_BATCH(batch, len_in_dwords);
741 OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
743 OUT_BCS_BATCH(batch, msg[2]); /* 32 MV*/
744 OUT_BCS_BATCH(batch, offset);
746 OUT_BCS_BATCH(batch, msg[0]);
748 OUT_BCS_BATCH(batch, (0xFFFF<<16) | (y << 8) | x); /* Code Block Pattern for Y*/
749 OUT_BCS_BATCH(batch, 0x000F000F); /* Code Block Pattern */
751 if ( slice_type == SLICE_TYPE_B) {
752 OUT_BCS_BATCH(batch, (0xF<<28) | (end_mb << 26) | qp); /* Last MB */
754 OUT_BCS_BATCH(batch, (end_mb << 26) | qp); /* Last MB */
757 OUT_BCS_BATCH(batch, (end_mb << 26) | qp); /* Last MB */
761 /*Stuff for Inter MB*/
762 OUT_BCS_BATCH(batch, msg[1]);
763 OUT_BCS_BATCH(batch, vme_context->ref_index_in_mb[0]);
764 OUT_BCS_BATCH(batch, vme_context->ref_index_in_mb[1]);
766 /*MaxSizeInWord and TargetSzieInWord*/
767 OUT_BCS_BATCH(batch, (max_mb_size << 24) |
768 (target_mb_size << 16) );
770 ADVANCE_BCS_BATCH(batch);
772 return len_in_dwords;
776 gen6_mfc_avc_pipeline_slice_programing(VADriverContextP ctx,
777 struct encode_state *encode_state,
778 struct intel_encoder_context *encoder_context,
780 struct intel_batchbuffer *slice_batch)
782 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
783 struct gen6_vme_context *vme_context = encoder_context->vme_context;
784 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
785 VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
786 VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer;
787 unsigned int *msg = NULL, offset = 0;
788 int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
789 int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
790 int last_slice = (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks) == (width_in_mbs * height_in_mbs);
792 int qp = pPicParameter->pic_init_qp + pSliceParameter->slice_qp_delta;
793 unsigned int rate_control_mode = encoder_context->rate_control_mode;
794 unsigned int tail_data[] = { 0x0, 0x0 };
795 int slice_type = intel_avc_enc_slice_type_fixup(pSliceParameter->slice_type);
796 int is_intra = slice_type == SLICE_TYPE_I;
801 if (rate_control_mode == VA_RC_CBR) {
802 qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY;
803 if (encode_state->slice_header_index[slice_index] == 0) {
804 pSliceParameter->slice_qp_delta = qp - pPicParameter->pic_init_qp;
809 /* only support for 8-bit pixel bit-depth */
810 assert(pSequenceParameter->bit_depth_luma_minus8 == 0);
811 assert(pSequenceParameter->bit_depth_chroma_minus8 == 0);
812 assert(pPicParameter->pic_init_qp >= 0 && pPicParameter->pic_init_qp < 52);
813 assert(qp >= 0 && qp < 52);
815 gen6_mfc_avc_slice_state(ctx,
818 encode_state, encoder_context,
819 (rate_control_mode == VA_RC_CBR), qp_slice, slice_batch);
821 if ( slice_index == 0)
822 intel_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch);
824 intel_avc_slice_insert_packed_data(ctx, encode_state, encoder_context, slice_index, slice_batch);
826 dri_bo_map(vme_context->vme_output.bo , 1);
827 msg = (unsigned int *)vme_context->vme_output.bo->virtual;
830 msg += pSliceParameter->macroblock_address * INTRA_VME_OUTPUT_IN_DWS;
832 msg += pSliceParameter->macroblock_address * INTER_VME_OUTPUT_IN_DWS;
833 msg += 32; /* the first 32 DWs are MVs */
834 offset = pSliceParameter->macroblock_address * INTER_VME_OUTPUT_IN_BYTES;
837 for (i = pSliceParameter->macroblock_address;
838 i < pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks; i++) {
839 int last_mb = (i == (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks - 1) );
840 x = i % width_in_mbs;
841 y = i / width_in_mbs;
843 if (vme_context->roi_enabled) {
844 qp_mb = *(vme_context->qp_per_mb + i);
851 gen6_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp_mb, msg, encoder_context, 0, 0, slice_batch);
852 msg += INTRA_VME_OUTPUT_IN_DWS;
854 if (msg[0] & INTRA_MB_FLAG_MASK) {
855 gen6_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp_mb, msg, encoder_context, 0, 0, slice_batch);
857 gen6_mfc_avc_pak_object_inter(ctx, x, y, last_mb, qp_mb,
858 msg, offset, encoder_context,
859 0, 0, slice_type, slice_batch);
862 msg += INTER_VME_OUTPUT_IN_DWS;
863 offset += INTER_VME_OUTPUT_IN_BYTES;
867 dri_bo_unmap(vme_context->vme_output.bo);
870 mfc_context->insert_object(ctx, encoder_context,
872 2, 1, 1, 0, slice_batch);
874 mfc_context->insert_object(ctx, encoder_context,
876 1, 1, 1, 0, slice_batch);
883 gen6_mfc_avc_software_batchbuffer(VADriverContextP ctx,
884 struct encode_state *encode_state,
885 struct intel_encoder_context *encoder_context)
887 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
888 struct intel_batchbuffer *batch;;
892 batch = mfc_context->aux_batchbuffer;
893 batch_bo = batch->buffer;
895 for (i = 0; i < encode_state->num_slice_params_ext; i++) {
896 gen6_mfc_avc_pipeline_slice_programing(ctx, encode_state, encoder_context, i, batch);
899 intel_batchbuffer_align(batch, 8);
901 BEGIN_BCS_BATCH(batch, 2);
902 OUT_BCS_BATCH(batch, 0);
903 OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_END);
904 ADVANCE_BCS_BATCH(batch);
906 dri_bo_reference(batch_bo);
908 intel_batchbuffer_free(batch);
909 mfc_context->aux_batchbuffer = NULL;
916 gen6_mfc_batchbuffer_surfaces_input(VADriverContextP ctx,
917 struct encode_state *encode_state,
918 struct intel_encoder_context *encoder_context)
921 struct gen6_vme_context *vme_context = encoder_context->vme_context;
922 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
924 assert(vme_context->vme_output.bo);
925 mfc_context->buffer_suface_setup(ctx,
926 &mfc_context->gpe_context,
927 &vme_context->vme_output,
928 BINDING_TABLE_OFFSET(BIND_IDX_VME_OUTPUT),
929 SURFACE_STATE_OFFSET(BIND_IDX_VME_OUTPUT));
930 assert(mfc_context->aux_batchbuffer_surface.bo);
931 mfc_context->buffer_suface_setup(ctx,
932 &mfc_context->gpe_context,
933 &mfc_context->aux_batchbuffer_surface,
934 BINDING_TABLE_OFFSET(BIND_IDX_MFC_SLICE_HEADER),
935 SURFACE_STATE_OFFSET(BIND_IDX_MFC_SLICE_HEADER));
939 gen6_mfc_batchbuffer_surfaces_output(VADriverContextP ctx,
940 struct encode_state *encode_state,
941 struct intel_encoder_context *encoder_context)
944 struct i965_driver_data *i965 = i965_driver_data(ctx);
945 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
946 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
947 int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
948 int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
949 mfc_context->mfc_batchbuffer_surface.num_blocks = width_in_mbs * height_in_mbs + encode_state->num_slice_params_ext * 8 + 1;
950 mfc_context->mfc_batchbuffer_surface.size_block = 16 * CMD_LEN_IN_OWORD; /* 3 OWORDs */
951 mfc_context->mfc_batchbuffer_surface.pitch = 16;
952 mfc_context->mfc_batchbuffer_surface.bo = dri_bo_alloc(i965->intel.bufmgr,
954 mfc_context->mfc_batchbuffer_surface.num_blocks * mfc_context->mfc_batchbuffer_surface.size_block,
956 mfc_context->buffer_suface_setup(ctx,
957 &mfc_context->gpe_context,
958 &mfc_context->mfc_batchbuffer_surface,
959 BINDING_TABLE_OFFSET(BIND_IDX_MFC_BATCHBUFFER),
960 SURFACE_STATE_OFFSET(BIND_IDX_MFC_BATCHBUFFER));
964 gen6_mfc_batchbuffer_surfaces_setup(VADriverContextP ctx,
965 struct encode_state *encode_state,
966 struct intel_encoder_context *encoder_context)
968 gen6_mfc_batchbuffer_surfaces_input(ctx, encode_state, encoder_context);
969 gen6_mfc_batchbuffer_surfaces_output(ctx, encode_state, encoder_context);
973 gen6_mfc_batchbuffer_idrt_setup(VADriverContextP ctx,
974 struct encode_state *encode_state,
975 struct intel_encoder_context *encoder_context)
977 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
978 struct gen6_interface_descriptor_data *desc;
982 bo = mfc_context->gpe_context.idrt.bo;
987 for (i = 0; i < mfc_context->gpe_context.num_kernels; i++) {
988 struct i965_kernel *kernel;
990 kernel = &mfc_context->gpe_context.kernels[i];
991 assert(sizeof(*desc) == 32);
993 /*Setup the descritor table*/
994 memset(desc, 0, sizeof(*desc));
995 desc->desc0.kernel_start_pointer = (kernel->bo->offset >> 6);
996 desc->desc2.sampler_count = 0;
997 desc->desc2.sampler_state_pointer = 0;
998 desc->desc3.binding_table_entry_count = 2;
999 desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET(0) >> 5);
1000 desc->desc4.constant_urb_entry_read_offset = 0;
1001 desc->desc4.constant_urb_entry_read_length = 4;
1004 dri_bo_emit_reloc(bo,
1005 I915_GEM_DOMAIN_INSTRUCTION, 0,
1007 i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc0),
1016 gen6_mfc_batchbuffer_constant_setup(VADriverContextP ctx,
1017 struct encode_state *encode_state,
1018 struct intel_encoder_context *encoder_context)
1020 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1026 gen6_mfc_batchbuffer_emit_object_command(struct intel_batchbuffer *batch,
1029 int batchbuffer_offset,
1040 unsigned int ref_index[2])
1042 BEGIN_BATCH(batch, 14);
1044 OUT_BATCH(batch, CMD_MEDIA_OBJECT | (14 - 2));
1045 OUT_BATCH(batch, index);
1046 OUT_BATCH(batch, 0);
1047 OUT_BATCH(batch, 0);
1048 OUT_BATCH(batch, 0);
1049 OUT_BATCH(batch, 0);
1052 OUT_BATCH(batch, head_offset);
1053 OUT_BATCH(batch, batchbuffer_offset);
1058 number_mb_cmds << 16 |
1068 OUT_BATCH(batch, ref_index[0]);
1069 OUT_BATCH(batch, ref_index[1]);
1071 ADVANCE_BATCH(batch);
1075 gen6_mfc_avc_batchbuffer_slice_command(VADriverContextP ctx,
1076 struct intel_encoder_context *encoder_context,
1077 VAEncSliceParameterBufferH264 *slice_param,
1079 unsigned short head_size,
1080 unsigned short tail_size,
1081 int batchbuffer_offset,
1085 struct intel_batchbuffer *batch = encoder_context->base.batch;
1086 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1087 struct gen6_vme_context *vme_context = encoder_context->vme_context;
1088 int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
1089 int total_mbs = slice_param->num_macroblocks;
1090 int number_mb_cmds = 128;
1091 int starting_mb = 0;
1092 int last_object = 0;
1093 int first_object = 1;
1096 int index = (slice_param->slice_type == SLICE_TYPE_I) ? MFC_BATCHBUFFER_AVC_INTRA : MFC_BATCHBUFFER_AVC_INTER;
1098 for (i = 0; i < total_mbs / number_mb_cmds; i++) {
1099 last_object = (total_mbs - starting_mb) == number_mb_cmds;
1100 mb_x = (slice_param->macroblock_address + starting_mb) % width_in_mbs;
1101 mb_y = (slice_param->macroblock_address + starting_mb) / width_in_mbs;
1102 assert(mb_x <= 255 && mb_y <= 255);
1104 starting_mb += number_mb_cmds;
1106 gen6_mfc_batchbuffer_emit_object_command(batch,
1120 vme_context->ref_index_in_mb);
1123 head_offset += head_size;
1124 batchbuffer_offset += head_size;
1128 head_offset += tail_size;
1129 batchbuffer_offset += tail_size;
1132 batchbuffer_offset += number_mb_cmds * CMD_LEN_IN_OWORD;
1139 number_mb_cmds = total_mbs % number_mb_cmds;
1140 mb_x = (slice_param->macroblock_address + starting_mb) % width_in_mbs;
1141 mb_y = (slice_param->macroblock_address + starting_mb) / width_in_mbs;
1142 assert(mb_x <= 255 && mb_y <= 255);
1143 starting_mb += number_mb_cmds;
1145 gen6_mfc_batchbuffer_emit_object_command(batch,
1159 vme_context->ref_index_in_mb);
1164 * return size in Owords (16bytes)
1167 gen6_mfc_avc_batchbuffer_slice(VADriverContextP ctx,
1168 struct encode_state *encode_state,
1169 struct intel_encoder_context *encoder_context,
1171 int batchbuffer_offset)
1173 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1174 struct intel_batchbuffer *slice_batch = mfc_context->aux_batchbuffer;
1175 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
1176 VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
1177 VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer;
1178 int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
1179 int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
1180 int last_slice = (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks) == (width_in_mbs * height_in_mbs);
1181 int qp = pPicParameter->pic_init_qp + pSliceParameter->slice_qp_delta;
1182 unsigned int rate_control_mode = encoder_context->rate_control_mode;
1183 unsigned int tail_data[] = { 0x0, 0x0 };
1185 int old_used = intel_batchbuffer_used_size(slice_batch), used;
1186 unsigned short head_size, tail_size;
1187 int slice_type = intel_avc_enc_slice_type_fixup(pSliceParameter->slice_type);
1191 if (rate_control_mode == VA_RC_CBR) {
1192 qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY;
1193 if (encode_state->slice_header_index[slice_index] == 0) {
1194 pSliceParameter->slice_qp_delta = qp - pPicParameter->pic_init_qp;
1195 /* Use the adjusted qp when slice_header is generated by driver */
1200 /* only support for 8-bit pixel bit-depth */
1201 assert(pSequenceParameter->bit_depth_luma_minus8 == 0);
1202 assert(pSequenceParameter->bit_depth_chroma_minus8 == 0);
1203 assert(pPicParameter->pic_init_qp >= 0 && pPicParameter->pic_init_qp < 52);
1204 assert(qp >= 0 && qp < 52);
1206 head_offset = old_used / 16;
1207 gen6_mfc_avc_slice_state(ctx,
1212 (rate_control_mode == VA_RC_CBR),
1216 if (slice_index == 0)
1217 intel_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch);
1219 intel_avc_slice_insert_packed_data(ctx, encode_state, encoder_context, slice_index, slice_batch);
1221 intel_batchbuffer_align(slice_batch, 16); /* aligned by an Oword */
1222 used = intel_batchbuffer_used_size(slice_batch);
1223 head_size = (used - old_used) / 16;
1228 mfc_context->insert_object(ctx,
1239 mfc_context->insert_object(ctx,
1251 intel_batchbuffer_align(slice_batch, 16); /* aligned by an Oword */
1252 used = intel_batchbuffer_used_size(slice_batch);
1253 tail_size = (used - old_used) / 16;
1256 gen6_mfc_avc_batchbuffer_slice_command(ctx,
1266 return head_size + tail_size + pSliceParameter->num_macroblocks * CMD_LEN_IN_OWORD;
1270 gen6_mfc_avc_batchbuffer_pipeline(VADriverContextP ctx,
1271 struct encode_state *encode_state,
1272 struct intel_encoder_context *encoder_context)
1274 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1275 struct intel_batchbuffer *batch = encoder_context->base.batch;
1276 int i, size, offset = 0;
1277 intel_batchbuffer_start_atomic(batch, 0x4000);
1278 gen6_gpe_pipeline_setup(ctx, &mfc_context->gpe_context, batch);
1280 for ( i = 0; i < encode_state->num_slice_params_ext; i++) {
1281 size = gen6_mfc_avc_batchbuffer_slice(ctx, encode_state, encoder_context, i, offset);
1285 intel_batchbuffer_end_atomic(batch);
1286 intel_batchbuffer_flush(batch);
1290 gen6_mfc_build_avc_batchbuffer(VADriverContextP ctx,
1291 struct encode_state *encode_state,
1292 struct intel_encoder_context *encoder_context)
1294 gen6_mfc_batchbuffer_surfaces_setup(ctx, encode_state, encoder_context);
1295 gen6_mfc_batchbuffer_idrt_setup(ctx, encode_state, encoder_context);
1296 gen6_mfc_batchbuffer_constant_setup(ctx, encode_state, encoder_context);
1297 gen6_mfc_avc_batchbuffer_pipeline(ctx, encode_state, encoder_context);
1301 gen6_mfc_avc_hardware_batchbuffer(VADriverContextP ctx,
1302 struct encode_state *encode_state,
1303 struct intel_encoder_context *encoder_context)
1305 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1307 gen6_mfc_build_avc_batchbuffer(ctx, encode_state, encoder_context);
1308 dri_bo_reference(mfc_context->mfc_batchbuffer_surface.bo);
1310 return mfc_context->mfc_batchbuffer_surface.bo;
1316 gen6_mfc_avc_pipeline_programing(VADriverContextP ctx,
1317 struct encode_state *encode_state,
1318 struct intel_encoder_context *encoder_context)
1320 struct intel_batchbuffer *batch = encoder_context->base.batch;
1321 dri_bo *slice_batch_bo;
1323 if ( intel_mfc_interlace_check(ctx, encode_state, encoder_context) ) {
1324 fprintf(stderr, "Current VA driver don't support interlace mode!\n");
1329 if (encoder_context->soft_batch_force)
1330 slice_batch_bo = gen6_mfc_avc_software_batchbuffer(ctx, encode_state, encoder_context);
1332 slice_batch_bo = gen6_mfc_avc_hardware_batchbuffer(ctx, encode_state, encoder_context);
1335 intel_batchbuffer_start_atomic_bcs(batch, 0x4000);
1336 intel_batchbuffer_emit_mi_flush(batch);
1338 // picture level programing
1339 gen6_mfc_avc_pipeline_picture_programing(ctx, encode_state, encoder_context);
1341 BEGIN_BCS_BATCH(batch, 2);
1342 OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8));
1343 OUT_BCS_RELOC(batch,
1345 I915_GEM_DOMAIN_COMMAND, 0,
1347 ADVANCE_BCS_BATCH(batch);
1350 intel_batchbuffer_end_atomic(batch);
1352 dri_bo_unreference(slice_batch_bo);
1356 gen6_mfc_avc_encode_picture(VADriverContextP ctx,
1357 struct encode_state *encode_state,
1358 struct intel_encoder_context *encoder_context)
1360 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1361 unsigned int rate_control_mode = encoder_context->rate_control_mode;
1362 int current_frame_bits_size;
1366 gen6_mfc_init(ctx, encode_state, encoder_context);
1367 intel_mfc_avc_prepare(ctx, encode_state, encoder_context);
1368 /*Programing bcs pipeline*/
1369 gen6_mfc_avc_pipeline_programing(ctx, encode_state, encoder_context); //filling the pipeline
1370 gen6_mfc_run(ctx, encode_state, encoder_context);
1371 if (rate_control_mode == VA_RC_CBR /*|| rate_control_mode == VA_RC_VBR*/) {
1372 gen6_mfc_stop(ctx, encode_state, encoder_context, ¤t_frame_bits_size);
1373 sts = intel_mfc_brc_postpack(encode_state, mfc_context, current_frame_bits_size);
1374 if (sts == BRC_NO_HRD_VIOLATION) {
1375 intel_mfc_hrd_context_update(encode_state, mfc_context);
1378 else if (sts == BRC_OVERFLOW_WITH_MIN_QP || sts == BRC_UNDERFLOW_WITH_MAX_QP) {
1379 if (!mfc_context->hrd.violation_noted) {
1380 fprintf(stderr, "Unrepairable %s!\n", (sts == BRC_OVERFLOW_WITH_MIN_QP)? "overflow": "underflow");
1381 mfc_context->hrd.violation_noted = 1;
1383 return VA_STATUS_SUCCESS;
1390 return VA_STATUS_SUCCESS;
1394 gen6_mfc_pipeline(VADriverContextP ctx,
1396 struct encode_state *encode_state,
1397 struct intel_encoder_context *encoder_context)
1402 case VAProfileH264ConstrainedBaseline:
1403 case VAProfileH264Main:
1404 case VAProfileH264High:
1405 vaStatus = gen6_mfc_avc_encode_picture(ctx, encode_state, encoder_context);
1408 /* FIXME: add for other profile */
1410 vaStatus = VA_STATUS_ERROR_UNSUPPORTED_PROFILE;
1418 gen6_mfc_context_destroy(void *context)
1420 struct gen6_mfc_context *mfc_context = context;
1423 dri_bo_unreference(mfc_context->post_deblocking_output.bo);
1424 mfc_context->post_deblocking_output.bo = NULL;
1426 dri_bo_unreference(mfc_context->pre_deblocking_output.bo);
1427 mfc_context->pre_deblocking_output.bo = NULL;
1429 dri_bo_unreference(mfc_context->uncompressed_picture_source.bo);
1430 mfc_context->uncompressed_picture_source.bo = NULL;
1432 dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo);
1433 mfc_context->mfc_indirect_pak_bse_object.bo = NULL;
1435 for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){
1436 dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
1437 mfc_context->direct_mv_buffers[i].bo = NULL;
1440 dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
1441 mfc_context->intra_row_store_scratch_buffer.bo = NULL;
1443 dri_bo_unreference(mfc_context->macroblock_status_buffer.bo);
1444 mfc_context->macroblock_status_buffer.bo = NULL;
1446 dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
1447 mfc_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
1449 dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
1450 mfc_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
1453 for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){
1454 dri_bo_unreference(mfc_context->reference_surfaces[i].bo);
1455 mfc_context->reference_surfaces[i].bo = NULL;
1458 i965_gpe_context_destroy(&mfc_context->gpe_context);
1460 dri_bo_unreference(mfc_context->mfc_batchbuffer_surface.bo);
1461 mfc_context->mfc_batchbuffer_surface.bo = NULL;
1463 dri_bo_unreference(mfc_context->aux_batchbuffer_surface.bo);
1464 mfc_context->aux_batchbuffer_surface.bo = NULL;
1466 if (mfc_context->aux_batchbuffer)
1467 intel_batchbuffer_free(mfc_context->aux_batchbuffer);
1469 mfc_context->aux_batchbuffer = NULL;
1474 Bool gen6_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
1476 struct gen6_mfc_context *mfc_context = calloc(1, sizeof(struct gen6_mfc_context));
1481 mfc_context->gpe_context.surface_state_binding_table.length = (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6;
1483 mfc_context->gpe_context.idrt.max_entries = MAX_GPE_KERNELS;
1484 mfc_context->gpe_context.idrt.entry_size = sizeof(struct gen6_interface_descriptor_data);
1486 mfc_context->gpe_context.curbe.length = 32 * 4;
1488 mfc_context->gpe_context.vfe_state.max_num_threads = 60 - 1;
1489 mfc_context->gpe_context.vfe_state.num_urb_entries = 16;
1490 mfc_context->gpe_context.vfe_state.gpgpu_mode = 0;
1491 mfc_context->gpe_context.vfe_state.urb_entry_size = 59 - 1;
1492 mfc_context->gpe_context.vfe_state.curbe_allocation_size = 37 - 1;
1494 i965_gpe_load_kernels(ctx,
1495 &mfc_context->gpe_context,
1499 mfc_context->pipe_mode_select = gen6_mfc_pipe_mode_select;
1500 mfc_context->set_surface_state = gen6_mfc_surface_state;
1501 mfc_context->ind_obj_base_addr_state = gen6_mfc_ind_obj_base_addr_state;
1502 mfc_context->avc_img_state = gen6_mfc_avc_img_state;
1503 mfc_context->avc_qm_state = gen6_mfc_avc_qm_state;
1504 mfc_context->avc_fqm_state = gen6_mfc_avc_fqm_state;
1505 mfc_context->insert_object = gen6_mfc_avc_insert_object;
1506 mfc_context->buffer_suface_setup = i965_gpe_buffer_suface_setup;
1508 encoder_context->mfc_context = mfc_context;
1509 encoder_context->mfc_context_destroy = gen6_mfc_context_destroy;
1510 encoder_context->mfc_pipeline = gen6_mfc_pipeline;
1511 encoder_context->mfc_brc_prepare = intel_mfc_brc_prepare;