src/gen6_mfc.c

   1 /*
   2  * Copyright © 2010-2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Zhou Chang <chang.zhou@intel.com>
  26  *
  27  */
  28
  29 #include <stdio.h>
  30 #include <stdlib.h>
  31 #include <string.h>
  32 #include <assert.h>
  33 #include <math.h>
  34
  35 #include "intel_batchbuffer.h"
  36 #include "i965_defines.h"
  37 #include "i965_structs.h"
  38 #include "i965_drv_video.h"
  39 #include "i965_encoder.h"
  40 #include "i965_encoder_utils.h"
  41 #include "gen6_mfc.h"
  42 #include "gen6_vme.h"
  43 #include "intel_media.h"
  44
  45 #define SURFACE_STATE_PADDED_SIZE               MAX(SURFACE_STATE_PADDED_SIZE_GEN6, SURFACE_STATE_PADDED_SIZE_GEN7)
  46 #define SURFACE_STATE_OFFSET(index)             (SURFACE_STATE_PADDED_SIZE * index)
  47 #define BINDING_TABLE_OFFSET(index)             (SURFACE_STATE_OFFSET(MAX_MEDIA_SURFACES_GEN6) + sizeof(unsigned int) * index)
  48
  49 static const uint32_t gen6_mfc_batchbuffer_avc_intra[][4] = {
  50 #include "shaders/utils/mfc_batchbuffer_avc_intra.g6b"
  51 };
  52
  53 static const uint32_t gen6_mfc_batchbuffer_avc_inter[][4] = {
  54 #include "shaders/utils/mfc_batchbuffer_avc_inter.g6b"
  55 };
  56
  57 static struct i965_kernel gen6_mfc_kernels[] = {
  58     {
  59         "MFC AVC INTRA BATCHBUFFER ",
  60         MFC_BATCHBUFFER_AVC_INTRA,
  61         gen6_mfc_batchbuffer_avc_intra,
  62         sizeof(gen6_mfc_batchbuffer_avc_intra),
  63         NULL
  64     },
  65
  66     {
  67         "MFC AVC INTER BATCHBUFFER ",
  68         MFC_BATCHBUFFER_AVC_INTER,
  69         gen6_mfc_batchbuffer_avc_inter,
  70         sizeof(gen6_mfc_batchbuffer_avc_inter),
  71         NULL
  72     },
  73 };
  74
  75 static void
  76 gen6_mfc_pipe_mode_select(VADriverContextP ctx,
  77                           int standard_select,
  78                           struct intel_encoder_context *encoder_context)
  79 {
  80     struct intel_batchbuffer *batch = encoder_context->base.batch;
  81     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
  82
  83     assert(standard_select == MFX_FORMAT_AVC);
  84
  85     BEGIN_BCS_BATCH(batch, 4);
  86
  87     OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (4 - 2));
  88     OUT_BCS_BATCH(batch,
  89                   (1 << 10) | /* disable Stream-Out , advanced QP/bitrate control need enable it*/
  90                   ((!!mfc_context->post_deblocking_output.bo) << 9)  | /* Post Deblocking Output */
  91                   ((!!mfc_context->pre_deblocking_output.bo) << 8)  | /* Pre Deblocking Output */
  92                   (0 << 7)  | /* disable TLB prefectch */
  93                   (0 << 5)  | /* not in stitch mode */
  94                   (1 << 4)  | /* encoding mode */
  95                   (2 << 0));  /* Standard Select: AVC */
  96     OUT_BCS_BATCH(batch,
  97                   (0 << 20) | /* round flag in PB slice */
  98                   (0 << 19) | /* round flag in Intra8x8 */
  99                   (0 << 7)  | /* expand NOA bus flag */
 100                   (1 << 6)  | /* must be 1 */
 101                   (0 << 5)  | /* disable clock gating for NOA */
 102                   (0 << 4)  | /* terminate if AVC motion and POC table error occurs */
 103                   (0 << 3)  | /* terminate if AVC mbdata error occurs */
 104                   (0 << 2)  | /* terminate if AVC CABAC/CAVLC decode error occurs */
 105                   (0 << 1)  | /* AVC long field motion vector */
 106                   (0 << 0));  /* always calculate AVC ILDB boundary strength */
 107     OUT_BCS_BATCH(batch, 0);
 108
 109     ADVANCE_BCS_BATCH(batch);
 110 }
 111
 112 static void
 113 gen6_mfc_surface_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 114 {
 115     struct intel_batchbuffer *batch = encoder_context->base.batch;
 116     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 117
 118     BEGIN_BCS_BATCH(batch, 6);
 119
 120     OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
 121     OUT_BCS_BATCH(batch, 0);
 122     OUT_BCS_BATCH(batch,
 123                   ((mfc_context->surface_state.height - 1) << 19) |
 124                   ((mfc_context->surface_state.width - 1) << 6));
 125     OUT_BCS_BATCH(batch,
 126                   (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
 127                   (1 << 27) | /* must be 1 for interleave U/V, hardware requirement */
 128                   (0 << 22) | /* surface object control state, FIXME??? */
 129                   ((mfc_context->surface_state.w_pitch - 1) << 3) | /* pitch */
 130                   (0 << 2)  | /* must be 0 for interleave U/V */
 131                   (1 << 1)  | /* must be y-tiled */
 132                   (I965_TILEWALK_YMAJOR << 0));             /* tile walk, TILEWALK_YMAJOR */
 133     OUT_BCS_BATCH(batch,
 134                   (0 << 16) |                               /* must be 0 for interleave U/V */
 135                   (mfc_context->surface_state.h_pitch));        /* y offset for U(cb) */
 136     OUT_BCS_BATCH(batch, 0);
 137     ADVANCE_BCS_BATCH(batch);
 138 }
 139
 140 void
 141 gen6_mfc_pipe_buf_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 142 {
 143     struct intel_batchbuffer *batch = encoder_context->base.batch;
 144     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 145     int i;
 146
 147     BEGIN_BCS_BATCH(batch, 24);
 148
 149     OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
 150
 151     if (mfc_context->pre_deblocking_output.bo)
 152         OUT_BCS_RELOC(batch, mfc_context->pre_deblocking_output.bo,
 153                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 154                       0);
 155     else
 156         OUT_BCS_BATCH(batch, 0);                                            /* pre output addr   */
 157
 158     if (mfc_context->post_deblocking_output.bo)
 159         OUT_BCS_RELOC(batch, mfc_context->post_deblocking_output.bo,
 160                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 161                       0);                                           /* post output addr  */
 162     else
 163         OUT_BCS_BATCH(batch, 0);
 164
 165     OUT_BCS_RELOC(batch, mfc_context->uncompressed_picture_source.bo,
 166                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 167                   0);                                           /* uncompressed data */
 168     OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo,
 169                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 170                   0);                                           /* StreamOut data*/
 171     OUT_BCS_RELOC(batch, mfc_context->intra_row_store_scratch_buffer.bo,
 172                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 173                   0);
 174     OUT_BCS_RELOC(batch, mfc_context->deblocking_filter_row_store_scratch_buffer.bo,
 175                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 176                   0);
 177     /* 7..22 Reference pictures*/
 178     for (i = 0; i < ARRAY_ELEMS(mfc_context->reference_surfaces); i++) {
 179         if (mfc_context->reference_surfaces[i].bo != NULL) {
 180             OUT_BCS_RELOC(batch, mfc_context->reference_surfaces[i].bo,
 181                           I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 182                           0);
 183         } else {
 184             OUT_BCS_BATCH(batch, 0);
 185         }
 186     }
 187     OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo,
 188                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 189                   0);                                           /* Macroblock status buffer*/
 190
 191     ADVANCE_BCS_BATCH(batch);
 192 }
 193
 194 static void
 195 gen6_mfc_ind_obj_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 196 {
 197     struct intel_batchbuffer *batch = encoder_context->base.batch;
 198     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 199     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 200
 201     BEGIN_BCS_BATCH(batch, 11);
 202
 203     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
 204     OUT_BCS_BATCH(batch, 0);
 205     OUT_BCS_BATCH(batch, 0);
 206     /* MFX Indirect MV Object Base Address */
 207     OUT_BCS_RELOC(batch, vme_context->vme_output.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 208     OUT_BCS_BATCH(batch, 0);
 209     OUT_BCS_BATCH(batch, 0);
 210     OUT_BCS_BATCH(batch, 0);
 211     OUT_BCS_BATCH(batch, 0);
 212     OUT_BCS_BATCH(batch, 0);
 213     /*MFC Indirect PAK-BSE Object Base Address for Encoder*/
 214     OUT_BCS_RELOC(batch,
 215                   mfc_context->mfc_indirect_pak_bse_object.bo,
 216                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 217                   0);
 218     OUT_BCS_RELOC(batch,
 219                   mfc_context->mfc_indirect_pak_bse_object.bo,
 220                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 221                   mfc_context->mfc_indirect_pak_bse_object.end_offset);
 222
 223     ADVANCE_BCS_BATCH(batch);
 224 }
 225
 226 void
 227 gen6_mfc_bsp_buf_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 228 {
 229     struct intel_batchbuffer *batch = encoder_context->base.batch;
 230     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 231
 232     BEGIN_BCS_BATCH(batch, 4);
 233
 234     OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
 235     OUT_BCS_RELOC(batch, mfc_context->bsd_mpc_row_store_scratch_buffer.bo,
 236                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 237                   0);
 238     OUT_BCS_BATCH(batch, 0);
 239     OUT_BCS_BATCH(batch, 0);
 240
 241     ADVANCE_BCS_BATCH(batch);
 242 }
 243
 244 static void
 245 gen6_mfc_avc_img_state(VADriverContextP ctx, struct encode_state *encode_state,
 246                        struct intel_encoder_context *encoder_context)
 247 {
 248     struct intel_batchbuffer *batch = encoder_context->base.batch;
 249     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 250     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 251     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
 252     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
 253     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
 254
 255     BEGIN_BCS_BATCH(batch, 13);
 256     OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (13 - 2));
 257     OUT_BCS_BATCH(batch,
 258                   ((width_in_mbs * height_in_mbs) & 0xFFFF));
 259     OUT_BCS_BATCH(batch,
 260                   (height_in_mbs << 16) |
 261                   (width_in_mbs << 0));
 262     OUT_BCS_BATCH(batch,
 263                   (0 << 24) |     /*Second Chroma QP Offset*/
 264                   (0 << 16) |     /*Chroma QP Offset*/
 265                   (0 << 14) |   /*Max-bit conformance Intra flag*/
 266                   (0 << 13) |   /*Max Macroblock size conformance Inter flag*/
 267                   (1 << 12) |   /*Should always be written as "1" */
 268                   (0 << 10) |   /*QM Preset FLag */
 269                   (0 << 8)  |   /*Image Structure*/
 270                   (0 << 0));    /*Current Decoed Image Frame Store ID, reserved in Encode mode*/
 271     OUT_BCS_BATCH(batch,
 272                   (400 << 16) |   /*Mininum Frame size*/
 273                   (0 << 15) |   /*Disable reading of Macroblock Status Buffer*/
 274                   (0 << 14) |   /*Load BitStream Pointer only once, 1 slic 1 frame*/
 275                   (0 << 13) |   /*CABAC 0 word insertion test enable*/
 276                   (1 << 12) |   /*MVUnpackedEnable,compliant to DXVA*/
 277                   (1 << 10) |   /*Chroma Format IDC, 4:2:0*/
 278                   (pPicParameter->pic_fields.bits.entropy_coding_mode_flag << 7)  |   /*0:CAVLC encoding mode,1:CABAC*/
 279                   (0 << 6)  |   /*Only valid for VLD decoding mode*/
 280                   (0 << 5)  |   /*Constrained Intra Predition Flag, from PPS*/
 281                   (pSequenceParameter->seq_fields.bits.direct_8x8_inference_flag << 4)  |   /*Direct 8x8 inference flag*/
 282                   (pPicParameter->pic_fields.bits.transform_8x8_mode_flag << 3)  |   /*8x8 or 4x4 IDCT Transform Mode Flag*/
 283                   (1 << 2)  |   /*Frame MB only flag*/
 284                   (0 << 1)  |   /*MBAFF mode is in active*/
 285                   (0 << 0));    /*Field picture flag*/
 286     OUT_BCS_BATCH(batch,
 287                   (1 << 16)   | /*Frame Size Rate Control Flag*/
 288                   (1 << 12)   |
 289                   (1 << 9)    | /*MB level Rate Control Enabling Flag*/
 290                   (1 << 3)  |   /*FrameBitRateMinReportMask*/
 291                   (1 << 2)  |   /*FrameBitRateMaxReportMask*/
 292                   (1 << 1)  |   /*InterMBMaxSizeReportMask*/
 293                   (1 << 0));    /*IntraMBMaxSizeReportMask*/
 294     OUT_BCS_BATCH(batch,            /*Inter and Intra Conformance Max size limit*/
 295                   (0x0600 << 16) |      /*InterMbMaxSz 192 Byte*/
 296                   (0x0800));            /*IntraMbMaxSz 256 Byte*/
 297     OUT_BCS_BATCH(batch, 0x00000000);   /*Reserved : MBZReserved*/
 298     OUT_BCS_BATCH(batch, 0x01020304);   /*Slice QP Delta for bitrate control*/
 299     OUT_BCS_BATCH(batch, 0xFEFDFCFB);
 300     OUT_BCS_BATCH(batch, 0x80601004);   /*MAX = 128KB, MIN = 64KB*/
 301     OUT_BCS_BATCH(batch, 0x00800001);
 302     OUT_BCS_BATCH(batch, 0);
 303
 304     ADVANCE_BCS_BATCH(batch);
 305 }
 306
 307 static void
 308 gen6_mfc_avc_directmode_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 309 {
 310     struct intel_batchbuffer *batch = encoder_context->base.batch;
 311     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 312
 313     int i;
 314
 315     BEGIN_BCS_BATCH(batch, 69);
 316
 317     OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
 318
 319     /* Reference frames and Current frames */
 320     for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++) {
 321         if (mfc_context->direct_mv_buffers[i].bo != NULL) {
 322             OUT_BCS_RELOC(batch, mfc_context->direct_mv_buffers[i].bo,
 323                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 324                           0);
 325         } else {
 326             OUT_BCS_BATCH(batch, 0);
 327         }
 328     }
 329
 330     /* POL list */
 331     for (i = 0; i < 32; i++) {
 332         OUT_BCS_BATCH(batch, i / 2);
 333     }
 334     OUT_BCS_BATCH(batch, 0);
 335     OUT_BCS_BATCH(batch, 0);
 336
 337     ADVANCE_BCS_BATCH(batch);
 338 }
 339
 340 static void
 341 gen6_mfc_avc_slice_state(VADriverContextP ctx,
 342                          VAEncPictureParameterBufferH264 *pic_param,
 343                          VAEncSliceParameterBufferH264 *slice_param,
 344                          struct encode_state *encode_state,
 345                          struct intel_encoder_context *encoder_context,
 346                          int rate_control_enable,
 347                          int qp,
 348                          struct intel_batchbuffer *batch)
 349 {
 350     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 351     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
 352     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
 353     int beginmb = slice_param->macroblock_address;
 354     int endmb = beginmb + slice_param->num_macroblocks;
 355     int beginx = beginmb % width_in_mbs;
 356     int beginy = beginmb / width_in_mbs;
 357     int nextx =  endmb % width_in_mbs;
 358     int nexty = endmb / width_in_mbs;
 359     int slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type);
 360     int last_slice = (endmb == (width_in_mbs * height_in_mbs));
 361     int maxQpN, maxQpP;
 362     unsigned char correct[6], grow, shrink;
 363     int i;
 364     int weighted_pred_idc = 0;
 365     unsigned int luma_log2_weight_denom = slice_param->luma_log2_weight_denom;
 366     unsigned int chroma_log2_weight_denom = slice_param->chroma_log2_weight_denom;
 367     int num_ref_l0 = 0, num_ref_l1 = 0;
 368
 369     if (batch == NULL)
 370         batch = encoder_context->base.batch;
 371
 372     if (slice_type == SLICE_TYPE_I) {
 373         luma_log2_weight_denom = 0;
 374         chroma_log2_weight_denom = 0;
 375     } else if (slice_type == SLICE_TYPE_P) {
 376         weighted_pred_idc = pic_param->pic_fields.bits.weighted_pred_flag;
 377         num_ref_l0 = pic_param->num_ref_idx_l0_active_minus1 + 1;
 378
 379         if (slice_param->num_ref_idx_active_override_flag)
 380             num_ref_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
 381     } else if (slice_type == SLICE_TYPE_B) {
 382         weighted_pred_idc = pic_param->pic_fields.bits.weighted_bipred_idc;
 383         num_ref_l0 = pic_param->num_ref_idx_l0_active_minus1 + 1;
 384         num_ref_l1 = pic_param->num_ref_idx_l1_active_minus1 + 1;
 385
 386         if (slice_param->num_ref_idx_active_override_flag) {
 387             num_ref_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
 388             num_ref_l1 = slice_param->num_ref_idx_l1_active_minus1 + 1;
 389         }
 390
 391         if (weighted_pred_idc == 2) {
 392             /* 8.4.3 - Derivation process for prediction weights (8-279) */
 393             luma_log2_weight_denom = 5;
 394             chroma_log2_weight_denom = 5;
 395         }
 396     }
 397
 398     maxQpN = mfc_context->bit_rate_control_context[slice_type].MaxQpNegModifier;
 399     maxQpP = mfc_context->bit_rate_control_context[slice_type].MaxQpPosModifier;
 400
 401     for (i = 0; i < 6; i++)
 402         correct[i] = mfc_context->bit_rate_control_context[slice_type].Correct[i];
 403
 404     grow = mfc_context->bit_rate_control_context[slice_type].GrowInit +
 405            (mfc_context->bit_rate_control_context[slice_type].GrowResistance << 4);
 406     shrink = mfc_context->bit_rate_control_context[slice_type].ShrinkInit +
 407              (mfc_context->bit_rate_control_context[slice_type].ShrinkResistance << 4);
 408
 409     BEGIN_BCS_BATCH(batch, 11);;
 410
 411     OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2));
 412     OUT_BCS_BATCH(batch, slice_type);           /*Slice Type: I:P:B Slice*/
 413
 414     OUT_BCS_BATCH(batch,
 415                   (num_ref_l0 << 16) |
 416                   (num_ref_l1 << 24) |
 417                   (chroma_log2_weight_denom << 8) |
 418                   (luma_log2_weight_denom << 0));
 419
 420     OUT_BCS_BATCH(batch,
 421                   (weighted_pred_idc << 30) |
 422                   (slice_param->direct_spatial_mv_pred_flag << 29) |           /*Direct Prediction Type*/
 423                   (slice_param->disable_deblocking_filter_idc << 27) |
 424                   (slice_param->cabac_init_idc << 24) |
 425                   (qp << 16) |          /*Slice Quantization Parameter*/
 426                   ((slice_param->slice_beta_offset_div2 & 0xf) << 8) |
 427                   ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0));
 428     OUT_BCS_BATCH(batch,
 429                   (beginy << 24) |          /*First MB X&Y , the begin postion of current slice*/
 430                   (beginx << 16) |
 431                   slice_param->macroblock_address);
 432     OUT_BCS_BATCH(batch, (nexty << 16) | nextx);                       /*Next slice first MB X&Y*/
 433     OUT_BCS_BATCH(batch,
 434                   (0/*rate_control_enable*/ << 31) |        /*in CBR mode RateControlCounterEnable = enable*/
 435                   (1 << 30) |       /*ResetRateControlCounter*/
 436                   (0 << 28) |       /*RC Triggle Mode = Always Rate Control*/
 437                   (4 << 24) |     /*RC Stable Tolerance, middle level*/
 438                   (0/*rate_control_enable*/ << 23) |     /*RC Panic Enable*/
 439                   (0 << 22) |     /*QP mode, don't modfiy CBP*/
 440                   (0 << 21) |     /*MB Type Direct Conversion Enabled*/
 441                   (0 << 20) |     /*MB Type Skip Conversion Enabled*/
 442                   (last_slice << 19) |     /*IsLastSlice*/
 443                   (0 << 18) |   /*BitstreamOutputFlag Compressed BitStream Output Disable Flag 0:enable 1:disable*/
 444                   (1 << 17) |       /*HeaderPresentFlag*/
 445                   (1 << 16) |       /*SliceData PresentFlag*/
 446                   (1 << 15) |       /*TailPresentFlag*/
 447                   (1 << 13) |       /*RBSP NAL TYPE*/
 448                   (0 << 12));     /*CabacZeroWordInsertionEnable*/
 449     OUT_BCS_BATCH(batch, mfc_context->mfc_indirect_pak_bse_object.offset);
 450     OUT_BCS_BATCH(batch,
 451                   (maxQpN << 24) |     /*Target QP - 24 is lowest QP*/
 452                   (maxQpP << 16) |     /*Target QP + 20 is highest QP*/
 453                   (shrink << 8)  |
 454                   (grow << 0));
 455     OUT_BCS_BATCH(batch,
 456                   (correct[5] << 20) |
 457                   (correct[4] << 16) |
 458                   (correct[3] << 12) |
 459                   (correct[2] << 8) |
 460                   (correct[1] << 4) |
 461                   (correct[0] << 0));
 462     OUT_BCS_BATCH(batch, 0);
 463
 464     ADVANCE_BCS_BATCH(batch);
 465 }
 466
 467 static void gen6_mfc_avc_qm_state(VADriverContextP ctx,
 468                                   struct encode_state *encode_state,
 469                                   struct intel_encoder_context *encoder_context)
 470 {
 471     struct intel_batchbuffer *batch = encoder_context->base.batch;
 472     int i;
 473
 474     BEGIN_BCS_BATCH(batch, 58);
 475
 476     OUT_BCS_BATCH(batch, MFX_AVC_QM_STATE | 56);
 477     OUT_BCS_BATCH(batch, 0xFF) ;
 478     for (i = 0; i < 56; i++) {
 479         OUT_BCS_BATCH(batch, 0x10101010);
 480     }
 481
 482     ADVANCE_BCS_BATCH(batch);
 483 }
 484
 485 static void gen6_mfc_avc_fqm_state(VADriverContextP ctx,
 486                                    struct encode_state *encode_state,
 487                                    struct intel_encoder_context *encoder_context)
 488 {
 489     struct intel_batchbuffer *batch = encoder_context->base.batch;
 490     int i;
 491
 492     BEGIN_BCS_BATCH(batch, 113);
 493     OUT_BCS_BATCH(batch, MFC_AVC_FQM_STATE | (113 - 2));
 494
 495     for (i = 0; i < 112; i++) {
 496         OUT_BCS_BATCH(batch, 0x10001000);
 497     }
 498
 499     ADVANCE_BCS_BATCH(batch);
 500 }
 501
 502 static void
 503 gen6_mfc_avc_insert_object(VADriverContextP ctx, struct intel_encoder_context *encoder_context,
 504                            unsigned int *insert_data, int lenght_in_dws, int data_bits_in_last_dw,
 505                            int skip_emul_byte_count, int is_last_header, int is_end_of_slice, int emulation_flag,
 506                            struct intel_batchbuffer *batch)
 507 {
 508     if (batch == NULL)
 509         batch = encoder_context->base.batch;
 510
 511     BEGIN_BCS_BATCH(batch, lenght_in_dws + 2);
 512
 513     OUT_BCS_BATCH(batch, MFC_AVC_INSERT_OBJECT | (lenght_in_dws + 2 - 2));
 514
 515     OUT_BCS_BATCH(batch,
 516                   (0 << 16) |   /* always start at offset 0 */
 517                   (data_bits_in_last_dw << 8) |
 518                   (skip_emul_byte_count << 4) |
 519                   (!!emulation_flag << 3) |
 520                   ((!!is_last_header) << 2) |
 521                   ((!!is_end_of_slice) << 1) |
 522                   (0 << 0));    /* FIXME: ??? */
 523
 524     intel_batchbuffer_data(batch, insert_data, lenght_in_dws * 4);
 525     ADVANCE_BCS_BATCH(batch);
 526 }
 527
 528 void
 529 gen6_mfc_init(VADriverContextP ctx,
 530               struct encode_state *encode_state,
 531               struct intel_encoder_context *encoder_context)
 532 {
 533     struct i965_driver_data *i965 = i965_driver_data(ctx);
 534     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 535     dri_bo *bo;
 536     int i;
 537     int width_in_mbs = 0;
 538     int height_in_mbs = 0;
 539     int slice_batchbuffer_size;
 540
 541     if (encoder_context->codec == CODEC_H264) {
 542         VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 543         width_in_mbs = pSequenceParameter->picture_width_in_mbs;
 544         height_in_mbs = pSequenceParameter->picture_height_in_mbs;
 545     } else {
 546         VAEncSequenceParameterBufferMPEG2 *pSequenceParameter = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer;
 547
 548         assert(encoder_context->codec == CODEC_MPEG2);
 549
 550         width_in_mbs = ALIGN(pSequenceParameter->picture_width, 16) / 16;
 551         height_in_mbs = ALIGN(pSequenceParameter->picture_height, 16) / 16;
 552     }
 553
 554     slice_batchbuffer_size = 64 * width_in_mbs * height_in_mbs + 4096 +
 555                              (SLICE_HEADER + SLICE_TAIL) * encode_state->num_slice_params_ext;
 556
 557     /*Encode common setup for MFC*/
 558     dri_bo_unreference(mfc_context->post_deblocking_output.bo);
 559     mfc_context->post_deblocking_output.bo = NULL;
 560
 561     dri_bo_unreference(mfc_context->pre_deblocking_output.bo);
 562     mfc_context->pre_deblocking_output.bo = NULL;
 563
 564     dri_bo_unreference(mfc_context->uncompressed_picture_source.bo);
 565     mfc_context->uncompressed_picture_source.bo = NULL;
 566
 567     dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo);
 568     mfc_context->mfc_indirect_pak_bse_object.bo = NULL;
 569
 570     for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++) {
 571         if (mfc_context->direct_mv_buffers[i].bo != NULL)
 572             dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
 573         mfc_context->direct_mv_buffers[i].bo = NULL;
 574     }
 575
 576     for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++) {
 577         if (mfc_context->reference_surfaces[i].bo != NULL)
 578             dri_bo_unreference(mfc_context->reference_surfaces[i].bo);
 579         mfc_context->reference_surfaces[i].bo = NULL;
 580     }
 581
 582     dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
 583     bo = dri_bo_alloc(i965->intel.bufmgr,
 584                       "Buffer",
 585                       width_in_mbs * 64,
 586                       64);
 587     assert(bo);
 588     mfc_context->intra_row_store_scratch_buffer.bo = bo;
 589
 590     dri_bo_unreference(mfc_context->macroblock_status_buffer.bo);
 591     bo = dri_bo_alloc(i965->intel.bufmgr,
 592                       "Buffer",
 593                       width_in_mbs * height_in_mbs * 16,
 594                       64);
 595     assert(bo);
 596     mfc_context->macroblock_status_buffer.bo = bo;
 597
 598     dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
 599     bo = dri_bo_alloc(i965->intel.bufmgr,
 600                       "Buffer",
 601                       4 * width_in_mbs * 64,  /* 4 * width_in_mbs * 64 */
 602                       64);
 603     assert(bo);
 604     mfc_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
 605
 606     dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
 607     bo = dri_bo_alloc(i965->intel.bufmgr,
 608                       "Buffer",
 609                       128 * width_in_mbs, /* 2 * widht_in_mbs * 64 */
 610                       0x1000);
 611     assert(bo);
 612     mfc_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
 613
 614     dri_bo_unreference(mfc_context->mfc_batchbuffer_surface.bo);
 615     mfc_context->mfc_batchbuffer_surface.bo = NULL;
 616
 617     dri_bo_unreference(mfc_context->aux_batchbuffer_surface.bo);
 618     mfc_context->aux_batchbuffer_surface.bo = NULL;
 619
 620     if (mfc_context->aux_batchbuffer)
 621         intel_batchbuffer_free(mfc_context->aux_batchbuffer);
 622
 623     mfc_context->aux_batchbuffer = intel_batchbuffer_new(&i965->intel, I915_EXEC_BSD,
 624                                                          slice_batchbuffer_size);
 625     mfc_context->aux_batchbuffer_surface.bo = mfc_context->aux_batchbuffer->buffer;
 626     dri_bo_reference(mfc_context->aux_batchbuffer_surface.bo);
 627     mfc_context->aux_batchbuffer_surface.pitch = 16;
 628     mfc_context->aux_batchbuffer_surface.num_blocks = mfc_context->aux_batchbuffer->size / 16;
 629     mfc_context->aux_batchbuffer_surface.size_block = 16;
 630
 631     i965_gpe_context_init(ctx, &mfc_context->gpe_context);
 632 }
 633
 634 static void gen6_mfc_avc_pipeline_picture_programing(VADriverContextP ctx,
 635                                                      struct encode_state *encode_state,
 636                                                      struct intel_encoder_context *encoder_context)
 637 {
 638     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 639
 640     mfc_context->pipe_mode_select(ctx, MFX_FORMAT_AVC, encoder_context);
 641     mfc_context->set_surface_state(ctx, encoder_context);
 642     mfc_context->ind_obj_base_addr_state(ctx, encoder_context);
 643     gen6_mfc_pipe_buf_addr_state(ctx, encoder_context);
 644     gen6_mfc_bsp_buf_base_addr_state(ctx, encoder_context);
 645     mfc_context->avc_img_state(ctx, encode_state, encoder_context);
 646     mfc_context->avc_qm_state(ctx, encode_state, encoder_context);
 647     mfc_context->avc_fqm_state(ctx, encode_state, encoder_context);
 648     gen6_mfc_avc_directmode_state(ctx, encoder_context);
 649     intel_mfc_avc_ref_idx_state(ctx, encode_state, encoder_context);
 650 }
 651
 652
 653 VAStatus
 654 gen6_mfc_run(VADriverContextP ctx,
 655              struct encode_state *encode_state,
 656              struct intel_encoder_context *encoder_context)
 657 {
 658     struct intel_batchbuffer *batch = encoder_context->base.batch;
 659
 660     intel_batchbuffer_flush(batch);     //run the pipeline
 661
 662     return VA_STATUS_SUCCESS;
 663 }
 664
 665 VAStatus
 666 gen6_mfc_stop(VADriverContextP ctx,
 667               struct encode_state *encode_state,
 668               struct intel_encoder_context *encoder_context,
 669               int *encoded_bits_size)
 670 {
 671     VAStatus vaStatus = VA_STATUS_ERROR_UNKNOWN;
 672     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
 673     VACodedBufferSegment *coded_buffer_segment;
 674
 675     vaStatus = i965_MapBuffer(ctx, pPicParameter->coded_buf, (void **)&coded_buffer_segment);
 676     assert(vaStatus == VA_STATUS_SUCCESS);
 677     *encoded_bits_size = coded_buffer_segment->size * 8;
 678     i965_UnmapBuffer(ctx, pPicParameter->coded_buf);
 679
 680     return VA_STATUS_SUCCESS;
 681 }
 682
 683
 684 static int
 685 gen6_mfc_avc_pak_object_intra(VADriverContextP ctx, int x, int y, int end_mb, int qp, unsigned int *msg,
 686                               struct intel_encoder_context *encoder_context,
 687                               unsigned char target_mb_size, unsigned char max_mb_size,
 688                               struct intel_batchbuffer *batch)
 689 {
 690     int len_in_dwords = 11;
 691
 692     if (batch == NULL)
 693         batch = encoder_context->base.batch;
 694
 695     BEGIN_BCS_BATCH(batch, len_in_dwords);
 696
 697     OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
 698     OUT_BCS_BATCH(batch, 0);
 699     OUT_BCS_BATCH(batch, 0);
 700     OUT_BCS_BATCH(batch,
 701                   (0 << 24) |       /* PackedMvNum, Debug*/
 702                   (0 << 20) |       /* No motion vector */
 703                   (1 << 19) |       /* CbpDcY */
 704                   (1 << 18) |       /* CbpDcU */
 705                   (1 << 17) |       /* CbpDcV */
 706                   (msg[0] & 0xFFFF));
 707
 708     OUT_BCS_BATCH(batch, (0xFFFF << 16) | (y << 8) | x);        /* Code Block Pattern for Y*/
 709     OUT_BCS_BATCH(batch, 0x000F000F);                           /* Code Block Pattern */
 710     OUT_BCS_BATCH(batch, (0 << 27) | (end_mb << 26) | qp);  /* Last MB */
 711
 712     /*Stuff for Intra MB*/
 713     OUT_BCS_BATCH(batch, msg[1]);           /* We using Intra16x16 no 4x4 predmode*/
 714     OUT_BCS_BATCH(batch, msg[2]);
 715     OUT_BCS_BATCH(batch, msg[3] & 0xFC);
 716
 717     /*MaxSizeInWord and TargetSzieInWord*/
 718     OUT_BCS_BATCH(batch, (max_mb_size << 24) |
 719                   (target_mb_size << 16));
 720
 721     ADVANCE_BCS_BATCH(batch);
 722
 723     return len_in_dwords;
 724 }
 725
 726 static int
 727 gen6_mfc_avc_pak_object_inter(VADriverContextP ctx, int x, int y, int end_mb, int qp,
 728                               unsigned int *msg, unsigned int offset,
 729                               struct intel_encoder_context *encoder_context,
 730                               unsigned char target_mb_size, unsigned char max_mb_size, int slice_type,
 731                               struct intel_batchbuffer *batch)
 732 {
 733     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 734     int len_in_dwords = 11;
 735
 736     if (batch == NULL)
 737         batch = encoder_context->base.batch;
 738
 739     BEGIN_BCS_BATCH(batch, len_in_dwords);
 740
 741     OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
 742
 743     OUT_BCS_BATCH(batch, msg[2]);         /* 32 MV*/
 744     OUT_BCS_BATCH(batch, offset);
 745
 746     OUT_BCS_BATCH(batch, msg[0]);
 747
 748     OUT_BCS_BATCH(batch, (0xFFFF << 16) | (y << 8) | x);      /* Code Block Pattern for Y*/
 749     OUT_BCS_BATCH(batch, 0x000F000F);                         /* Code Block Pattern */
 750 #if 0
 751     if (slice_type == SLICE_TYPE_B) {
 752         OUT_BCS_BATCH(batch, (0xF << 28) | (end_mb << 26) | qp); /* Last MB */
 753     } else {
 754         OUT_BCS_BATCH(batch, (end_mb << 26) | qp);  /* Last MB */
 755     }
 756 #else
 757     OUT_BCS_BATCH(batch, (end_mb << 26) | qp);  /* Last MB */
 758 #endif
 759
 760
 761     /*Stuff for Inter MB*/
 762     OUT_BCS_BATCH(batch, msg[1]);
 763     OUT_BCS_BATCH(batch, vme_context->ref_index_in_mb[0]);
 764     OUT_BCS_BATCH(batch, vme_context->ref_index_in_mb[1]);
 765
 766     /*MaxSizeInWord and TargetSzieInWord*/
 767     OUT_BCS_BATCH(batch, (max_mb_size << 24) |
 768                   (target_mb_size << 16));
 769
 770     ADVANCE_BCS_BATCH(batch);
 771
 772     return len_in_dwords;
 773 }
 774
 775 static void
 776 gen6_mfc_avc_pipeline_slice_programing(VADriverContextP ctx,
 777                                        struct encode_state *encode_state,
 778                                        struct intel_encoder_context *encoder_context,
 779                                        int slice_index,
 780                                        struct intel_batchbuffer *slice_batch)
 781 {
 782     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 783     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 784     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 785     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
 786     VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer;
 787     unsigned int *msg = NULL, offset = 0;
 788     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
 789     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
 790     int last_slice = (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks) == (width_in_mbs * height_in_mbs);
 791     int i, x, y;
 792     int qp = pPicParameter->pic_init_qp + pSliceParameter->slice_qp_delta;
 793     unsigned int rate_control_mode = encoder_context->rate_control_mode;
 794     unsigned int tail_data[] = { 0x0, 0x0 };
 795     int slice_type = intel_avc_enc_slice_type_fixup(pSliceParameter->slice_type);
 796     int is_intra = slice_type == SLICE_TYPE_I;
 797     int qp_slice;
 798     int qp_mb;
 799
 800     qp_slice = qp;
 801     if (rate_control_mode != VA_RC_CQP) {
 802         qp = mfc_context->brc.qp_prime_y[encoder_context->layer.curr_frame_layer_id][slice_type];
 803         if (encode_state->slice_header_index[slice_index] == 0) {
 804             pSliceParameter->slice_qp_delta = qp - pPicParameter->pic_init_qp;
 805             qp_slice = qp;
 806         }
 807     }
 808
 809     /* only support for 8-bit pixel bit-depth */
 810     assert(pSequenceParameter->bit_depth_luma_minus8 == 0);
 811     assert(pSequenceParameter->bit_depth_chroma_minus8 == 0);
 812     assert(pPicParameter->pic_init_qp >= 0 && pPicParameter->pic_init_qp < 52);
 813     assert(qp >= 0 && qp < 52);
 814
 815     gen6_mfc_avc_slice_state(ctx,
 816                              pPicParameter,
 817                              pSliceParameter,
 818                              encode_state, encoder_context,
 819                              (rate_control_mode != VA_RC_CQP), qp_slice, slice_batch);
 820
 821     if (slice_index == 0)
 822         intel_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch);
 823
 824     intel_avc_slice_insert_packed_data(ctx, encode_state, encoder_context, slice_index, slice_batch);
 825
 826     dri_bo_map(vme_context->vme_output.bo, 1);
 827     msg = (unsigned int *)vme_context->vme_output.bo->virtual;
 828
 829     if (is_intra) {
 830         msg += pSliceParameter->macroblock_address * INTRA_VME_OUTPUT_IN_DWS;
 831     } else {
 832         msg += pSliceParameter->macroblock_address * INTER_VME_OUTPUT_IN_DWS;
 833         msg += 32; /* the first 32 DWs are MVs */
 834         offset = pSliceParameter->macroblock_address * INTER_VME_OUTPUT_IN_BYTES;
 835     }
 836
 837     for (i = pSliceParameter->macroblock_address;
 838          i < pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks; i++) {
 839         int last_mb = (i == (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks - 1));
 840         x = i % width_in_mbs;
 841         y = i / width_in_mbs;
 842
 843         if (vme_context->roi_enabled) {
 844             qp_mb = *(vme_context->qp_per_mb + i);
 845         } else {
 846             qp_mb = qp;
 847         }
 848
 849         if (is_intra) {
 850             assert(msg);
 851             gen6_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp_mb, msg, encoder_context, 0, 0, slice_batch);
 852             msg += INTRA_VME_OUTPUT_IN_DWS;
 853         } else {
 854             if (msg[0] & INTRA_MB_FLAG_MASK) {
 855                 gen6_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp_mb, msg, encoder_context, 0, 0, slice_batch);
 856             } else {
 857                 gen6_mfc_avc_pak_object_inter(ctx, x, y, last_mb, qp_mb,
 858                                               msg, offset, encoder_context,
 859                                               0, 0, slice_type, slice_batch);
 860             }
 861
 862             msg += INTER_VME_OUTPUT_IN_DWS;
 863             offset += INTER_VME_OUTPUT_IN_BYTES;
 864         }
 865     }
 866
 867     dri_bo_unmap(vme_context->vme_output.bo);
 868
 869     if (last_slice) {
 870         mfc_context->insert_object(ctx, encoder_context,
 871                                    tail_data, 2, 8,
 872                                    2, 1, 1, 0, slice_batch);
 873     } else {
 874         mfc_context->insert_object(ctx, encoder_context,
 875                                    tail_data, 1, 8,
 876                                    1, 1, 1, 0, slice_batch);
 877     }
 878
 879
 880 }
 881
 882 static dri_bo *
 883 gen6_mfc_avc_software_batchbuffer(VADriverContextP ctx,
 884                                   struct encode_state *encode_state,
 885                                   struct intel_encoder_context *encoder_context)
 886 {
 887     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 888     struct intel_batchbuffer *batch;;
 889     dri_bo *batch_bo;
 890     int i;
 891
 892     batch = mfc_context->aux_batchbuffer;
 893     batch_bo = batch->buffer;
 894
 895     for (i = 0; i < encode_state->num_slice_params_ext; i++) {
 896         gen6_mfc_avc_pipeline_slice_programing(ctx, encode_state, encoder_context, i, batch);
 897     }
 898
 899     intel_batchbuffer_align(batch, 8);
 900
 901     BEGIN_BCS_BATCH(batch, 2);
 902     OUT_BCS_BATCH(batch, 0);
 903     OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_END);
 904     ADVANCE_BCS_BATCH(batch);
 905
 906     dri_bo_reference(batch_bo);
 907
 908     intel_batchbuffer_free(batch);
 909     mfc_context->aux_batchbuffer = NULL;
 910
 911     return batch_bo;
 912 }
 913
 914
 915 static void
 916 gen6_mfc_batchbuffer_surfaces_input(VADriverContextP ctx,
 917                                     struct encode_state *encode_state,
 918                                     struct intel_encoder_context *encoder_context)
 919
 920 {
 921     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 922     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 923
 924     assert(vme_context->vme_output.bo);
 925     mfc_context->buffer_suface_setup(ctx,
 926                                      &mfc_context->gpe_context,
 927                                      &vme_context->vme_output,
 928                                      BINDING_TABLE_OFFSET(BIND_IDX_VME_OUTPUT),
 929                                      SURFACE_STATE_OFFSET(BIND_IDX_VME_OUTPUT));
 930     assert(mfc_context->aux_batchbuffer_surface.bo);
 931     mfc_context->buffer_suface_setup(ctx,
 932                                      &mfc_context->gpe_context,
 933                                      &mfc_context->aux_batchbuffer_surface,
 934                                      BINDING_TABLE_OFFSET(BIND_IDX_MFC_SLICE_HEADER),
 935                                      SURFACE_STATE_OFFSET(BIND_IDX_MFC_SLICE_HEADER));
 936 }
 937
 938 static void
 939 gen6_mfc_batchbuffer_surfaces_output(VADriverContextP ctx,
 940                                      struct encode_state *encode_state,
 941                                      struct intel_encoder_context *encoder_context)
 942
 943 {
 944     struct i965_driver_data *i965 = i965_driver_data(ctx);
 945     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 946     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 947     int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
 948     int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
 949     mfc_context->mfc_batchbuffer_surface.num_blocks = width_in_mbs * height_in_mbs + encode_state->num_slice_params_ext * 8 + 1;
 950     mfc_context->mfc_batchbuffer_surface.size_block = 16 * CMD_LEN_IN_OWORD; /* 3 OWORDs */
 951     mfc_context->mfc_batchbuffer_surface.pitch = 16;
 952     mfc_context->mfc_batchbuffer_surface.bo = dri_bo_alloc(i965->intel.bufmgr,
 953                                                            "MFC batchbuffer",
 954                                                            mfc_context->mfc_batchbuffer_surface.num_blocks * mfc_context->mfc_batchbuffer_surface.size_block,
 955                                                            0x1000);
 956     mfc_context->buffer_suface_setup(ctx,
 957                                      &mfc_context->gpe_context,
 958                                      &mfc_context->mfc_batchbuffer_surface,
 959                                      BINDING_TABLE_OFFSET(BIND_IDX_MFC_BATCHBUFFER),
 960                                      SURFACE_STATE_OFFSET(BIND_IDX_MFC_BATCHBUFFER));
 961 }
 962
 963 static void
 964 gen6_mfc_batchbuffer_surfaces_setup(VADriverContextP ctx,
 965                                     struct encode_state *encode_state,
 966                                     struct intel_encoder_context *encoder_context)
 967 {
 968     gen6_mfc_batchbuffer_surfaces_input(ctx, encode_state, encoder_context);
 969     gen6_mfc_batchbuffer_surfaces_output(ctx, encode_state, encoder_context);
 970 }
 971
 972 static void
 973 gen6_mfc_batchbuffer_idrt_setup(VADriverContextP ctx,
 974                                 struct encode_state *encode_state,
 975                                 struct intel_encoder_context *encoder_context)
 976 {
 977     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 978     struct gen6_interface_descriptor_data *desc;
 979     int i;
 980     dri_bo *bo;
 981
 982     bo = mfc_context->gpe_context.idrt.bo;
 983     dri_bo_map(bo, 1);
 984     assert(bo->virtual);
 985     desc = bo->virtual;
 986
 987     for (i = 0; i < mfc_context->gpe_context.num_kernels; i++) {
 988         struct i965_kernel *kernel;
 989
 990         kernel = &mfc_context->gpe_context.kernels[i];
 991         assert(sizeof(*desc) == 32);
 992
 993         /*Setup the descritor table*/
 994         memset(desc, 0, sizeof(*desc));
 995         desc->desc0.kernel_start_pointer = (kernel->bo->offset >> 6);
 996         desc->desc2.sampler_count = 0;
 997         desc->desc2.sampler_state_pointer = 0;
 998         desc->desc3.binding_table_entry_count = 2;
 999         desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET(0) >> 5);
1000         desc->desc4.constant_urb_entry_read_offset = 0;
1001         desc->desc4.constant_urb_entry_read_length = 4;
1002
1003         /*kernel start*/
1004         dri_bo_emit_reloc(bo,
1005                           I915_GEM_DOMAIN_INSTRUCTION, 0,
1006                           0,
1007                           i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc0),
1008                           kernel->bo);
1009         desc++;
1010     }
1011
1012     dri_bo_unmap(bo);
1013 }
1014
1015 static void
1016 gen6_mfc_batchbuffer_constant_setup(VADriverContextP ctx,
1017                                     struct encode_state *encode_state,
1018                                     struct intel_encoder_context *encoder_context)
1019 {
1020     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1021
1022     (void)mfc_context;
1023 }
1024
1025 static void
1026 gen6_mfc_batchbuffer_emit_object_command(struct intel_batchbuffer *batch,
1027                                          int index,
1028                                          int head_offset,
1029                                          int batchbuffer_offset,
1030                                          int head_size,
1031                                          int tail_size,
1032                                          int number_mb_cmds,
1033                                          int first_object,
1034                                          int last_object,
1035                                          int last_slice,
1036                                          int mb_x,
1037                                          int mb_y,
1038                                          int width_in_mbs,
1039                                          int qp,
1040                                          unsigned int ref_index[2])
1041 {
1042     BEGIN_BATCH(batch, 14);
1043
1044     OUT_BATCH(batch, CMD_MEDIA_OBJECT | (14 - 2));
1045     OUT_BATCH(batch, index);
1046     OUT_BATCH(batch, 0);
1047     OUT_BATCH(batch, 0);
1048     OUT_BATCH(batch, 0);
1049     OUT_BATCH(batch, 0);
1050
1051     /*inline data */
1052     OUT_BATCH(batch, head_offset);
1053     OUT_BATCH(batch, batchbuffer_offset);
1054     OUT_BATCH(batch,
1055               head_size << 16 |
1056               tail_size);
1057     OUT_BATCH(batch,
1058               number_mb_cmds << 16 |
1059               first_object << 2 |
1060               last_object << 1 |
1061               last_slice);
1062     OUT_BATCH(batch,
1063               mb_y << 8 |
1064               mb_x);
1065     OUT_BATCH(batch,
1066               qp << 16 |
1067               width_in_mbs);
1068     OUT_BATCH(batch, ref_index[0]);
1069     OUT_BATCH(batch, ref_index[1]);
1070
1071     ADVANCE_BATCH(batch);
1072 }
1073
1074 static void
1075 gen6_mfc_avc_batchbuffer_slice_command(VADriverContextP ctx,
1076                                        struct intel_encoder_context *encoder_context,
1077                                        VAEncSliceParameterBufferH264 *slice_param,
1078                                        int head_offset,
1079                                        unsigned short head_size,
1080                                        unsigned short tail_size,
1081                                        int batchbuffer_offset,
1082                                        int qp,
1083                                        int last_slice)
1084 {
1085     struct intel_batchbuffer *batch = encoder_context->base.batch;
1086     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1087     struct gen6_vme_context *vme_context = encoder_context->vme_context;
1088     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
1089     int total_mbs = slice_param->num_macroblocks;
1090     int number_mb_cmds = 128;
1091     int starting_mb = 0;
1092     int last_object = 0;
1093     int first_object = 1;
1094     int i;
1095     int mb_x, mb_y;
1096     int index = (slice_param->slice_type == SLICE_TYPE_I) ? MFC_BATCHBUFFER_AVC_INTRA : MFC_BATCHBUFFER_AVC_INTER;
1097
1098     for (i = 0; i < total_mbs / number_mb_cmds; i++) {
1099         last_object = (total_mbs - starting_mb) == number_mb_cmds;
1100         mb_x = (slice_param->macroblock_address + starting_mb) % width_in_mbs;
1101         mb_y = (slice_param->macroblock_address + starting_mb) / width_in_mbs;
1102         assert(mb_x <= 255 && mb_y <= 255);
1103
1104         starting_mb += number_mb_cmds;
1105
1106         gen6_mfc_batchbuffer_emit_object_command(batch,
1107                                                  index,
1108                                                  head_offset,
1109                                                  batchbuffer_offset,
1110                                                  head_size,
1111                                                  tail_size,
1112                                                  number_mb_cmds,
1113                                                  first_object,
1114                                                  last_object,
1115                                                  last_slice,
1116                                                  mb_x,
1117                                                  mb_y,
1118                                                  width_in_mbs,
1119                                                  qp,
1120                                                  vme_context->ref_index_in_mb);
1121
1122         if (first_object) {
1123             head_offset += head_size;
1124             batchbuffer_offset += head_size;
1125         }
1126
1127         if (last_object) {
1128             head_offset += tail_size;
1129             batchbuffer_offset += tail_size;
1130         }
1131
1132         batchbuffer_offset += number_mb_cmds * CMD_LEN_IN_OWORD;
1133
1134         first_object = 0;
1135     }
1136
1137     if (!last_object) {
1138         last_object = 1;
1139         number_mb_cmds = total_mbs % number_mb_cmds;
1140         mb_x = (slice_param->macroblock_address + starting_mb) % width_in_mbs;
1141         mb_y = (slice_param->macroblock_address + starting_mb) / width_in_mbs;
1142         assert(mb_x <= 255 && mb_y <= 255);
1143         starting_mb += number_mb_cmds;
1144
1145         gen6_mfc_batchbuffer_emit_object_command(batch,
1146                                                  index,
1147                                                  head_offset,
1148                                                  batchbuffer_offset,
1149                                                  head_size,
1150                                                  tail_size,
1151                                                  number_mb_cmds,
1152                                                  first_object,
1153                                                  last_object,
1154                                                  last_slice,
1155                                                  mb_x,
1156                                                  mb_y,
1157                                                  width_in_mbs,
1158                                                  qp,
1159                                                  vme_context->ref_index_in_mb);
1160     }
1161 }
1162
1163 /*
1164  * return size in Owords (16bytes)
1165  */
1166 static int
1167 gen6_mfc_avc_batchbuffer_slice(VADriverContextP ctx,
1168                                struct encode_state *encode_state,
1169                                struct intel_encoder_context *encoder_context,
1170                                int slice_index,
1171                                int batchbuffer_offset)
1172 {
1173     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1174     struct intel_batchbuffer *slice_batch = mfc_context->aux_batchbuffer;
1175     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
1176     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
1177     VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer;
1178     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
1179     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
1180     int last_slice = (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks) == (width_in_mbs * height_in_mbs);
1181     int qp = pPicParameter->pic_init_qp + pSliceParameter->slice_qp_delta;
1182     unsigned int rate_control_mode = encoder_context->rate_control_mode;
1183     unsigned int tail_data[] = { 0x0, 0x0 };
1184     long head_offset;
1185     int old_used = intel_batchbuffer_used_size(slice_batch), used;
1186     unsigned short head_size, tail_size;
1187     int slice_type = intel_avc_enc_slice_type_fixup(pSliceParameter->slice_type);
1188     int qp_slice;
1189
1190     qp_slice = qp;
1191     if (rate_control_mode != VA_RC_CQP) {
1192         qp = mfc_context->brc.qp_prime_y[encoder_context->layer.curr_frame_layer_id][slice_type];
1193         if (encode_state->slice_header_index[slice_index] == 0) {
1194             pSliceParameter->slice_qp_delta = qp - pPicParameter->pic_init_qp;
1195             /* Use the adjusted qp when slice_header is generated by driver */
1196             qp_slice = qp;
1197         }
1198     }
1199
1200     /* only support for 8-bit pixel bit-depth */
1201     assert(pSequenceParameter->bit_depth_luma_minus8 == 0);
1202     assert(pSequenceParameter->bit_depth_chroma_minus8 == 0);
1203     assert(pPicParameter->pic_init_qp >= 0 && pPicParameter->pic_init_qp < 52);
1204     assert(qp >= 0 && qp < 52);
1205
1206     head_offset = old_used / 16;
1207     gen6_mfc_avc_slice_state(ctx,
1208                              pPicParameter,
1209                              pSliceParameter,
1210                              encode_state,
1211                              encoder_context,
1212                              (rate_control_mode != VA_RC_CQP),
1213                              qp_slice,
1214                              slice_batch);
1215
1216     if (slice_index == 0) {
1217         intel_avc_insert_aud_packed_data(ctx, encode_state, encoder_context, slice_batch);
1218         intel_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch);
1219     }
1220
1221     intel_avc_slice_insert_packed_data(ctx, encode_state, encoder_context, slice_index, slice_batch);
1222
1223     intel_batchbuffer_align(slice_batch, 16); /* aligned by an Oword */
1224     used = intel_batchbuffer_used_size(slice_batch);
1225     head_size = (used - old_used) / 16;
1226     old_used = used;
1227
1228     /* tail */
1229     if (last_slice) {
1230         mfc_context->insert_object(ctx,
1231                                    encoder_context,
1232                                    tail_data,
1233                                    2,
1234                                    8,
1235                                    2,
1236                                    1,
1237                                    1,
1238                                    0,
1239                                    slice_batch);
1240     } else {
1241         mfc_context->insert_object(ctx,
1242                                    encoder_context,
1243                                    tail_data,
1244                                    1,
1245                                    8,
1246                                    1,
1247                                    1,
1248                                    1,
1249                                    0,
1250                                    slice_batch);
1251     }
1252
1253     intel_batchbuffer_align(slice_batch, 16); /* aligned by an Oword */
1254     used = intel_batchbuffer_used_size(slice_batch);
1255     tail_size = (used - old_used) / 16;
1256
1257
1258     gen6_mfc_avc_batchbuffer_slice_command(ctx,
1259                                            encoder_context,
1260                                            pSliceParameter,
1261                                            head_offset,
1262                                            head_size,
1263                                            tail_size,
1264                                            batchbuffer_offset,
1265                                            qp,
1266                                            last_slice);
1267
1268     return head_size + tail_size + pSliceParameter->num_macroblocks * CMD_LEN_IN_OWORD;
1269 }
1270
1271 static void
1272 gen6_mfc_avc_batchbuffer_pipeline(VADriverContextP ctx,
1273                                   struct encode_state *encode_state,
1274                                   struct intel_encoder_context *encoder_context)
1275 {
1276     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1277     struct intel_batchbuffer *batch = encoder_context->base.batch;
1278     int i, size, offset = 0;
1279     intel_batchbuffer_start_atomic(batch, 0x4000);
1280     gen6_gpe_pipeline_setup(ctx, &mfc_context->gpe_context, batch);
1281
1282     for (i = 0; i < encode_state->num_slice_params_ext; i++) {
1283         size = gen6_mfc_avc_batchbuffer_slice(ctx, encode_state, encoder_context, i, offset);
1284         offset += size;
1285     }
1286
1287     intel_batchbuffer_end_atomic(batch);
1288     intel_batchbuffer_flush(batch);
1289 }
1290
1291 static void
1292 gen6_mfc_build_avc_batchbuffer(VADriverContextP ctx,
1293                                struct encode_state *encode_state,
1294                                struct intel_encoder_context *encoder_context)
1295 {
1296     gen6_mfc_batchbuffer_surfaces_setup(ctx, encode_state, encoder_context);
1297     gen6_mfc_batchbuffer_idrt_setup(ctx, encode_state, encoder_context);
1298     gen6_mfc_batchbuffer_constant_setup(ctx, encode_state, encoder_context);
1299     gen6_mfc_avc_batchbuffer_pipeline(ctx, encode_state, encoder_context);
1300 }
1301
1302 static dri_bo *
1303 gen6_mfc_avc_hardware_batchbuffer(VADriverContextP ctx,
1304                                   struct encode_state *encode_state,
1305                                   struct intel_encoder_context *encoder_context)
1306 {
1307     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1308
1309     gen6_mfc_build_avc_batchbuffer(ctx, encode_state, encoder_context);
1310     dri_bo_reference(mfc_context->mfc_batchbuffer_surface.bo);
1311
1312     return mfc_context->mfc_batchbuffer_surface.bo;
1313 }
1314
1315
1316
1317 static void
1318 gen6_mfc_avc_pipeline_programing(VADriverContextP ctx,
1319                                  struct encode_state *encode_state,
1320                                  struct intel_encoder_context *encoder_context)
1321 {
1322     struct intel_batchbuffer *batch = encoder_context->base.batch;
1323     dri_bo *slice_batch_bo;
1324
1325     if (intel_mfc_interlace_check(ctx, encode_state, encoder_context)) {
1326         fprintf(stderr, "Current VA driver don't support interlace mode!\n");
1327         assert(0);
1328         return;
1329     }
1330
1331     if (encoder_context->soft_batch_force)
1332         slice_batch_bo = gen6_mfc_avc_software_batchbuffer(ctx, encode_state, encoder_context);
1333     else
1334         slice_batch_bo = gen6_mfc_avc_hardware_batchbuffer(ctx, encode_state, encoder_context);
1335
1336     // begin programing
1337     intel_batchbuffer_start_atomic_bcs(batch, 0x4000);
1338     intel_batchbuffer_emit_mi_flush(batch);
1339
1340     // picture level programing
1341     gen6_mfc_avc_pipeline_picture_programing(ctx, encode_state, encoder_context);
1342
1343     BEGIN_BCS_BATCH(batch, 2);
1344     OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8));
1345     OUT_BCS_RELOC(batch,
1346                   slice_batch_bo,
1347                   I915_GEM_DOMAIN_COMMAND, 0,
1348                   0);
1349     ADVANCE_BCS_BATCH(batch);
1350
1351     // end programing
1352     intel_batchbuffer_end_atomic(batch);
1353
1354     dri_bo_unreference(slice_batch_bo);
1355 }
1356
1357 VAStatus
1358 gen6_mfc_avc_encode_picture(VADriverContextP ctx,
1359                             struct encode_state *encode_state,
1360                             struct intel_encoder_context *encoder_context)
1361 {
1362     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1363     unsigned int rate_control_mode = encoder_context->rate_control_mode;
1364     int current_frame_bits_size;
1365     int sts;
1366
1367     for (;;) {
1368         gen6_mfc_init(ctx, encode_state, encoder_context);
1369         intel_mfc_avc_prepare(ctx, encode_state, encoder_context);
1370         /*Programing bcs pipeline*/
1371         gen6_mfc_avc_pipeline_programing(ctx, encode_state, encoder_context);   //filling the pipeline
1372         gen6_mfc_run(ctx, encode_state, encoder_context);
1373         if (rate_control_mode == VA_RC_CBR || rate_control_mode == VA_RC_VBR) {
1374             gen6_mfc_stop(ctx, encode_state, encoder_context, &current_frame_bits_size);
1375             sts = intel_mfc_brc_postpack(encode_state, encoder_context, current_frame_bits_size);
1376             if (sts == BRC_NO_HRD_VIOLATION) {
1377                 intel_mfc_hrd_context_update(encode_state, mfc_context);
1378                 break;
1379             } else if (sts == BRC_OVERFLOW_WITH_MIN_QP || sts == BRC_UNDERFLOW_WITH_MAX_QP) {
1380                 if (!mfc_context->hrd.violation_noted) {
1381                     fprintf(stderr, "Unrepairable %s!\n", (sts == BRC_OVERFLOW_WITH_MIN_QP) ? "overflow" : "underflow");
1382                     mfc_context->hrd.violation_noted = 1;
1383                 }
1384                 return VA_STATUS_SUCCESS;
1385             }
1386         } else {
1387             break;
1388         }
1389     }
1390
1391     return VA_STATUS_SUCCESS;
1392 }
1393
1394 VAStatus
1395 gen6_mfc_pipeline(VADriverContextP ctx,
1396                   VAProfile profile,
1397                   struct encode_state *encode_state,
1398                   struct intel_encoder_context *encoder_context)
1399 {
1400     VAStatus vaStatus;
1401
1402     switch (profile) {
1403     case VAProfileH264ConstrainedBaseline:
1404     case VAProfileH264Main:
1405     case VAProfileH264High:
1406         vaStatus = gen6_mfc_avc_encode_picture(ctx, encode_state, encoder_context);
1407         break;
1408
1409     default:
1410         vaStatus = VA_STATUS_ERROR_UNSUPPORTED_PROFILE;
1411         break;
1412     }
1413
1414     return vaStatus;
1415 }
1416
1417 void
1418 gen6_mfc_context_destroy(void *context)
1419 {
1420     struct gen6_mfc_context *mfc_context = context;
1421     int i;
1422
1423     dri_bo_unreference(mfc_context->post_deblocking_output.bo);
1424     mfc_context->post_deblocking_output.bo = NULL;
1425
1426     dri_bo_unreference(mfc_context->pre_deblocking_output.bo);
1427     mfc_context->pre_deblocking_output.bo = NULL;
1428
1429     dri_bo_unreference(mfc_context->uncompressed_picture_source.bo);
1430     mfc_context->uncompressed_picture_source.bo = NULL;
1431
1432     dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo);
1433     mfc_context->mfc_indirect_pak_bse_object.bo = NULL;
1434
1435     for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++) {
1436         dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
1437         mfc_context->direct_mv_buffers[i].bo = NULL;
1438     }
1439
1440     dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
1441     mfc_context->intra_row_store_scratch_buffer.bo = NULL;
1442
1443     dri_bo_unreference(mfc_context->macroblock_status_buffer.bo);
1444     mfc_context->macroblock_status_buffer.bo = NULL;
1445
1446     dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
1447     mfc_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
1448
1449     dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
1450     mfc_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
1451
1452
1453     for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++) {
1454         dri_bo_unreference(mfc_context->reference_surfaces[i].bo);
1455         mfc_context->reference_surfaces[i].bo = NULL;
1456     }
1457
1458     i965_gpe_context_destroy(&mfc_context->gpe_context);
1459
1460     dri_bo_unreference(mfc_context->mfc_batchbuffer_surface.bo);
1461     mfc_context->mfc_batchbuffer_surface.bo = NULL;
1462
1463     dri_bo_unreference(mfc_context->aux_batchbuffer_surface.bo);
1464     mfc_context->aux_batchbuffer_surface.bo = NULL;
1465
1466     if (mfc_context->aux_batchbuffer)
1467         intel_batchbuffer_free(mfc_context->aux_batchbuffer);
1468
1469     mfc_context->aux_batchbuffer = NULL;
1470
1471     free(mfc_context);
1472 }
1473
1474 Bool gen6_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
1475 {
1476     struct gen6_mfc_context *mfc_context = calloc(1, sizeof(struct gen6_mfc_context));
1477
1478     if (!mfc_context)
1479         return False;
1480
1481     mfc_context->gpe_context.surface_state_binding_table.length = (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6;
1482
1483     mfc_context->gpe_context.idrt.max_entries = MAX_GPE_KERNELS;
1484     mfc_context->gpe_context.idrt.entry_size = sizeof(struct gen6_interface_descriptor_data);
1485
1486     mfc_context->gpe_context.curbe.length = 32 * 4;
1487
1488     mfc_context->gpe_context.vfe_state.max_num_threads = 60 - 1;
1489     mfc_context->gpe_context.vfe_state.num_urb_entries = 16;
1490     mfc_context->gpe_context.vfe_state.gpgpu_mode = 0;
1491     mfc_context->gpe_context.vfe_state.urb_entry_size = 59 - 1;
1492     mfc_context->gpe_context.vfe_state.curbe_allocation_size = 37 - 1;
1493
1494     i965_gpe_load_kernels(ctx,
1495                           &mfc_context->gpe_context,
1496                           gen6_mfc_kernels,
1497                           NUM_MFC_KERNEL);
1498
1499     mfc_context->pipe_mode_select = gen6_mfc_pipe_mode_select;
1500     mfc_context->set_surface_state = gen6_mfc_surface_state;
1501     mfc_context->ind_obj_base_addr_state = gen6_mfc_ind_obj_base_addr_state;
1502     mfc_context->avc_img_state = gen6_mfc_avc_img_state;
1503     mfc_context->avc_qm_state = gen6_mfc_avc_qm_state;
1504     mfc_context->avc_fqm_state = gen6_mfc_avc_fqm_state;
1505     mfc_context->insert_object = gen6_mfc_avc_insert_object;
1506     mfc_context->buffer_suface_setup = i965_gpe_buffer_suface_setup;
1507
1508     encoder_context->mfc_context = mfc_context;
1509     encoder_context->mfc_context_destroy = gen6_mfc_context_destroy;
1510     encoder_context->mfc_pipeline = gen6_mfc_pipeline;
1511     encoder_context->mfc_brc_prepare = intel_mfc_brc_prepare;
1512
1513     return True;
1514 }