src/gen6_mfc.h

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Zhou Chang <chang.zhou@intel.com>
  26  *
  27  */
  28
  29 #ifndef _GEN6_MFC_H_
  30 #define _GEN6_MFC_H_
  31
  32 #include <drm.h>
  33 #include <i915_drm.h>
  34 #include <intel_bufmgr.h>
  35
  36 #include "i965_encoder.h"
  37 #include "i965_gpe_utils.h"
  38
  39 struct encode_state;
  40
  41 #define MAX_MFC_REFERENCE_SURFACES      16
  42 #define NUM_MFC_DMV_BUFFERS             34
  43
  44 #define INTRA_MB_FLAG_MASK              0x00002000
  45
  46 /* The space required for slice header SLICE_STATE + header.
  47  * Is it enough? */
  48 #define SLICE_HEADER                    80
  49
  50 /* the space required for slice tail. */
  51 #define SLICE_TAIL                      16
  52
  53
  54 #define MFC_BATCHBUFFER_AVC_INTRA       0
  55 #define MFC_BATCHBUFFER_AVC_INTER       1
  56 #define NUM_MFC_KERNEL                  2
  57
  58 #define BIND_IDX_VME_OUTPUT             0
  59 #define BIND_IDX_MFC_SLICE_HEADER       1
  60 #define BIND_IDX_MFC_BATCHBUFFER        2
  61
  62 #define CMD_LEN_IN_OWORD        4
  63
  64 #define BRC_CLIP(x, min, max)                                   \
  65     {                                                           \
  66         x = ((x > (max)) ? (max) : ((x < (min)) ? (min) : x));  \
  67     }
  68
  69 #define BRC_P_B_QP_DIFF 4
  70 #define BRC_I_P_QP_DIFF 2
  71 #define BRC_I_B_QP_DIFF (BRC_I_P_QP_DIFF + BRC_P_B_QP_DIFF)
  72
  73 #define BRC_PWEIGHT 0.6  /* weight if P slice with comparison to I slice */
  74 #define BRC_BWEIGHT 0.25 /* weight if B slice with comparison to I slice */
  75
  76 #define BRC_QP_MAX_CHANGE 5 /* maximum qp modification */
  77 #define BRC_CY 0.1 /* weight for */
  78 #define BRC_CX_UNDERFLOW 5.
  79 #define BRC_CX_OVERFLOW -4.
  80
  81 #define BRC_PI_0_5 1.5707963267948966192313216916398
  82
  83 typedef enum {
  84    VME_V_PRED = 0,
  85    VME_H_PRED = 1,
  86    VME_DC_PRED = 2,
  87    VME_PL_PRED = 3,
  88
  89    VME_MB_INTRA_MODE_COUNT
  90 } VME_MB_INTRA_PRED_MODE;
  91
  92 typedef enum {
  93    PAK_DC_PRED = 0,
  94    PAK_V_PRED = 1,
  95    PAK_H_PRED = 2,
  96    PAK_TM_PRED = 3,
  97
  98    PAK_MB_INTRA_MODE_COUNT
  99 } VP8_PAK_MB_INTRA_PRED_MODE;
 100
 101 typedef enum
 102 {
 103     VME_B_V_PRED = 0,
 104     VME_B_H_PRED = 1,
 105     VME_B_DC_PRED = 2,
 106     VME_B_DL_PRED = 3,
 107     VME_B_DR_PRED = 4,
 108     VME_B_VR_PRED = 5,
 109     VME_B_HD_PRED = 6,
 110     VME_B_VL_PRED = 7,
 111     VME_B_HU_PRED = 8,
 112
 113     VME_B_INTRA_MODE_COUNT
 114 } VME_BLOCK_INTRA_PRED_MODE;
 115
 116 typedef enum
 117 {
 118     PAK_B_DC_PRED = 0,
 119     PAK_B_TM_PRED = 1,
 120     PAK_B_VE_PRED = 2,
 121     PAK_B_HE_PRED = 3,
 122     PAK_B_LD_PRED = 4,
 123     PAK_B_RD_PRED = 5,
 124     PAK_B_VR_PRED = 6,
 125     PAK_B_VL_PRED = 7,
 126     PAK_B_HD_PRED = 8,
 127     PAK_B_HU_PRED = 9,
 128
 129     PAK_B_INTRA_MODE_COUNT
 130 } VP8_PAK_BLOCK_INTRA_PRED_MODE;
 131
 132 typedef struct
 133 {
 134   int vme_intra_mb_mode;
 135   int vp8_pak_intra_mb_mode;
 136 } vp8_intra_mb_mode_map_t;
 137
 138 typedef struct
 139 {
 140   int vme_intra_block_mode;
 141   int vp8_pak_intra_block_mode;
 142 } vp8_intra_block_mode_map_t;
 143
 144 typedef enum _gen6_brc_status
 145 {
 146     BRC_NO_HRD_VIOLATION = 0,
 147     BRC_UNDERFLOW = 1,
 148     BRC_OVERFLOW = 2,
 149     BRC_UNDERFLOW_WITH_MAX_QP = 3,
 150     BRC_OVERFLOW_WITH_MIN_QP = 4,
 151 } gen6_brc_status;
 152
 153 struct gen6_mfc_avc_surface_aux
 154 {
 155     dri_bo *dmv_top;
 156     dri_bo *dmv_bottom;
 157 };
 158
 159 struct gen6_mfc_context
 160 {
 161     struct {
 162         unsigned int width;
 163         unsigned int height;
 164         unsigned int w_pitch;
 165         unsigned int h_pitch;
 166     } surface_state;
 167
 168     //MFX_PIPE_BUF_ADDR_STATE
 169     struct {
 170         dri_bo *bo;
 171     } post_deblocking_output;           //OUTPUT: reconstructed picture
 172
 173     struct {
 174         dri_bo *bo;
 175     } pre_deblocking_output;            //OUTPUT: reconstructed picture with deblocked
 176
 177     struct {
 178         dri_bo *bo;
 179     } uncompressed_picture_source;      //INPUT: original compressed image
 180
 181     struct {
 182         dri_bo *bo;
 183     } intra_row_store_scratch_buffer;   //INTERNAL:
 184
 185     struct {
 186         dri_bo *bo;
 187     } macroblock_status_buffer;         //INTERNAL:
 188
 189     struct {
 190         dri_bo *bo;
 191     } deblocking_filter_row_store_scratch_buffer;       //INTERNAL:
 192
 193     struct {
 194         dri_bo *bo;
 195     } reference_surfaces[MAX_MFC_REFERENCE_SURFACES];   //INTERNAL: refrence surfaces
 196
 197     //MFX_IND_OBJ_BASE_ADDR_STATE
 198     struct{
 199         dri_bo *bo;
 200     } mfc_indirect_mv_object;           //INPUT: the blocks' mv info
 201
 202     struct {
 203         dri_bo *bo;
 204         int offset;
 205         int end_offset;
 206     } mfc_indirect_pak_bse_object;      //OUTPUT: the compressed bitstream
 207
 208     //MFX_BSP_BUF_BASE_ADDR_STATE
 209     struct {
 210         dri_bo *bo;
 211     } bsd_mpc_row_store_scratch_buffer; //INTERNAL:
 212
 213     //MFX_AVC_DIRECTMODE_STATE
 214     struct {
 215         dri_bo *bo;
 216     } direct_mv_buffers[NUM_MFC_DMV_BUFFERS];   //INTERNAL: 0-31 as input,32 and 33 as output
 217
 218     //Bit rate tracking context
 219     struct {
 220         unsigned int MaxQpNegModifier;
 221         unsigned int MaxQpPosModifier;
 222         unsigned char Correct[6];
 223         unsigned char GrowInit;
 224         unsigned char GrowResistance;
 225         unsigned char ShrinkInit;
 226         unsigned char ShrinkResistance;
 227     } bit_rate_control_context[3];      //INTERNAL: for I, P, B frames
 228
 229     struct {
 230         int mode;
 231         int gop_nums[MAX_MFC_REFERENCE_SURFACES][3];
 232         int target_frame_size[MAX_TEMPORAL_LAYERS][3]; // I,P,B
 233         int qp_prime_y[MAX_TEMPORAL_LAYERS][3];
 234         double bits_per_frame[MAX_TEMPORAL_LAYERS];
 235         double qpf_rounding_accumulator[MAX_TEMPORAL_LAYERS];
 236         int bits_prev_frame[MAX_TEMPORAL_LAYERS];
 237         int prev_slice_type[MAX_TEMPORAL_LAYERS];
 238     } brc;
 239
 240     struct {
 241         double current_buffer_fullness[MAX_TEMPORAL_LAYERS];
 242         double target_buffer_fullness[MAX_TEMPORAL_LAYERS];
 243         double buffer_capacity[MAX_TEMPORAL_LAYERS];
 244         unsigned int buffer_size[MAX_TEMPORAL_LAYERS];
 245         unsigned int violation_noted;
 246     } hrd;
 247
 248     //HRD control context
 249     struct {
 250         int i_bit_rate_value;
 251
 252         int i_initial_cpb_removal_delay;
 253         int i_cpb_removal_delay;
 254
 255         int i_frame_number;
 256
 257         int i_initial_cpb_removal_delay_length;
 258         int i_cpb_removal_delay_length;
 259         int i_dpb_output_delay_length;
 260     }vui_hrd;
 261
 262     struct {
 263         unsigned char *vp8_frame_header;
 264         unsigned int frame_header_bit_count;
 265         unsigned int frame_header_qindex_update_pos;
 266         unsigned int frame_header_lf_update_pos;
 267         unsigned int frame_header_token_update_pos;
 268         unsigned int frame_header_bin_mv_upate_pos;
 269
 270         unsigned int intermediate_partition_offset[8];
 271         unsigned int intermediate_buffer_max_size;
 272         unsigned int final_frame_byte_offset;
 273
 274         unsigned char mb_segment_tree_probs[3];
 275         unsigned char y_mode_probs[4];
 276         unsigned char uv_mode_probs[3];
 277         unsigned char mv_probs[2][19];
 278
 279         unsigned char prob_skip_false;
 280         unsigned char prob_intra;
 281         unsigned char prob_last;
 282         unsigned char prob_gf;
 283
 284         dri_bo *frame_header_bo;
 285         dri_bo *intermediate_bo;
 286         dri_bo *final_frame_bo;
 287         dri_bo *stream_out_bo;
 288         dri_bo *coeff_probs_stream_in_bo;
 289         dri_bo *token_statistics_bo;
 290         dri_bo *mpc_row_store_bo;
 291     }vp8_state;
 292
 293     //"buffered_QMatrix" will be used to buffer the QMatrix if the app sends one.
 294     // Or else, we will load a default QMatrix from the driver for JPEG encode.
 295     VAQMatrixBufferJPEG buffered_qmatrix;
 296     struct i965_gpe_context gpe_context;
 297     struct i965_buffer_surface mfc_batchbuffer_surface;
 298     struct intel_batchbuffer *aux_batchbuffer;
 299     struct i965_buffer_surface aux_batchbuffer_surface;
 300
 301     void (*pipe_mode_select)(VADriverContextP ctx,
 302                              int standard_select,
 303                              struct intel_encoder_context *encoder_context);
 304     void (*set_surface_state)(VADriverContextP ctx,
 305                               struct intel_encoder_context *encoder_context);
 306     void (*ind_obj_base_addr_state)(VADriverContextP ctx,
 307                                     struct intel_encoder_context *encoder_context);
 308     void (*avc_img_state)(VADriverContextP ctx,
 309                           struct encode_state *encode_state,
 310                           struct intel_encoder_context *encoder_context);
 311     void (*avc_qm_state)(VADriverContextP ctx,
 312                          struct encode_state *encode_state,
 313                          struct intel_encoder_context *encoder_context);
 314     void (*avc_fqm_state)(VADriverContextP ctx,
 315                           struct encode_state *encode_state,
 316                           struct intel_encoder_context *encoder_context);
 317     void (*insert_object)(VADriverContextP ctx,
 318                           struct intel_encoder_context *encoder_context,
 319                           unsigned int *insert_data,
 320                           int lenght_in_dws, int data_bits_in_last_dw,
 321                           int skip_emul_byte_count,
 322                           int is_last_header, int is_end_of_slice,
 323                           int emulation_flag,
 324                           struct intel_batchbuffer *batch);
 325     void (*buffer_suface_setup)(VADriverContextP ctx,
 326                                 struct i965_gpe_context *gpe_context,
 327                                 struct i965_buffer_surface *buffer_surface,
 328                                 unsigned long binding_table_offset,
 329                                 unsigned long surface_state_offset);
 330 };
 331
 332 VAStatus gen6_mfc_pipeline(VADriverContextP ctx,
 333                            VAProfile profile,
 334                            struct encode_state *encode_state,
 335                            struct intel_encoder_context *encoder_context);
 336 void gen6_mfc_context_destroy(void *context);
 337
 338 extern
 339 Bool gen6_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context);
 340
 341 extern
 342 Bool gen7_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context);
 343
 344 extern
 345 Bool gen75_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context);
 346
 347
 348 extern int intel_mfc_update_hrd(struct encode_state *encode_state,
 349                                 struct intel_encoder_context *encoder_context,
 350                                 int frame_bits);
 351
 352 extern int intel_mfc_brc_postpack(struct encode_state *encode_state,
 353                                   struct intel_encoder_context *encoder_context,
 354                                   int frame_bits);
 355
 356 extern void intel_mfc_hrd_context_update(struct encode_state *encode_state,
 357                                          struct gen6_mfc_context *mfc_context);
 358
 359 extern int intel_mfc_interlace_check(VADriverContextP ctx,
 360                                      struct encode_state *encode_state,
 361                                      struct intel_encoder_context *encoder_context);
 362
 363 extern void intel_mfc_brc_prepare(struct encode_state *encode_state,
 364                                   struct intel_encoder_context *encoder_context);
 365
 366 extern void intel_mfc_avc_pipeline_header_programing(VADriverContextP ctx,
 367                                                      struct encode_state *encode_state,
 368                                                      struct intel_encoder_context *encoder_context,
 369                                                      struct intel_batchbuffer *slice_batch);
 370
 371 extern VAStatus intel_mfc_avc_prepare(VADriverContextP ctx,
 372                                       struct encode_state *encode_state,
 373                                       struct intel_encoder_context *encoder_context);
 374
 375 extern int intel_avc_enc_slice_type_fixup(int type);
 376
 377 extern void
 378 intel_mfc_avc_ref_idx_state(VADriverContextP ctx,
 379                             struct encode_state *encode_state,
 380                             struct intel_encoder_context *encoder_context);
 381
 382 extern
 383 Bool gen8_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context);
 384
 385 extern void
 386 intel_avc_slice_insert_packed_data(VADriverContextP ctx,
 387                              struct encode_state *encode_state,
 388                              struct intel_encoder_context *encoder_context,
 389                              int slice_index,
 390                              struct intel_batchbuffer *slice_batch);
 391
 392 extern
 393 Bool gen9_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context);
 394
 395 #endif  /* _GEN6_MFC_BCS_H_ */