2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Xiang Haihao <haihao.xiang@intel.com>
30 #include "intel_batchbuffer.h"
31 #include "intel_driver.h"
32 #include "i965_defines.h"
33 #include "i965_drv_video.h"
34 #include "i965_decoder_utils.h"
37 #include "intel_media.h"
39 static const uint32_t zigzag_direct[64] = {
40 0, 1, 8, 16, 9, 2, 3, 10,
41 17, 24, 32, 25, 18, 11, 4, 5,
42 12, 19, 26, 33, 40, 48, 41, 34,
43 27, 20, 13, 6, 7, 14, 21, 28,
44 35, 42, 49, 56, 57, 50, 43, 36,
45 29, 22, 15, 23, 30, 37, 44, 51,
46 58, 59, 52, 45, 38, 31, 39, 46,
47 53, 60, 61, 54, 47, 55, 62, 63
51 gen6_mfd_init_avc_surface(VADriverContextP ctx,
52 VAPictureParameterBufferH264 *pic_param,
53 struct object_surface *obj_surface)
55 struct i965_driver_data *i965 = i965_driver_data(ctx);
56 GenAvcSurface *gen6_avc_surface = obj_surface->private_data;
59 obj_surface->free_private_data = gen_free_avc_surface;
60 height_in_mbs = ((pic_param->picture_height_in_mbs_minus1 + 1) & 0xff); /* frame height */
62 if (!gen6_avc_surface) {
63 gen6_avc_surface = calloc(sizeof(GenAvcSurface), 1);
64 assert(gen6_avc_surface);
65 gen6_avc_surface->base.frame_store_id = -1;
66 assert((obj_surface->size & 0x3f) == 0);
67 obj_surface->private_data = gen6_avc_surface;
70 gen6_avc_surface->dmv_bottom_flag = (pic_param->pic_fields.bits.field_pic_flag &&
71 !pic_param->seq_fields.bits.direct_8x8_inference_flag);
73 if (gen6_avc_surface->dmv_top == NULL) {
74 gen6_avc_surface->dmv_top = dri_bo_alloc(i965->intel.bufmgr,
75 "direct mv w/r buffer",
76 128 * height_in_mbs * 64, /* scalable with frame height */
80 if (gen6_avc_surface->dmv_bottom_flag &&
81 gen6_avc_surface->dmv_bottom == NULL) {
82 gen6_avc_surface->dmv_bottom = dri_bo_alloc(i965->intel.bufmgr,
83 "direct mv w/r buffer",
84 128 * height_in_mbs * 64, /* scalable with frame height */
90 gen6_mfd_pipe_mode_select(VADriverContextP ctx,
91 struct decode_state *decode_state,
93 struct gen6_mfd_context *gen6_mfd_context)
95 struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
97 assert(standard_select == MFX_FORMAT_MPEG2 ||
98 standard_select == MFX_FORMAT_AVC ||
99 standard_select == MFX_FORMAT_VC1);
101 BEGIN_BCS_BATCH(batch, 4);
102 OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (4 - 2));
104 (MFD_MODE_VLD << 16) | /* VLD mode */
105 (0 << 10) | /* disable Stream-Out */
106 (gen6_mfd_context->post_deblocking_output.valid << 9) | /* Post Deblocking Output */
107 (gen6_mfd_context->pre_deblocking_output.valid << 8) | /* Pre Deblocking Output */
108 (0 << 7) | /* disable TLB prefectch */
109 (0 << 5) | /* not in stitch mode */
110 (MFX_CODEC_DECODE << 4) | /* decoding mode */
111 (standard_select << 0));
113 (0 << 20) | /* round flag in PB slice */
114 (0 << 19) | /* round flag in Intra8x8 */
115 (0 << 7) | /* expand NOA bus flag */
116 (1 << 6) | /* must be 1 */
117 (0 << 5) | /* disable clock gating for NOA */
118 (0 << 4) | /* terminate if AVC motion and POC table error occurs */
119 (0 << 3) | /* terminate if AVC mbdata error occurs */
120 (0 << 2) | /* terminate if AVC CABAC/CAVLC decode error occurs */
121 (0 << 1) | /* AVC long field motion vector */
122 (1 << 0)); /* always calculate AVC ILDB boundary strength */
123 OUT_BCS_BATCH(batch, 0);
124 ADVANCE_BCS_BATCH(batch);
128 gen6_mfd_surface_state(VADriverContextP ctx,
129 struct decode_state *decode_state,
131 struct gen6_mfd_context *gen6_mfd_context)
133 struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
134 struct object_surface *obj_surface = decode_state->render_object;
135 unsigned int surface_format;
137 surface_format = obj_surface->fourcc == VA_FOURCC_Y800 ?
138 MFX_SURFACE_MONOCHROME : MFX_SURFACE_PLANAR_420_8;
140 BEGIN_BCS_BATCH(batch, 6);
141 OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
142 OUT_BCS_BATCH(batch, 0);
144 ((obj_surface->orig_height - 1) << 19) |
145 ((obj_surface->orig_width - 1) << 6));
147 (surface_format << 28) | /* 420 planar YUV surface */
148 (1 << 27) | /* must be 1 for interleave U/V, hardware requirement */
149 (0 << 22) | /* surface object control state, FIXME??? */
150 ((obj_surface->width - 1) << 3) | /* pitch */
151 (0 << 2) | /* must be 0 for interleave U/V */
152 (1 << 1) | /* must be y-tiled */
153 (I965_TILEWALK_YMAJOR << 0)); /* tile walk, FIXME: must be 1 ??? */
155 (0 << 16) | /* must be 0 for interleave U/V */
156 (obj_surface->height)); /* y offset for U(cb) */
157 OUT_BCS_BATCH(batch, 0);
158 ADVANCE_BCS_BATCH(batch);
162 gen6_mfd_pipe_buf_addr_state(VADriverContextP ctx,
163 struct decode_state *decode_state,
165 struct gen6_mfd_context *gen6_mfd_context)
167 struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
170 BEGIN_BCS_BATCH(batch, 24);
171 OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
172 if (gen6_mfd_context->pre_deblocking_output.valid)
173 OUT_BCS_RELOC(batch, gen6_mfd_context->pre_deblocking_output.bo,
174 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
177 OUT_BCS_BATCH(batch, 0);
179 if (gen6_mfd_context->post_deblocking_output.valid)
180 OUT_BCS_RELOC(batch, gen6_mfd_context->post_deblocking_output.bo,
181 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
184 OUT_BCS_BATCH(batch, 0);
186 OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
187 OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
189 if (gen6_mfd_context->intra_row_store_scratch_buffer.valid)
190 OUT_BCS_RELOC(batch, gen6_mfd_context->intra_row_store_scratch_buffer.bo,
191 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
194 OUT_BCS_BATCH(batch, 0);
196 if (gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.valid)
197 OUT_BCS_RELOC(batch, gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo,
198 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
201 OUT_BCS_BATCH(batch, 0);
204 for (i = 0; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface); i++) {
205 struct object_surface *obj_surface;
207 if (gen6_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID &&
208 gen6_mfd_context->reference_surface[i].obj_surface &&
209 gen6_mfd_context->reference_surface[i].obj_surface->bo) {
210 obj_surface = gen6_mfd_context->reference_surface[i].obj_surface;
212 OUT_BCS_RELOC(batch, obj_surface->bo,
213 I915_GEM_DOMAIN_INSTRUCTION, 0,
216 OUT_BCS_BATCH(batch, 0);
220 OUT_BCS_BATCH(batch, 0); /* ignore DW23 for decoding */
221 ADVANCE_BCS_BATCH(batch);
225 gen6_mfd_ind_obj_base_addr_state(VADriverContextP ctx,
226 dri_bo *slice_data_bo,
228 struct gen6_mfd_context *gen6_mfd_context)
230 struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
232 BEGIN_BCS_BATCH(batch, 11);
233 OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
234 OUT_BCS_RELOC(batch, slice_data_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); /* MFX Indirect Bitstream Object Base Address */
235 OUT_BCS_BATCH(batch, 0);
236 OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
237 OUT_BCS_BATCH(batch, 0);
238 OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
239 OUT_BCS_BATCH(batch, 0);
240 OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
241 OUT_BCS_BATCH(batch, 0);
242 OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
243 OUT_BCS_BATCH(batch, 0);
244 ADVANCE_BCS_BATCH(batch);
248 gen6_mfd_bsp_buf_base_addr_state(VADriverContextP ctx,
249 struct decode_state *decode_state,
251 struct gen6_mfd_context *gen6_mfd_context)
253 struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
255 BEGIN_BCS_BATCH(batch, 4);
256 OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
258 if (gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.valid)
259 OUT_BCS_RELOC(batch, gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo,
260 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
263 OUT_BCS_BATCH(batch, 0);
265 if (gen6_mfd_context->mpr_row_store_scratch_buffer.valid)
266 OUT_BCS_RELOC(batch, gen6_mfd_context->mpr_row_store_scratch_buffer.bo,
267 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
270 OUT_BCS_BATCH(batch, 0);
272 if (gen6_mfd_context->bitplane_read_buffer.valid)
273 OUT_BCS_RELOC(batch, gen6_mfd_context->bitplane_read_buffer.bo,
274 I915_GEM_DOMAIN_INSTRUCTION, 0,
277 OUT_BCS_BATCH(batch, 0);
279 ADVANCE_BCS_BATCH(batch);
283 gen6_mfd_avc_img_state(VADriverContextP ctx,
284 struct decode_state *decode_state,
285 struct gen6_mfd_context *gen6_mfd_context)
287 struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
290 int mbaff_frame_flag;
291 unsigned int width_in_mbs, height_in_mbs;
292 VAPictureParameterBufferH264 *pic_param;
294 assert(decode_state->pic_param && decode_state->pic_param->buffer);
295 pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
297 if (decode_state->iq_matrix && decode_state->iq_matrix->buffer)
300 qm_present_flag = 0; /* built-in QM matrices */
302 if (pic_param->CurrPic.flags & VA_PICTURE_H264_TOP_FIELD)
304 else if (pic_param->CurrPic.flags & VA_PICTURE_H264_BOTTOM_FIELD)
309 if ((img_struct & 0x1) == 0x1) {
310 assert(pic_param->pic_fields.bits.field_pic_flag == 0x1);
312 assert(pic_param->pic_fields.bits.field_pic_flag == 0x0);
315 if (pic_param->seq_fields.bits.frame_mbs_only_flag) { /* a frame containing only frame macroblocks */
316 assert(pic_param->seq_fields.bits.mb_adaptive_frame_field_flag == 0);
317 assert(pic_param->pic_fields.bits.field_pic_flag == 0);
319 assert(pic_param->seq_fields.bits.direct_8x8_inference_flag == 1); /* see H.264 spec */
322 mbaff_frame_flag = (pic_param->seq_fields.bits.mb_adaptive_frame_field_flag &&
323 !pic_param->pic_fields.bits.field_pic_flag);
325 width_in_mbs = ((pic_param->picture_width_in_mbs_minus1 + 1) & 0xff);
326 height_in_mbs = ((pic_param->picture_height_in_mbs_minus1 + 1) & 0xff); /* frame height */
327 assert(!((width_in_mbs * height_in_mbs) & 0x8000)); /* hardware requirement */
329 /* MFX unit doesn't support 4:2:2 and 4:4:4 picture */
330 assert(pic_param->seq_fields.bits.chroma_format_idc == 0 || /* monochrome picture */
331 pic_param->seq_fields.bits.chroma_format_idc == 1); /* 4:2:0 */
332 assert(pic_param->seq_fields.bits.residual_colour_transform_flag == 0); /* only available for 4:4:4 */
334 BEGIN_BCS_BATCH(batch, 13);
335 OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (13 - 2));
337 ((width_in_mbs * height_in_mbs) & 0x7fff));
339 (height_in_mbs << 16) |
340 (width_in_mbs << 0));
342 ((pic_param->second_chroma_qp_index_offset & 0x1f) << 24) |
343 ((pic_param->chroma_qp_index_offset & 0x1f) << 16) |
344 (0 << 14) | /* Max-bit conformance Intra flag ??? FIXME */
345 (0 << 13) | /* Max Macroblock size conformance Inter flag ??? FIXME */
346 (1 << 12) | /* always 1, hardware requirement */
347 (qm_present_flag << 10) |
351 (pic_param->seq_fields.bits.chroma_format_idc << 10) |
352 (pic_param->pic_fields.bits.entropy_coding_mode_flag << 7) |
353 ((!pic_param->pic_fields.bits.reference_pic_flag) << 6) |
354 (pic_param->pic_fields.bits.constrained_intra_pred_flag << 5) |
355 (pic_param->seq_fields.bits.direct_8x8_inference_flag << 4) |
356 (pic_param->pic_fields.bits.transform_8x8_mode_flag << 3) |
357 (pic_param->seq_fields.bits.frame_mbs_only_flag << 2) |
358 (mbaff_frame_flag << 1) |
359 (pic_param->pic_fields.bits.field_pic_flag << 0));
360 OUT_BCS_BATCH(batch, 0);
361 OUT_BCS_BATCH(batch, 0);
362 OUT_BCS_BATCH(batch, 0);
363 OUT_BCS_BATCH(batch, 0);
364 OUT_BCS_BATCH(batch, 0);
365 OUT_BCS_BATCH(batch, 0);
366 OUT_BCS_BATCH(batch, 0);
367 OUT_BCS_BATCH(batch, 0);
368 ADVANCE_BCS_BATCH(batch);
372 gen6_mfd_avc_qm_state(VADriverContextP ctx,
373 struct decode_state *decode_state,
374 struct gen6_mfd_context *gen6_mfd_context)
376 struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
378 VAIQMatrixBufferH264 *iq_matrix;
379 VAPictureParameterBufferH264 *pic_param;
381 if (!decode_state->iq_matrix || !decode_state->iq_matrix->buffer)
384 iq_matrix = (VAIQMatrixBufferH264 *)decode_state->iq_matrix->buffer;
386 assert(decode_state->pic_param && decode_state->pic_param->buffer);
387 pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
389 cmd_len = 2 + 6 * 4; /* always load six 4x4 scaling matrices */
391 if (pic_param->pic_fields.bits.transform_8x8_mode_flag)
392 cmd_len += 2 * 16; /* load two 8x8 scaling matrices */
394 BEGIN_BCS_BATCH(batch, cmd_len);
395 OUT_BCS_BATCH(batch, MFX_AVC_QM_STATE | (cmd_len - 2));
397 if (pic_param->pic_fields.bits.transform_8x8_mode_flag)
399 (0x0 << 8) | /* don't use default built-in matrices */
400 (0xff << 0)); /* six 4x4 and two 8x8 scaling matrices */
403 (0x0 << 8) | /* don't use default built-in matrices */
404 (0x3f << 0)); /* six 4x4 scaling matrices */
406 intel_batchbuffer_data(batch, &iq_matrix->ScalingList4x4[0][0], 6 * 4 * 4);
408 if (pic_param->pic_fields.bits.transform_8x8_mode_flag)
409 intel_batchbuffer_data(batch, &iq_matrix->ScalingList8x8[0][0], 2 * 16 * 4);
411 ADVANCE_BCS_BATCH(batch);
415 gen6_mfd_avc_directmode_state(VADriverContextP ctx,
416 struct decode_state *decode_state,
417 VAPictureParameterBufferH264 *pic_param,
418 VASliceParameterBufferH264 *slice_param,
419 struct gen6_mfd_context *gen6_mfd_context)
421 struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
422 struct object_surface *obj_surface;
423 GenAvcSurface *gen6_avc_surface;
424 VAPictureH264 *va_pic;
427 BEGIN_BCS_BATCH(batch, 69);
428 OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
430 /* reference surfaces 0..15 */
431 for (i = 0; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface); i++) {
432 if (gen6_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID &&
433 gen6_mfd_context->reference_surface[i].obj_surface &&
434 gen6_mfd_context->reference_surface[i].obj_surface->private_data) {
436 obj_surface = gen6_mfd_context->reference_surface[i].obj_surface;
437 gen6_avc_surface = obj_surface->private_data;
438 OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_top,
439 I915_GEM_DOMAIN_INSTRUCTION, 0,
442 if (gen6_avc_surface->dmv_bottom_flag == 1)
443 OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_bottom,
444 I915_GEM_DOMAIN_INSTRUCTION, 0,
447 OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_top,
448 I915_GEM_DOMAIN_INSTRUCTION, 0,
451 OUT_BCS_BATCH(batch, 0);
452 OUT_BCS_BATCH(batch, 0);
456 /* the current decoding frame/field */
457 va_pic = &pic_param->CurrPic;
458 obj_surface = decode_state->render_object;
459 assert(obj_surface->bo && obj_surface->private_data);
460 gen6_avc_surface = obj_surface->private_data;
462 OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_top,
463 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
466 if (gen6_avc_surface->dmv_bottom_flag == 1)
467 OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_bottom,
468 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
471 OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_top,
472 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
476 for (i = 0; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface); i++) {
477 obj_surface = gen6_mfd_context->reference_surface[i].obj_surface;
480 const VAPictureH264 * const va_pic = avc_find_picture(
481 obj_surface->base.id, pic_param->ReferenceFrames,
482 ARRAY_ELEMS(pic_param->ReferenceFrames));
484 assert(va_pic != NULL);
485 OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
486 OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
488 OUT_BCS_BATCH(batch, 0);
489 OUT_BCS_BATCH(batch, 0);
493 va_pic = &pic_param->CurrPic;
494 OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
495 OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
497 ADVANCE_BCS_BATCH(batch);
501 gen6_mfd_avc_slice_state(VADriverContextP ctx,
502 VAPictureParameterBufferH264 *pic_param,
503 VASliceParameterBufferH264 *slice_param,
504 VASliceParameterBufferH264 *next_slice_param,
505 struct gen6_mfd_context *gen6_mfd_context)
507 struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
508 int width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
509 int height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1;
510 int slice_hor_pos, slice_ver_pos, next_slice_hor_pos, next_slice_ver_pos;
511 int num_ref_idx_l0, num_ref_idx_l1;
512 int mbaff_picture = (!pic_param->pic_fields.bits.field_pic_flag &&
513 pic_param->seq_fields.bits.mb_adaptive_frame_field_flag);
514 int weighted_pred_idc = 0;
515 int first_mb_in_slice = 0, first_mb_in_next_slice = 0;
516 unsigned int chroma_log2_weight_denom, luma_log2_weight_denom;
519 if (slice_param->slice_type == SLICE_TYPE_I ||
520 slice_param->slice_type == SLICE_TYPE_SI) {
521 slice_type = SLICE_TYPE_I;
522 } else if (slice_param->slice_type == SLICE_TYPE_P ||
523 slice_param->slice_type == SLICE_TYPE_SP) {
524 slice_type = SLICE_TYPE_P;
526 assert(slice_param->slice_type == SLICE_TYPE_B);
527 slice_type = SLICE_TYPE_B;
530 luma_log2_weight_denom = slice_param->luma_log2_weight_denom;
531 chroma_log2_weight_denom = slice_param->chroma_log2_weight_denom;
533 if (slice_type == SLICE_TYPE_I) {
534 assert(slice_param->num_ref_idx_l0_active_minus1 == 0);
535 assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
538 } else if (slice_type == SLICE_TYPE_P) {
539 assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
540 num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
542 weighted_pred_idc = (pic_param->pic_fields.bits.weighted_pred_flag == 1);
544 num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
545 num_ref_idx_l1 = slice_param->num_ref_idx_l1_active_minus1 + 1;
546 weighted_pred_idc = pic_param->pic_fields.bits.weighted_bipred_idc;
548 if (weighted_pred_idc == 2) {
549 /* 8.4.3 - Derivation process for prediction weights (8-279) */
550 luma_log2_weight_denom = 5;
551 chroma_log2_weight_denom = 5;
555 first_mb_in_slice = slice_param->first_mb_in_slice;
556 slice_hor_pos = first_mb_in_slice % width_in_mbs;
557 slice_ver_pos = first_mb_in_slice / width_in_mbs;
560 slice_ver_pos = slice_ver_pos << 1;
562 if (next_slice_param) {
563 first_mb_in_next_slice = next_slice_param->first_mb_in_slice;
564 next_slice_hor_pos = first_mb_in_next_slice % width_in_mbs;
565 next_slice_ver_pos = first_mb_in_next_slice / width_in_mbs;
568 next_slice_ver_pos = next_slice_ver_pos << 1;
570 next_slice_hor_pos = 0;
571 next_slice_ver_pos = height_in_mbs;
574 BEGIN_BCS_BATCH(batch, 11); /* FIXME: is it 10??? */
575 OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2));
576 OUT_BCS_BATCH(batch, slice_type);
578 (num_ref_idx_l1 << 24) |
579 (num_ref_idx_l0 << 16) |
580 (chroma_log2_weight_denom << 8) |
581 (luma_log2_weight_denom << 0));
583 (weighted_pred_idc << 30) |
584 (slice_param->direct_spatial_mv_pred_flag << 29) |
585 (slice_param->disable_deblocking_filter_idc << 27) |
586 (slice_param->cabac_init_idc << 24) |
587 ((pic_param->pic_init_qp_minus26 + 26 + slice_param->slice_qp_delta) << 16) |
588 ((slice_param->slice_beta_offset_div2 & 0xf) << 8) |
589 ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0));
591 (slice_ver_pos << 24) |
592 (slice_hor_pos << 16) |
593 (first_mb_in_slice << 0));
595 (next_slice_ver_pos << 16) |
596 (next_slice_hor_pos << 0));
598 (next_slice_param == NULL) << 19); /* last slice flag */
599 OUT_BCS_BATCH(batch, 0);
600 OUT_BCS_BATCH(batch, 0);
601 OUT_BCS_BATCH(batch, 0);
602 OUT_BCS_BATCH(batch, 0);
603 ADVANCE_BCS_BATCH(batch);
607 gen6_mfd_avc_ref_idx_state(VADriverContextP ctx,
608 VAPictureParameterBufferH264 *pic_param,
609 VASliceParameterBufferH264 *slice_param,
610 struct gen6_mfd_context *gen6_mfd_context)
612 gen6_send_avc_ref_idx_state(
613 gen6_mfd_context->base.batch,
615 gen6_mfd_context->reference_surface
620 gen6_mfd_avc_weightoffset_state(VADriverContextP ctx,
621 VAPictureParameterBufferH264 *pic_param,
622 VASliceParameterBufferH264 *slice_param,
623 struct gen6_mfd_context *gen6_mfd_context)
625 struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
626 int i, j, num_weight_offset_table = 0;
627 short weightoffsets[32 * 6];
629 if ((slice_param->slice_type == SLICE_TYPE_P ||
630 slice_param->slice_type == SLICE_TYPE_SP) &&
631 (pic_param->pic_fields.bits.weighted_pred_flag == 1)) {
632 num_weight_offset_table = 1;
635 if ((slice_param->slice_type == SLICE_TYPE_B) &&
636 (pic_param->pic_fields.bits.weighted_bipred_idc == 1)) {
637 num_weight_offset_table = 2;
640 for (i = 0; i < num_weight_offset_table; i++) {
641 BEGIN_BCS_BATCH(batch, 98);
642 OUT_BCS_BATCH(batch, MFX_AVC_WEIGHTOFFSET_STATE | (98 - 2));
643 OUT_BCS_BATCH(batch, i);
646 for (j = 0; j < 32; j++) {
647 weightoffsets[j * 6 + 0] = slice_param->luma_weight_l0[j];
648 weightoffsets[j * 6 + 1] = slice_param->luma_offset_l0[j];
649 weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l0[j][0];
650 weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l0[j][0];
651 weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l0[j][1];
652 weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l0[j][1];
655 for (j = 0; j < 32; j++) {
656 weightoffsets[j * 6 + 0] = slice_param->luma_weight_l1[j];
657 weightoffsets[j * 6 + 1] = slice_param->luma_offset_l1[j];
658 weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l1[j][0];
659 weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l1[j][0];
660 weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l1[j][1];
661 weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l1[j][1];
665 intel_batchbuffer_data(batch, weightoffsets, sizeof(weightoffsets));
666 ADVANCE_BCS_BATCH(batch);
671 gen6_mfd_avc_bsd_object(VADriverContextP ctx,
672 VAPictureParameterBufferH264 *pic_param,
673 VASliceParameterBufferH264 *slice_param,
674 dri_bo *slice_data_bo,
675 struct gen6_mfd_context *gen6_mfd_context)
677 struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
678 unsigned int slice_data_bit_offset;
680 slice_data_bit_offset = avc_get_first_mb_bit_offset(
683 pic_param->pic_fields.bits.entropy_coding_mode_flag
686 BEGIN_BCS_BATCH(batch, 6);
687 OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2));
689 (slice_param->slice_data_size - slice_param->slice_data_offset));
690 OUT_BCS_BATCH(batch, slice_param->slice_data_offset);
698 ((slice_data_bit_offset >> 3) << 16) |
701 ((0x7 - (slice_data_bit_offset & 0x7)) << 0));
702 OUT_BCS_BATCH(batch, 0);
703 ADVANCE_BCS_BATCH(batch);
707 gen6_mfd_avc_phantom_slice_first(VADriverContextP ctx,
708 VAPictureParameterBufferH264 *pic_param,
709 VASliceParameterBufferH264 *next_slice_param,
710 struct gen6_mfd_context *gen6_mfd_context)
712 gen6_mfd_avc_phantom_slice(ctx, pic_param, next_slice_param, gen6_mfd_context->base.batch);
716 gen6_mfd_avc_phantom_slice_last(VADriverContextP ctx,
717 VAPictureParameterBufferH264 *pic_param,
718 struct gen6_mfd_context *gen6_mfd_context)
720 gen6_mfd_avc_phantom_slice(ctx, pic_param, NULL, gen6_mfd_context->base.batch);
724 gen6_mfd_avc_decode_init(VADriverContextP ctx,
725 struct decode_state *decode_state,
726 struct gen6_mfd_context *gen6_mfd_context)
728 VAPictureParameterBufferH264 *pic_param;
729 VASliceParameterBufferH264 *slice_param;
730 struct i965_driver_data *i965 = i965_driver_data(ctx);
731 struct object_surface *obj_surface;
733 int i, j, enable_avc_ildb = 0;
736 for (j = 0; j < decode_state->num_slice_params && enable_avc_ildb == 0; j++) {
737 assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
738 slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
740 for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
741 assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
742 assert((slice_param->slice_type == SLICE_TYPE_I) ||
743 (slice_param->slice_type == SLICE_TYPE_SI) ||
744 (slice_param->slice_type == SLICE_TYPE_P) ||
745 (slice_param->slice_type == SLICE_TYPE_SP) ||
746 (slice_param->slice_type == SLICE_TYPE_B));
748 if (slice_param->disable_deblocking_filter_idc != 1) {
757 assert(decode_state->pic_param && decode_state->pic_param->buffer);
758 pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
759 intel_update_avc_frame_store_index(ctx, decode_state, pic_param,
760 gen6_mfd_context->reference_surface, &gen6_mfd_context->fs_ctx);
761 width_in_mbs = ((pic_param->picture_width_in_mbs_minus1 + 1) & 0xff);
763 /* Current decoded picture */
764 obj_surface = decode_state->render_object;
765 if (pic_param->pic_fields.bits.reference_pic_flag)
766 obj_surface->flags |= SURFACE_REFERENCED;
768 obj_surface->flags &= ~SURFACE_REFERENCED;
770 avc_ensure_surface_bo(ctx, decode_state, obj_surface, pic_param);
771 gen6_mfd_init_avc_surface(ctx, pic_param, obj_surface);
773 dri_bo_unreference(gen6_mfd_context->post_deblocking_output.bo);
774 gen6_mfd_context->post_deblocking_output.bo = obj_surface->bo;
775 dri_bo_reference(gen6_mfd_context->post_deblocking_output.bo);
776 gen6_mfd_context->post_deblocking_output.valid = enable_avc_ildb;
778 dri_bo_unreference(gen6_mfd_context->pre_deblocking_output.bo);
779 gen6_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
780 dri_bo_reference(gen6_mfd_context->pre_deblocking_output.bo);
781 gen6_mfd_context->pre_deblocking_output.valid = !enable_avc_ildb;
783 dri_bo_unreference(gen6_mfd_context->intra_row_store_scratch_buffer.bo);
784 bo = dri_bo_alloc(i965->intel.bufmgr,
789 gen6_mfd_context->intra_row_store_scratch_buffer.bo = bo;
790 gen6_mfd_context->intra_row_store_scratch_buffer.valid = 1;
792 dri_bo_unreference(gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
793 bo = dri_bo_alloc(i965->intel.bufmgr,
794 "deblocking filter row store",
795 width_in_mbs * 64 * 4,
798 gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
799 gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1;
801 dri_bo_unreference(gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
802 bo = dri_bo_alloc(i965->intel.bufmgr,
807 gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
808 gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
810 dri_bo_unreference(gen6_mfd_context->mpr_row_store_scratch_buffer.bo);
811 bo = dri_bo_alloc(i965->intel.bufmgr,
816 gen6_mfd_context->mpr_row_store_scratch_buffer.bo = bo;
817 gen6_mfd_context->mpr_row_store_scratch_buffer.valid = 1;
819 gen6_mfd_context->bitplane_read_buffer.valid = 0;
823 gen6_mfd_avc_decode_picture(VADriverContextP ctx,
824 struct decode_state *decode_state,
825 struct gen6_mfd_context *gen6_mfd_context)
827 struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
828 VAPictureParameterBufferH264 *pic_param;
829 VASliceParameterBufferH264 *slice_param, *next_slice_param, *next_slice_group_param;
830 dri_bo *slice_data_bo;
833 assert(decode_state->pic_param && decode_state->pic_param->buffer);
834 pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
835 gen6_mfd_avc_decode_init(ctx, decode_state, gen6_mfd_context);
837 intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
838 intel_batchbuffer_emit_mi_flush(batch);
839 gen6_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_AVC, gen6_mfd_context);
840 gen6_mfd_surface_state(ctx, decode_state, MFX_FORMAT_AVC, gen6_mfd_context);
841 gen6_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen6_mfd_context);
842 gen6_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen6_mfd_context);
843 gen6_mfd_avc_img_state(ctx, decode_state, gen6_mfd_context);
844 gen6_mfd_avc_qm_state(ctx, decode_state, gen6_mfd_context);
846 for (j = 0; j < decode_state->num_slice_params; j++) {
847 assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
848 slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
849 slice_data_bo = decode_state->slice_datas[j]->bo;
850 gen6_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_AVC, gen6_mfd_context);
852 if (j == decode_state->num_slice_params - 1)
853 next_slice_group_param = NULL;
855 next_slice_group_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j + 1]->buffer;
858 slice_param->first_mb_in_slice)
859 gen6_mfd_avc_phantom_slice_first(ctx, pic_param, slice_param, gen6_mfd_context);
861 for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
862 assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
863 assert((slice_param->slice_type == SLICE_TYPE_I) ||
864 (slice_param->slice_type == SLICE_TYPE_SI) ||
865 (slice_param->slice_type == SLICE_TYPE_P) ||
866 (slice_param->slice_type == SLICE_TYPE_SP) ||
867 (slice_param->slice_type == SLICE_TYPE_B));
869 if (i < decode_state->slice_params[j]->num_elements - 1)
870 next_slice_param = slice_param + 1;
872 next_slice_param = next_slice_group_param;
874 gen6_mfd_avc_directmode_state(ctx, decode_state, pic_param, slice_param, gen6_mfd_context);
875 gen6_mfd_avc_slice_state(ctx, pic_param, slice_param, next_slice_param, gen6_mfd_context);
876 gen6_mfd_avc_ref_idx_state(ctx, pic_param, slice_param, gen6_mfd_context);
877 gen6_mfd_avc_weightoffset_state(ctx, pic_param, slice_param, gen6_mfd_context);
878 gen6_mfd_avc_bsd_object(ctx, pic_param, slice_param, slice_data_bo, gen6_mfd_context);
883 gen6_mfd_avc_phantom_slice_last(ctx, pic_param, gen6_mfd_context);
884 intel_batchbuffer_end_atomic(batch);
885 intel_batchbuffer_flush(batch);
889 gen6_mfd_mpeg2_decode_init(VADriverContextP ctx,
890 struct decode_state *decode_state,
891 struct gen6_mfd_context *gen6_mfd_context)
893 VAPictureParameterBufferMPEG2 *pic_param;
894 struct i965_driver_data *i965 = i965_driver_data(ctx);
895 struct object_surface *obj_surface;
897 unsigned int width_in_mbs;
899 assert(decode_state->pic_param && decode_state->pic_param->buffer);
900 pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
901 width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16;
903 mpeg2_set_reference_surfaces(
905 gen6_mfd_context->reference_surface,
910 /* Current decoded picture */
911 obj_surface = decode_state->render_object;
912 i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
914 dri_bo_unreference(gen6_mfd_context->pre_deblocking_output.bo);
915 gen6_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
916 dri_bo_reference(gen6_mfd_context->pre_deblocking_output.bo);
917 gen6_mfd_context->pre_deblocking_output.valid = 1;
919 dri_bo_unreference(gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
920 bo = dri_bo_alloc(i965->intel.bufmgr,
925 gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
926 gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
928 gen6_mfd_context->post_deblocking_output.valid = 0;
929 gen6_mfd_context->intra_row_store_scratch_buffer.valid = 0;
930 gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 0;
931 gen6_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
932 gen6_mfd_context->bitplane_read_buffer.valid = 0;
936 gen6_mfd_mpeg2_pic_state(VADriverContextP ctx,
937 struct decode_state *decode_state,
938 struct gen6_mfd_context *gen6_mfd_context)
940 struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
941 VAPictureParameterBufferMPEG2 *pic_param;
942 unsigned int tff, pic_structure;
944 assert(decode_state->pic_param && decode_state->pic_param->buffer);
945 pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
947 pic_structure = pic_param->picture_coding_extension.bits.picture_structure;
948 if (pic_structure == MPEG_FRAME)
949 tff = pic_param->picture_coding_extension.bits.top_field_first;
951 tff = !(pic_param->picture_coding_extension.bits.is_first_field ^
952 (pic_structure & MPEG_TOP_FIELD));
954 BEGIN_BCS_BATCH(batch, 4);
955 OUT_BCS_BATCH(batch, MFX_MPEG2_PIC_STATE | (4 - 2));
957 (pic_param->f_code & 0xf) << 28 | /* f_code[1][1] */
958 ((pic_param->f_code >> 4) & 0xf) << 24 | /* f_code[1][0] */
959 ((pic_param->f_code >> 8) & 0xf) << 20 | /* f_code[0][1] */
960 ((pic_param->f_code >> 12) & 0xf) << 16 | /* f_code[0][0] */
961 pic_param->picture_coding_extension.bits.intra_dc_precision << 14 |
962 pic_param->picture_coding_extension.bits.picture_structure << 12 |
964 pic_param->picture_coding_extension.bits.frame_pred_frame_dct << 10 |
965 pic_param->picture_coding_extension.bits.concealment_motion_vectors << 9 |
966 pic_param->picture_coding_extension.bits.q_scale_type << 8 |
967 pic_param->picture_coding_extension.bits.intra_vlc_format << 7 |
968 pic_param->picture_coding_extension.bits.alternate_scan << 6);
970 pic_param->picture_coding_type << 9);
972 (ALIGN(pic_param->vertical_size, 16) / 16) << 16 |
973 (ALIGN(pic_param->horizontal_size, 16) / 16));
974 ADVANCE_BCS_BATCH(batch);
978 gen6_mfd_mpeg2_qm_state(VADriverContextP ctx,
979 struct decode_state *decode_state,
980 struct gen6_mfd_context *gen6_mfd_context)
982 struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
983 VAIQMatrixBufferMPEG2 * const gen_iq_matrix = &gen6_mfd_context->iq_matrix.mpeg2;
986 /* Update internal QM state */
987 if (decode_state->iq_matrix && decode_state->iq_matrix->buffer) {
988 VAIQMatrixBufferMPEG2 * const iq_matrix =
989 (VAIQMatrixBufferMPEG2 *)decode_state->iq_matrix->buffer;
991 gen_iq_matrix->load_intra_quantiser_matrix =
992 iq_matrix->load_intra_quantiser_matrix;
993 if (iq_matrix->load_intra_quantiser_matrix) {
994 for (j = 0; j < 64; j++)
995 gen_iq_matrix->intra_quantiser_matrix[zigzag_direct[j]] =
996 iq_matrix->intra_quantiser_matrix[j];
999 gen_iq_matrix->load_non_intra_quantiser_matrix =
1000 iq_matrix->load_non_intra_quantiser_matrix;
1001 if (iq_matrix->load_non_intra_quantiser_matrix) {
1002 for (j = 0; j < 64; j++)
1003 gen_iq_matrix->non_intra_quantiser_matrix[zigzag_direct[j]] =
1004 iq_matrix->non_intra_quantiser_matrix[j];
1008 /* Commit QM state to HW */
1009 for (i = 0; i < 2; i++) {
1010 unsigned char *qm = NULL;
1013 if (gen_iq_matrix->load_intra_quantiser_matrix)
1014 qm = gen_iq_matrix->intra_quantiser_matrix;
1016 if (gen_iq_matrix->load_non_intra_quantiser_matrix)
1017 qm = gen_iq_matrix->non_intra_quantiser_matrix;
1023 BEGIN_BCS_BATCH(batch, 18);
1024 OUT_BCS_BATCH(batch, MFX_MPEG2_QM_STATE | (18 - 2));
1025 OUT_BCS_BATCH(batch, i);
1026 intel_batchbuffer_data(batch, qm, 64);
1027 ADVANCE_BCS_BATCH(batch);
1032 gen6_mfd_mpeg2_bsd_object(VADriverContextP ctx,
1033 VAPictureParameterBufferMPEG2 *pic_param,
1034 VASliceParameterBufferMPEG2 *slice_param,
1035 VASliceParameterBufferMPEG2 *next_slice_param,
1036 struct gen6_mfd_context *gen6_mfd_context)
1038 struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1039 unsigned int width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16;
1040 int mb_count, vpos0, hpos0, vpos1, hpos1, is_field_pic_wa, is_field_pic = 0;
1042 if (pic_param->picture_coding_extension.bits.picture_structure == MPEG_TOP_FIELD ||
1043 pic_param->picture_coding_extension.bits.picture_structure == MPEG_BOTTOM_FIELD)
1045 is_field_pic_wa = is_field_pic &&
1046 gen6_mfd_context->wa_mpeg2_slice_vertical_position > 0;
1048 vpos0 = slice_param->slice_vertical_position / (1 + is_field_pic_wa);
1049 hpos0 = slice_param->slice_horizontal_position;
1051 if (next_slice_param == NULL) {
1052 vpos1 = ALIGN(pic_param->vertical_size, 16) / 16 / (1 + is_field_pic);
1055 vpos1 = next_slice_param->slice_vertical_position / (1 + is_field_pic_wa);
1056 hpos1 = next_slice_param->slice_horizontal_position;
1059 mb_count = (vpos1 * width_in_mbs + hpos1) - (vpos0 * width_in_mbs + hpos0);
1061 BEGIN_BCS_BATCH(batch, 5);
1062 OUT_BCS_BATCH(batch, MFD_MPEG2_BSD_OBJECT | (5 - 2));
1063 OUT_BCS_BATCH(batch,
1064 slice_param->slice_data_size - (slice_param->macroblock_offset >> 3));
1065 OUT_BCS_BATCH(batch,
1066 slice_param->slice_data_offset + (slice_param->macroblock_offset >> 3));
1067 OUT_BCS_BATCH(batch,
1071 (next_slice_param == NULL) << 5 |
1072 (next_slice_param == NULL) << 3 |
1073 (slice_param->macroblock_offset & 0x7));
1074 OUT_BCS_BATCH(batch,
1075 slice_param->quantiser_scale_code << 24);
1076 ADVANCE_BCS_BATCH(batch);
1080 gen6_mfd_mpeg2_decode_picture(VADriverContextP ctx,
1081 struct decode_state *decode_state,
1082 struct gen6_mfd_context *gen6_mfd_context)
1084 struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1085 VAPictureParameterBufferMPEG2 *pic_param;
1086 VASliceParameterBufferMPEG2 *slice_param, *next_slice_param;
1087 dri_bo *slice_data_bo;
1088 int group_idx = 0, pre_group_idx = -1, element_idx = 0;
1090 assert(decode_state->pic_param && decode_state->pic_param->buffer);
1091 pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
1093 gen6_mfd_mpeg2_decode_init(ctx, decode_state, gen6_mfd_context);
1094 intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
1095 intel_batchbuffer_emit_mi_flush(batch);
1096 gen6_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_MPEG2, gen6_mfd_context);
1097 gen6_mfd_surface_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen6_mfd_context);
1098 gen6_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen6_mfd_context);
1099 gen6_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen6_mfd_context);
1100 gen6_mfd_mpeg2_pic_state(ctx, decode_state, gen6_mfd_context);
1101 gen6_mfd_mpeg2_qm_state(ctx, decode_state, gen6_mfd_context);
1103 if (gen6_mfd_context->wa_mpeg2_slice_vertical_position < 0)
1104 gen6_mfd_context->wa_mpeg2_slice_vertical_position =
1105 mpeg2_wa_slice_vertical_position(decode_state, pic_param);
1107 slice_param = (VASliceParameterBufferMPEG2 *)decode_state->slice_params[group_idx]->buffer;
1109 for (; slice_param;) {
1110 if (pre_group_idx != group_idx) {
1111 slice_data_bo = decode_state->slice_datas[group_idx]->bo;
1112 gen6_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_MPEG2, gen6_mfd_context);
1113 pre_group_idx = group_idx;
1116 next_slice_param = intel_mpeg2_find_next_slice(decode_state, pic_param, slice_param, &group_idx, &element_idx);
1117 gen6_mfd_mpeg2_bsd_object(ctx, pic_param, slice_param, next_slice_param, gen6_mfd_context);
1118 slice_param = next_slice_param;
1121 intel_batchbuffer_end_atomic(batch);
1122 intel_batchbuffer_flush(batch);
1125 static const int va_to_gen6_vc1_pic_type[5] = {
1129 GEN6_VC1_BI_PICTURE,
1133 static const int va_to_gen6_vc1_mv[4] = {
1135 2, /* 1-MV half-pel */
1136 3, /* 1-MV half-pef bilinear */
1140 static const int b_picture_scale_factor[21] = {
1141 128, 85, 170, 64, 192,
1142 51, 102, 153, 204, 43,
1143 215, 37, 74, 111, 148,
1144 185, 222, 32, 96, 160,
1148 static const int va_to_gen6_vc1_condover[3] = {
1154 static const int va_to_gen6_vc1_profile[4] = {
1155 GEN6_VC1_SIMPLE_PROFILE,
1156 GEN6_VC1_MAIN_PROFILE,
1157 GEN6_VC1_RESERVED_PROFILE,
1158 GEN6_VC1_ADVANCED_PROFILE
1162 gen6_mfd_free_vc1_surface(void **data)
1164 struct gen6_vc1_surface *gen6_vc1_surface = *data;
1166 if (!gen6_vc1_surface)
1169 dri_bo_unreference(gen6_vc1_surface->dmv);
1170 free(gen6_vc1_surface);
1175 gen6_mfd_init_vc1_surface(VADriverContextP ctx,
1176 VAPictureParameterBufferVC1 *pic_param,
1177 struct object_surface *obj_surface)
1179 struct i965_driver_data *i965 = i965_driver_data(ctx);
1180 struct gen6_vc1_surface *gen6_vc1_surface = obj_surface->private_data;
1181 int height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16;
1183 obj_surface->free_private_data = gen6_mfd_free_vc1_surface;
1185 if (!gen6_vc1_surface) {
1186 gen6_vc1_surface = calloc(sizeof(struct gen6_vc1_surface), 1);
1188 if (!gen6_vc1_surface)
1191 assert((obj_surface->size & 0x3f) == 0);
1192 obj_surface->private_data = gen6_vc1_surface;
1195 gen6_vc1_surface->picture_type = pic_param->picture_fields.bits.picture_type;
1196 gen6_vc1_surface->intensity_compensation = 0;
1197 gen6_vc1_surface->luma_scale = 0;
1198 gen6_vc1_surface->luma_shift = 0;
1200 if (gen6_vc1_surface->dmv == NULL) {
1201 gen6_vc1_surface->dmv = dri_bo_alloc(i965->intel.bufmgr,
1202 "direct mv w/r buffer",
1203 128 * height_in_mbs * 64, /* scalable with frame height */
1209 gen6_mfd_vc1_decode_init(VADriverContextP ctx,
1210 struct decode_state *decode_state,
1211 struct gen6_mfd_context *gen6_mfd_context)
1213 VAPictureParameterBufferVC1 *pic_param;
1214 struct i965_driver_data *i965 = i965_driver_data(ctx);
1215 struct object_surface *obj_surface;
1219 int intensity_compensation;
1221 assert(decode_state->pic_param && decode_state->pic_param->buffer);
1222 pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1223 width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1224 picture_type = pic_param->picture_fields.bits.picture_type;
1225 intensity_compensation = (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation);
1227 intel_update_vc1_frame_store_index(ctx,
1230 gen6_mfd_context->reference_surface);
1232 /* Forward reference picture */
1233 obj_surface = decode_state->reference_objects[0];
1234 if (pic_param->forward_reference_picture != VA_INVALID_ID &&
1236 obj_surface->private_data) {
1237 if (picture_type == 1 && intensity_compensation) { /* P picture */
1238 struct gen6_vc1_surface *gen6_vc1_surface = obj_surface->private_data;
1240 gen6_vc1_surface->intensity_compensation = intensity_compensation;
1241 gen6_vc1_surface->luma_scale = pic_param->luma_scale;
1242 gen6_vc1_surface->luma_shift = pic_param->luma_shift;
1246 /* Current decoded picture */
1247 obj_surface = decode_state->render_object;
1248 i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
1249 gen6_mfd_init_vc1_surface(ctx, pic_param, obj_surface);
1251 dri_bo_unreference(gen6_mfd_context->post_deblocking_output.bo);
1252 gen6_mfd_context->post_deblocking_output.bo = obj_surface->bo;
1253 dri_bo_reference(gen6_mfd_context->post_deblocking_output.bo);
1254 gen6_mfd_context->post_deblocking_output.valid = pic_param->entrypoint_fields.bits.loopfilter;
1256 dri_bo_unreference(gen6_mfd_context->pre_deblocking_output.bo);
1257 gen6_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
1258 dri_bo_reference(gen6_mfd_context->pre_deblocking_output.bo);
1259 gen6_mfd_context->pre_deblocking_output.valid = !pic_param->entrypoint_fields.bits.loopfilter;
1261 dri_bo_unreference(gen6_mfd_context->intra_row_store_scratch_buffer.bo);
1262 bo = dri_bo_alloc(i965->intel.bufmgr,
1267 gen6_mfd_context->intra_row_store_scratch_buffer.bo = bo;
1268 gen6_mfd_context->intra_row_store_scratch_buffer.valid = 1;
1270 dri_bo_unreference(gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
1271 bo = dri_bo_alloc(i965->intel.bufmgr,
1272 "deblocking filter row store",
1273 width_in_mbs * 7 * 64,
1276 gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
1277 gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1;
1279 dri_bo_unreference(gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
1280 bo = dri_bo_alloc(i965->intel.bufmgr,
1281 "bsd mpc row store",
1285 gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
1286 gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
1288 gen6_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
1290 gen6_mfd_context->bitplane_read_buffer.valid = !!pic_param->bitplane_present.value;
1291 dri_bo_unreference(gen6_mfd_context->bitplane_read_buffer.bo);
1293 if (gen6_mfd_context->bitplane_read_buffer.valid) {
1294 int width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1295 int height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16;
1296 int bitplane_width = ALIGN(width_in_mbs, 2) / 2;
1298 uint8_t *src = NULL, *dst = NULL;
1300 assert(decode_state->bit_plane->buffer);
1301 src = decode_state->bit_plane->buffer;
1303 bo = dri_bo_alloc(i965->intel.bufmgr,
1305 bitplane_width * height_in_mbs,
1308 gen6_mfd_context->bitplane_read_buffer.bo = bo;
1310 dri_bo_map(bo, True);
1311 assert(bo->virtual);
1314 for (src_h = 0; src_h < height_in_mbs; src_h++) {
1315 for (src_w = 0; src_w < width_in_mbs; src_w++) {
1316 int src_index, dst_index;
1320 src_index = (src_h * width_in_mbs + src_w) / 2;
1321 src_shift = !((src_h * width_in_mbs + src_w) & 1) * 4;
1322 src_value = ((src[src_index] >> src_shift) & 0xf);
1324 if (picture_type == GEN6_VC1_SKIPPED_PICTURE) {
1328 dst_index = src_w / 2;
1329 dst[dst_index] = ((dst[dst_index] >> 4) | (src_value << 4));
1333 dst[src_w / 2] >>= 4;
1335 dst += bitplane_width;
1340 gen6_mfd_context->bitplane_read_buffer.bo = NULL;
1344 gen6_mfd_vc1_pic_state(VADriverContextP ctx,
1345 struct decode_state *decode_state,
1346 struct gen6_mfd_context *gen6_mfd_context)
1348 struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1349 VAPictureParameterBufferVC1 *pic_param;
1350 struct object_surface *obj_surface;
1351 int alt_pquant_config = 0, alt_pquant_edge_mask = 0, alt_pq;
1352 int dquant, dquantfrm, dqprofile, dqdbedge, dqsbedge, dqbilevel;
1353 int unified_mv_mode;
1354 int ref_field_pic_polarity = 0;
1355 int scale_factor = 0;
1357 int dmv_surface_valid = 0;
1364 assert(decode_state->pic_param && decode_state->pic_param->buffer);
1365 pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1367 profile = va_to_gen6_vc1_profile[pic_param->sequence_fields.bits.profile];
1368 dquant = pic_param->pic_quantizer_fields.bits.dquant;
1369 dquantfrm = pic_param->pic_quantizer_fields.bits.dq_frame;
1370 dqprofile = pic_param->pic_quantizer_fields.bits.dq_profile;
1371 dqdbedge = pic_param->pic_quantizer_fields.bits.dq_db_edge;
1372 dqsbedge = pic_param->pic_quantizer_fields.bits.dq_sb_edge;
1373 dqbilevel = pic_param->pic_quantizer_fields.bits.dq_binary_level;
1374 alt_pq = pic_param->pic_quantizer_fields.bits.alt_pic_quantizer;
1377 alt_pquant_config = 0;
1378 alt_pquant_edge_mask = 0;
1379 } else if (dquant == 2) {
1380 alt_pquant_config = 1;
1381 alt_pquant_edge_mask = 0xf;
1383 assert(dquant == 1);
1384 if (dquantfrm == 0) {
1385 alt_pquant_config = 0;
1386 alt_pquant_edge_mask = 0;
1389 assert(dquantfrm == 1);
1390 alt_pquant_config = 1;
1392 switch (dqprofile) {
1394 if (dqbilevel == 0) {
1395 alt_pquant_config = 2;
1396 alt_pquant_edge_mask = 0;
1398 assert(dqbilevel == 1);
1399 alt_pquant_config = 3;
1400 alt_pquant_edge_mask = 0;
1405 alt_pquant_edge_mask = 0xf;
1410 alt_pquant_edge_mask = 0x9;
1412 alt_pquant_edge_mask = (0x3 << dqdbedge);
1417 alt_pquant_edge_mask = (0x1 << dqsbedge);
1426 if (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation) {
1427 assert(pic_param->mv_fields.bits.mv_mode2 < 4);
1428 unified_mv_mode = va_to_gen6_vc1_mv[pic_param->mv_fields.bits.mv_mode2];
1430 assert(pic_param->mv_fields.bits.mv_mode < 4);
1431 unified_mv_mode = va_to_gen6_vc1_mv[pic_param->mv_fields.bits.mv_mode];
1434 if (pic_param->sequence_fields.bits.interlace == 1 &&
1435 pic_param->picture_fields.bits.frame_coding_mode != 0) { /* frame-interlace or field-interlace */
1436 /* FIXME: calculate reference field picture polarity */
1438 ref_field_pic_polarity = 0;
1441 if (pic_param->b_picture_fraction < 21)
1442 scale_factor = b_picture_scale_factor[pic_param->b_picture_fraction];
1444 picture_type = va_to_gen6_vc1_pic_type[pic_param->picture_fields.bits.picture_type];
1446 if (profile == GEN6_VC1_ADVANCED_PROFILE &&
1447 picture_type == GEN6_VC1_I_PICTURE)
1448 picture_type = GEN6_VC1_BI_PICTURE;
1450 if (picture_type == GEN6_VC1_I_PICTURE || picture_type == GEN6_VC1_BI_PICTURE) /* I picture */
1451 trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx2;
1453 trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx1;
1455 * 8.3.6.2.1 Transform Type Selection
1456 * If variable-sized transform coding is not enabled,
1457 * then the 8x8 transform shall be used for all blocks.
1458 * it is also MFX_VC1_PIC_STATE requirement.
1460 if (pic_param->transform_fields.bits.variable_sized_transform_flag == 0) {
1461 pic_param->transform_fields.bits.mb_level_transform_type_flag = 1;
1462 pic_param->transform_fields.bits.frame_level_transform_type = 0;
1466 if (picture_type == GEN6_VC1_B_PICTURE) {
1467 struct gen6_vc1_surface *gen6_vc1_surface = NULL;
1469 obj_surface = decode_state->reference_objects[1];
1472 gen6_vc1_surface = obj_surface->private_data;
1474 if (!gen6_vc1_surface ||
1475 (va_to_gen6_vc1_pic_type[gen6_vc1_surface->picture_type] == GEN6_VC1_I_PICTURE ||
1476 va_to_gen6_vc1_pic_type[gen6_vc1_surface->picture_type] == GEN6_VC1_BI_PICTURE))
1477 dmv_surface_valid = 0;
1479 dmv_surface_valid = 1;
1482 assert(pic_param->picture_fields.bits.frame_coding_mode < 3);
1484 if (pic_param->picture_fields.bits.frame_coding_mode < 2)
1485 fcm = pic_param->picture_fields.bits.frame_coding_mode;
1487 if (pic_param->picture_fields.bits.top_field_first)
1493 if (pic_param->picture_fields.bits.picture_type == GEN6_VC1_B_PICTURE) { /* B picture */
1494 brfd = pic_param->reference_fields.bits.reference_distance;
1495 brfd = (scale_factor * brfd) >> 8;
1496 brfd = pic_param->reference_fields.bits.reference_distance - brfd - 1;
1502 overlap = pic_param->sequence_fields.bits.overlap;
1506 if (profile != GEN6_VC1_ADVANCED_PROFILE) {
1507 if (pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9 &&
1508 pic_param->picture_fields.bits.picture_type != GEN6_VC1_B_PICTURE) {
1512 if (pic_param->picture_fields.bits.picture_type == GEN6_VC1_P_PICTURE &&
1513 pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9) {
1516 if (pic_param->picture_fields.bits.picture_type == GEN6_VC1_I_PICTURE ||
1517 pic_param->picture_fields.bits.picture_type == GEN6_VC1_BI_PICTURE) {
1518 if (pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9) {
1520 } else if (va_to_gen6_vc1_condover[pic_param->conditional_overlap_flag] == 2 ||
1521 va_to_gen6_vc1_condover[pic_param->conditional_overlap_flag] == 3) {
1528 assert(pic_param->conditional_overlap_flag < 3);
1529 assert(pic_param->mv_fields.bits.mv_table < 4); /* FIXME: interlace mode */
1531 BEGIN_BCS_BATCH(batch, 6);
1532 OUT_BCS_BATCH(batch, MFX_VC1_PIC_STATE | (6 - 2));
1533 OUT_BCS_BATCH(batch,
1534 (ALIGN(pic_param->coded_height, 16) / 16) << 16 |
1535 (ALIGN(pic_param->coded_width, 16) / 16));
1536 OUT_BCS_BATCH(batch,
1537 pic_param->sequence_fields.bits.syncmarker << 31 |
1538 1 << 29 | /* concealment */
1540 pic_param->entrypoint_fields.bits.loopfilter << 23 |
1542 (pic_param->pic_quantizer_fields.bits.quantizer == 0) << 21 | /* implicit quantizer */
1543 pic_param->pic_quantizer_fields.bits.pic_quantizer_scale << 16 |
1544 alt_pquant_edge_mask << 12 |
1545 alt_pquant_config << 10 |
1546 pic_param->pic_quantizer_fields.bits.half_qp << 9 |
1547 pic_param->pic_quantizer_fields.bits.pic_quantizer_type << 8 |
1548 va_to_gen6_vc1_condover[pic_param->conditional_overlap_flag] << 6 |
1549 !pic_param->picture_fields.bits.is_first_field << 5 |
1552 OUT_BCS_BATCH(batch,
1553 !!pic_param->bitplane_present.value << 23 |
1554 !pic_param->bitplane_present.flags.bp_forward_mb << 22 |
1555 !pic_param->bitplane_present.flags.bp_mv_type_mb << 21 |
1556 !pic_param->bitplane_present.flags.bp_skip_mb << 20 |
1557 !pic_param->bitplane_present.flags.bp_direct_mb << 19 |
1558 !pic_param->bitplane_present.flags.bp_overflags << 18 |
1559 !pic_param->bitplane_present.flags.bp_ac_pred << 17 |
1560 !pic_param->bitplane_present.flags.bp_field_tx << 16 |
1561 pic_param->mv_fields.bits.extended_dmv_range << 14 |
1562 pic_param->mv_fields.bits.extended_mv_range << 12 |
1563 pic_param->mv_fields.bits.four_mv_switch << 11 |
1564 pic_param->fast_uvmc_flag << 10 |
1565 unified_mv_mode << 8 |
1566 ref_field_pic_polarity << 6 |
1567 pic_param->reference_fields.bits.num_reference_pictures << 5 |
1568 pic_param->reference_fields.bits.reference_distance << 0);
1569 OUT_BCS_BATCH(batch,
1570 scale_factor << 24 |
1571 pic_param->mv_fields.bits.mv_table << 20 |
1572 pic_param->mv_fields.bits.four_mv_block_pattern_table << 18 |
1573 pic_param->mv_fields.bits.two_mv_block_pattern_table << 16 |
1574 pic_param->transform_fields.bits.frame_level_transform_type << 12 |
1575 pic_param->transform_fields.bits.mb_level_transform_type_flag << 11 |
1576 pic_param->mb_mode_table << 8 |
1578 pic_param->transform_fields.bits.transform_ac_codingset_idx1 << 4 |
1579 pic_param->transform_fields.bits.intra_transform_dc_table << 3 |
1580 pic_param->cbp_table << 0);
1581 OUT_BCS_BATCH(batch,
1582 dmv_surface_valid << 13 |
1584 ((ALIGN(pic_param->coded_width, 16) / 16 + 1) / 2 - 1));
1585 ADVANCE_BCS_BATCH(batch);
1589 gen6_mfd_vc1_pred_pipe_state(VADriverContextP ctx,
1590 struct decode_state *decode_state,
1591 struct gen6_mfd_context *gen6_mfd_context)
1593 struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1594 VAPictureParameterBufferVC1 *pic_param;
1596 int interpolation_mode = 0;
1597 int intensitycomp_single_fwd = 0;
1598 int luma_scale1 = 0;
1599 int luma_shift1 = 0;
1601 assert(decode_state->pic_param && decode_state->pic_param->buffer);
1602 pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1603 picture_type = pic_param->picture_fields.bits.picture_type;
1605 if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPelBilinear ||
1606 (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation &&
1607 pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPelBilinear))
1608 interpolation_mode = 2; /* Half-pel bilinear */
1609 else if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPel ||
1610 (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation &&
1611 pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPel))
1612 interpolation_mode = 0; /* Half-pel bicubic */
1614 interpolation_mode = 1; /* Quarter-pel bicubic */
1616 assert(decode_state->pic_param && decode_state->pic_param->buffer);
1617 pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1619 if (gen6_mfd_context->reference_surface[0].surface_id != VA_INVALID_ID) {
1620 if (picture_type == 1 || picture_type == 2) { /* P/B picture */
1621 struct gen6_vc1_surface *gen6_vc1_surface = gen6_mfd_context->reference_surface[0].obj_surface->private_data;
1622 if (gen6_vc1_surface) {
1623 intensitycomp_single_fwd = gen6_vc1_surface->intensity_compensation;
1624 luma_scale1 = gen6_vc1_surface->luma_scale;
1625 luma_shift1 = gen6_vc1_surface->luma_shift;
1630 BEGIN_BCS_BATCH(batch, 7);
1631 OUT_BCS_BATCH(batch, MFX_VC1_PRED_PIPE_STATE | (7 - 2));
1632 OUT_BCS_BATCH(batch,
1633 0 << 8 | /* FIXME: interlace mode */
1634 pic_param->rounding_control << 4 |
1635 va_to_gen6_vc1_profile[pic_param->sequence_fields.bits.profile] << 2);
1636 OUT_BCS_BATCH(batch,
1639 OUT_BCS_BATCH(batch, 0);
1640 OUT_BCS_BATCH(batch, 0);
1641 OUT_BCS_BATCH(batch, 0);
1642 OUT_BCS_BATCH(batch,
1643 interpolation_mode << 19 |
1644 pic_param->fast_uvmc_flag << 18 |
1645 0 << 17 | /* FIXME: scale up or down ??? */
1646 pic_param->range_reduction_frame << 16 |
1647 0 << 6 | /* FIXME: double ??? */
1649 intensitycomp_single_fwd << 2 |
1651 ADVANCE_BCS_BATCH(batch);
1656 gen6_mfd_vc1_directmode_state(VADriverContextP ctx,
1657 struct decode_state *decode_state,
1658 struct gen6_mfd_context *gen6_mfd_context)
1660 struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1661 struct object_surface *obj_surface;
1662 dri_bo *dmv_read_buffer = NULL, *dmv_write_buffer = NULL;
1664 obj_surface = decode_state->render_object;
1666 if (obj_surface && obj_surface->private_data) {
1667 dmv_write_buffer = ((struct gen6_vc1_surface *)(obj_surface->private_data))->dmv;
1670 obj_surface = decode_state->reference_objects[1];
1672 if (obj_surface && obj_surface->private_data) {
1673 dmv_read_buffer = ((struct gen6_vc1_surface *)(obj_surface->private_data))->dmv;
1676 BEGIN_BCS_BATCH(batch, 3);
1677 OUT_BCS_BATCH(batch, MFX_VC1_DIRECTMODE_STATE | (3 - 2));
1679 if (dmv_write_buffer)
1680 OUT_BCS_RELOC(batch, dmv_write_buffer,
1681 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
1684 OUT_BCS_BATCH(batch, 0);
1686 if (dmv_read_buffer)
1687 OUT_BCS_RELOC(batch, dmv_read_buffer,
1688 I915_GEM_DOMAIN_INSTRUCTION, 0,
1691 OUT_BCS_BATCH(batch, 0);
1693 ADVANCE_BCS_BATCH(batch);
1697 gen6_mfd_vc1_get_macroblock_bit_offset(uint8_t *buf, int in_slice_data_bit_offset, int profile)
1699 int out_slice_data_bit_offset;
1700 int slice_header_size = in_slice_data_bit_offset / 8;
1704 out_slice_data_bit_offset = in_slice_data_bit_offset;
1706 for (i = 0, j = 0; i < slice_header_size; i++, j++) {
1707 if (!buf[j] && !buf[j + 1] && buf[j + 2] == 3 && buf[j + 3] < 4) {
1712 out_slice_data_bit_offset = 8 * j + in_slice_data_bit_offset % 8;
1715 return out_slice_data_bit_offset;
1719 gen6_mfd_vc1_bsd_object(VADriverContextP ctx,
1720 VAPictureParameterBufferVC1 *pic_param,
1721 VASliceParameterBufferVC1 *slice_param,
1722 VASliceParameterBufferVC1 *next_slice_param,
1723 dri_bo *slice_data_bo,
1724 struct gen6_mfd_context *gen6_mfd_context)
1726 struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1727 int next_slice_start_vert_pos;
1728 int macroblock_offset;
1729 uint8_t *slice_data = NULL;
1731 dri_bo_map(slice_data_bo, 0);
1732 slice_data = (uint8_t *)(slice_data_bo->virtual + slice_param->slice_data_offset);
1733 macroblock_offset = gen6_mfd_vc1_get_macroblock_bit_offset(slice_data,
1734 slice_param->macroblock_offset,
1735 pic_param->sequence_fields.bits.profile);
1736 dri_bo_unmap(slice_data_bo);
1738 if (next_slice_param)
1739 next_slice_start_vert_pos = next_slice_param->slice_vertical_position;
1741 next_slice_start_vert_pos = ALIGN(pic_param->coded_height, 16) / 16;
1743 BEGIN_BCS_BATCH(batch, 4);
1744 OUT_BCS_BATCH(batch, MFD_VC1_BSD_OBJECT | (4 - 2));
1745 OUT_BCS_BATCH(batch,
1746 slice_param->slice_data_size - (macroblock_offset >> 3));
1747 OUT_BCS_BATCH(batch,
1748 slice_param->slice_data_offset + (macroblock_offset >> 3));
1749 OUT_BCS_BATCH(batch,
1750 slice_param->slice_vertical_position << 24 |
1751 next_slice_start_vert_pos << 16 |
1752 (macroblock_offset & 0x7));
1753 ADVANCE_BCS_BATCH(batch);
1757 gen6_mfd_vc1_decode_picture(VADriverContextP ctx,
1758 struct decode_state *decode_state,
1759 struct gen6_mfd_context *gen6_mfd_context)
1761 struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1762 VAPictureParameterBufferVC1 *pic_param;
1763 VASliceParameterBufferVC1 *slice_param, *next_slice_param, *next_slice_group_param;
1764 dri_bo *slice_data_bo;
1767 assert(decode_state->pic_param && decode_state->pic_param->buffer);
1768 pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1770 gen6_mfd_vc1_decode_init(ctx, decode_state, gen6_mfd_context);
1771 intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
1772 intel_batchbuffer_emit_mi_flush(batch);
1773 gen6_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_VC1, gen6_mfd_context);
1774 gen6_mfd_surface_state(ctx, decode_state, MFX_FORMAT_VC1, gen6_mfd_context);
1775 gen6_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen6_mfd_context);
1776 gen6_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen6_mfd_context);
1777 gen6_mfd_vc1_pic_state(ctx, decode_state, gen6_mfd_context);
1778 gen6_mfd_vc1_pred_pipe_state(ctx, decode_state, gen6_mfd_context);
1779 gen6_mfd_vc1_directmode_state(ctx, decode_state, gen6_mfd_context);
1781 for (j = 0; j < decode_state->num_slice_params; j++) {
1782 assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
1783 slice_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j]->buffer;
1784 slice_data_bo = decode_state->slice_datas[j]->bo;
1785 gen6_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_VC1, gen6_mfd_context);
1787 if (j == decode_state->num_slice_params - 1)
1788 next_slice_group_param = NULL;
1790 next_slice_group_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j + 1]->buffer;
1792 for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
1793 assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
1795 if (i < decode_state->slice_params[j]->num_elements - 1)
1796 next_slice_param = slice_param + 1;
1798 next_slice_param = next_slice_group_param;
1800 gen6_mfd_vc1_bsd_object(ctx, pic_param, slice_param, next_slice_param, slice_data_bo, gen6_mfd_context);
1805 intel_batchbuffer_end_atomic(batch);
1806 intel_batchbuffer_flush(batch);
1810 gen6_mfd_decode_picture(VADriverContextP ctx,
1812 union codec_state *codec_state,
1813 struct hw_context *hw_context)
1816 struct gen6_mfd_context *gen6_mfd_context = (struct gen6_mfd_context *)hw_context;
1817 struct decode_state *decode_state = &codec_state->decode;
1820 assert(gen6_mfd_context);
1822 vaStatus = intel_decoder_sanity_check_input(ctx, profile, decode_state);
1824 if (vaStatus != VA_STATUS_SUCCESS)
1828 case VAProfileMPEG2Simple:
1829 case VAProfileMPEG2Main:
1830 gen6_mfd_mpeg2_decode_picture(ctx, decode_state, gen6_mfd_context);
1833 case VAProfileH264ConstrainedBaseline:
1834 case VAProfileH264Main:
1835 case VAProfileH264High:
1836 case VAProfileH264StereoHigh:
1837 gen6_mfd_avc_decode_picture(ctx, decode_state, gen6_mfd_context);
1840 case VAProfileVC1Simple:
1841 case VAProfileVC1Main:
1842 case VAProfileVC1Advanced:
1843 gen6_mfd_vc1_decode_picture(ctx, decode_state, gen6_mfd_context);
1851 vaStatus = VA_STATUS_SUCCESS;
1858 gen6_mfd_context_destroy(void *hw_context)
1860 struct gen6_mfd_context *gen6_mfd_context = (struct gen6_mfd_context *)hw_context;
1862 dri_bo_unreference(gen6_mfd_context->post_deblocking_output.bo);
1863 gen6_mfd_context->post_deblocking_output.bo = NULL;
1865 dri_bo_unreference(gen6_mfd_context->pre_deblocking_output.bo);
1866 gen6_mfd_context->pre_deblocking_output.bo = NULL;
1868 dri_bo_unreference(gen6_mfd_context->intra_row_store_scratch_buffer.bo);
1869 gen6_mfd_context->intra_row_store_scratch_buffer.bo = NULL;
1871 dri_bo_unreference(gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
1872 gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
1874 dri_bo_unreference(gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
1875 gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
1877 dri_bo_unreference(gen6_mfd_context->mpr_row_store_scratch_buffer.bo);
1878 gen6_mfd_context->mpr_row_store_scratch_buffer.bo = NULL;
1880 dri_bo_unreference(gen6_mfd_context->bitplane_read_buffer.bo);
1881 gen6_mfd_context->bitplane_read_buffer.bo = NULL;
1883 intel_batchbuffer_free(gen6_mfd_context->base.batch);
1884 free(gen6_mfd_context);
1888 gen6_dec_hw_context_init(VADriverContextP ctx, struct object_config *obj_config)
1890 struct intel_driver_data *intel = intel_driver_data(ctx);
1891 struct gen6_mfd_context *gen6_mfd_context = calloc(1, sizeof(struct gen6_mfd_context));
1894 if (!gen6_mfd_context)
1897 gen6_mfd_context->base.destroy = gen6_mfd_context_destroy;
1898 gen6_mfd_context->base.run = gen6_mfd_decode_picture;
1899 gen6_mfd_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER, 0);
1901 for (i = 0; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface); i++) {
1902 gen6_mfd_context->reference_surface[i].surface_id = VA_INVALID_ID;
1903 gen6_mfd_context->reference_surface[i].frame_store_id = -1;
1904 gen6_mfd_context->reference_surface[i].obj_surface = NULL;
1907 gen6_mfd_context->wa_mpeg2_slice_vertical_position = -1;
1909 return (struct hw_context *)gen6_mfd_context;