src/gen6_mfd.c

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Xiang Haihao <haihao.xiang@intel.com>
  26  *
  27  */
  28
  29 #include "sysdeps.h"
  30 #include "intel_batchbuffer.h"
  31 #include "intel_driver.h"
  32 #include "i965_defines.h"
  33 #include "i965_drv_video.h"
  34 #include "i965_decoder_utils.h"
  35
  36 #include "gen6_mfd.h"
  37 #include "intel_media.h"
  38
  39 static const uint32_t zigzag_direct[64] = {
  40     0,   1,  8, 16,  9,  2,  3, 10,
  41     17, 24, 32, 25, 18, 11,  4,  5,
  42     12, 19, 26, 33, 40, 48, 41, 34,
  43     27, 20, 13,  6,  7, 14, 21, 28,
  44     35, 42, 49, 56, 57, 50, 43, 36,
  45     29, 22, 15, 23, 30, 37, 44, 51,
  46     58, 59, 52, 45, 38, 31, 39, 46,
  47     53, 60, 61, 54, 47, 55, 62, 63
  48 };
  49
  50 static void
  51 gen6_mfd_init_avc_surface(VADriverContextP ctx,
  52                           VAPictureParameterBufferH264 *pic_param,
  53                           struct object_surface *obj_surface)
  54 {
  55     struct i965_driver_data *i965 = i965_driver_data(ctx);
  56     GenAvcSurface *gen6_avc_surface = obj_surface->private_data;
  57     int height_in_mbs;
  58
  59     obj_surface->free_private_data = gen_free_avc_surface;
  60     height_in_mbs = ((pic_param->picture_height_in_mbs_minus1 + 1) & 0xff); /* frame height */
  61
  62     if (!gen6_avc_surface) {
  63         gen6_avc_surface = calloc(sizeof(GenAvcSurface), 1);
  64         assert(gen6_avc_surface);
  65         gen6_avc_surface->base.frame_store_id = -1;
  66         assert((obj_surface->size & 0x3f) == 0);
  67         obj_surface->private_data = gen6_avc_surface;
  68     }
  69
  70     gen6_avc_surface->dmv_bottom_flag = (pic_param->pic_fields.bits.field_pic_flag &&
  71                                          !pic_param->seq_fields.bits.direct_8x8_inference_flag);
  72
  73     if (gen6_avc_surface->dmv_top == NULL) {
  74         gen6_avc_surface->dmv_top = dri_bo_alloc(i965->intel.bufmgr,
  75                                                  "direct mv w/r buffer",
  76                                                  128 * height_in_mbs * 64,      /* scalable with frame height */
  77                                                  0x1000);
  78     }
  79
  80     if (gen6_avc_surface->dmv_bottom_flag &&
  81         gen6_avc_surface->dmv_bottom == NULL) {
  82         gen6_avc_surface->dmv_bottom = dri_bo_alloc(i965->intel.bufmgr,
  83                                                     "direct mv w/r buffer",
  84                                                     128 * height_in_mbs * 64,   /* scalable with frame height */
  85                                                     0x1000);
  86     }
  87 }
  88
  89 static void
  90 gen6_mfd_pipe_mode_select(VADriverContextP ctx,
  91                           struct decode_state *decode_state,
  92                           int standard_select,
  93                           struct gen6_mfd_context *gen6_mfd_context)
  94 {
  95     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
  96
  97     assert(standard_select == MFX_FORMAT_MPEG2 ||
  98            standard_select == MFX_FORMAT_AVC ||
  99            standard_select == MFX_FORMAT_VC1);
 100
 101     BEGIN_BCS_BATCH(batch, 4);
 102     OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (4 - 2));
 103     OUT_BCS_BATCH(batch,
 104                   (MFD_MODE_VLD << 16) | /* VLD mode */
 105                   (0 << 10) | /* disable Stream-Out */
 106                   (gen6_mfd_context->post_deblocking_output.valid << 9)  | /* Post Deblocking Output */
 107                   (gen6_mfd_context->pre_deblocking_output.valid << 8)  | /* Pre Deblocking Output */
 108                   (0 << 7)  | /* disable TLB prefectch */
 109                   (0 << 5)  | /* not in stitch mode */
 110                   (MFX_CODEC_DECODE << 4)  | /* decoding mode */
 111                   (standard_select << 0));
 112     OUT_BCS_BATCH(batch,
 113                   (0 << 20) | /* round flag in PB slice */
 114                   (0 << 19) | /* round flag in Intra8x8 */
 115                   (0 << 7)  | /* expand NOA bus flag */
 116                   (1 << 6)  | /* must be 1 */
 117                   (0 << 5)  | /* disable clock gating for NOA */
 118                   (0 << 4)  | /* terminate if AVC motion and POC table error occurs */
 119                   (0 << 3)  | /* terminate if AVC mbdata error occurs */
 120                   (0 << 2)  | /* terminate if AVC CABAC/CAVLC decode error occurs */
 121                   (0 << 1)  | /* AVC long field motion vector */
 122                   (1 << 0));  /* always calculate AVC ILDB boundary strength */
 123     OUT_BCS_BATCH(batch, 0);
 124     ADVANCE_BCS_BATCH(batch);
 125 }
 126
 127 static void
 128 gen6_mfd_surface_state(VADriverContextP ctx,
 129                        struct decode_state *decode_state,
 130                        int standard_select,
 131                        struct gen6_mfd_context *gen6_mfd_context)
 132 {
 133     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 134     struct object_surface *obj_surface = decode_state->render_object;
 135     unsigned int surface_format;
 136
 137     surface_format = obj_surface->fourcc == VA_FOURCC_Y800 ?
 138         MFX_SURFACE_MONOCHROME : MFX_SURFACE_PLANAR_420_8;
 139
 140     BEGIN_BCS_BATCH(batch, 6);
 141     OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
 142     OUT_BCS_BATCH(batch, 0);
 143     OUT_BCS_BATCH(batch,
 144                   ((obj_surface->orig_height - 1) << 19) |
 145                   ((obj_surface->orig_width - 1) << 6));
 146     OUT_BCS_BATCH(batch,
 147                   (surface_format << 28) | /* 420 planar YUV surface */
 148                   (1 << 27) | /* must be 1 for interleave U/V, hardware requirement */
 149                   (0 << 22) | /* surface object control state, FIXME??? */
 150                   ((obj_surface->width - 1) << 3) | /* pitch */
 151                   (0 << 2)  | /* must be 0 for interleave U/V */
 152                   (1 << 1)  | /* must be y-tiled */
 153                   (I965_TILEWALK_YMAJOR << 0));  /* tile walk, FIXME: must be 1 ??? */
 154     OUT_BCS_BATCH(batch,
 155                   (0 << 16) | /* must be 0 for interleave U/V */
 156                   (obj_surface->height)); /* y offset for U(cb) */
 157     OUT_BCS_BATCH(batch, 0);
 158     ADVANCE_BCS_BATCH(batch);
 159 }
 160
 161 static void
 162 gen6_mfd_pipe_buf_addr_state(VADriverContextP ctx,
 163                              struct decode_state *decode_state,
 164                              int standard_select,
 165                              struct gen6_mfd_context *gen6_mfd_context)
 166 {
 167     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 168     int i;
 169
 170     BEGIN_BCS_BATCH(batch, 24);
 171     OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
 172     if (gen6_mfd_context->pre_deblocking_output.valid)
 173         OUT_BCS_RELOC(batch, gen6_mfd_context->pre_deblocking_output.bo,
 174                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 175                       0);
 176     else
 177         OUT_BCS_BATCH(batch, 0);
 178
 179     if (gen6_mfd_context->post_deblocking_output.valid)
 180         OUT_BCS_RELOC(batch, gen6_mfd_context->post_deblocking_output.bo,
 181                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 182                       0);
 183     else
 184         OUT_BCS_BATCH(batch, 0);
 185
 186     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
 187     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
 188
 189     if (gen6_mfd_context->intra_row_store_scratch_buffer.valid)
 190         OUT_BCS_RELOC(batch, gen6_mfd_context->intra_row_store_scratch_buffer.bo,
 191                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 192                       0);
 193     else
 194         OUT_BCS_BATCH(batch, 0);
 195
 196     if (gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.valid)
 197         OUT_BCS_RELOC(batch, gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo,
 198                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 199                       0);
 200     else
 201         OUT_BCS_BATCH(batch, 0);
 202
 203     /* DW 7..22 */
 204     for (i = 0; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface); i++) {
 205         struct object_surface *obj_surface;
 206
 207         if (gen6_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID &&
 208             gen6_mfd_context->reference_surface[i].obj_surface &&
 209             gen6_mfd_context->reference_surface[i].obj_surface->bo) {
 210             obj_surface = gen6_mfd_context->reference_surface[i].obj_surface;
 211
 212             OUT_BCS_RELOC(batch, obj_surface->bo,
 213                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 214                           0);
 215         } else {
 216             OUT_BCS_BATCH(batch, 0);
 217         }
 218     }
 219
 220     OUT_BCS_BATCH(batch, 0);   /* ignore DW23 for decoding */
 221     ADVANCE_BCS_BATCH(batch);
 222 }
 223
 224 static void
 225 gen6_mfd_ind_obj_base_addr_state(VADriverContextP ctx,
 226                                  dri_bo *slice_data_bo,
 227                                  int standard_select,
 228                                  struct gen6_mfd_context *gen6_mfd_context)
 229 {
 230     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 231
 232     BEGIN_BCS_BATCH(batch, 11);
 233     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
 234     OUT_BCS_RELOC(batch, slice_data_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); /* MFX Indirect Bitstream Object Base Address */
 235     OUT_BCS_BATCH(batch, 0);
 236     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 237     OUT_BCS_BATCH(batch, 0);
 238     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 239     OUT_BCS_BATCH(batch, 0);
 240     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 241     OUT_BCS_BATCH(batch, 0);
 242     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 243     OUT_BCS_BATCH(batch, 0);
 244     ADVANCE_BCS_BATCH(batch);
 245 }
 246
 247 static void
 248 gen6_mfd_bsp_buf_base_addr_state(VADriverContextP ctx,
 249                                  struct decode_state *decode_state,
 250                                  int standard_select,
 251                                  struct gen6_mfd_context *gen6_mfd_context)
 252 {
 253     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 254
 255     BEGIN_BCS_BATCH(batch, 4);
 256     OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
 257
 258     if (gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.valid)
 259         OUT_BCS_RELOC(batch, gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo,
 260                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 261                       0);
 262     else
 263         OUT_BCS_BATCH(batch, 0);
 264
 265     if (gen6_mfd_context->mpr_row_store_scratch_buffer.valid)
 266         OUT_BCS_RELOC(batch, gen6_mfd_context->mpr_row_store_scratch_buffer.bo,
 267                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 268                       0);
 269     else
 270         OUT_BCS_BATCH(batch, 0);
 271
 272     if (gen6_mfd_context->bitplane_read_buffer.valid)
 273         OUT_BCS_RELOC(batch, gen6_mfd_context->bitplane_read_buffer.bo,
 274                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 275                       0);
 276     else
 277         OUT_BCS_BATCH(batch, 0);
 278
 279     ADVANCE_BCS_BATCH(batch);
 280 }
 281
 282 static void
 283 gen6_mfd_avc_img_state(VADriverContextP ctx,
 284                        struct decode_state *decode_state,
 285                        struct gen6_mfd_context *gen6_mfd_context)
 286 {
 287     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 288     int qm_present_flag;
 289     int img_struct;
 290     int mbaff_frame_flag;
 291     unsigned int width_in_mbs, height_in_mbs;
 292     VAPictureParameterBufferH264 *pic_param;
 293
 294     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 295     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 296
 297     if (decode_state->iq_matrix && decode_state->iq_matrix->buffer)
 298         qm_present_flag = 1;
 299     else
 300         qm_present_flag = 0; /* built-in QM matrices */
 301
 302     if (pic_param->CurrPic.flags & VA_PICTURE_H264_TOP_FIELD)
 303         img_struct = 1;
 304     else if (pic_param->CurrPic.flags & VA_PICTURE_H264_BOTTOM_FIELD)
 305         img_struct = 3;
 306     else
 307         img_struct = 0;
 308
 309     if ((img_struct & 0x1) == 0x1) {
 310         assert(pic_param->pic_fields.bits.field_pic_flag == 0x1);
 311     } else {
 312         assert(pic_param->pic_fields.bits.field_pic_flag == 0x0);
 313     }
 314
 315     if (pic_param->seq_fields.bits.frame_mbs_only_flag) { /* a frame containing only frame macroblocks */
 316         assert(pic_param->seq_fields.bits.mb_adaptive_frame_field_flag == 0);
 317         assert(pic_param->pic_fields.bits.field_pic_flag == 0);
 318     } else {
 319         assert(pic_param->seq_fields.bits.direct_8x8_inference_flag == 1); /* see H.264 spec */
 320     }
 321
 322     mbaff_frame_flag = (pic_param->seq_fields.bits.mb_adaptive_frame_field_flag &&
 323                         !pic_param->pic_fields.bits.field_pic_flag);
 324
 325     width_in_mbs = ((pic_param->picture_width_in_mbs_minus1 + 1) & 0xff);
 326     height_in_mbs = ((pic_param->picture_height_in_mbs_minus1 + 1) & 0xff); /* frame height */
 327     assert(!((width_in_mbs * height_in_mbs) & 0x8000)); /* hardware requirement */
 328
 329     /* MFX unit doesn't support 4:2:2 and 4:4:4 picture */
 330     assert(pic_param->seq_fields.bits.chroma_format_idc == 0 || /* monochrome picture */
 331            pic_param->seq_fields.bits.chroma_format_idc == 1);  /* 4:2:0 */
 332     assert(pic_param->seq_fields.bits.residual_colour_transform_flag == 0); /* only available for 4:4:4 */
 333
 334     BEGIN_BCS_BATCH(batch, 13);
 335     OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (13 - 2));
 336     OUT_BCS_BATCH(batch,
 337                   ((width_in_mbs * height_in_mbs) & 0x7fff));
 338     OUT_BCS_BATCH(batch,
 339                   (height_in_mbs << 16) |
 340                   (width_in_mbs << 0));
 341     OUT_BCS_BATCH(batch,
 342                   ((pic_param->second_chroma_qp_index_offset & 0x1f) << 24) |
 343                   ((pic_param->chroma_qp_index_offset & 0x1f) << 16) |
 344                   (0 << 14) | /* Max-bit conformance Intra flag ??? FIXME */
 345                   (0 << 13) | /* Max Macroblock size conformance Inter flag ??? FIXME */
 346                   (1 << 12) | /* always 1, hardware requirement */
 347                   (qm_present_flag << 10) |
 348                   (img_struct << 8) |
 349                   (16 << 0));
 350     OUT_BCS_BATCH(batch,
 351                   (pic_param->seq_fields.bits.chroma_format_idc << 10) |
 352                   (pic_param->pic_fields.bits.entropy_coding_mode_flag << 7) |
 353                   ((!pic_param->pic_fields.bits.reference_pic_flag) << 6) |
 354                   (pic_param->pic_fields.bits.constrained_intra_pred_flag << 5) |
 355                   (pic_param->seq_fields.bits.direct_8x8_inference_flag << 4) |
 356                   (pic_param->pic_fields.bits.transform_8x8_mode_flag << 3) |
 357                   (pic_param->seq_fields.bits.frame_mbs_only_flag << 2) |
 358                   (mbaff_frame_flag << 1) |
 359                   (pic_param->pic_fields.bits.field_pic_flag << 0));
 360     OUT_BCS_BATCH(batch, 0);
 361     OUT_BCS_BATCH(batch, 0);
 362     OUT_BCS_BATCH(batch, 0);
 363     OUT_BCS_BATCH(batch, 0);
 364     OUT_BCS_BATCH(batch, 0);
 365     OUT_BCS_BATCH(batch, 0);
 366     OUT_BCS_BATCH(batch, 0);
 367     OUT_BCS_BATCH(batch, 0);
 368     ADVANCE_BCS_BATCH(batch);
 369 }
 370
 371 static void
 372 gen6_mfd_avc_qm_state(VADriverContextP ctx,
 373                       struct decode_state *decode_state,
 374                       struct gen6_mfd_context *gen6_mfd_context)
 375 {
 376     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 377     int cmd_len;
 378     VAIQMatrixBufferH264 *iq_matrix;
 379     VAPictureParameterBufferH264 *pic_param;
 380
 381     if (!decode_state->iq_matrix || !decode_state->iq_matrix->buffer)
 382         return;
 383
 384     iq_matrix = (VAIQMatrixBufferH264 *)decode_state->iq_matrix->buffer;
 385
 386     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 387     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 388
 389     cmd_len = 2 + 6 * 4; /* always load six 4x4 scaling matrices */
 390
 391     if (pic_param->pic_fields.bits.transform_8x8_mode_flag)
 392         cmd_len += 2 * 16; /* load two 8x8 scaling matrices */
 393
 394     BEGIN_BCS_BATCH(batch, cmd_len);
 395     OUT_BCS_BATCH(batch, MFX_AVC_QM_STATE | (cmd_len - 2));
 396
 397     if (pic_param->pic_fields.bits.transform_8x8_mode_flag)
 398         OUT_BCS_BATCH(batch,
 399                       (0x0  << 8) | /* don't use default built-in matrices */
 400                       (0xff << 0)); /* six 4x4 and two 8x8 scaling matrices */
 401     else
 402         OUT_BCS_BATCH(batch,
 403                       (0x0  << 8) | /* don't use default built-in matrices */
 404                       (0x3f << 0)); /* six 4x4 scaling matrices */
 405
 406     intel_batchbuffer_data(batch, &iq_matrix->ScalingList4x4[0][0], 6 * 4 * 4);
 407
 408     if (pic_param->pic_fields.bits.transform_8x8_mode_flag)
 409         intel_batchbuffer_data(batch, &iq_matrix->ScalingList8x8[0][0], 2 * 16 * 4);
 410
 411     ADVANCE_BCS_BATCH(batch);
 412 }
 413
 414 static void
 415 gen6_mfd_avc_directmode_state(VADriverContextP ctx,
 416                               struct decode_state *decode_state,
 417                               VAPictureParameterBufferH264 *pic_param,
 418                               VASliceParameterBufferH264 *slice_param,
 419                               struct gen6_mfd_context *gen6_mfd_context)
 420 {
 421     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 422     struct object_surface *obj_surface;
 423     GenAvcSurface *gen6_avc_surface;
 424     VAPictureH264 *va_pic;
 425     int i;
 426
 427     BEGIN_BCS_BATCH(batch, 69);
 428     OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
 429
 430     /* reference surfaces 0..15 */
 431     for (i = 0; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface); i++) {
 432         if (gen6_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID &&
 433             gen6_mfd_context->reference_surface[i].obj_surface &&
 434             gen6_mfd_context->reference_surface[i].obj_surface->private_data) {
 435
 436             obj_surface = gen6_mfd_context->reference_surface[i].obj_surface;
 437             gen6_avc_surface = obj_surface->private_data;
 438             OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_top,
 439                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 440                           0);
 441
 442             if (gen6_avc_surface->dmv_bottom_flag == 1)
 443                 OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_bottom,
 444                               I915_GEM_DOMAIN_INSTRUCTION, 0,
 445                               0);
 446             else
 447                 OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_top,
 448                               I915_GEM_DOMAIN_INSTRUCTION, 0,
 449                               0);
 450         } else {
 451             OUT_BCS_BATCH(batch, 0);
 452             OUT_BCS_BATCH(batch, 0);
 453         }
 454     }
 455
 456     /* the current decoding frame/field */
 457     va_pic = &pic_param->CurrPic;
 458     obj_surface = decode_state->render_object;
 459     assert(obj_surface->bo && obj_surface->private_data);
 460     gen6_avc_surface = obj_surface->private_data;
 461
 462     OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_top,
 463                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 464                   0);
 465
 466     if (gen6_avc_surface->dmv_bottom_flag == 1)
 467         OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_bottom,
 468                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 469                       0);
 470     else
 471         OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_top,
 472                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 473                       0);
 474
 475     /* POC List */
 476     for (i = 0; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface); i++) {
 477         obj_surface = gen6_mfd_context->reference_surface[i].obj_surface;
 478
 479         if (obj_surface) {
 480             const VAPictureH264 * const va_pic = avc_find_picture(
 481                 obj_surface->base.id, pic_param->ReferenceFrames,
 482                 ARRAY_ELEMS(pic_param->ReferenceFrames));
 483
 484             assert(va_pic != NULL);
 485             OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
 486             OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
 487         } else {
 488             OUT_BCS_BATCH(batch, 0);
 489             OUT_BCS_BATCH(batch, 0);
 490         }
 491     }
 492
 493     va_pic = &pic_param->CurrPic;
 494     OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
 495     OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
 496
 497     ADVANCE_BCS_BATCH(batch);
 498 }
 499
 500 static void
 501 gen6_mfd_avc_slice_state(VADriverContextP ctx,
 502                          VAPictureParameterBufferH264 *pic_param,
 503                          VASliceParameterBufferH264 *slice_param,
 504                          VASliceParameterBufferH264 *next_slice_param,
 505                          struct gen6_mfd_context *gen6_mfd_context)
 506 {
 507     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 508     int width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
 509     int height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1;
 510     int slice_hor_pos, slice_ver_pos, next_slice_hor_pos, next_slice_ver_pos;
 511     int num_ref_idx_l0, num_ref_idx_l1;
 512     int mbaff_picture = (!pic_param->pic_fields.bits.field_pic_flag &&
 513                          pic_param->seq_fields.bits.mb_adaptive_frame_field_flag);
 514     int weighted_pred_idc = 0;
 515     int first_mb_in_slice = 0, first_mb_in_next_slice = 0;
 516     unsigned int chroma_log2_weight_denom, luma_log2_weight_denom;
 517     int slice_type;
 518
 519     if (slice_param->slice_type == SLICE_TYPE_I ||
 520         slice_param->slice_type == SLICE_TYPE_SI) {
 521         slice_type = SLICE_TYPE_I;
 522     } else if (slice_param->slice_type == SLICE_TYPE_P ||
 523                slice_param->slice_type == SLICE_TYPE_SP) {
 524         slice_type = SLICE_TYPE_P;
 525     } else {
 526         assert(slice_param->slice_type == SLICE_TYPE_B);
 527         slice_type = SLICE_TYPE_B;
 528     }
 529
 530     luma_log2_weight_denom   = slice_param->luma_log2_weight_denom;
 531     chroma_log2_weight_denom = slice_param->chroma_log2_weight_denom;
 532
 533     if (slice_type == SLICE_TYPE_I) {
 534         assert(slice_param->num_ref_idx_l0_active_minus1 == 0);
 535         assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
 536         num_ref_idx_l0 = 0;
 537         num_ref_idx_l1 = 0;
 538     } else if (slice_type == SLICE_TYPE_P) {
 539         assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
 540         num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
 541         num_ref_idx_l1 = 0;
 542         weighted_pred_idc = (pic_param->pic_fields.bits.weighted_pred_flag == 1);
 543     } else {
 544         num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
 545         num_ref_idx_l1 = slice_param->num_ref_idx_l1_active_minus1 + 1;
 546         weighted_pred_idc = pic_param->pic_fields.bits.weighted_bipred_idc;
 547
 548         if (weighted_pred_idc == 2) {
 549             /* 8.4.3 - Derivation process for prediction weights (8-279) */
 550             luma_log2_weight_denom   = 5;
 551             chroma_log2_weight_denom = 5;
 552         }
 553     }
 554
 555     first_mb_in_slice = slice_param->first_mb_in_slice;
 556     slice_hor_pos = first_mb_in_slice % width_in_mbs;
 557     slice_ver_pos = first_mb_in_slice / width_in_mbs;
 558
 559     if (mbaff_picture)
 560         slice_ver_pos = slice_ver_pos << 1;
 561
 562     if (next_slice_param) {
 563         first_mb_in_next_slice = next_slice_param->first_mb_in_slice;
 564         next_slice_hor_pos = first_mb_in_next_slice % width_in_mbs;
 565         next_slice_ver_pos = first_mb_in_next_slice / width_in_mbs;
 566
 567         if (mbaff_picture)
 568             next_slice_ver_pos = next_slice_ver_pos << 1;
 569     } else {
 570         next_slice_hor_pos = 0;
 571         next_slice_ver_pos = height_in_mbs;
 572     }
 573
 574     BEGIN_BCS_BATCH(batch, 11); /* FIXME: is it 10??? */
 575     OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2));
 576     OUT_BCS_BATCH(batch, slice_type);
 577     OUT_BCS_BATCH(batch,
 578                   (num_ref_idx_l1 << 24) |
 579                   (num_ref_idx_l0 << 16) |
 580                   (chroma_log2_weight_denom << 8) |
 581                   (luma_log2_weight_denom << 0));
 582     OUT_BCS_BATCH(batch,
 583                   (weighted_pred_idc << 30) |
 584                   (slice_param->direct_spatial_mv_pred_flag << 29) |
 585                   (slice_param->disable_deblocking_filter_idc << 27) |
 586                   (slice_param->cabac_init_idc << 24) |
 587                   ((pic_param->pic_init_qp_minus26 + 26 + slice_param->slice_qp_delta) << 16) |
 588                   ((slice_param->slice_beta_offset_div2 & 0xf) << 8) |
 589                   ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0));
 590     OUT_BCS_BATCH(batch,
 591                   (slice_ver_pos << 24) |
 592                   (slice_hor_pos << 16) |
 593                   (first_mb_in_slice << 0));
 594     OUT_BCS_BATCH(batch,
 595                   (next_slice_ver_pos << 16) |
 596                   (next_slice_hor_pos << 0));
 597     OUT_BCS_BATCH(batch,
 598                   (next_slice_param == NULL) << 19); /* last slice flag */
 599     OUT_BCS_BATCH(batch, 0);
 600     OUT_BCS_BATCH(batch, 0);
 601     OUT_BCS_BATCH(batch, 0);
 602     OUT_BCS_BATCH(batch, 0);
 603     ADVANCE_BCS_BATCH(batch);
 604 }
 605
 606 static inline void
 607 gen6_mfd_avc_ref_idx_state(VADriverContextP ctx,
 608                            VAPictureParameterBufferH264 *pic_param,
 609                            VASliceParameterBufferH264 *slice_param,
 610                            struct gen6_mfd_context *gen6_mfd_context)
 611 {
 612     gen6_send_avc_ref_idx_state(
 613         gen6_mfd_context->base.batch,
 614         slice_param,
 615         gen6_mfd_context->reference_surface
 616     );
 617 }
 618
 619 static void
 620 gen6_mfd_avc_weightoffset_state(VADriverContextP ctx,
 621                                 VAPictureParameterBufferH264 *pic_param,
 622                                 VASliceParameterBufferH264 *slice_param,
 623                                 struct gen6_mfd_context *gen6_mfd_context)
 624 {
 625     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 626     int i, j, num_weight_offset_table = 0;
 627     short weightoffsets[32 * 6];
 628
 629     if ((slice_param->slice_type == SLICE_TYPE_P ||
 630          slice_param->slice_type == SLICE_TYPE_SP) &&
 631         (pic_param->pic_fields.bits.weighted_pred_flag == 1)) {
 632         num_weight_offset_table = 1;
 633     }
 634
 635     if ((slice_param->slice_type == SLICE_TYPE_B) &&
 636         (pic_param->pic_fields.bits.weighted_bipred_idc == 1)) {
 637         num_weight_offset_table = 2;
 638     }
 639
 640     for (i = 0; i < num_weight_offset_table; i++) {
 641         BEGIN_BCS_BATCH(batch, 98);
 642         OUT_BCS_BATCH(batch, MFX_AVC_WEIGHTOFFSET_STATE | (98 - 2));
 643         OUT_BCS_BATCH(batch, i);
 644
 645         if (i == 0) {
 646             for (j = 0; j < 32; j++) {
 647                 weightoffsets[j * 6 + 0] = slice_param->luma_weight_l0[j];
 648                 weightoffsets[j * 6 + 1] = slice_param->luma_offset_l0[j];
 649                 weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l0[j][0];
 650                 weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l0[j][0];
 651                 weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l0[j][1];
 652                 weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l0[j][1];
 653             }
 654         } else {
 655             for (j = 0; j < 32; j++) {
 656                 weightoffsets[j * 6 + 0] = slice_param->luma_weight_l1[j];
 657                 weightoffsets[j * 6 + 1] = slice_param->luma_offset_l1[j];
 658                 weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l1[j][0];
 659                 weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l1[j][0];
 660                 weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l1[j][1];
 661                 weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l1[j][1];
 662             }
 663         }
 664
 665         intel_batchbuffer_data(batch, weightoffsets, sizeof(weightoffsets));
 666         ADVANCE_BCS_BATCH(batch);
 667     }
 668 }
 669
 670 static void
 671 gen6_mfd_avc_bsd_object(VADriverContextP ctx,
 672                         VAPictureParameterBufferH264 *pic_param,
 673                         VASliceParameterBufferH264 *slice_param,
 674                         dri_bo *slice_data_bo,
 675                         struct gen6_mfd_context *gen6_mfd_context)
 676 {
 677     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 678     unsigned int slice_data_bit_offset;
 679
 680     slice_data_bit_offset = avc_get_first_mb_bit_offset(
 681         slice_data_bo,
 682         slice_param,
 683         pic_param->pic_fields.bits.entropy_coding_mode_flag
 684     );
 685
 686     BEGIN_BCS_BATCH(batch, 6);
 687     OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2));
 688     OUT_BCS_BATCH(batch,
 689                   (slice_param->slice_data_size - slice_param->slice_data_offset));
 690     OUT_BCS_BATCH(batch, slice_param->slice_data_offset);
 691     OUT_BCS_BATCH(batch,
 692                   (0 << 31) |
 693                   (0 << 14) |
 694                   (0 << 12) |
 695                   (0 << 10) |
 696                   (0 << 8));
 697     OUT_BCS_BATCH(batch,
 698                   ((slice_data_bit_offset >> 3) << 16) |
 699                   (1 << 7)  |
 700                   (1 << 6)  |
 701                   ((0x7 - (slice_data_bit_offset & 0x7)) << 0));
 702     OUT_BCS_BATCH(batch, 0);
 703     ADVANCE_BCS_BATCH(batch);
 704 }
 705
 706 static void
 707 gen6_mfd_avc_phantom_slice_first(VADriverContextP ctx,
 708                                  VAPictureParameterBufferH264 *pic_param,
 709                                  VASliceParameterBufferH264 *next_slice_param,
 710                                  struct gen6_mfd_context *gen6_mfd_context)
 711 {
 712     gen6_mfd_avc_phantom_slice(ctx, pic_param, next_slice_param, gen6_mfd_context->base.batch);
 713 }
 714
 715 static void
 716 gen6_mfd_avc_phantom_slice_last(VADriverContextP ctx,
 717                                 VAPictureParameterBufferH264 *pic_param,
 718                                 struct gen6_mfd_context *gen6_mfd_context)
 719 {
 720     gen6_mfd_avc_phantom_slice(ctx, pic_param, NULL, gen6_mfd_context->base.batch);
 721 }
 722
 723 static void
 724 gen6_mfd_avc_decode_init(VADriverContextP ctx,
 725                          struct decode_state *decode_state,
 726                          struct gen6_mfd_context *gen6_mfd_context)
 727 {
 728     VAPictureParameterBufferH264 *pic_param;
 729     VASliceParameterBufferH264 *slice_param;
 730     struct i965_driver_data *i965 = i965_driver_data(ctx);
 731     struct object_surface *obj_surface;
 732     dri_bo *bo;
 733     int i, j, enable_avc_ildb = 0;
 734     int width_in_mbs;
 735
 736     for (j = 0; j < decode_state->num_slice_params && enable_avc_ildb == 0; j++) {
 737         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
 738         slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
 739
 740         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
 741             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
 742             assert((slice_param->slice_type == SLICE_TYPE_I) ||
 743                    (slice_param->slice_type == SLICE_TYPE_SI) ||
 744                    (slice_param->slice_type == SLICE_TYPE_P) ||
 745                    (slice_param->slice_type == SLICE_TYPE_SP) ||
 746                    (slice_param->slice_type == SLICE_TYPE_B));
 747
 748             if (slice_param->disable_deblocking_filter_idc != 1) {
 749                 enable_avc_ildb = 1;
 750                 break;
 751             }
 752
 753             slice_param++;
 754         }
 755     }
 756
 757     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 758     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 759     intel_update_avc_frame_store_index(ctx, decode_state, pic_param,
 760         gen6_mfd_context->reference_surface, &gen6_mfd_context->fs_ctx);
 761     width_in_mbs = ((pic_param->picture_width_in_mbs_minus1 + 1) & 0xff);
 762
 763     /* Current decoded picture */
 764     obj_surface = decode_state->render_object;
 765     if (pic_param->pic_fields.bits.reference_pic_flag)
 766         obj_surface->flags |= SURFACE_REFERENCED;
 767     else
 768         obj_surface->flags &= ~SURFACE_REFERENCED;
 769
 770     avc_ensure_surface_bo(ctx, decode_state, obj_surface, pic_param);
 771     gen6_mfd_init_avc_surface(ctx, pic_param, obj_surface);
 772
 773     dri_bo_unreference(gen6_mfd_context->post_deblocking_output.bo);
 774     gen6_mfd_context->post_deblocking_output.bo = obj_surface->bo;
 775     dri_bo_reference(gen6_mfd_context->post_deblocking_output.bo);
 776     gen6_mfd_context->post_deblocking_output.valid = enable_avc_ildb;
 777
 778     dri_bo_unreference(gen6_mfd_context->pre_deblocking_output.bo);
 779     gen6_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
 780     dri_bo_reference(gen6_mfd_context->pre_deblocking_output.bo);
 781     gen6_mfd_context->pre_deblocking_output.valid = !enable_avc_ildb;
 782
 783     dri_bo_unreference(gen6_mfd_context->intra_row_store_scratch_buffer.bo);
 784     bo = dri_bo_alloc(i965->intel.bufmgr,
 785                       "intra row store",
 786                       width_in_mbs * 64,
 787                       0x1000);
 788     assert(bo);
 789     gen6_mfd_context->intra_row_store_scratch_buffer.bo = bo;
 790     gen6_mfd_context->intra_row_store_scratch_buffer.valid = 1;
 791
 792     dri_bo_unreference(gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
 793     bo = dri_bo_alloc(i965->intel.bufmgr,
 794                       "deblocking filter row store",
 795                       width_in_mbs * 64 * 4,
 796                       0x1000);
 797     assert(bo);
 798     gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
 799     gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1;
 800
 801     dri_bo_unreference(gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
 802     bo = dri_bo_alloc(i965->intel.bufmgr,
 803                       "bsd mpc row store",
 804                       width_in_mbs * 96,
 805                       0x1000);
 806     assert(bo);
 807     gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
 808     gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
 809
 810     dri_bo_unreference(gen6_mfd_context->mpr_row_store_scratch_buffer.bo);
 811     bo = dri_bo_alloc(i965->intel.bufmgr,
 812                       "mpr row store",
 813                       width_in_mbs * 64,
 814                       0x1000);
 815     assert(bo);
 816     gen6_mfd_context->mpr_row_store_scratch_buffer.bo = bo;
 817     gen6_mfd_context->mpr_row_store_scratch_buffer.valid = 1;
 818
 819     gen6_mfd_context->bitplane_read_buffer.valid = 0;
 820 }
 821
 822 static void
 823 gen6_mfd_avc_decode_picture(VADriverContextP ctx,
 824                             struct decode_state *decode_state,
 825                             struct gen6_mfd_context *gen6_mfd_context)
 826 {
 827     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 828     VAPictureParameterBufferH264 *pic_param;
 829     VASliceParameterBufferH264 *slice_param, *next_slice_param, *next_slice_group_param;
 830     dri_bo *slice_data_bo;
 831     int i, j;
 832
 833     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 834     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 835     gen6_mfd_avc_decode_init(ctx, decode_state, gen6_mfd_context);
 836
 837     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
 838     intel_batchbuffer_emit_mi_flush(batch);
 839     gen6_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_AVC, gen6_mfd_context);
 840     gen6_mfd_surface_state(ctx, decode_state, MFX_FORMAT_AVC, gen6_mfd_context);
 841     gen6_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen6_mfd_context);
 842     gen6_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen6_mfd_context);
 843     gen6_mfd_avc_img_state(ctx, decode_state, gen6_mfd_context);
 844     gen6_mfd_avc_qm_state(ctx, decode_state, gen6_mfd_context);
 845
 846     for (j = 0; j < decode_state->num_slice_params; j++) {
 847         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
 848         slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
 849         slice_data_bo = decode_state->slice_datas[j]->bo;
 850         gen6_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_AVC, gen6_mfd_context);
 851
 852         if (j == decode_state->num_slice_params - 1)
 853             next_slice_group_param = NULL;
 854         else
 855             next_slice_group_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j + 1]->buffer;
 856
 857             if (j == 0 &&
 858                 slice_param->first_mb_in_slice)
 859                 gen6_mfd_avc_phantom_slice_first(ctx, pic_param, slice_param, gen6_mfd_context);
 860
 861         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
 862             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
 863             assert((slice_param->slice_type == SLICE_TYPE_I) ||
 864                    (slice_param->slice_type == SLICE_TYPE_SI) ||
 865                    (slice_param->slice_type == SLICE_TYPE_P) ||
 866                    (slice_param->slice_type == SLICE_TYPE_SP) ||
 867                    (slice_param->slice_type == SLICE_TYPE_B));
 868
 869             if (i < decode_state->slice_params[j]->num_elements - 1)
 870                 next_slice_param = slice_param + 1;
 871             else
 872                 next_slice_param = next_slice_group_param;
 873
 874             gen6_mfd_avc_directmode_state(ctx, decode_state, pic_param, slice_param, gen6_mfd_context);
 875             gen6_mfd_avc_slice_state(ctx, pic_param, slice_param, next_slice_param, gen6_mfd_context);
 876             gen6_mfd_avc_ref_idx_state(ctx, pic_param, slice_param, gen6_mfd_context);
 877             gen6_mfd_avc_weightoffset_state(ctx, pic_param, slice_param, gen6_mfd_context);
 878             gen6_mfd_avc_bsd_object(ctx, pic_param, slice_param, slice_data_bo, gen6_mfd_context);
 879             slice_param++;
 880         }
 881     }
 882
 883     gen6_mfd_avc_phantom_slice_last(ctx, pic_param, gen6_mfd_context);
 884     intel_batchbuffer_end_atomic(batch);
 885     intel_batchbuffer_flush(batch);
 886 }
 887
 888 static void
 889 gen6_mfd_mpeg2_decode_init(VADriverContextP ctx,
 890                            struct decode_state *decode_state,
 891                            struct gen6_mfd_context *gen6_mfd_context)
 892 {
 893     VAPictureParameterBufferMPEG2 *pic_param;
 894     struct i965_driver_data *i965 = i965_driver_data(ctx);
 895     struct object_surface *obj_surface;
 896     dri_bo *bo;
 897     unsigned int width_in_mbs;
 898
 899     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 900     pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
 901     width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16;
 902
 903     mpeg2_set_reference_surfaces(
 904         ctx,
 905         gen6_mfd_context->reference_surface,
 906         decode_state,
 907         pic_param
 908     );
 909
 910     /* Current decoded picture */
 911     obj_surface = decode_state->render_object;
 912     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
 913
 914     dri_bo_unreference(gen6_mfd_context->pre_deblocking_output.bo);
 915     gen6_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
 916     dri_bo_reference(gen6_mfd_context->pre_deblocking_output.bo);
 917     gen6_mfd_context->pre_deblocking_output.valid = 1;
 918
 919     dri_bo_unreference(gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
 920     bo = dri_bo_alloc(i965->intel.bufmgr,
 921                       "bsd mpc row store",
 922                       width_in_mbs * 96,
 923                       0x1000);
 924     assert(bo);
 925     gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
 926     gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
 927
 928     gen6_mfd_context->post_deblocking_output.valid = 0;
 929     gen6_mfd_context->intra_row_store_scratch_buffer.valid = 0;
 930     gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 0;
 931     gen6_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
 932     gen6_mfd_context->bitplane_read_buffer.valid = 0;
 933 }
 934
 935 static void
 936 gen6_mfd_mpeg2_pic_state(VADriverContextP ctx,
 937                          struct decode_state *decode_state,
 938                          struct gen6_mfd_context *gen6_mfd_context)
 939 {
 940     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 941     VAPictureParameterBufferMPEG2 *pic_param;
 942     unsigned int tff, pic_structure;
 943
 944     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 945     pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
 946
 947     pic_structure = pic_param->picture_coding_extension.bits.picture_structure;
 948     if (pic_structure == MPEG_FRAME)
 949         tff = pic_param->picture_coding_extension.bits.top_field_first;
 950     else
 951         tff = !(pic_param->picture_coding_extension.bits.is_first_field ^
 952                 (pic_structure & MPEG_TOP_FIELD));
 953
 954     BEGIN_BCS_BATCH(batch, 4);
 955     OUT_BCS_BATCH(batch, MFX_MPEG2_PIC_STATE | (4 - 2));
 956     OUT_BCS_BATCH(batch,
 957                   (pic_param->f_code & 0xf) << 28 | /* f_code[1][1] */
 958                   ((pic_param->f_code >> 4) & 0xf) << 24 | /* f_code[1][0] */
 959                   ((pic_param->f_code >> 8) & 0xf) << 20 | /* f_code[0][1] */
 960                   ((pic_param->f_code >> 12) & 0xf) << 16 | /* f_code[0][0] */
 961                   pic_param->picture_coding_extension.bits.intra_dc_precision << 14 |
 962                   pic_param->picture_coding_extension.bits.picture_structure << 12 |
 963                   tff << 11 |
 964                   pic_param->picture_coding_extension.bits.frame_pred_frame_dct << 10 |
 965                   pic_param->picture_coding_extension.bits.concealment_motion_vectors << 9 |
 966                   pic_param->picture_coding_extension.bits.q_scale_type << 8 |
 967                   pic_param->picture_coding_extension.bits.intra_vlc_format << 7 |
 968                   pic_param->picture_coding_extension.bits.alternate_scan << 6);
 969     OUT_BCS_BATCH(batch,
 970                   pic_param->picture_coding_type << 9);
 971     OUT_BCS_BATCH(batch,
 972                   (ALIGN(pic_param->vertical_size, 16) / 16) << 16 |
 973                   (ALIGN(pic_param->horizontal_size, 16) / 16));
 974     ADVANCE_BCS_BATCH(batch);
 975 }
 976
 977 static void
 978 gen6_mfd_mpeg2_qm_state(VADriverContextP ctx,
 979                         struct decode_state *decode_state,
 980                         struct gen6_mfd_context *gen6_mfd_context)
 981 {
 982     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 983     VAIQMatrixBufferMPEG2 * const gen_iq_matrix = &gen6_mfd_context->iq_matrix.mpeg2;
 984     int i, j;
 985
 986     /* Update internal QM state */
 987     if (decode_state->iq_matrix && decode_state->iq_matrix->buffer) {
 988         VAIQMatrixBufferMPEG2 * const iq_matrix =
 989             (VAIQMatrixBufferMPEG2 *)decode_state->iq_matrix->buffer;
 990
 991         gen_iq_matrix->load_intra_quantiser_matrix =
 992             iq_matrix->load_intra_quantiser_matrix;
 993         if (iq_matrix->load_intra_quantiser_matrix) {
 994             for (j = 0; j < 64; j++)
 995                 gen_iq_matrix->intra_quantiser_matrix[zigzag_direct[j]] =
 996                     iq_matrix->intra_quantiser_matrix[j];
 997         }
 998
 999         gen_iq_matrix->load_non_intra_quantiser_matrix =
1000             iq_matrix->load_non_intra_quantiser_matrix;
1001         if (iq_matrix->load_non_intra_quantiser_matrix) {
1002             for (j = 0; j < 64; j++)
1003                 gen_iq_matrix->non_intra_quantiser_matrix[zigzag_direct[j]] =
1004                     iq_matrix->non_intra_quantiser_matrix[j];
1005         }
1006     }
1007
1008     /* Commit QM state to HW */
1009     for (i = 0; i < 2; i++) {
1010         unsigned char *qm = NULL;
1011
1012         if (i == 0) {
1013             if (gen_iq_matrix->load_intra_quantiser_matrix)
1014                 qm = gen_iq_matrix->intra_quantiser_matrix;
1015         } else {
1016             if (gen_iq_matrix->load_non_intra_quantiser_matrix)
1017                 qm = gen_iq_matrix->non_intra_quantiser_matrix;
1018         }
1019
1020         if (!qm)
1021             continue;
1022
1023         BEGIN_BCS_BATCH(batch, 18);
1024         OUT_BCS_BATCH(batch, MFX_MPEG2_QM_STATE | (18 - 2));
1025         OUT_BCS_BATCH(batch, i);
1026         intel_batchbuffer_data(batch, qm, 64);
1027         ADVANCE_BCS_BATCH(batch);
1028     }
1029 }
1030
1031 static void
1032 gen6_mfd_mpeg2_bsd_object(VADriverContextP ctx,
1033                           VAPictureParameterBufferMPEG2 *pic_param,
1034                           VASliceParameterBufferMPEG2 *slice_param,
1035                           VASliceParameterBufferMPEG2 *next_slice_param,
1036                           struct gen6_mfd_context *gen6_mfd_context)
1037 {
1038     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1039     unsigned int width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16;
1040     int mb_count, vpos0, hpos0, vpos1, hpos1, is_field_pic_wa, is_field_pic = 0;
1041
1042     if (pic_param->picture_coding_extension.bits.picture_structure == MPEG_TOP_FIELD ||
1043         pic_param->picture_coding_extension.bits.picture_structure == MPEG_BOTTOM_FIELD)
1044         is_field_pic = 1;
1045     is_field_pic_wa = is_field_pic &&
1046         gen6_mfd_context->wa_mpeg2_slice_vertical_position > 0;
1047
1048     vpos0 = slice_param->slice_vertical_position / (1 + is_field_pic_wa);
1049     hpos0 = slice_param->slice_horizontal_position;
1050
1051     if (next_slice_param == NULL) {
1052         vpos1 = ALIGN(pic_param->vertical_size, 16) / 16 / (1 + is_field_pic);
1053         hpos1 = 0;
1054     } else {
1055         vpos1 = next_slice_param->slice_vertical_position / (1 + is_field_pic_wa);
1056         hpos1 = next_slice_param->slice_horizontal_position;
1057     }
1058
1059     mb_count = (vpos1 * width_in_mbs + hpos1) - (vpos0 * width_in_mbs + hpos0);
1060
1061     BEGIN_BCS_BATCH(batch, 5);
1062     OUT_BCS_BATCH(batch, MFD_MPEG2_BSD_OBJECT | (5 - 2));
1063     OUT_BCS_BATCH(batch,
1064                   slice_param->slice_data_size - (slice_param->macroblock_offset >> 3));
1065     OUT_BCS_BATCH(batch,
1066                   slice_param->slice_data_offset + (slice_param->macroblock_offset >> 3));
1067     OUT_BCS_BATCH(batch,
1068                   hpos0 << 24 |
1069                   vpos0 << 16 |
1070                   mb_count << 8 |
1071                   (next_slice_param == NULL) << 5 |
1072                   (next_slice_param == NULL) << 3 |
1073                   (slice_param->macroblock_offset & 0x7));
1074     OUT_BCS_BATCH(batch,
1075                   slice_param->quantiser_scale_code << 24);
1076     ADVANCE_BCS_BATCH(batch);
1077 }
1078
1079 static void
1080 gen6_mfd_mpeg2_decode_picture(VADriverContextP ctx,
1081                               struct decode_state *decode_state,
1082                               struct gen6_mfd_context *gen6_mfd_context)
1083 {
1084     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1085     VAPictureParameterBufferMPEG2 *pic_param;
1086     VASliceParameterBufferMPEG2 *slice_param, *next_slice_param;
1087     dri_bo *slice_data_bo;
1088     int group_idx = 0, pre_group_idx = -1, element_idx = 0;
1089
1090     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1091     pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
1092
1093     gen6_mfd_mpeg2_decode_init(ctx, decode_state, gen6_mfd_context);
1094     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
1095     intel_batchbuffer_emit_mi_flush(batch);
1096     gen6_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_MPEG2, gen6_mfd_context);
1097     gen6_mfd_surface_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen6_mfd_context);
1098     gen6_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen6_mfd_context);
1099     gen6_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen6_mfd_context);
1100     gen6_mfd_mpeg2_pic_state(ctx, decode_state, gen6_mfd_context);
1101     gen6_mfd_mpeg2_qm_state(ctx, decode_state, gen6_mfd_context);
1102
1103     if (gen6_mfd_context->wa_mpeg2_slice_vertical_position < 0)
1104         gen6_mfd_context->wa_mpeg2_slice_vertical_position =
1105             mpeg2_wa_slice_vertical_position(decode_state, pic_param);
1106
1107     slice_param = (VASliceParameterBufferMPEG2 *)decode_state->slice_params[group_idx]->buffer;
1108
1109     for (; slice_param;) {
1110         if (pre_group_idx != group_idx) {
1111             slice_data_bo = decode_state->slice_datas[group_idx]->bo;
1112             gen6_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_MPEG2, gen6_mfd_context);
1113             pre_group_idx = group_idx;
1114         }
1115
1116         next_slice_param = intel_mpeg2_find_next_slice(decode_state, pic_param, slice_param, &group_idx, &element_idx);
1117         gen6_mfd_mpeg2_bsd_object(ctx, pic_param, slice_param, next_slice_param, gen6_mfd_context);
1118         slice_param = next_slice_param;
1119     }
1120
1121     intel_batchbuffer_end_atomic(batch);
1122     intel_batchbuffer_flush(batch);
1123 }
1124
1125 static const int va_to_gen6_vc1_pic_type[5] = {
1126     GEN6_VC1_I_PICTURE,
1127     GEN6_VC1_P_PICTURE,
1128     GEN6_VC1_B_PICTURE,
1129     GEN6_VC1_BI_PICTURE,
1130     GEN6_VC1_P_PICTURE,
1131 };
1132
1133 static const int va_to_gen6_vc1_mv[4] = {
1134     1, /* 1-MV */
1135     2, /* 1-MV half-pel */
1136     3, /* 1-MV half-pef bilinear */
1137     0, /* Mixed MV */
1138 };
1139
1140 static const int b_picture_scale_factor[21] = {
1141     128, 85,  170, 64,  192,
1142     51,  102, 153, 204, 43,
1143     215, 37,  74,  111, 148,
1144     185, 222, 32,  96,  160,
1145     224,
1146 };
1147
1148 static const int va_to_gen6_vc1_condover[3] = {
1149     0,
1150     2,
1151     3
1152 };
1153
1154 static const int va_to_gen6_vc1_profile[4] = {
1155     GEN6_VC1_SIMPLE_PROFILE,
1156     GEN6_VC1_MAIN_PROFILE,
1157     GEN6_VC1_RESERVED_PROFILE,
1158     GEN6_VC1_ADVANCED_PROFILE
1159 };
1160
1161 static void
1162 gen6_mfd_free_vc1_surface(void **data)
1163 {
1164     struct gen6_vc1_surface *gen6_vc1_surface = *data;
1165
1166     if (!gen6_vc1_surface)
1167         return;
1168
1169     dri_bo_unreference(gen6_vc1_surface->dmv);
1170     free(gen6_vc1_surface);
1171     *data = NULL;
1172 }
1173
1174 static void
1175 gen6_mfd_init_vc1_surface(VADriverContextP ctx,
1176                           VAPictureParameterBufferVC1 *pic_param,
1177                           struct object_surface *obj_surface)
1178 {
1179     struct i965_driver_data *i965 = i965_driver_data(ctx);
1180     struct gen6_vc1_surface *gen6_vc1_surface = obj_surface->private_data;
1181     int height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16;
1182
1183     obj_surface->free_private_data = gen6_mfd_free_vc1_surface;
1184
1185     if (!gen6_vc1_surface) {
1186         gen6_vc1_surface = calloc(sizeof(struct gen6_vc1_surface), 1);
1187
1188         if (!gen6_vc1_surface)
1189             return;
1190
1191         assert((obj_surface->size & 0x3f) == 0);
1192         obj_surface->private_data = gen6_vc1_surface;
1193     }
1194
1195     gen6_vc1_surface->picture_type = pic_param->picture_fields.bits.picture_type;
1196
1197     if (gen6_vc1_surface->dmv == NULL) {
1198         gen6_vc1_surface->dmv = dri_bo_alloc(i965->intel.bufmgr,
1199                                              "direct mv w/r buffer",
1200                                              128 * height_in_mbs * 64,  /* scalable with frame height */
1201                                              0x1000);
1202     }
1203 }
1204
1205 static void
1206 gen6_mfd_vc1_decode_init(VADriverContextP ctx,
1207                          struct decode_state *decode_state,
1208                          struct gen6_mfd_context *gen6_mfd_context)
1209 {
1210     VAPictureParameterBufferVC1 *pic_param;
1211     struct i965_driver_data *i965 = i965_driver_data(ctx);
1212     struct object_surface *obj_surface;
1213     dri_bo *bo;
1214     int width_in_mbs;
1215     int picture_type;
1216
1217     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1218     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1219     width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1220     picture_type = pic_param->picture_fields.bits.picture_type;
1221
1222     intel_update_vc1_frame_store_index(ctx,
1223                                        decode_state,
1224                                        pic_param,
1225                                        gen6_mfd_context->reference_surface);
1226
1227     /* Current decoded picture */
1228     obj_surface = decode_state->render_object;
1229     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
1230     gen6_mfd_init_vc1_surface(ctx, pic_param, obj_surface);
1231
1232     dri_bo_unreference(gen6_mfd_context->post_deblocking_output.bo);
1233     gen6_mfd_context->post_deblocking_output.bo = obj_surface->bo;
1234     dri_bo_reference(gen6_mfd_context->post_deblocking_output.bo);
1235     gen6_mfd_context->post_deblocking_output.valid = pic_param->entrypoint_fields.bits.loopfilter;
1236
1237     dri_bo_unreference(gen6_mfd_context->pre_deblocking_output.bo);
1238     gen6_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
1239     dri_bo_reference(gen6_mfd_context->pre_deblocking_output.bo);
1240     gen6_mfd_context->pre_deblocking_output.valid = !pic_param->entrypoint_fields.bits.loopfilter;
1241
1242     dri_bo_unreference(gen6_mfd_context->intra_row_store_scratch_buffer.bo);
1243     bo = dri_bo_alloc(i965->intel.bufmgr,
1244                       "intra row store",
1245                       width_in_mbs * 64,
1246                       0x1000);
1247     assert(bo);
1248     gen6_mfd_context->intra_row_store_scratch_buffer.bo = bo;
1249     gen6_mfd_context->intra_row_store_scratch_buffer.valid = 1;
1250
1251     dri_bo_unreference(gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
1252     bo = dri_bo_alloc(i965->intel.bufmgr,
1253                       "deblocking filter row store",
1254                       width_in_mbs * 7 * 64,
1255                       0x1000);
1256     assert(bo);
1257     gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
1258     gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1;
1259
1260     dri_bo_unreference(gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
1261     bo = dri_bo_alloc(i965->intel.bufmgr,
1262                       "bsd mpc row store",
1263                       width_in_mbs * 96,
1264                       0x1000);
1265     assert(bo);
1266     gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
1267     gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
1268
1269     gen6_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
1270
1271     gen6_mfd_context->bitplane_read_buffer.valid = !!pic_param->bitplane_present.value;
1272     dri_bo_unreference(gen6_mfd_context->bitplane_read_buffer.bo);
1273
1274     if (gen6_mfd_context->bitplane_read_buffer.valid) {
1275         int width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1276         int height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16;
1277         int bitplane_width = ALIGN(width_in_mbs, 2) / 2;
1278         int src_w, src_h;
1279         uint8_t *src = NULL, *dst = NULL;
1280
1281         assert(decode_state->bit_plane->buffer);
1282         src = decode_state->bit_plane->buffer;
1283
1284         bo = dri_bo_alloc(i965->intel.bufmgr,
1285                           "VC-1 Bitplane",
1286                           bitplane_width * height_in_mbs,
1287                           0x1000);
1288         assert(bo);
1289         gen6_mfd_context->bitplane_read_buffer.bo = bo;
1290
1291         dri_bo_map(bo, True);
1292         assert(bo->virtual);
1293         dst = bo->virtual;
1294
1295         for (src_h = 0; src_h < height_in_mbs; src_h++) {
1296             for(src_w = 0; src_w < width_in_mbs; src_w++) {
1297                 int src_index, dst_index;
1298                 int src_shift;
1299                 uint8_t src_value;
1300
1301                 src_index = (src_h * width_in_mbs + src_w) / 2;
1302                 src_shift = !((src_h * width_in_mbs + src_w) & 1) * 4;
1303                 src_value = ((src[src_index] >> src_shift) & 0xf);
1304
1305                 if (picture_type == GEN6_VC1_SKIPPED_PICTURE){
1306                     src_value |= 0x2;
1307                 }
1308
1309                 dst_index = src_w / 2;
1310                 dst[dst_index] = ((dst[dst_index] >> 4) | (src_value << 4));
1311             }
1312
1313             if (src_w & 1)
1314                 dst[src_w / 2] >>= 4;
1315
1316             dst += bitplane_width;
1317         }
1318
1319         dri_bo_unmap(bo);
1320     } else
1321         gen6_mfd_context->bitplane_read_buffer.bo = NULL;
1322 }
1323
1324 static void
1325 gen6_mfd_vc1_pic_state(VADriverContextP ctx,
1326                        struct decode_state *decode_state,
1327                        struct gen6_mfd_context *gen6_mfd_context)
1328 {
1329     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1330     VAPictureParameterBufferVC1 *pic_param;
1331     struct object_surface *obj_surface;
1332     int alt_pquant_config = 0, alt_pquant_edge_mask = 0, alt_pq;
1333     int dquant, dquantfrm, dqprofile, dqdbedge, dqsbedge, dqbilevel;
1334     int unified_mv_mode;
1335     int ref_field_pic_polarity = 0;
1336     int scale_factor = 0;
1337     int trans_ac_y = 0;
1338     int dmv_surface_valid = 0;
1339     int brfd = 0;
1340     int fcm = 0;
1341     int picture_type;
1342     int profile;
1343     int overlap;
1344
1345     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1346     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1347
1348     profile = va_to_gen6_vc1_profile[pic_param->sequence_fields.bits.profile];
1349     dquant = pic_param->pic_quantizer_fields.bits.dquant;
1350     dquantfrm = pic_param->pic_quantizer_fields.bits.dq_frame;
1351     dqprofile = pic_param->pic_quantizer_fields.bits.dq_profile;
1352     dqdbedge = pic_param->pic_quantizer_fields.bits.dq_db_edge;
1353     dqsbedge = pic_param->pic_quantizer_fields.bits.dq_sb_edge;
1354     dqbilevel = pic_param->pic_quantizer_fields.bits.dq_binary_level;
1355     alt_pq = pic_param->pic_quantizer_fields.bits.alt_pic_quantizer;
1356
1357     if (dquant == 0) {
1358         alt_pquant_config = 0;
1359         alt_pquant_edge_mask = 0;
1360     } else if (dquant == 2) {
1361         alt_pquant_config = 1;
1362         alt_pquant_edge_mask = 0xf;
1363     } else {
1364         assert(dquant == 1);
1365         if (dquantfrm == 0) {
1366             alt_pquant_config = 0;
1367             alt_pquant_edge_mask = 0;
1368             alt_pq = 0;
1369         } else {
1370             assert(dquantfrm == 1);
1371             alt_pquant_config = 1;
1372
1373             switch (dqprofile) {
1374             case 3:
1375                 if (dqbilevel == 0) {
1376                     alt_pquant_config = 2;
1377                     alt_pquant_edge_mask = 0;
1378                 } else {
1379                     assert(dqbilevel == 1);
1380                     alt_pquant_config = 3;
1381                     alt_pquant_edge_mask = 0;
1382                 }
1383                 break;
1384
1385             case 0:
1386                 alt_pquant_edge_mask = 0xf;
1387                 break;
1388
1389             case 1:
1390                 if (dqdbedge == 3)
1391                     alt_pquant_edge_mask = 0x9;
1392                 else
1393                     alt_pquant_edge_mask = (0x3 << dqdbedge);
1394
1395                 break;
1396
1397             case 2:
1398                 alt_pquant_edge_mask = (0x1 << dqsbedge);
1399                 break;
1400
1401             default:
1402                 assert(0);
1403             }
1404         }
1405     }
1406
1407     if (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation) {
1408         assert(pic_param->mv_fields.bits.mv_mode2 < 4);
1409         unified_mv_mode = va_to_gen6_vc1_mv[pic_param->mv_fields.bits.mv_mode2];
1410     } else {
1411         assert(pic_param->mv_fields.bits.mv_mode < 4);
1412         unified_mv_mode = va_to_gen6_vc1_mv[pic_param->mv_fields.bits.mv_mode];
1413     }
1414
1415     if (pic_param->sequence_fields.bits.interlace == 1 &&
1416         pic_param->picture_fields.bits.frame_coding_mode != 0) { /* frame-interlace or field-interlace */
1417         /* FIXME: calculate reference field picture polarity */
1418         assert(0);
1419         ref_field_pic_polarity = 0;
1420     }
1421
1422     if (pic_param->b_picture_fraction < 21)
1423         scale_factor = b_picture_scale_factor[pic_param->b_picture_fraction];
1424
1425     picture_type = va_to_gen6_vc1_pic_type[pic_param->picture_fields.bits.picture_type];
1426
1427     if (profile == GEN6_VC1_ADVANCED_PROFILE &&
1428         picture_type == GEN6_VC1_I_PICTURE)
1429         picture_type = GEN6_VC1_BI_PICTURE;
1430
1431     if (picture_type == GEN6_VC1_I_PICTURE || picture_type == GEN6_VC1_BI_PICTURE) /* I picture */
1432         trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx2;
1433     else {
1434         trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx1;
1435         /*
1436          * 8.3.6.2.1 Transform Type Selection
1437          * If variable-sized transform coding is not enabled,
1438          * then the 8x8 transform shall be used for all blocks.
1439          * it is also MFX_VC1_PIC_STATE requirement.
1440          */
1441         if (pic_param->transform_fields.bits.variable_sized_transform_flag == 0) {
1442             pic_param->transform_fields.bits.mb_level_transform_type_flag   = 1;
1443             pic_param->transform_fields.bits.frame_level_transform_type     = 0;
1444         }
1445     }
1446
1447     if (picture_type == GEN6_VC1_B_PICTURE) {
1448         struct gen6_vc1_surface *gen6_vc1_surface = NULL;
1449
1450         obj_surface = decode_state->reference_objects[1];
1451
1452         if (obj_surface)
1453             gen6_vc1_surface = obj_surface->private_data;
1454
1455         if (!gen6_vc1_surface ||
1456             (va_to_gen6_vc1_pic_type[gen6_vc1_surface->picture_type] == GEN6_VC1_I_PICTURE ||
1457              va_to_gen6_vc1_pic_type[gen6_vc1_surface->picture_type] == GEN6_VC1_BI_PICTURE))
1458             dmv_surface_valid = 0;
1459         else
1460             dmv_surface_valid = 1;
1461     }
1462
1463     assert(pic_param->picture_fields.bits.frame_coding_mode < 3);
1464
1465     if (pic_param->picture_fields.bits.frame_coding_mode < 2)
1466         fcm = pic_param->picture_fields.bits.frame_coding_mode;
1467     else {
1468         if (pic_param->picture_fields.bits.top_field_first)
1469             fcm = 2;
1470         else
1471             fcm = 3;
1472     }
1473
1474     if (pic_param->picture_fields.bits.picture_type == GEN6_VC1_B_PICTURE) { /* B picture */
1475         brfd = pic_param->reference_fields.bits.reference_distance;
1476         brfd = (scale_factor * brfd) >> 8;
1477         brfd = pic_param->reference_fields.bits.reference_distance - brfd - 1;
1478
1479         if (brfd < 0)
1480             brfd = 0;
1481     }
1482
1483     overlap = pic_param->sequence_fields.bits.overlap;
1484
1485     if (overlap) {
1486         overlap = 0;
1487         if (profile != GEN6_VC1_ADVANCED_PROFILE){
1488             if (pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9 &&
1489                 pic_param->picture_fields.bits.picture_type != GEN6_VC1_B_PICTURE) {
1490                 overlap = 1;
1491             }
1492         }else {
1493             if (pic_param->picture_fields.bits.picture_type == GEN6_VC1_P_PICTURE &&
1494                 pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9){
1495                 overlap = 1;
1496             }
1497             if (pic_param->picture_fields.bits.picture_type == GEN6_VC1_I_PICTURE ||
1498                 pic_param->picture_fields.bits.picture_type == GEN6_VC1_BI_PICTURE){
1499                 if (pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9){
1500                     overlap = 1;
1501                 } else if (va_to_gen6_vc1_condover[pic_param->conditional_overlap_flag] == 2 ||
1502                            va_to_gen6_vc1_condover[pic_param->conditional_overlap_flag] == 3) {
1503                     overlap = 1;
1504                 }
1505             }
1506         }
1507     }
1508
1509     assert(pic_param->conditional_overlap_flag < 3);
1510     assert(pic_param->mv_fields.bits.mv_table < 4); /* FIXME: interlace mode */
1511
1512     BEGIN_BCS_BATCH(batch, 6);
1513     OUT_BCS_BATCH(batch, MFX_VC1_PIC_STATE | (6 - 2));
1514     OUT_BCS_BATCH(batch,
1515                   (ALIGN(pic_param->coded_height, 16) / 16) << 16 |
1516                   (ALIGN(pic_param->coded_width, 16) / 16));
1517     OUT_BCS_BATCH(batch,
1518                   pic_param->sequence_fields.bits.syncmarker << 31 |
1519                   1 << 29 | /* concealment */
1520                   alt_pq << 24 |
1521                   pic_param->entrypoint_fields.bits.loopfilter << 23 |
1522                   overlap << 22 |
1523                   (pic_param->pic_quantizer_fields.bits.quantizer == 0) << 21 | /* implicit quantizer */
1524                   pic_param->pic_quantizer_fields.bits.pic_quantizer_scale << 16 |
1525                   alt_pquant_edge_mask << 12 |
1526                   alt_pquant_config << 10 |
1527                   pic_param->pic_quantizer_fields.bits.half_qp << 9 |
1528                   pic_param->pic_quantizer_fields.bits.pic_quantizer_type << 8 |
1529                   va_to_gen6_vc1_condover[pic_param->conditional_overlap_flag] << 6 |
1530                   !pic_param->picture_fields.bits.is_first_field << 5 |
1531                   picture_type << 2 |
1532                   fcm << 0);
1533     OUT_BCS_BATCH(batch,
1534                   !!pic_param->bitplane_present.value << 23 |
1535                   !pic_param->bitplane_present.flags.bp_forward_mb << 22 |
1536                   !pic_param->bitplane_present.flags.bp_mv_type_mb << 21 |
1537                   !pic_param->bitplane_present.flags.bp_skip_mb << 20 |
1538                   !pic_param->bitplane_present.flags.bp_direct_mb << 19 |
1539                   !pic_param->bitplane_present.flags.bp_overflags << 18 |
1540                   !pic_param->bitplane_present.flags.bp_ac_pred << 17 |
1541                   !pic_param->bitplane_present.flags.bp_field_tx << 16 |
1542                   pic_param->mv_fields.bits.extended_dmv_range << 14 |
1543                   pic_param->mv_fields.bits.extended_mv_range << 12 |
1544                   pic_param->mv_fields.bits.four_mv_switch << 11 |
1545                   pic_param->fast_uvmc_flag << 10 |
1546                   unified_mv_mode << 8 |
1547                   ref_field_pic_polarity << 6 |
1548                   pic_param->reference_fields.bits.num_reference_pictures << 5 |
1549                   pic_param->reference_fields.bits.reference_distance << 0);
1550     OUT_BCS_BATCH(batch,
1551                   scale_factor << 24 |
1552                   pic_param->mv_fields.bits.mv_table << 20 |
1553                   pic_param->mv_fields.bits.four_mv_block_pattern_table << 18 |
1554                   pic_param->mv_fields.bits.two_mv_block_pattern_table << 16 |
1555                   pic_param->transform_fields.bits.frame_level_transform_type << 12 |
1556                   pic_param->transform_fields.bits.mb_level_transform_type_flag << 11 |
1557                   pic_param->mb_mode_table << 8 |
1558                   trans_ac_y << 6 |
1559                   pic_param->transform_fields.bits.transform_ac_codingset_idx1 << 4 |
1560                   pic_param->transform_fields.bits.intra_transform_dc_table << 3 |
1561                   pic_param->cbp_table << 0);
1562     OUT_BCS_BATCH(batch,
1563                   dmv_surface_valid << 13 |
1564                   brfd << 8 |
1565                   ((ALIGN(pic_param->coded_width, 16) / 16 + 1) / 2 - 1));
1566     ADVANCE_BCS_BATCH(batch);
1567 }
1568
1569 static void
1570 gen6_mfd_vc1_pred_pipe_state(VADriverContextP ctx,
1571                              struct decode_state *decode_state,
1572                              struct gen6_mfd_context *gen6_mfd_context)
1573 {
1574     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1575     VAPictureParameterBufferVC1 *pic_param;
1576     int interpolation_mode = 0;
1577     int intensitycomp_single;
1578
1579     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1580     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1581
1582     if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPelBilinear ||
1583         (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation &&
1584          pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPelBilinear))
1585         interpolation_mode = 2; /* Half-pel bilinear */
1586     else if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPel ||
1587              (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation &&
1588               pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPel))
1589         interpolation_mode = 0; /* Half-pel bicubic */
1590     else
1591         interpolation_mode = 1; /* Quarter-pel bicubic */
1592
1593     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1594     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1595     intensitycomp_single = (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation);
1596
1597     BEGIN_BCS_BATCH(batch, 7);
1598     OUT_BCS_BATCH(batch, MFX_VC1_PRED_PIPE_STATE | (7 - 2));
1599     OUT_BCS_BATCH(batch,
1600                   0 << 8 | /* FIXME: interlace mode */
1601                   pic_param->rounding_control << 4 |
1602                   va_to_gen6_vc1_profile[pic_param->sequence_fields.bits.profile] << 2);
1603     OUT_BCS_BATCH(batch,
1604                   pic_param->luma_shift << 16 |
1605                   pic_param->luma_scale << 0); /* FIXME: Luma Scaling */
1606     OUT_BCS_BATCH(batch, 0);
1607     OUT_BCS_BATCH(batch, 0);
1608     OUT_BCS_BATCH(batch, 0);
1609     OUT_BCS_BATCH(batch,
1610                   interpolation_mode << 19 |
1611                   pic_param->fast_uvmc_flag << 18 |
1612                   0 << 17 | /* FIXME: scale up or down ??? */
1613                   pic_param->range_reduction_frame << 16 |
1614                   0 << 6 | /* FIXME: double ??? */
1615                   0 << 4 |
1616                   intensitycomp_single << 2 |
1617                   intensitycomp_single << 0);
1618     ADVANCE_BCS_BATCH(batch);
1619 }
1620
1621
1622 static void
1623 gen6_mfd_vc1_directmode_state(VADriverContextP ctx,
1624                               struct decode_state *decode_state,
1625                               struct gen6_mfd_context *gen6_mfd_context)
1626 {
1627     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1628     struct object_surface *obj_surface;
1629     dri_bo *dmv_read_buffer = NULL, *dmv_write_buffer = NULL;
1630
1631     obj_surface = decode_state->render_object;
1632
1633     if (obj_surface && obj_surface->private_data) {
1634         dmv_write_buffer = ((struct gen6_vc1_surface *)(obj_surface->private_data))->dmv;
1635     }
1636
1637     obj_surface = decode_state->reference_objects[1];
1638
1639     if (obj_surface && obj_surface->private_data) {
1640         dmv_read_buffer = ((struct gen6_vc1_surface *)(obj_surface->private_data))->dmv;
1641     }
1642
1643     BEGIN_BCS_BATCH(batch, 3);
1644     OUT_BCS_BATCH(batch, MFX_VC1_DIRECTMODE_STATE | (3 - 2));
1645
1646     if (dmv_write_buffer)
1647         OUT_BCS_RELOC(batch, dmv_write_buffer,
1648                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
1649                       0);
1650     else
1651         OUT_BCS_BATCH(batch, 0);
1652
1653     if (dmv_read_buffer)
1654         OUT_BCS_RELOC(batch, dmv_read_buffer,
1655                       I915_GEM_DOMAIN_INSTRUCTION, 0,
1656                       0);
1657     else
1658         OUT_BCS_BATCH(batch, 0);
1659
1660     ADVANCE_BCS_BATCH(batch);
1661 }
1662
1663 static int
1664 gen6_mfd_vc1_get_macroblock_bit_offset(uint8_t *buf, int in_slice_data_bit_offset, int profile)
1665 {
1666     int out_slice_data_bit_offset;
1667     int slice_header_size = in_slice_data_bit_offset / 8;
1668     int i, j;
1669
1670     if (profile != 3)
1671         out_slice_data_bit_offset = in_slice_data_bit_offset;
1672     else {
1673         for (i = 0, j = 0; i < slice_header_size; i++, j++) {
1674             if (!buf[j] && !buf[j + 1] && buf[j + 2] == 3 && buf[j + 3] < 4) {
1675                 i++, j += 2;
1676             }
1677         }
1678
1679         out_slice_data_bit_offset = 8 * j + in_slice_data_bit_offset % 8;
1680     }
1681
1682     return out_slice_data_bit_offset;
1683 }
1684
1685 static void
1686 gen6_mfd_vc1_bsd_object(VADriverContextP ctx,
1687                         VAPictureParameterBufferVC1 *pic_param,
1688                         VASliceParameterBufferVC1 *slice_param,
1689                         VASliceParameterBufferVC1 *next_slice_param,
1690                         dri_bo *slice_data_bo,
1691                         struct gen6_mfd_context *gen6_mfd_context)
1692 {
1693     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1694     int next_slice_start_vert_pos;
1695     int macroblock_offset;
1696     uint8_t *slice_data = NULL;
1697
1698     dri_bo_map(slice_data_bo, 0);
1699     slice_data = (uint8_t *)(slice_data_bo->virtual + slice_param->slice_data_offset);
1700     macroblock_offset = gen6_mfd_vc1_get_macroblock_bit_offset(slice_data,
1701                                                                slice_param->macroblock_offset,
1702                                                                pic_param->sequence_fields.bits.profile);
1703     dri_bo_unmap(slice_data_bo);
1704
1705     if (next_slice_param)
1706         next_slice_start_vert_pos = next_slice_param->slice_vertical_position;
1707     else
1708         next_slice_start_vert_pos = ALIGN(pic_param->coded_height, 16) / 16;
1709
1710     BEGIN_BCS_BATCH(batch, 4);
1711     OUT_BCS_BATCH(batch, MFD_VC1_BSD_OBJECT | (4 - 2));
1712     OUT_BCS_BATCH(batch,
1713                   slice_param->slice_data_size - (macroblock_offset >> 3));
1714     OUT_BCS_BATCH(batch,
1715                   slice_param->slice_data_offset + (macroblock_offset >> 3));
1716     OUT_BCS_BATCH(batch,
1717                   slice_param->slice_vertical_position << 24 |
1718                   next_slice_start_vert_pos << 16 |
1719                   (macroblock_offset & 0x7));
1720     ADVANCE_BCS_BATCH(batch);
1721 }
1722
1723 static void
1724 gen6_mfd_vc1_decode_picture(VADriverContextP ctx,
1725                             struct decode_state *decode_state,
1726                             struct gen6_mfd_context *gen6_mfd_context)
1727 {
1728     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1729     VAPictureParameterBufferVC1 *pic_param;
1730     VASliceParameterBufferVC1 *slice_param, *next_slice_param, *next_slice_group_param;
1731     dri_bo *slice_data_bo;
1732     int i, j;
1733
1734     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1735     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1736
1737     gen6_mfd_vc1_decode_init(ctx, decode_state, gen6_mfd_context);
1738     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
1739     intel_batchbuffer_emit_mi_flush(batch);
1740     gen6_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_VC1, gen6_mfd_context);
1741     gen6_mfd_surface_state(ctx, decode_state, MFX_FORMAT_VC1, gen6_mfd_context);
1742     gen6_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen6_mfd_context);
1743     gen6_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen6_mfd_context);
1744     gen6_mfd_vc1_pic_state(ctx, decode_state, gen6_mfd_context);
1745     gen6_mfd_vc1_pred_pipe_state(ctx, decode_state, gen6_mfd_context);
1746     gen6_mfd_vc1_directmode_state(ctx, decode_state, gen6_mfd_context);
1747
1748     for (j = 0; j < decode_state->num_slice_params; j++) {
1749         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
1750         slice_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j]->buffer;
1751         slice_data_bo = decode_state->slice_datas[j]->bo;
1752         gen6_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_VC1, gen6_mfd_context);
1753
1754         if (j == decode_state->num_slice_params - 1)
1755             next_slice_group_param = NULL;
1756         else
1757             next_slice_group_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j + 1]->buffer;
1758
1759         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
1760             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
1761
1762             if (i < decode_state->slice_params[j]->num_elements - 1)
1763                 next_slice_param = slice_param + 1;
1764             else
1765                 next_slice_param = next_slice_group_param;
1766
1767             gen6_mfd_vc1_bsd_object(ctx, pic_param, slice_param, next_slice_param, slice_data_bo, gen6_mfd_context);
1768             slice_param++;
1769         }
1770     }
1771
1772     intel_batchbuffer_end_atomic(batch);
1773     intel_batchbuffer_flush(batch);
1774 }
1775
1776 static VAStatus
1777 gen6_mfd_decode_picture(VADriverContextP ctx,
1778                         VAProfile profile,
1779                         union codec_state *codec_state,
1780                         struct hw_context *hw_context)
1781
1782 {
1783     struct gen6_mfd_context *gen6_mfd_context = (struct gen6_mfd_context *)hw_context;
1784     struct decode_state *decode_state = &codec_state->decode;
1785     VAStatus vaStatus;
1786
1787     assert(gen6_mfd_context);
1788
1789     vaStatus = intel_decoder_sanity_check_input(ctx, profile, decode_state);
1790
1791     if (vaStatus != VA_STATUS_SUCCESS)
1792         goto out;
1793
1794     switch (profile) {
1795     case VAProfileMPEG2Simple:
1796     case VAProfileMPEG2Main:
1797         gen6_mfd_mpeg2_decode_picture(ctx, decode_state, gen6_mfd_context);
1798         break;
1799
1800     case VAProfileH264ConstrainedBaseline:
1801     case VAProfileH264Main:
1802     case VAProfileH264High:
1803     case VAProfileH264StereoHigh:
1804         gen6_mfd_avc_decode_picture(ctx, decode_state, gen6_mfd_context);
1805         break;
1806
1807     case VAProfileVC1Simple:
1808     case VAProfileVC1Main:
1809     case VAProfileVC1Advanced:
1810         gen6_mfd_vc1_decode_picture(ctx, decode_state, gen6_mfd_context);
1811         break;
1812
1813     default:
1814         assert(0);
1815         break;
1816     }
1817
1818     vaStatus = VA_STATUS_SUCCESS;
1819
1820 out:
1821     return vaStatus;
1822 }
1823
1824 static void
1825 gen6_mfd_context_destroy(void *hw_context)
1826 {
1827     struct gen6_mfd_context *gen6_mfd_context = (struct gen6_mfd_context *)hw_context;
1828
1829     dri_bo_unreference(gen6_mfd_context->post_deblocking_output.bo);
1830     gen6_mfd_context->post_deblocking_output.bo = NULL;
1831
1832     dri_bo_unreference(gen6_mfd_context->pre_deblocking_output.bo);
1833     gen6_mfd_context->pre_deblocking_output.bo = NULL;
1834
1835     dri_bo_unreference(gen6_mfd_context->intra_row_store_scratch_buffer.bo);
1836     gen6_mfd_context->intra_row_store_scratch_buffer.bo = NULL;
1837
1838     dri_bo_unreference(gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
1839     gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
1840
1841     dri_bo_unreference(gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
1842     gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
1843
1844     dri_bo_unreference(gen6_mfd_context->mpr_row_store_scratch_buffer.bo);
1845     gen6_mfd_context->mpr_row_store_scratch_buffer.bo = NULL;
1846
1847     dri_bo_unreference(gen6_mfd_context->bitplane_read_buffer.bo);
1848     gen6_mfd_context->bitplane_read_buffer.bo = NULL;
1849
1850     intel_batchbuffer_free(gen6_mfd_context->base.batch);
1851     free(gen6_mfd_context);
1852 }
1853
1854 struct hw_context *
1855 gen6_dec_hw_context_init(VADriverContextP ctx, struct object_config *obj_config)
1856 {
1857     struct intel_driver_data *intel = intel_driver_data(ctx);
1858     struct gen6_mfd_context *gen6_mfd_context = calloc(1, sizeof(struct gen6_mfd_context));
1859     int i;
1860
1861     if (!gen6_mfd_context)
1862         return NULL;
1863
1864     gen6_mfd_context->base.destroy = gen6_mfd_context_destroy;
1865     gen6_mfd_context->base.run = gen6_mfd_decode_picture;
1866     gen6_mfd_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER, 0);
1867
1868     for (i = 0; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface); i++) {
1869         gen6_mfd_context->reference_surface[i].surface_id = VA_INVALID_ID;
1870         gen6_mfd_context->reference_surface[i].frame_store_id = -1;
1871         gen6_mfd_context->reference_surface[i].obj_surface = NULL;
1872     }
1873
1874     gen6_mfd_context->wa_mpeg2_slice_vertical_position = -1;
1875
1876     return (struct hw_context *)gen6_mfd_context;
1877 }