2 * Copyright © 2010-2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Zhou Chang <chang.zhou@intel.com>
34 #include "intel_batchbuffer.h"
35 #include "intel_driver.h"
37 #include "i965_defines.h"
38 #include "i965_drv_video.h"
39 #include "i965_encoder.h"
43 #define SURFACE_STATE_PADDED_SIZE MAX(SURFACE_STATE_PADDED_SIZE_GEN6, SURFACE_STATE_PADDED_SIZE_GEN7)
44 #define SURFACE_STATE_OFFSET(index) (SURFACE_STATE_PADDED_SIZE * index)
45 #define BINDING_TABLE_OFFSET(index) (SURFACE_STATE_OFFSET(MAX_MEDIA_SURFACES_GEN6) + sizeof(unsigned int) * index)
47 #define CURBE_ALLOCATION_SIZE 37 /* in 256-bit */
48 #define CURBE_TOTAL_DATA_LENGTH (4 * 32) /* in byte, it should be less than or equal to CURBE_ALLOCATION_SIZE * 32 */
49 #define CURBE_URB_ENTRY_LENGTH 4 /* in 256-bit, it should be less than or equal to CURBE_TOTAL_DATA_LENGTH / 32 */
51 enum VIDEO_CODING_TYPE{
56 enum AVC_VME_KERNEL_TYPE{
57 AVC_VME_INTRA_SHADER = 0,
63 static const uint32_t gen6_vme_intra_frame[][4] = {
64 #include "shaders/vme/intra_frame.g6b"
67 static const uint32_t gen6_vme_inter_frame[][4] = {
68 #include "shaders/vme/inter_frame.g6b"
71 static const uint32_t gen6_vme_batchbuffer[][4] = {
72 #include "shaders/vme/batchbuffer.g6b"
75 static struct i965_kernel gen6_vme_kernels[] = {
77 "AVC VME Intra Frame",
78 AVC_VME_INTRA_SHADER, /*index*/
80 sizeof(gen6_vme_intra_frame),
84 "AVC VME inter Frame",
87 sizeof(gen6_vme_inter_frame),
91 "AVC VME BATCHBUFFER",
94 sizeof(gen6_vme_batchbuffer),
99 /* only used for VME source surface state */
101 gen6_vme_source_surface_state(VADriverContextP ctx,
103 struct object_surface *obj_surface,
104 struct intel_encoder_context *encoder_context)
106 struct gen6_vme_context *vme_context = encoder_context->vme_context;
108 vme_context->vme_surface2_setup(ctx,
109 &vme_context->gpe_context,
111 BINDING_TABLE_OFFSET(index),
112 SURFACE_STATE_OFFSET(index));
116 gen6_vme_media_source_surface_state(VADriverContextP ctx,
118 struct object_surface *obj_surface,
119 struct intel_encoder_context *encoder_context)
121 struct gen6_vme_context *vme_context = encoder_context->vme_context;
123 vme_context->vme_media_rw_surface_setup(ctx,
124 &vme_context->gpe_context,
126 BINDING_TABLE_OFFSET(index),
127 SURFACE_STATE_OFFSET(index),
132 gen6_vme_output_buffer_setup(VADriverContextP ctx,
133 struct encode_state *encode_state,
135 struct intel_encoder_context *encoder_context)
138 struct i965_driver_data *i965 = i965_driver_data(ctx);
139 struct gen6_vme_context *vme_context = encoder_context->vme_context;
140 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
141 VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
142 int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
143 int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
144 int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
146 vme_context->vme_output.num_blocks = width_in_mbs * height_in_mbs;
147 vme_context->vme_output.pitch = 16; /* in bytes, always 16 */
150 vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES;
152 vme_context->vme_output.size_block = INTER_VME_OUTPUT_IN_BYTES;
154 vme_context->vme_output.bo = dri_bo_alloc(i965->intel.bufmgr,
156 vme_context->vme_output.num_blocks * vme_context->vme_output.size_block,
158 assert(vme_context->vme_output.bo);
159 vme_context->vme_buffer_suface_setup(ctx,
160 &vme_context->gpe_context,
161 &vme_context->vme_output,
162 BINDING_TABLE_OFFSET(index),
163 SURFACE_STATE_OFFSET(index));
167 gen6_vme_output_vme_batchbuffer_setup(VADriverContextP ctx,
168 struct encode_state *encode_state,
170 struct intel_encoder_context *encoder_context)
173 struct i965_driver_data *i965 = i965_driver_data(ctx);
174 struct gen6_vme_context *vme_context = encoder_context->vme_context;
175 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
176 int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
177 int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
179 vme_context->vme_batchbuffer.num_blocks = width_in_mbs * height_in_mbs + 1;
180 vme_context->vme_batchbuffer.size_block = 32; /* 2 OWORDs */
181 vme_context->vme_batchbuffer.pitch = 16;
182 vme_context->vme_batchbuffer.bo = dri_bo_alloc(i965->intel.bufmgr,
184 vme_context->vme_batchbuffer.num_blocks * vme_context->vme_batchbuffer.size_block,
186 vme_context->vme_buffer_suface_setup(ctx,
187 &vme_context->gpe_context,
188 &vme_context->vme_batchbuffer,
189 BINDING_TABLE_OFFSET(index),
190 SURFACE_STATE_OFFSET(index));
194 gen6_vme_surface_setup(VADriverContextP ctx,
195 struct encode_state *encode_state,
197 struct intel_encoder_context *encoder_context)
199 struct object_surface *obj_surface;
201 /*Setup surfaces state*/
202 /* current picture for encoding */
203 obj_surface = encode_state->input_yuv_object;
204 gen6_vme_source_surface_state(ctx, 0, obj_surface, encoder_context);
205 gen6_vme_media_source_surface_state(ctx, 4, obj_surface, encoder_context);
208 VAEncSliceParameterBufferH264 *slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
211 slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type);
212 assert(slice_type != SLICE_TYPE_I && slice_type != SLICE_TYPE_SI);
214 intel_avc_vme_reference_state(ctx, encode_state, encoder_context, 0, 1, gen6_vme_source_surface_state);
216 if (slice_type == SLICE_TYPE_B)
217 intel_avc_vme_reference_state(ctx, encode_state, encoder_context, 1, 2, gen6_vme_source_surface_state);
221 gen6_vme_output_buffer_setup(ctx, encode_state, 3, encoder_context);
222 gen6_vme_output_vme_batchbuffer_setup(ctx, encode_state, 5, encoder_context);
224 return VA_STATUS_SUCCESS;
227 static VAStatus gen6_vme_interface_setup(VADriverContextP ctx,
228 struct encode_state *encode_state,
229 struct intel_encoder_context *encoder_context)
231 struct gen6_vme_context *vme_context = encoder_context->vme_context;
232 struct gen6_interface_descriptor_data *desc;
236 bo = vme_context->gpe_context.idrt.bo;
241 for (i = 0; i < vme_context->vme_kernel_sum; i++) {
242 struct i965_kernel *kernel;
243 kernel = &vme_context->gpe_context.kernels[i];
244 assert(sizeof(*desc) == 32);
245 /*Setup the descritor table*/
246 memset(desc, 0, sizeof(*desc));
247 desc->desc0.kernel_start_pointer = (kernel->bo->offset >> 6);
248 desc->desc2.sampler_count = 1; /* FIXME: */
249 desc->desc2.sampler_state_pointer = (vme_context->vme_state.bo->offset >> 5);
250 desc->desc3.binding_table_entry_count = 1; /* FIXME: */
251 desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET(0) >> 5);
252 desc->desc4.constant_urb_entry_read_offset = 0;
253 desc->desc4.constant_urb_entry_read_length = CURBE_URB_ENTRY_LENGTH;
256 dri_bo_emit_reloc(bo,
257 I915_GEM_DOMAIN_INSTRUCTION, 0,
259 i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc0),
261 /*Sampler State(VME state pointer)*/
262 dri_bo_emit_reloc(bo,
263 I915_GEM_DOMAIN_INSTRUCTION, 0,
265 i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc2),
266 vme_context->vme_state.bo);
271 return VA_STATUS_SUCCESS;
274 static VAStatus gen6_vme_constant_setup(VADriverContextP ctx,
275 struct encode_state *encode_state,
276 struct intel_encoder_context *encoder_context)
278 struct gen6_vme_context *vme_context = encoder_context->vme_context;
279 // unsigned char *constant_buffer;
280 unsigned int *vme_state_message;
282 if (vme_context->h264_level >= 30) {
284 if (vme_context->h264_level >= 31)
288 dri_bo_map(vme_context->gpe_context.curbe.bo, 1);
289 assert(vme_context->gpe_context.curbe.bo->virtual);
290 // constant_buffer = vme_context->curbe.bo->virtual;
291 vme_state_message = (unsigned int *)vme_context->gpe_context.curbe.bo->virtual;
292 vme_state_message[31] = mv_num;
294 /*TODO copy buffer into CURB*/
296 dri_bo_unmap( vme_context->gpe_context.curbe.bo);
298 return VA_STATUS_SUCCESS;
301 static const unsigned int intra_mb_mode_cost_table[] = {
302 0x31110001, // for qp0
303 0x09110001, // for qp1
304 0x15030001, // for qp2
305 0x0b030001, // for qp3
306 0x0d030011, // for qp4
307 0x17210011, // for qp5
308 0x41210011, // for qp6
309 0x19210011, // for qp7
310 0x25050003, // for qp8
311 0x1b130003, // for qp9
312 0x1d130003, // for qp10
313 0x27070021, // for qp11
314 0x51310021, // for qp12
315 0x29090021, // for qp13
316 0x35150005, // for qp14
317 0x2b0b0013, // for qp15
318 0x2d0d0013, // for qp16
319 0x37170007, // for qp17
320 0x61410031, // for qp18
321 0x39190009, // for qp19
322 0x45250015, // for qp20
323 0x3b1b000b, // for qp21
324 0x3d1d000d, // for qp22
325 0x47270017, // for qp23
326 0x71510041, // for qp24 ! center for qp=0..30
327 0x49290019, // for qp25
328 0x55350025, // for qp26
329 0x4b2b001b, // for qp27
330 0x4d2d001d, // for qp28
331 0x57370027, // for qp29
332 0x81610051, // for qp30
333 0x57270017, // for qp31
334 0x81510041, // for qp32 ! center for qp=31..51
335 0x59290019, // for qp33
336 0x65350025, // for qp34
337 0x5b2b001b, // for qp35
338 0x5d2d001d, // for qp36
339 0x67370027, // for qp37
340 0x91610051, // for qp38
341 0x69390029, // for qp39
342 0x75450035, // for qp40
343 0x6b3b002b, // for qp41
344 0x6d3d002d, // for qp42
345 0x77470037, // for qp43
346 0xa1710061, // for qp44
347 0x79490039, // for qp45
348 0x85550045, // for qp46
349 0x7b4b003b, // for qp47
350 0x7d4d003d, // for qp48
351 0x87570047, // for qp49
352 0xb1810071, // for qp50
353 0x89590049 // for qp51
356 static void gen6_vme_state_setup_fixup(VADriverContextP ctx,
357 struct encode_state *encode_state,
358 struct intel_encoder_context *encoder_context,
359 unsigned int *vme_state_message)
361 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
362 VAEncPictureParameterBufferH264 *pic_param = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
363 VAEncSliceParameterBufferH264 *slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
365 if (slice_param->slice_type != SLICE_TYPE_I &&
366 slice_param->slice_type != SLICE_TYPE_SI)
369 if (encoder_context->rate_control_mode == VA_RC_CQP)
370 vme_state_message[16] = intra_mb_mode_cost_table[pic_param->pic_init_qp + slice_param->slice_qp_delta];
372 vme_state_message[16] = intra_mb_mode_cost_table[mfc_context->brc.qp_prime_y[encoder_context->layer.curr_frame_layer_id][SLICE_TYPE_I]];
375 static VAStatus gen6_vme_vme_state_setup(VADriverContextP ctx,
376 struct encode_state *encode_state,
378 struct intel_encoder_context *encoder_context)
380 struct gen6_vme_context *vme_context = encoder_context->vme_context;
381 unsigned int *vme_state_message;
384 //building VME state message
385 dri_bo_map(vme_context->vme_state.bo, 1);
386 assert(vme_context->vme_state.bo->virtual);
387 vme_state_message = (unsigned int *)vme_context->vme_state.bo->virtual;
389 if (encoder_context->quality_level != ENCODER_LOW_QUALITY) {
390 vme_state_message[0] = 0x01010101;
391 vme_state_message[1] = 0x10010101;
392 vme_state_message[2] = 0x0F0F0F0F;
393 vme_state_message[3] = 0x100F0F0F;
394 vme_state_message[4] = 0x01010101;
395 vme_state_message[5] = 0x10010101;
396 vme_state_message[6] = 0x0F0F0F0F;
397 vme_state_message[7] = 0x100F0F0F;
398 vme_state_message[8] = 0x01010101;
399 vme_state_message[9] = 0x10010101;
400 vme_state_message[10] = 0x0F0F0F0F;
401 vme_state_message[11] = 0x000F0F0F;
402 vme_state_message[12] = 0x00;
403 vme_state_message[13] = 0x00;
405 vme_state_message[0] = 0x10010101;
406 vme_state_message[1] = 0x100F0F0F;
407 vme_state_message[2] = 0x10010101;
408 vme_state_message[3] = 0x000F0F0F;
409 vme_state_message[4] = 0;
410 vme_state_message[5] = 0;
411 vme_state_message[6] = 0;
412 vme_state_message[7] = 0;
413 vme_state_message[8] = 0;
414 vme_state_message[9] = 0;
415 vme_state_message[10] = 0;
416 vme_state_message[11] = 0;
417 vme_state_message[12] = 0;
418 vme_state_message[13] = 0;
421 vme_state_message[14] = 0x4a4a;
422 vme_state_message[15] = 0x0;
423 vme_state_message[16] = 0x4a4a4a4a;
424 vme_state_message[17] = 0x4a4a4a4a;
425 vme_state_message[18] = 0x21110100;
426 vme_state_message[19] = 0x61514131;
428 for(i = 20; i < 32; i++) {
429 vme_state_message[i] = 0;
431 //vme_state_message[16] = 0x42424242; //cost function LUT set 0 for Intra
433 gen6_vme_state_setup_fixup(ctx, encode_state, encoder_context, vme_state_message);
435 dri_bo_unmap( vme_context->vme_state.bo);
436 return VA_STATUS_SUCCESS;
440 gen6_vme_fill_vme_batchbuffer(VADriverContextP ctx,
441 struct encode_state *encode_state,
442 int mb_width, int mb_height,
444 int transform_8x8_mode_flag,
445 struct intel_encoder_context *encoder_context)
447 struct gen6_vme_context *vme_context = encoder_context->vme_context;
449 int mb_x = 0, mb_y = 0;
451 unsigned int *command_ptr;
453 dri_bo_map(vme_context->vme_batchbuffer.bo, 1);
454 command_ptr = vme_context->vme_batchbuffer.bo->virtual;
456 for (s = 0; s < encode_state->num_slice_params_ext; s++) {
457 VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[s]->buffer;
458 int slice_mb_begin = pSliceParameter->macroblock_address;
459 int slice_mb_number = pSliceParameter->num_macroblocks;
461 for (i = 0; i < slice_mb_number; ) {
462 int mb_count = i + slice_mb_begin;
463 mb_x = mb_count % mb_width;
464 mb_y = mb_count / mb_width;
466 number_mb_cmds = mb_width; // we must mark the slice edge.
467 } else if ( (i + 128 ) <= slice_mb_number) {
468 number_mb_cmds = 128;
470 number_mb_cmds = slice_mb_number - i;
473 *command_ptr++ = (CMD_MEDIA_OBJECT | (9 - 2));
474 *command_ptr++ = kernel;
481 *command_ptr++ = (mb_width << 16 | mb_y << 8 | mb_x);
482 *command_ptr++ = (number_mb_cmds << 16 | transform_8x8_mode_flag | ((i==0) << 1));
483 *command_ptr++ = encoder_context->quality_level;
490 *command_ptr++ = MI_BATCH_BUFFER_END;
492 dri_bo_unmap(vme_context->vme_batchbuffer.bo);
495 static void gen6_vme_media_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
497 struct i965_driver_data *i965 = i965_driver_data(ctx);
498 struct gen6_vme_context *vme_context = encoder_context->vme_context;
501 i965_gpe_context_init(ctx, &vme_context->gpe_context);
503 /* VME output buffer */
504 dri_bo_unreference(vme_context->vme_output.bo);
505 vme_context->vme_output.bo = NULL;
507 dri_bo_unreference(vme_context->vme_batchbuffer.bo);
508 vme_context->vme_batchbuffer.bo = NULL;
511 dri_bo_unreference(vme_context->vme_state.bo);
512 bo = dri_bo_alloc(i965->intel.bufmgr,
516 vme_context->vme_state.bo = bo;
519 static void gen6_vme_pipeline_programing(VADriverContextP ctx,
520 struct encode_state *encode_state,
521 struct intel_encoder_context *encoder_context)
523 struct gen6_vme_context *vme_context = encoder_context->vme_context;
524 struct intel_batchbuffer *batch = encoder_context->base.batch;
525 VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
526 VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
527 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
528 int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
529 int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
530 int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
532 gen6_vme_fill_vme_batchbuffer(ctx,
534 width_in_mbs, height_in_mbs,
535 is_intra ? AVC_VME_INTRA_SHADER : AVC_VME_INTER_SHADER,
536 pPicParameter->pic_fields.bits.transform_8x8_mode_flag,
539 intel_batchbuffer_start_atomic(batch, 0x1000);
540 gen6_gpe_pipeline_setup(ctx, &vme_context->gpe_context, batch);
541 BEGIN_BATCH(batch, 2);
542 OUT_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8));
544 vme_context->vme_batchbuffer.bo,
545 I915_GEM_DOMAIN_COMMAND, 0,
547 ADVANCE_BATCH(batch);
549 intel_batchbuffer_end_atomic(batch);
552 static VAStatus gen6_vme_prepare(VADriverContextP ctx,
553 struct encode_state *encode_state,
554 struct intel_encoder_context *encoder_context)
556 VAStatus vaStatus = VA_STATUS_SUCCESS;
557 VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
558 int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
559 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
560 struct gen6_vme_context *vme_context = encoder_context->vme_context;
562 if (!vme_context->h264_level ||
563 (vme_context->h264_level != pSequenceParameter->level_idc)) {
564 vme_context->h264_level = pSequenceParameter->level_idc;
566 /*Setup all the memory object*/
567 gen6_vme_surface_setup(ctx, encode_state, is_intra, encoder_context);
568 gen6_vme_interface_setup(ctx, encode_state, encoder_context);
569 gen6_vme_constant_setup(ctx, encode_state, encoder_context);
570 gen6_vme_vme_state_setup(ctx, encode_state, is_intra, encoder_context);
572 /*Programing media pipeline*/
573 gen6_vme_pipeline_programing(ctx, encode_state, encoder_context);
578 static VAStatus gen6_vme_run(VADriverContextP ctx,
579 struct encode_state *encode_state,
580 struct intel_encoder_context *encoder_context)
582 struct intel_batchbuffer *batch = encoder_context->base.batch;
584 intel_batchbuffer_flush(batch);
586 return VA_STATUS_SUCCESS;
589 static VAStatus gen6_vme_stop(VADriverContextP ctx,
590 struct encode_state *encode_state,
591 struct intel_encoder_context *encoder_context)
593 return VA_STATUS_SUCCESS;
597 gen6_vme_pipeline(VADriverContextP ctx,
599 struct encode_state *encode_state,
600 struct intel_encoder_context *encoder_context)
602 gen6_vme_media_init(ctx, encoder_context);
603 gen6_vme_prepare(ctx, encode_state, encoder_context);
604 gen6_vme_run(ctx, encode_state, encoder_context);
605 gen6_vme_stop(ctx, encode_state, encoder_context);
607 return VA_STATUS_SUCCESS;
611 gen6_vme_context_destroy(void *context)
613 struct gen6_vme_context *vme_context = context;
615 i965_gpe_context_destroy(&vme_context->gpe_context);
617 dri_bo_unreference(vme_context->vme_output.bo);
618 vme_context->vme_output.bo = NULL;
620 dri_bo_unreference(vme_context->vme_state.bo);
621 vme_context->vme_state.bo = NULL;
623 dri_bo_unreference(vme_context->vme_batchbuffer.bo);
624 vme_context->vme_batchbuffer.bo = NULL;
626 free(vme_context->qp_per_mb);
627 vme_context->qp_per_mb = NULL;
632 Bool gen6_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
634 struct gen6_vme_context *vme_context = NULL;
636 if (encoder_context->codec != CODEC_H264) {
642 vme_context = calloc(1, sizeof(struct gen6_vme_context));
647 vme_context->gpe_context.surface_state_binding_table.length =
648 (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6;
650 vme_context->gpe_context.idrt.max_entries = MAX_INTERFACE_DESC_GEN6;
651 vme_context->gpe_context.idrt.entry_size = sizeof(struct gen6_interface_descriptor_data);
652 vme_context->gpe_context.curbe.length = CURBE_TOTAL_DATA_LENGTH;
654 vme_context->gpe_context.vfe_state.max_num_threads = 60 - 1;
655 vme_context->gpe_context.vfe_state.num_urb_entries = 16;
656 vme_context->gpe_context.vfe_state.gpgpu_mode = 0;
657 vme_context->gpe_context.vfe_state.urb_entry_size = 59 - 1;
658 vme_context->gpe_context.vfe_state.curbe_allocation_size = CURBE_ALLOCATION_SIZE - 1;
660 vme_context->video_coding_type = VIDEO_CODING_AVC;
661 vme_context->vme_kernel_sum = AVC_VME_KERNEL_SUM;
662 i965_gpe_load_kernels(ctx,
663 &vme_context->gpe_context,
665 vme_context->vme_kernel_sum);
667 encoder_context->vme_pipeline = gen6_vme_pipeline;
668 vme_context->vme_surface2_setup = i965_gpe_surface2_setup;
669 vme_context->vme_media_rw_surface_setup = i965_gpe_media_rw_surface_setup;
670 vme_context->vme_buffer_suface_setup = i965_gpe_buffer_suface_setup;
672 encoder_context->vme_context = vme_context;
673 encoder_context->vme_context_destroy = gen6_vme_context_destroy;