2 * Copyright © 2010-2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Zhao Yakui <yakui.zhao@intel.com>
26 * Xiang Haihao <haihao.xiang@intel.com>
32 #include "intel_batchbuffer.h"
33 #include "intel_driver.h"
35 #include "i965_defines.h"
36 #include "i965_drv_video.h"
37 #include "i965_encoder.h"
41 #define SURFACE_STATE_PADDED_SIZE MAX(SURFACE_STATE_PADDED_SIZE_GEN6, SURFACE_STATE_PADDED_SIZE_GEN7)
42 #define SURFACE_STATE_OFFSET(index) (SURFACE_STATE_PADDED_SIZE * index)
43 #define BINDING_TABLE_OFFSET(index) (SURFACE_STATE_OFFSET(MAX_MEDIA_SURFACES_GEN6) + sizeof(unsigned int) * index)
45 #define VME_INTRA_SHADER 0
46 #define VME_INTER_SHADER 1
47 #define VME_BINTER_SHADER 3
48 #define VME_BATCHBUFFER 2
50 #define CURBE_ALLOCATION_SIZE 37 /* in 256-bit */
51 #define CURBE_TOTAL_DATA_LENGTH (4 * 32) /* in byte, it should be less than or equal to CURBE_ALLOCATION_SIZE * 32 */
52 #define CURBE_URB_ENTRY_LENGTH 4 /* in 256-bit, it should be less than or equal to CURBE_TOTAL_DATA_LENGTH / 32 */
54 #define VME_MSG_LENGTH 32
56 static const uint32_t gen75_vme_intra_frame[][4] = {
57 #include "shaders/vme/intra_frame_haswell.g75b"
60 static const uint32_t gen75_vme_inter_frame[][4] = {
61 #include "shaders/vme/inter_frame_haswell.g75b"
64 static const uint32_t gen75_vme_inter_bframe[][4] = {
65 #include "shaders/vme/inter_bframe_haswell.g75b"
68 static const uint32_t gen75_vme_batchbuffer[][4] = {
69 #include "shaders/vme/batchbuffer.g75b"
72 static struct i965_kernel gen75_vme_kernels[] = {
75 VME_INTRA_SHADER, /*index*/
76 gen75_vme_intra_frame,
77 sizeof(gen75_vme_intra_frame),
83 gen75_vme_inter_frame,
84 sizeof(gen75_vme_inter_frame),
90 gen75_vme_batchbuffer,
91 sizeof(gen75_vme_batchbuffer),
97 gen75_vme_inter_bframe,
98 sizeof(gen75_vme_inter_bframe),
103 static const uint32_t gen75_vme_mpeg2_intra_frame[][4] = {
104 #include "shaders/vme/intra_frame_haswell.g75b"
107 static const uint32_t gen75_vme_mpeg2_inter_frame[][4] = {
108 #include "shaders/vme/mpeg2_inter_haswell.g75b"
111 static const uint32_t gen75_vme_mpeg2_batchbuffer[][4] = {
112 #include "shaders/vme/batchbuffer.g75b"
115 static struct i965_kernel gen75_vme_mpeg2_kernels[] = {
118 VME_INTRA_SHADER, /*index*/
119 gen75_vme_mpeg2_intra_frame,
120 sizeof(gen75_vme_mpeg2_intra_frame),
126 gen75_vme_mpeg2_inter_frame,
127 sizeof(gen75_vme_mpeg2_inter_frame),
133 gen75_vme_mpeg2_batchbuffer,
134 sizeof(gen75_vme_mpeg2_batchbuffer),
139 /* only used for VME source surface state */
141 gen75_vme_source_surface_state(VADriverContextP ctx,
143 struct object_surface *obj_surface,
144 struct intel_encoder_context *encoder_context)
146 struct gen6_vme_context *vme_context = encoder_context->vme_context;
148 vme_context->vme_surface2_setup(ctx,
149 &vme_context->gpe_context,
151 BINDING_TABLE_OFFSET(index),
152 SURFACE_STATE_OFFSET(index));
156 gen75_vme_media_source_surface_state(VADriverContextP ctx,
158 struct object_surface *obj_surface,
159 struct intel_encoder_context *encoder_context)
161 struct gen6_vme_context *vme_context = encoder_context->vme_context;
163 vme_context->vme_media_rw_surface_setup(ctx,
164 &vme_context->gpe_context,
166 BINDING_TABLE_OFFSET(index),
167 SURFACE_STATE_OFFSET(index),
172 gen75_vme_media_chroma_source_surface_state(VADriverContextP ctx,
174 struct object_surface *obj_surface,
175 struct intel_encoder_context *encoder_context)
177 struct gen6_vme_context *vme_context = encoder_context->vme_context;
179 vme_context->vme_media_chroma_surface_setup(ctx,
180 &vme_context->gpe_context,
182 BINDING_TABLE_OFFSET(index),
183 SURFACE_STATE_OFFSET(index),
188 gen75_vme_output_buffer_setup(VADriverContextP ctx,
189 struct encode_state *encode_state,
191 struct intel_encoder_context *encoder_context)
194 struct i965_driver_data *i965 = i965_driver_data(ctx);
195 struct gen6_vme_context *vme_context = encoder_context->vme_context;
196 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
197 VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
198 int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
199 int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
200 int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
202 vme_context->vme_output.num_blocks = width_in_mbs * height_in_mbs;
203 vme_context->vme_output.pitch = 16; /* in bytes, always 16 */
206 vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES * 2;
208 vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES * 24;
210 * Inter MV . 32-byte Intra search + 16 IME info + 128 IME MV + 32 IME Ref
211 * + 16 FBR Info + 128 FBR MV + 32 FBR Ref.
212 * 16 * (2 + 2 * (1 + 8 + 2))= 16 * 24.
215 vme_context->vme_output.bo = dri_bo_alloc(i965->intel.bufmgr,
217 vme_context->vme_output.num_blocks * vme_context->vme_output.size_block,
219 assert(vme_context->vme_output.bo);
220 vme_context->vme_buffer_suface_setup(ctx,
221 &vme_context->gpe_context,
222 &vme_context->vme_output,
223 BINDING_TABLE_OFFSET(index),
224 SURFACE_STATE_OFFSET(index));
228 gen75_vme_output_vme_batchbuffer_setup(VADriverContextP ctx,
229 struct encode_state *encode_state,
231 struct intel_encoder_context *encoder_context)
234 struct i965_driver_data *i965 = i965_driver_data(ctx);
235 struct gen6_vme_context *vme_context = encoder_context->vme_context;
236 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
237 int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
238 int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
240 vme_context->vme_batchbuffer.num_blocks = width_in_mbs * height_in_mbs + 1;
241 vme_context->vme_batchbuffer.size_block = 64; /* 4 OWORDs */
242 vme_context->vme_batchbuffer.pitch = 16;
243 vme_context->vme_batchbuffer.bo = dri_bo_alloc(i965->intel.bufmgr,
245 vme_context->vme_batchbuffer.num_blocks * vme_context->vme_batchbuffer.size_block,
247 vme_context->vme_buffer_suface_setup(ctx,
248 &vme_context->gpe_context,
249 &vme_context->vme_batchbuffer,
250 BINDING_TABLE_OFFSET(index),
251 SURFACE_STATE_OFFSET(index));
255 gen75_vme_surface_setup(VADriverContextP ctx,
256 struct encode_state *encode_state,
258 struct intel_encoder_context *encoder_context)
260 struct object_surface *obj_surface;
262 /*Setup surfaces state*/
263 /* current picture for encoding */
264 obj_surface = encode_state->input_yuv_object;
265 gen75_vme_source_surface_state(ctx, 0, obj_surface, encoder_context);
266 gen75_vme_media_source_surface_state(ctx, 4, obj_surface, encoder_context);
267 gen75_vme_media_chroma_source_surface_state(ctx, 6, obj_surface, encoder_context);
270 VAEncSliceParameterBufferH264 *slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
273 slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type);
274 assert(slice_type != SLICE_TYPE_I && slice_type != SLICE_TYPE_SI);
276 intel_avc_vme_reference_state(ctx, encode_state, encoder_context, 0, 1, gen75_vme_source_surface_state);
278 if (slice_type == SLICE_TYPE_B)
279 intel_avc_vme_reference_state(ctx, encode_state, encoder_context, 1, 2, gen75_vme_source_surface_state);
283 gen75_vme_output_buffer_setup(ctx, encode_state, 3, encoder_context);
284 gen75_vme_output_vme_batchbuffer_setup(ctx, encode_state, 5, encoder_context);
285 intel_h264_setup_cost_surface(ctx, encode_state, encoder_context,
286 BINDING_TABLE_OFFSET(INTEL_COST_TABLE_OFFSET),
287 SURFACE_STATE_OFFSET(INTEL_COST_TABLE_OFFSET));
289 return VA_STATUS_SUCCESS;
292 static VAStatus gen75_vme_interface_setup(VADriverContextP ctx,
293 struct encode_state *encode_state,
294 struct intel_encoder_context *encoder_context)
296 struct gen6_vme_context *vme_context = encoder_context->vme_context;
297 struct gen6_interface_descriptor_data *desc;
301 bo = vme_context->gpe_context.idrt.bo;
306 for (i = 0; i < vme_context->vme_kernel_sum; i++) {
307 struct i965_kernel *kernel;
308 kernel = &vme_context->gpe_context.kernels[i];
309 assert(sizeof(*desc) == 32);
310 /*Setup the descritor table*/
311 memset(desc, 0, sizeof(*desc));
312 desc->desc0.kernel_start_pointer = (kernel->bo->offset >> 6);
313 desc->desc2.sampler_count = 0; /* FIXME: */
314 desc->desc2.sampler_state_pointer = 0;
315 desc->desc3.binding_table_entry_count = 1; /* FIXME: */
316 desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET(0) >> 5);
317 desc->desc4.constant_urb_entry_read_offset = 0;
318 desc->desc4.constant_urb_entry_read_length = CURBE_URB_ENTRY_LENGTH;
321 dri_bo_emit_reloc(bo,
322 I915_GEM_DOMAIN_INSTRUCTION, 0,
324 i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc0),
330 return VA_STATUS_SUCCESS;
333 static VAStatus gen75_vme_constant_setup(VADriverContextP ctx,
334 struct encode_state *encode_state,
335 struct intel_encoder_context *encoder_context,
338 struct gen6_vme_context *vme_context = encoder_context->vme_context;
339 unsigned char *constant_buffer;
340 unsigned int *vme_state_message;
343 vme_state_message = (unsigned int *)vme_context->vme_state_message;
345 if (encoder_context->codec == CODEC_H264 ||
346 encoder_context->codec == CODEC_H264_MVC) {
347 if (vme_context->h264_level >= 30) {
350 if (vme_context->h264_level >= 31)
353 } else if (encoder_context->codec == CODEC_MPEG2) {
357 vme_state_message[31] = mv_num;
359 dri_bo_map(vme_context->gpe_context.curbe.bo, 1);
360 assert(vme_context->gpe_context.curbe.bo->virtual);
361 constant_buffer = vme_context->gpe_context.curbe.bo->virtual;
363 /* VME MV/Mb cost table is passed by using const buffer */
364 /* Now it uses the fixed search path. So it is constructed directly
367 memcpy(constant_buffer, (char *)vme_context->vme_state_message, 128);
369 dri_bo_unmap(vme_context->gpe_context.curbe.bo);
371 return VA_STATUS_SUCCESS;
374 static const unsigned int intra_mb_mode_cost_table[] = {
375 0x31110001, // for qp0
376 0x09110001, // for qp1
377 0x15030001, // for qp2
378 0x0b030001, // for qp3
379 0x0d030011, // for qp4
380 0x17210011, // for qp5
381 0x41210011, // for qp6
382 0x19210011, // for qp7
383 0x25050003, // for qp8
384 0x1b130003, // for qp9
385 0x1d130003, // for qp10
386 0x27070021, // for qp11
387 0x51310021, // for qp12
388 0x29090021, // for qp13
389 0x35150005, // for qp14
390 0x2b0b0013, // for qp15
391 0x2d0d0013, // for qp16
392 0x37170007, // for qp17
393 0x61410031, // for qp18
394 0x39190009, // for qp19
395 0x45250015, // for qp20
396 0x3b1b000b, // for qp21
397 0x3d1d000d, // for qp22
398 0x47270017, // for qp23
399 0x71510041, // for qp24 ! center for qp=0..30
400 0x49290019, // for qp25
401 0x55350025, // for qp26
402 0x4b2b001b, // for qp27
403 0x4d2d001d, // for qp28
404 0x57370027, // for qp29
405 0x81610051, // for qp30
406 0x57270017, // for qp31
407 0x81510041, // for qp32 ! center for qp=31..51
408 0x59290019, // for qp33
409 0x65350025, // for qp34
410 0x5b2b001b, // for qp35
411 0x5d2d001d, // for qp36
412 0x67370027, // for qp37
413 0x91610051, // for qp38
414 0x69390029, // for qp39
415 0x75450035, // for qp40
416 0x6b3b002b, // for qp41
417 0x6d3d002d, // for qp42
418 0x77470037, // for qp43
419 0xa1710061, // for qp44
420 0x79490039, // for qp45
421 0x85550045, // for qp46
422 0x7b4b003b, // for qp47
423 0x7d4d003d, // for qp48
424 0x87570047, // for qp49
425 0xb1810071, // for qp50
426 0x89590049 // for qp51
429 static void gen75_vme_state_setup_fixup(VADriverContextP ctx,
430 struct encode_state *encode_state,
431 struct intel_encoder_context *encoder_context,
432 unsigned int *vme_state_message)
434 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
435 VAEncPictureParameterBufferH264 *pic_param = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
436 VAEncSliceParameterBufferH264 *slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
438 if (slice_param->slice_type != SLICE_TYPE_I &&
439 slice_param->slice_type != SLICE_TYPE_SI)
441 if (encoder_context->rate_control_mode == VA_RC_CQP)
442 vme_state_message[0] = intra_mb_mode_cost_table[pic_param->pic_init_qp + slice_param->slice_qp_delta];
444 vme_state_message[0] = intra_mb_mode_cost_table[mfc_context->brc.qp_prime_y[encoder_context->layer.curr_frame_layer_id][SLICE_TYPE_I]];
447 static VAStatus gen75_vme_vme_state_setup(VADriverContextP ctx,
448 struct encode_state *encode_state,
450 struct intel_encoder_context *encoder_context)
452 struct gen6_vme_context *vme_context = encoder_context->vme_context;
453 unsigned int *vme_state_message;
456 //pass the MV/Mb cost into VME message on HASWell
457 assert(vme_context->vme_state_message);
458 vme_state_message = (unsigned int *)vme_context->vme_state_message;
460 vme_state_message[0] = 0x4a4a4a4a;
461 vme_state_message[1] = 0x4a4a4a4a;
462 vme_state_message[2] = 0x4a4a4a4a;
463 vme_state_message[3] = 0x22120200;
464 vme_state_message[4] = 0x62524232;
466 for (i = 5; i < 8; i++) {
467 vme_state_message[i] = 0;
470 switch (encoder_context->codec) {
473 gen75_vme_state_setup_fixup(ctx, encode_state, encoder_context, vme_state_message);
482 return VA_STATUS_SUCCESS;
486 gen75_vme_fill_vme_batchbuffer(VADriverContextP ctx,
487 struct encode_state *encode_state,
488 int mb_width, int mb_height,
490 int transform_8x8_mode_flag,
491 struct intel_encoder_context *encoder_context)
493 struct gen6_vme_context *vme_context = encoder_context->vme_context;
494 int mb_x = 0, mb_y = 0;
496 unsigned int *command_ptr;
497 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
498 VAEncPictureParameterBufferH264 *pic_param = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
499 VAEncSliceParameterBufferH264 *slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
501 int slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type);
504 if (encoder_context->rate_control_mode == VA_RC_CQP)
505 qp = pic_param->pic_init_qp + slice_param->slice_qp_delta;
507 qp = mfc_context->brc.qp_prime_y[encoder_context->layer.curr_frame_layer_id][slice_type];
509 dri_bo_map(vme_context->vme_batchbuffer.bo, 1);
510 command_ptr = vme_context->vme_batchbuffer.bo->virtual;
512 for (s = 0; s < encode_state->num_slice_params_ext; s++) {
513 VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[s]->buffer;
514 int slice_mb_begin = pSliceParameter->macroblock_address;
515 int slice_mb_number = pSliceParameter->num_macroblocks;
516 unsigned int mb_intra_ub;
517 int slice_mb_x = pSliceParameter->macroblock_address % mb_width;
518 for (i = 0; i < slice_mb_number;) {
519 int mb_count = i + slice_mb_begin;
520 mb_x = mb_count % mb_width;
521 mb_y = mb_count / mb_width;
524 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_AE;
527 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_B;
529 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_D;
530 if (mb_x != (mb_width - 1))
531 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C;
535 mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_AE);
536 mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_BCD_MASK);
537 if ((i == (mb_width - 1)) && slice_mb_x) {
538 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C;
542 if ((i == mb_width) && slice_mb_x) {
543 mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_D);
545 *command_ptr++ = (CMD_MEDIA_OBJECT | (9 - 2));
546 *command_ptr++ = kernel;
553 *command_ptr++ = (mb_width << 16 | mb_y << 8 | mb_x);
554 *command_ptr++ = ((encoder_context->quality_level << 24) | (1 << 16) | transform_8x8_mode_flag | (mb_intra_ub << 8));
555 /* qp occupies one byte */
556 if (vme_context->roi_enabled) {
557 qp_index = mb_y * mb_width + mb_x;
558 qp_mb = *(vme_context->qp_per_mb + qp_index);
561 *command_ptr++ = qp_mb;
568 *command_ptr++ = MI_BATCH_BUFFER_END;
570 dri_bo_unmap(vme_context->vme_batchbuffer.bo);
573 static void gen75_vme_media_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
575 struct gen6_vme_context *vme_context = encoder_context->vme_context;
577 i965_gpe_context_init(ctx, &vme_context->gpe_context);
579 /* VME output buffer */
580 dri_bo_unreference(vme_context->vme_output.bo);
581 vme_context->vme_output.bo = NULL;
583 dri_bo_unreference(vme_context->vme_batchbuffer.bo);
584 vme_context->vme_batchbuffer.bo = NULL;
587 dri_bo_unreference(vme_context->vme_state.bo);
588 vme_context->vme_state.bo = NULL;
591 static void gen75_vme_pipeline_programing(VADriverContextP ctx,
592 struct encode_state *encode_state,
593 struct intel_encoder_context *encoder_context)
595 struct gen6_vme_context *vme_context = encoder_context->vme_context;
596 struct intel_batchbuffer *batch = encoder_context->base.batch;
597 VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
598 VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
599 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
600 int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
601 int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
603 bool allow_hwscore = true;
605 unsigned int is_low_quality = (encoder_context->quality_level == ENCODER_LOW_QUALITY);
608 allow_hwscore = false;
610 for (s = 0; s < encode_state->num_slice_params_ext; s++) {
611 pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[s]->buffer;
612 if ((pSliceParameter->macroblock_address % width_in_mbs)) {
613 allow_hwscore = false;
619 if ((pSliceParameter->slice_type == SLICE_TYPE_I) ||
620 (pSliceParameter->slice_type == SLICE_TYPE_SI)) {
621 kernel_shader = VME_INTRA_SHADER;
622 } else if ((pSliceParameter->slice_type == SLICE_TYPE_P) ||
623 (pSliceParameter->slice_type == SLICE_TYPE_SP)) {
624 kernel_shader = VME_INTER_SHADER;
626 kernel_shader = VME_BINTER_SHADER;
628 kernel_shader = VME_INTER_SHADER;
631 gen7_vme_walker_fill_vme_batchbuffer(ctx,
633 width_in_mbs, height_in_mbs,
635 pPicParameter->pic_fields.bits.transform_8x8_mode_flag,
638 gen75_vme_fill_vme_batchbuffer(ctx,
640 width_in_mbs, height_in_mbs,
642 pPicParameter->pic_fields.bits.transform_8x8_mode_flag,
645 intel_batchbuffer_start_atomic(batch, 0x1000);
646 gen6_gpe_pipeline_setup(ctx, &vme_context->gpe_context, batch);
647 BEGIN_BATCH(batch, 2);
648 OUT_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8));
650 vme_context->vme_batchbuffer.bo,
651 I915_GEM_DOMAIN_COMMAND, 0,
653 ADVANCE_BATCH(batch);
655 intel_batchbuffer_end_atomic(batch);
658 static VAStatus gen75_vme_prepare(VADriverContextP ctx,
659 struct encode_state *encode_state,
660 struct intel_encoder_context *encoder_context)
662 VAStatus vaStatus = VA_STATUS_SUCCESS;
663 VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
664 int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
665 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
666 struct gen6_vme_context *vme_context = encoder_context->vme_context;
668 if (!vme_context->h264_level ||
669 (vme_context->h264_level != pSequenceParameter->level_idc)) {
670 vme_context->h264_level = pSequenceParameter->level_idc;
673 intel_vme_update_mbmv_cost(ctx, encode_state, encoder_context);
674 intel_h264_initialize_mbmv_cost(ctx, encode_state, encoder_context);
675 intel_h264_enc_roi_config(ctx, encode_state, encoder_context);
677 /*Setup all the memory object*/
678 gen75_vme_surface_setup(ctx, encode_state, is_intra, encoder_context);
679 gen75_vme_interface_setup(ctx, encode_state, encoder_context);
680 //gen75_vme_vme_state_setup(ctx, encode_state, is_intra, encoder_context);
681 gen75_vme_constant_setup(ctx, encode_state, encoder_context, (pSliceParameter->slice_type == SLICE_TYPE_B) ? 2 : 1);
683 /*Programing media pipeline*/
684 gen75_vme_pipeline_programing(ctx, encode_state, encoder_context);
689 static VAStatus gen75_vme_run(VADriverContextP ctx,
690 struct encode_state *encode_state,
691 struct intel_encoder_context *encoder_context)
693 struct intel_batchbuffer *batch = encoder_context->base.batch;
695 intel_batchbuffer_flush(batch);
697 return VA_STATUS_SUCCESS;
700 static VAStatus gen75_vme_stop(VADriverContextP ctx,
701 struct encode_state *encode_state,
702 struct intel_encoder_context *encoder_context)
704 return VA_STATUS_SUCCESS;
708 gen75_vme_pipeline(VADriverContextP ctx,
710 struct encode_state *encode_state,
711 struct intel_encoder_context *encoder_context)
713 gen75_vme_media_init(ctx, encoder_context);
714 gen75_vme_prepare(ctx, encode_state, encoder_context);
715 gen75_vme_run(ctx, encode_state, encoder_context);
716 gen75_vme_stop(ctx, encode_state, encoder_context);
718 return VA_STATUS_SUCCESS;
722 gen75_vme_mpeg2_output_buffer_setup(VADriverContextP ctx,
723 struct encode_state *encode_state,
726 struct intel_encoder_context *encoder_context)
729 struct i965_driver_data *i965 = i965_driver_data(ctx);
730 struct gen6_vme_context *vme_context = encoder_context->vme_context;
731 VAEncSequenceParameterBufferMPEG2 *seq_param = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer;
732 int width_in_mbs = ALIGN(seq_param->picture_width, 16) / 16;
733 int height_in_mbs = ALIGN(seq_param->picture_height, 16) / 16;
735 vme_context->vme_output.num_blocks = width_in_mbs * height_in_mbs;
736 vme_context->vme_output.pitch = 16; /* in bytes, always 16 */
739 vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES * 2;
741 vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES * 24;
743 * Inter MV . 32-byte Intra search + 16 IME info + 128 IME MV + 32 IME Ref
744 * + 16 FBR Info + 128 FBR MV + 32 FBR Ref.
745 * 16 * (2 + 2 * (1 + 8 + 2))= 16 * 24.
748 vme_context->vme_output.bo = dri_bo_alloc(i965->intel.bufmgr,
750 vme_context->vme_output.num_blocks * vme_context->vme_output.size_block,
752 assert(vme_context->vme_output.bo);
753 vme_context->vme_buffer_suface_setup(ctx,
754 &vme_context->gpe_context,
755 &vme_context->vme_output,
756 BINDING_TABLE_OFFSET(index),
757 SURFACE_STATE_OFFSET(index));
761 gen75_vme_mpeg2_output_vme_batchbuffer_setup(VADriverContextP ctx,
762 struct encode_state *encode_state,
764 struct intel_encoder_context *encoder_context)
767 struct i965_driver_data *i965 = i965_driver_data(ctx);
768 struct gen6_vme_context *vme_context = encoder_context->vme_context;
769 VAEncSequenceParameterBufferMPEG2 *seq_param = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer;
770 int width_in_mbs = ALIGN(seq_param->picture_width, 16) / 16;
771 int height_in_mbs = ALIGN(seq_param->picture_height, 16) / 16;
773 vme_context->vme_batchbuffer.num_blocks = width_in_mbs * height_in_mbs + 1;
774 vme_context->vme_batchbuffer.size_block = 64; /* 4 OWORDs */
775 vme_context->vme_batchbuffer.pitch = 16;
776 vme_context->vme_batchbuffer.bo = dri_bo_alloc(i965->intel.bufmgr,
778 vme_context->vme_batchbuffer.num_blocks * vme_context->vme_batchbuffer.size_block,
780 vme_context->vme_buffer_suface_setup(ctx,
781 &vme_context->gpe_context,
782 &vme_context->vme_batchbuffer,
783 BINDING_TABLE_OFFSET(index),
784 SURFACE_STATE_OFFSET(index));
788 gen75_vme_mpeg2_surface_setup(VADriverContextP ctx,
789 struct encode_state *encode_state,
791 struct intel_encoder_context *encoder_context)
793 struct object_surface *obj_surface;
795 /*Setup surfaces state*/
796 /* current picture for encoding */
797 obj_surface = encode_state->input_yuv_object;
798 gen75_vme_source_surface_state(ctx, 0, obj_surface, encoder_context);
799 gen75_vme_media_source_surface_state(ctx, 4, obj_surface, encoder_context);
800 gen75_vme_media_chroma_source_surface_state(ctx, 6, obj_surface, encoder_context);
804 obj_surface = encode_state->reference_objects[0];
805 if (obj_surface->bo != NULL)
806 gen75_vme_source_surface_state(ctx, 1, obj_surface, encoder_context);
809 obj_surface = encode_state->reference_objects[1];
810 if (obj_surface && obj_surface->bo != NULL)
811 gen75_vme_source_surface_state(ctx, 2, obj_surface, encoder_context);
815 gen75_vme_mpeg2_output_buffer_setup(ctx, encode_state, 3, is_intra, encoder_context);
816 gen75_vme_mpeg2_output_vme_batchbuffer_setup(ctx, encode_state, 5, encoder_context);
818 return VA_STATUS_SUCCESS;
822 gen75_vme_mpeg2_fill_vme_batchbuffer(VADriverContextP ctx,
823 struct encode_state *encode_state,
824 int mb_width, int mb_height,
826 int transform_8x8_mode_flag,
827 struct intel_encoder_context *encoder_context)
829 struct gen6_vme_context *vme_context = encoder_context->vme_context;
830 int mb_x = 0, mb_y = 0;
832 unsigned int *command_ptr;
835 dri_bo_map(vme_context->vme_batchbuffer.bo, 1);
836 command_ptr = vme_context->vme_batchbuffer.bo->virtual;
838 for (s = 0; s < encode_state->num_slice_params_ext; s++) {
839 VAEncSliceParameterBufferMPEG2 *slice_param = (VAEncSliceParameterBufferMPEG2 *)encode_state->slice_params_ext[s]->buffer;
841 for (j = 0; j < encode_state->slice_params_ext[s]->num_elements; j++) {
842 int slice_mb_begin = slice_param->macroblock_address;
843 int slice_mb_number = slice_param->num_macroblocks;
844 unsigned int mb_intra_ub;
845 int slice_mb_x = slice_param->macroblock_address % mb_width;
847 for (i = 0; i < slice_mb_number;) {
848 int mb_count = i + slice_mb_begin;
850 mb_x = mb_count % mb_width;
851 mb_y = mb_count / mb_width;
855 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_AE;
859 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_B;
862 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_D;
864 if (mb_x != (mb_width - 1))
865 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C;
870 mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_AE);
872 mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_BCD_MASK);
874 if ((i == (mb_width - 1)) && slice_mb_x) {
875 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C;
879 if ((i == mb_width) && slice_mb_x) {
880 mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_D);
883 *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2));
884 *command_ptr++ = kernel;
891 *command_ptr++ = (mb_width << 16 | mb_y << 8 | mb_x);
892 *command_ptr++ = ((1 << 16) | transform_8x8_mode_flag | (mb_intra_ub << 8));
902 *command_ptr++ = MI_BATCH_BUFFER_END;
904 dri_bo_unmap(vme_context->vme_batchbuffer.bo);
908 gen75_vme_mpeg2_pipeline_programing(VADriverContextP ctx,
909 struct encode_state *encode_state,
911 struct intel_encoder_context *encoder_context)
913 struct gen6_vme_context *vme_context = encoder_context->vme_context;
914 struct intel_batchbuffer *batch = encoder_context->base.batch;
915 VAEncPictureParameterBufferMPEG2 *pic_param = NULL;
916 VAEncSequenceParameterBufferMPEG2 *seq_param = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer;
917 int width_in_mbs = ALIGN(seq_param->picture_width, 16) / 16;
918 int height_in_mbs = ALIGN(seq_param->picture_height, 16) / 16;
919 bool allow_hwscore = true;
923 pic_param = (VAEncPictureParameterBufferMPEG2 *)encode_state->pic_param_ext->buffer;
925 for (s = 0; s < encode_state->num_slice_params_ext; s++) {
927 VAEncSliceParameterBufferMPEG2 *slice_param = (VAEncSliceParameterBufferMPEG2 *)encode_state->slice_params_ext[s]->buffer;
929 for (j = 0; j < encode_state->slice_params_ext[s]->num_elements; j++) {
930 if (slice_param->macroblock_address % width_in_mbs) {
931 allow_hwscore = false;
937 pic_param = (VAEncPictureParameterBufferMPEG2 *)encode_state->pic_param_ext->buffer;
938 if (pic_param->picture_type == VAEncPictureTypeIntra) {
939 allow_hwscore = false;
940 kernel_shader = VME_INTRA_SHADER;
942 kernel_shader = VME_INTER_SHADER;
946 gen7_vme_mpeg2_walker_fill_vme_batchbuffer(ctx,
948 width_in_mbs, height_in_mbs,
952 gen75_vme_mpeg2_fill_vme_batchbuffer(ctx,
954 width_in_mbs, height_in_mbs,
959 intel_batchbuffer_start_atomic(batch, 0x1000);
960 gen6_gpe_pipeline_setup(ctx, &vme_context->gpe_context, batch);
961 BEGIN_BATCH(batch, 2);
962 OUT_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8));
964 vme_context->vme_batchbuffer.bo,
965 I915_GEM_DOMAIN_COMMAND, 0,
967 ADVANCE_BATCH(batch);
969 intel_batchbuffer_end_atomic(batch);
973 gen75_vme_mpeg2_prepare(VADriverContextP ctx,
974 struct encode_state *encode_state,
975 struct intel_encoder_context *encoder_context)
977 VAStatus vaStatus = VA_STATUS_SUCCESS;
978 VAEncSliceParameterBufferMPEG2 *slice_param = (VAEncSliceParameterBufferMPEG2 *)encode_state->slice_params_ext[0]->buffer;
980 VAEncSequenceParameterBufferMPEG2 *seq_param = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer;
981 struct gen6_vme_context *vme_context = encoder_context->vme_context;
983 if ((!vme_context->mpeg2_level) ||
984 (vme_context->mpeg2_level != (seq_param->sequence_extension.bits.profile_and_level_indication & MPEG2_LEVEL_MASK))) {
985 vme_context->mpeg2_level = seq_param->sequence_extension.bits.profile_and_level_indication & MPEG2_LEVEL_MASK;
988 /*Setup all the memory object*/
989 gen75_vme_mpeg2_surface_setup(ctx, encode_state, slice_param->is_intra_slice, encoder_context);
990 gen75_vme_interface_setup(ctx, encode_state, encoder_context);
991 gen75_vme_vme_state_setup(ctx, encode_state, slice_param->is_intra_slice, encoder_context);
992 intel_vme_mpeg2_state_setup(ctx, encode_state, encoder_context);
993 gen75_vme_constant_setup(ctx, encode_state, encoder_context, 1);
995 /*Programing media pipeline*/
996 gen75_vme_mpeg2_pipeline_programing(ctx, encode_state, slice_param->is_intra_slice, encoder_context);
1002 gen75_vme_mpeg2_pipeline(VADriverContextP ctx,
1004 struct encode_state *encode_state,
1005 struct intel_encoder_context *encoder_context)
1007 gen75_vme_media_init(ctx, encoder_context);
1008 gen75_vme_mpeg2_prepare(ctx, encode_state, encoder_context);
1009 gen75_vme_run(ctx, encode_state, encoder_context);
1010 gen75_vme_stop(ctx, encode_state, encoder_context);
1012 return VA_STATUS_SUCCESS;
1016 gen75_vme_context_destroy(void *context)
1018 struct gen6_vme_context *vme_context = context;
1020 i965_gpe_context_destroy(&vme_context->gpe_context);
1022 dri_bo_unreference(vme_context->vme_output.bo);
1023 vme_context->vme_output.bo = NULL;
1025 dri_bo_unreference(vme_context->vme_state.bo);
1026 vme_context->vme_state.bo = NULL;
1028 dri_bo_unreference(vme_context->vme_batchbuffer.bo);
1029 vme_context->vme_batchbuffer.bo = NULL;
1031 free(vme_context->vme_state_message);
1032 vme_context->vme_state_message = NULL;
1034 dri_bo_unreference(vme_context->i_qp_cost_table);
1035 vme_context->i_qp_cost_table = NULL;
1037 dri_bo_unreference(vme_context->p_qp_cost_table);
1038 vme_context->p_qp_cost_table = NULL;
1040 dri_bo_unreference(vme_context->b_qp_cost_table);
1041 vme_context->b_qp_cost_table = NULL;
1043 free(vme_context->qp_per_mb);
1044 vme_context->qp_per_mb = NULL;
1049 Bool gen75_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
1051 struct gen6_vme_context *vme_context = calloc(1, sizeof(struct gen6_vme_context));
1052 struct i965_kernel *vme_kernel_list = NULL;
1053 int i965_kernel_num;
1055 switch (encoder_context->codec) {
1057 case CODEC_H264_MVC:
1058 vme_kernel_list = gen75_vme_kernels;
1059 encoder_context->vme_pipeline = gen75_vme_pipeline;
1060 i965_kernel_num = sizeof(gen75_vme_kernels) / sizeof(struct i965_kernel);
1064 vme_kernel_list = gen75_vme_mpeg2_kernels;
1065 encoder_context->vme_pipeline = gen75_vme_mpeg2_pipeline;
1066 i965_kernel_num = sizeof(gen75_vme_mpeg2_kernels) / sizeof(struct i965_kernel);
1071 /* never get here */
1077 assert(vme_context);
1078 vme_context->vme_kernel_sum = i965_kernel_num;
1079 vme_context->gpe_context.surface_state_binding_table.length = (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6;
1081 vme_context->gpe_context.idrt.max_entries = MAX_INTERFACE_DESC_GEN6;
1082 vme_context->gpe_context.idrt.entry_size = sizeof(struct gen6_interface_descriptor_data);
1084 vme_context->gpe_context.curbe.length = CURBE_TOTAL_DATA_LENGTH;
1086 vme_context->gpe_context.vfe_state.max_num_threads = 60 - 1;
1087 vme_context->gpe_context.vfe_state.num_urb_entries = 64;
1088 vme_context->gpe_context.vfe_state.gpgpu_mode = 0;
1089 vme_context->gpe_context.vfe_state.urb_entry_size = 16;
1090 vme_context->gpe_context.vfe_state.curbe_allocation_size = CURBE_ALLOCATION_SIZE - 1;
1092 gen7_vme_scoreboard_init(ctx, vme_context);
1094 i965_gpe_load_kernels(ctx,
1095 &vme_context->gpe_context,
1098 vme_context->vme_surface2_setup = gen7_gpe_surface2_setup;
1099 vme_context->vme_media_rw_surface_setup = gen7_gpe_media_rw_surface_setup;
1100 vme_context->vme_buffer_suface_setup = gen7_gpe_buffer_suface_setup;
1101 vme_context->vme_media_chroma_surface_setup = gen75_gpe_media_chroma_surface_setup;
1103 encoder_context->vme_context = vme_context;
1104 encoder_context->vme_context_destroy = gen75_vme_context_destroy;
1106 vme_context->vme_state_message = malloc(VME_MSG_LENGTH * sizeof(int));