2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Li Xiaowei <xiaowei.a.li@intel.com>
34 #include "intel_batchbuffer.h"
35 #include "intel_driver.h"
36 #include "i965_defines.h"
37 #include "i965_structs.h"
38 #include "gen75_vpp_vebox.h"
39 #include "intel_media.h"
44 i965_MapBuffer(VADriverContextP ctx, VABufferID buf_id, void **);
47 i965_UnmapBuffer(VADriverContextP ctx, VABufferID buf_id);
50 i965_DeriveImage(VADriverContextP ctx, VABufferID surface, VAImage *out_image);
53 i965_DestroyImage(VADriverContextP ctx, VAImageID image);
56 i965_DestroySurfaces(VADriverContextP ctx,
57 VASurfaceID *surface_list,
61 i965_CreateSurfaces(VADriverContextP ctx,
66 VASurfaceID *surfaces);
68 VAStatus vpp_surface_convert(VADriverContextP ctx,
69 struct object_surface *src_obj_surf,
70 struct object_surface *dst_obj_surf)
72 VAStatus va_status = VA_STATUS_SUCCESS;
74 assert(src_obj_surf->orig_width == dst_obj_surf->orig_width);
75 assert(src_obj_surf->orig_height == dst_obj_surf->orig_height);
77 VARectangle src_rect, dst_rect;
78 src_rect.x = dst_rect.x = 0;
79 src_rect.y = dst_rect.y = 0;
80 src_rect.width = dst_rect.width = src_obj_surf->orig_width;
81 src_rect.height = dst_rect.height = dst_obj_surf->orig_height;
83 struct i965_surface src_surface, dst_surface;
84 src_surface.base = (struct object_base *)src_obj_surf;
85 src_surface.type = I965_SURFACE_TYPE_SURFACE;
86 src_surface.flags = I965_SURFACE_FLAG_FRAME;
88 dst_surface.base = (struct object_base *)dst_obj_surf;
89 dst_surface.type = I965_SURFACE_TYPE_SURFACE;
90 dst_surface.flags = I965_SURFACE_FLAG_FRAME;
92 va_status = i965_image_processing(ctx,
100 VAStatus vpp_surface_scaling(VADriverContextP ctx,
101 struct object_surface *dst_obj_surf,
102 struct object_surface *src_obj_surf)
104 VAStatus va_status = VA_STATUS_SUCCESS;
105 int flags = I965_PP_FLAG_AVS;
107 assert(src_obj_surf->fourcc == VA_FOURCC('N','V','1','2'));
108 assert(dst_obj_surf->fourcc == VA_FOURCC('N','V','1','2'));
110 VARectangle src_rect, dst_rect;
113 src_rect.width = src_obj_surf->orig_width;
114 src_rect.height = src_obj_surf->orig_height;
118 dst_rect.width = dst_obj_surf->orig_width;
119 dst_rect.height = dst_obj_surf->orig_height;
121 va_status = i965_scaling_processing(ctx,
131 void hsw_veb_dndi_table(VADriverContextP ctx, struct intel_vebox_context *proc_ctx)
133 unsigned int* p_table ;
135 VAProcFilterParameterBufferDeinterlacing *di_param =
136 (VAProcFilterParameterBufferDeinterlacing *) proc_ctx->filter_di;
138 VAProcFilterParameterBuffer * dn_param =
139 (VAProcFilterParameterBuffer *) proc_ctx->filter_dn;
141 p_table = (unsigned int *)proc_ctx->dndi_state_table.ptr;
143 *p_table ++ = 0; // reserved . w0
144 *p_table ++ = ( 0 << 24 | // denoise STAD threshold . w1
145 128 << 16 | // dnmh_history_max
146 0 << 12 | // reserved
147 8 << 8 | // dnmh_delta[3:0]
148 0 ); // denoise ASD threshold
150 *p_table ++ = ( 0 << 30 | // reserved . w2
151 16 << 24 | // temporal diff th
152 0 << 22 | // reserved.
153 8 << 16 | // low temporal diff th
155 0 << 8 | // denoise moving pixel th
156 64 ); // denoise th for sum of complexity measure
158 *p_table ++ = ( 0 << 30 | // reserved . w3
159 4 << 24 | // good neighbor th[5:0]
160 9 << 20 | // CAT slope minus 1
161 5 << 16 | // SAD Tight in
162 0 << 14 | // smooth mv th
163 0 << 12 | // reserved
164 1 << 8 | // bne_edge_th[3:0]
165 15 ); // block noise estimate noise th
167 *p_table ++ = ( 0 << 31 | // STMM blending constant select. w4
168 64 << 24 | // STMM trc1
169 0 << 16 | // STMM trc2
170 0 << 14 | // reserved
172 128 ); // maximum STMM
174 *p_table ++ = ( 0 << 24 | // minumum STMM . W5
175 0 << 22 | // STMM shift down
176 0 << 20 | // STMM shift up
177 7 << 16 | // STMM output shift
178 128 << 8 | // SDI threshold
181 *p_table ++ = ( 0 << 24 | // SDI fallback mode 1 T1 constant . W6
182 0 << 16 | // SDI fallback mode 1 T2 constant
183 0 << 8 | // SDI fallback mode 2 constant(angle2x1)
184 0 ); // FMD temporal difference threshold
186 *p_table ++ = ( 32 << 24 | // FMD #1 vertical difference th . w7
187 32 << 16 | // FMD #2 vertical difference th
189 32 << 8 | // FMD tear threshold
190 0 << 7 | // MCDI Enable, use motion compensated deinterlace algorithm
191 0 << 6 | // progressive DN
193 0 << 3 | // DN/DI Top First
196 *p_table ++ = ( 0 << 29 | // reserved . W8
197 0 << 23 | // dnmh_history_init[5:0]
198 10 << 19 | // neighborPixel th
199 0 << 18 | // reserved
200 0 << 16 | // FMD for 2nd field of previous frame
201 25 << 10 | // MC pixel consistency th
202 0 << 8 | // FMD for 1st field for current frame
206 *p_table ++ = ( 0 << 24 | // reserved
207 0 << 16 | // chr_dnmh_stad_th
208 0 << 13 | // reserved
209 0 << 12 | // chrome denoise enable
210 0 << 6 | // chr temp diff th
211 0 ); // chr temp diff low
215 void hsw_veb_iecp_std_table(VADriverContextP ctx, struct intel_vebox_context *proc_ctx)
217 unsigned int *p_table = proc_ctx->iecp_state_table.ptr + 0 ;
218 //VAProcFilterParameterBuffer * std_param =
219 // (VAProcFilterParameterBuffer *) proc_ctx->filter_std;
221 if(!(proc_ctx->filters_mask & VPP_IECP_STD_STE)){
222 memset(p_table, 0, 29 * 4);
224 *p_table ++ = 0x9a6e39f0;
225 *p_table ++ = 0x400c0000;
226 *p_table ++ = 0x00001180;
227 *p_table ++ = 0xfe2f2e00;
228 *p_table ++ = 0x000000ff;
230 *p_table ++ = 0x00140000;
231 *p_table ++ = 0xd82e0000;
232 *p_table ++ = 0x8285ecec;
233 *p_table ++ = 0x00008282;
234 *p_table ++ = 0x00000000;
236 *p_table ++ = 0x02117000;
237 *p_table ++ = 0xa38fec96;
238 *p_table ++ = 0x0000c8c8;
239 *p_table ++ = 0x00000000;
240 *p_table ++ = 0x01478000;
242 *p_table ++ = 0x0007c306;
243 *p_table ++ = 0x00000000;
244 *p_table ++ = 0x00000000;
245 *p_table ++ = 0x1c1bd000;
246 *p_table ++ = 0x00000000;
248 *p_table ++ = 0x00000000;
249 *p_table ++ = 0x00000000;
250 *p_table ++ = 0x0007cf80;
251 *p_table ++ = 0x00000000;
252 *p_table ++ = 0x00000000;
254 *p_table ++ = 0x1c080000;
255 *p_table ++ = 0x00000000;
256 *p_table ++ = 0x00000000;
257 *p_table ++ = 0x00000000;
261 void hsw_veb_iecp_ace_table(VADriverContextP ctx, struct intel_vebox_context *proc_ctx)
263 unsigned int *p_table = (unsigned int*)(proc_ctx->iecp_state_table.ptr + 116);
265 if(!(proc_ctx->filters_mask & VPP_IECP_ACE)){
266 memset(p_table, 0, 13 * 4);
268 *p_table ++ = 0x00000068;
269 *p_table ++ = 0x4c382410;
270 *p_table ++ = 0x9c887460;
271 *p_table ++ = 0xebd8c4b0;
272 *p_table ++ = 0x604c3824;
274 *p_table ++ = 0xb09c8874;
275 *p_table ++ = 0x0000d8c4;
276 *p_table ++ = 0x00000000;
277 *p_table ++ = 0x00000000;
278 *p_table ++ = 0x00000000;
280 *p_table ++ = 0x00000000;
281 *p_table ++ = 0x00000000;
282 *p_table ++ = 0x00000000;
286 void hsw_veb_iecp_tcc_table(VADriverContextP ctx, struct intel_vebox_context *proc_ctx)
288 unsigned int *p_table = (unsigned int*)(proc_ctx->iecp_state_table.ptr + 168);
289 // VAProcFilterParameterBuffer * tcc_param =
290 // (VAProcFilterParameterBuffer *) proc_ctx->filter_iecp_tcc;
292 if(!(proc_ctx->filters_mask & VPP_IECP_TCC)){
293 memset(p_table, 0, 11 * 4);
295 *p_table ++ = 0x00000000;
296 *p_table ++ = 0x00000000;
297 *p_table ++ = 0x1e34cc91;
298 *p_table ++ = 0x3e3cce91;
299 *p_table ++ = 0x02e80195;
301 *p_table ++ = 0x0197046b;
302 *p_table ++ = 0x01790174;
303 *p_table ++ = 0x00000000;
304 *p_table ++ = 0x00000000;
305 *p_table ++ = 0x03030000;
307 *p_table ++ = 0x009201c0;
311 void hsw_veb_iecp_pro_amp_table(VADriverContextP ctx, struct intel_vebox_context *proc_ctx)
313 unsigned int contrast = 0x80; //default
314 int brightness = 0x00; //default
315 int cos_c_s = 256 ; //default
316 int sin_c_s = 0; //default
317 unsigned int *p_table = (unsigned int*)(proc_ctx->iecp_state_table.ptr + 212);
319 if(!(proc_ctx->filters_mask & VPP_IECP_PRO_AMP)){
320 memset(p_table, 0, 2 * 4);
322 float src_saturation = 1.0;
324 float src_contrast = 1.0;
325 float src_brightness = 0.0;
326 float tmp_value = 0.0;
329 VAProcFilterParameterBufferColorBalance * amp_params =
330 (VAProcFilterParameterBufferColorBalance *) proc_ctx->filter_iecp_amp;
332 for (i = 0; i < proc_ctx->filter_iecp_amp_num_elements; i++){
333 VAProcColorBalanceType attrib = amp_params[i].attrib;
335 if(attrib == VAProcColorBalanceHue) {
336 src_hue = amp_params[i].value; //(-180.0, 180.0)
337 }else if(attrib == VAProcColorBalanceSaturation) {
338 src_saturation = amp_params[i].value; //(0.0, 10.0)
339 }else if(attrib == VAProcColorBalanceBrightness) {
340 src_brightness = amp_params[i].value; // (-100.0, 100.0)
341 brightness = intel_format_convert(src_brightness, 7, 4, 1);
342 }else if(attrib == VAProcColorBalanceContrast) {
343 src_contrast = amp_params[i].value; // (0.0, 10.0)
344 contrast = intel_format_convert(src_contrast, 4, 7, 0);
348 tmp_value = cos(src_hue/180*PI) * src_contrast * src_saturation;
349 cos_c_s = intel_format_convert(tmp_value, 7, 8, 1);
351 tmp_value = sin(src_hue/180*PI) * src_contrast * src_saturation;
352 sin_c_s = intel_format_convert(tmp_value, 7, 8, 1);
354 *p_table ++ = ( 0 << 28 | //reserved
355 contrast << 17 | //contrast value (U4.7 format)
357 brightness << 1| // S7.4 format
360 *p_table ++ = ( cos_c_s << 16 | // cos(h) * contrast * saturation
361 sin_c_s); // sin(h) * contrast * saturation
367 void hsw_veb_iecp_csc_table(VADriverContextP ctx, struct intel_vebox_context *proc_ctx)
369 unsigned int *p_table = (unsigned int*)(proc_ctx->iecp_state_table.ptr + 220);
370 float tran_coef[9] = {1.0, 0.0, 0.0, 0.0, 1.0, 0.0, 0.0, 0.0, 1.0};
371 float v_coef[3] = {0.0, 0.0, 0.0};
372 float u_coef[3] = {0.0, 0.0, 0.0};
373 int is_transform_enabled = 0;
375 if(!(proc_ctx->filters_mask & VPP_IECP_CSC)){
376 memset(p_table, 0, 8 * 4);
380 if(proc_ctx->fourcc_input == VA_FOURCC('R','G','B','A') &&
381 (proc_ctx->fourcc_output == VA_FOURCC('N','V','1','2') ||
382 proc_ctx->fourcc_output == VA_FOURCC('Y','V','1','2') ||
383 proc_ctx->fourcc_output == VA_FOURCC('Y','V','Y','2') ||
384 proc_ctx->fourcc_output == VA_FOURCC('A','Y','U','V'))) {
386 tran_coef[0] = 0.257;
387 tran_coef[1] = 0.504;
388 tran_coef[2] = 0.098;
389 tran_coef[3] = -0.148;
390 tran_coef[4] = -0.291;
391 tran_coef[5] = 0.439;
392 tran_coef[6] = 0.439;
393 tran_coef[7] = -0.368;
394 tran_coef[8] = -0.071;
400 is_transform_enabled = 1;
401 }else if((proc_ctx->fourcc_input == VA_FOURCC('N','V','1','2') ||
402 proc_ctx->fourcc_input == VA_FOURCC('Y','V','1','2') ||
403 proc_ctx->fourcc_input == VA_FOURCC('Y','U','Y','2') ||
404 proc_ctx->fourcc_input == VA_FOURCC('A','Y','U','V'))&&
405 proc_ctx->fourcc_output == VA_FOURCC('R','G','B','A')) {
407 tran_coef[0] = 1.164;
408 tran_coef[1] = 0.000;
409 tran_coef[2] = 1.569;
410 tran_coef[3] = 1.164;
411 tran_coef[4] = -0.813;
412 tran_coef[5] = -0.392;
413 tran_coef[6] = 1.164;
414 tran_coef[7] = 2.017;
415 tran_coef[8] = 0.000;
418 v_coef[1] = -128 * 4;
419 v_coef[2] = -128 * 4;
421 is_transform_enabled = 1;
422 }else if(proc_ctx->fourcc_input != proc_ctx->fourcc_output){
423 //enable when input and output format are different.
424 is_transform_enabled = 1;
427 if(is_transform_enabled == 0){
428 memset(p_table, 0, 8 * 4);
430 *p_table ++ = ( 0 << 29 | //reserved
431 intel_format_convert(tran_coef[1], 2, 10, 1) << 16 | //c1, s2.10 format
432 intel_format_convert(tran_coef[0], 2, 10, 1) << 3 | //c0, s2.10 format
434 0 << 1 | // yuv_channel swap
435 is_transform_enabled);
437 *p_table ++ = ( 0 << 26 | //reserved
438 intel_format_convert(tran_coef[3], 2, 10, 1) << 13 |
439 intel_format_convert(tran_coef[2], 2, 10, 1));
441 *p_table ++ = ( 0 << 26 | //reserved
442 intel_format_convert(tran_coef[5], 2, 10, 1) << 13 |
443 intel_format_convert(tran_coef[4], 2, 10, 1));
445 *p_table ++ = ( 0 << 26 | //reserved
446 intel_format_convert(tran_coef[7], 2, 10, 1) << 13 |
447 intel_format_convert(tran_coef[6], 2, 10, 1));
449 *p_table ++ = ( 0 << 13 | //reserved
450 intel_format_convert(tran_coef[8], 2, 10, 1));
452 *p_table ++ = ( 0 << 22 | //reserved
453 intel_format_convert(u_coef[0], 10, 0, 1) << 11 |
454 intel_format_convert(v_coef[0], 10, 0, 1));
456 *p_table ++ = ( 0 << 22 | //reserved
457 intel_format_convert(u_coef[1], 10, 0, 1) << 11 |
458 intel_format_convert(v_coef[1], 10, 0, 1));
460 *p_table ++ = ( 0 << 22 | //reserved
461 intel_format_convert(u_coef[2], 10, 0, 1) << 11 |
462 intel_format_convert(v_coef[2], 10, 0, 1));
466 void hsw_veb_iecp_aoi_table(VADriverContextP ctx, struct intel_vebox_context *proc_ctx)
468 unsigned int *p_table = (unsigned int*)(proc_ctx->iecp_state_table.ptr + 252);
469 // VAProcFilterParameterBuffer * tcc_param =
470 // (VAProcFilterParameterBuffer *) proc_ctx->filter_iecp_tcc;
472 if(!(proc_ctx->filters_mask & VPP_IECP_AOI)){
473 memset(p_table, 0, 3 * 4);
475 *p_table ++ = 0x00000000;
476 *p_table ++ = 0x00030000;
477 *p_table ++ = 0x00030000;
481 void hsw_veb_state_table_setup(VADriverContextP ctx, struct intel_vebox_context *proc_ctx)
483 if(proc_ctx->filters_mask & 0x000000ff) {
484 dri_bo *dndi_bo = proc_ctx->dndi_state_table.bo;
485 dri_bo_map(dndi_bo, 1);
486 proc_ctx->dndi_state_table.ptr = dndi_bo->virtual;
488 hsw_veb_dndi_table(ctx, proc_ctx);
490 dri_bo_unmap(dndi_bo);
493 if(proc_ctx->filters_mask & 0x0000ff00) {
494 dri_bo *iecp_bo = proc_ctx->iecp_state_table.bo;
495 dri_bo_map(iecp_bo, 1);
496 proc_ctx->iecp_state_table.ptr = iecp_bo->virtual;
498 hsw_veb_iecp_std_table(ctx, proc_ctx);
499 hsw_veb_iecp_ace_table(ctx, proc_ctx);
500 hsw_veb_iecp_tcc_table(ctx, proc_ctx);
501 hsw_veb_iecp_pro_amp_table(ctx, proc_ctx);
502 hsw_veb_iecp_csc_table(ctx, proc_ctx);
503 hsw_veb_iecp_aoi_table(ctx, proc_ctx);
505 dri_bo_unmap(iecp_bo);
509 void hsw_veb_state_command(VADriverContextP ctx, struct intel_vebox_context *proc_ctx)
511 struct intel_batchbuffer *batch = proc_ctx->batch;
512 unsigned int is_dn_enabled = (proc_ctx->filters_mask & 0x01)? 1: 0;
513 unsigned int is_di_enabled = (proc_ctx->filters_mask & 0x02)? 1: 0;
514 unsigned int is_iecp_enabled = (proc_ctx->filters_mask & 0xff00)?1:0;
516 if(proc_ctx->fourcc_input != proc_ctx->fourcc_output ||
517 (is_dn_enabled == 0 && is_di_enabled == 0)){
521 BEGIN_VEB_BATCH(batch, 6);
522 OUT_VEB_BATCH(batch, VEB_STATE | (6 - 2));
524 0 << 26 | // state surface control bits
525 0 << 11 | // reserved.
526 0 << 10 | // pipe sync disable
527 2 << 8 | // DI output frame
528 0 << 7 | // 444->422 downsample method
529 0 << 6 | // 422->420 downsample method
530 !!(proc_ctx->is_first_frame && (is_di_enabled || is_dn_enabled)) << 5 | // DN/DI first frame
531 is_di_enabled << 4 | // DI enable
532 is_dn_enabled << 3 | // DN enable
533 is_iecp_enabled << 2 | // global IECP enabled
534 0 << 1 | // ColorGamutCompressionEnable
535 0 ) ; // ColorGamutExpansionEnable.
538 proc_ctx->dndi_state_table.bo,
539 I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
542 proc_ctx->iecp_state_table.bo,
543 I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
546 proc_ctx->gamut_state_table.bo,
547 I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
550 proc_ctx->vertex_state_table.bo,
551 I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
553 ADVANCE_VEB_BATCH(batch);
556 void hsw_veb_surface_state(VADriverContextP ctx, struct intel_vebox_context *proc_ctx, unsigned int is_output)
558 struct intel_batchbuffer *batch = proc_ctx->batch;
559 unsigned int u_offset_y = 0, v_offset_y = 0;
560 unsigned int is_uv_interleaved = 0, tiling = 0, swizzle = 0;
561 unsigned int surface_format = PLANAR_420_8;
562 struct object_surface* obj_surf = NULL;
563 unsigned int surface_pitch = 0;
564 unsigned int half_pitch_chroma = 0;
567 obj_surf = proc_ctx->frame_store[FRAME_OUT_CURRENT].obj_surface;
569 obj_surf = proc_ctx->frame_store[FRAME_IN_CURRENT].obj_surface;
572 assert(obj_surf->fourcc == VA_FOURCC_NV12 ||
573 obj_surf->fourcc == VA_FOURCC_YUY2 ||
574 obj_surf->fourcc == VA_FOURCC_AYUV ||
575 obj_surf->fourcc == VA_FOURCC_RGBA);
577 if (obj_surf->fourcc == VA_FOURCC_NV12) {
578 surface_format = PLANAR_420_8;
579 surface_pitch = obj_surf->width;
580 is_uv_interleaved = 1;
581 half_pitch_chroma = 0;
582 } else if (obj_surf->fourcc == VA_FOURCC_YUY2) {
583 surface_format = YCRCB_NORMAL;
584 surface_pitch = obj_surf->width * 2;
585 is_uv_interleaved = 0;
586 half_pitch_chroma = 0;
587 } else if (obj_surf->fourcc == VA_FOURCC_AYUV) {
588 surface_format = PACKED_444A_8;
589 surface_pitch = obj_surf->width * 4;
590 is_uv_interleaved = 0;
591 half_pitch_chroma = 0;
592 } else if (obj_surf->fourcc == VA_FOURCC_RGBA) {
593 surface_format = R8G8B8A8_UNORM_SRGB;
594 surface_pitch = obj_surf->width * 4;
595 is_uv_interleaved = 0;
596 half_pitch_chroma = 0;
599 u_offset_y = obj_surf->y_cb_offset;
600 v_offset_y = obj_surf->y_cr_offset;
602 dri_bo_get_tiling(obj_surf->bo, &tiling, &swizzle);
604 BEGIN_VEB_BATCH(batch, 6);
605 OUT_VEB_BATCH(batch, VEB_SURFACE_STATE | (6 - 2));
608 is_output); // surface indentification.
611 (proc_ctx->height_input - 1) << 18 | // height . w3
612 (proc_ctx->width_input) << 4 | // width
616 surface_format << 28 | // surface format, YCbCr420. w4
617 is_uv_interleaved << 27 | // interleave chrome , two seperate palar
618 0 << 20 | // reserved
619 (surface_pitch - 1) << 3 | // surface pitch, 64 align
620 half_pitch_chroma << 2 | // half pitch for chrome
621 !!tiling << 1 | // tiled surface, linear surface used
622 (tiling == I915_TILING_Y)); // tiled walk, ignored when liner surface
625 0 << 29 | // reserved . w5
626 0 << 16 | // X offset for V(Cb)
627 0 << 15 | // reserved
628 u_offset_y); // Y offset for V(Cb)
631 0 << 29 | // reserved . w6
632 0 << 16 | // X offset for V(Cr)
633 0 << 15 | // reserved
634 v_offset_y ); // Y offset for V(Cr)
636 ADVANCE_VEB_BATCH(batch);
639 void hsw_veb_dndi_iecp_command(VADriverContextP ctx, struct intel_vebox_context *proc_ctx)
641 struct intel_batchbuffer *batch = proc_ctx->batch;
642 unsigned char frame_ctrl_bits = 0;
643 unsigned int startingX = 0;
644 unsigned int endingX = proc_ctx->width_input;
646 /* s1:update the previous and current input */
647 /* tempFrame = proc_ctx->frame_store[FRAME_IN_PREVIOUS];
648 proc_ctx->frame_store[FRAME_IN_PREVIOUS] = proc_ctx->frame_store[FRAME_IN_CURRENT]; ;
649 proc_ctx->frame_store[FRAME_IN_CURRENT] = tempFrame;
651 if(proc_ctx->surface_input_vebox != -1){
652 vpp_surface_copy(ctx, proc_ctx->frame_store[FRAME_IN_CURRENT].surface_id,
653 proc_ctx->surface_input_vebox);
655 vpp_surface_copy(ctx, proc_ctx->frame_store[FRAME_IN_CURRENT].surface_id,
656 proc_ctx->surface_input);
659 /*s2: update the STMM input and output */
660 /* tempFrame = proc_ctx->frame_store[FRAME_IN_STMM];
661 proc_ctx->frame_store[FRAME_IN_STMM] = proc_ctx->frame_store[FRAME_OUT_STMM]; ;
662 proc_ctx->frame_store[FRAME_OUT_STMM] = tempFrame;
664 /*s3:set reloc buffer address */
665 BEGIN_VEB_BATCH(batch, 10);
666 OUT_VEB_BATCH(batch, VEB_DNDI_IECP_STATE | (10 - 2));
671 proc_ctx->frame_store[FRAME_IN_CURRENT].obj_surface->bo,
672 I915_GEM_DOMAIN_RENDER, 0, frame_ctrl_bits);
674 proc_ctx->frame_store[FRAME_IN_PREVIOUS].obj_surface->bo,
675 I915_GEM_DOMAIN_RENDER, 0, frame_ctrl_bits);
677 proc_ctx->frame_store[FRAME_IN_STMM].obj_surface->bo,
678 I915_GEM_DOMAIN_RENDER, 0, frame_ctrl_bits);
680 proc_ctx->frame_store[FRAME_OUT_STMM].obj_surface->bo,
681 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, frame_ctrl_bits);
683 proc_ctx->frame_store[FRAME_OUT_CURRENT_DN].obj_surface->bo,
684 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, frame_ctrl_bits);
686 proc_ctx->frame_store[FRAME_OUT_CURRENT].obj_surface->bo,
687 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, frame_ctrl_bits);
689 proc_ctx->frame_store[FRAME_OUT_PREVIOUS].obj_surface->bo,
690 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, frame_ctrl_bits);
692 proc_ctx->frame_store[FRAME_OUT_STATISTIC].obj_surface->bo,
693 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, frame_ctrl_bits);
695 ADVANCE_VEB_BATCH(batch);
698 void hsw_veb_resource_prepare(VADriverContextP ctx,
699 struct intel_vebox_context *proc_ctx)
703 struct i965_driver_data *i965 = i965_driver_data(ctx);
704 unsigned int input_fourcc, output_fourcc;
705 unsigned int input_sampling, output_sampling;
706 unsigned int input_tiling, output_tiling;
707 unsigned int i, swizzle;
708 struct object_surface *obj_surf_out = NULL, *obj_surf_in = NULL;
710 if (proc_ctx->surface_input_vebox_object != NULL) {
711 obj_surf_in = proc_ctx->surface_input_vebox_object;
713 obj_surf_in = proc_ctx->surface_input_object;
716 if (proc_ctx->surface_output_vebox_object != NULL) {
717 obj_surf_out = proc_ctx->surface_output_vebox_object;
719 obj_surf_out = proc_ctx->surface_output_object;
722 if(obj_surf_in->bo == NULL){
723 input_fourcc = VA_FOURCC('N','V','1','2');
724 input_sampling = SUBSAMPLE_YUV420;
726 i965_check_alloc_surface_bo(ctx, obj_surf_in, input_tiling, input_fourcc, input_sampling);
728 input_fourcc = obj_surf_in->fourcc;
729 input_sampling = obj_surf_in->subsampling;
730 dri_bo_get_tiling(obj_surf_in->bo, &input_tiling, &swizzle);
731 input_tiling = !!input_tiling;
734 if(obj_surf_out->bo == NULL){
735 output_fourcc = VA_FOURCC('N','V','1','2');
736 output_sampling = SUBSAMPLE_YUV420;
738 i965_check_alloc_surface_bo(ctx, obj_surf_out, output_tiling, output_fourcc, output_sampling);
740 output_fourcc = obj_surf_out->fourcc;
741 output_sampling = obj_surf_out->subsampling;
742 dri_bo_get_tiling(obj_surf_out->bo, &output_tiling, &swizzle);
743 output_tiling = !!output_tiling;
746 /* vebox pipelien input surface format info */
747 proc_ctx->fourcc_input = input_fourcc;
748 proc_ctx->fourcc_output = output_fourcc;
750 /* create pipeline surfaces */
751 VASurfaceID surfaces[FRAME_STORE_SUM];
752 va_status = i965_CreateSurfaces(ctx,
753 proc_ctx ->width_input,
754 proc_ctx ->height_input,
758 assert(va_status == VA_STATUS_SUCCESS);
760 for(i = 0; i < FRAME_STORE_SUM; i ++) {
761 if(proc_ctx->frame_store[i].obj_surface){
762 continue; //refer external surface for vebox pipeline
765 VASurfaceID new_surface;
766 struct object_surface *obj_surf = NULL;
768 va_status = i965_CreateSurfaces(ctx,
769 proc_ctx ->width_input,
770 proc_ctx ->height_input,
774 assert(va_status == VA_STATUS_SUCCESS);
776 obj_surf = SURFACE(new_surface);
779 if( i <= FRAME_IN_PREVIOUS || i == FRAME_OUT_CURRENT_DN) {
780 i965_check_alloc_surface_bo(ctx, obj_surf, input_tiling, input_fourcc, input_sampling);
781 } else if( i == FRAME_IN_STMM || i == FRAME_OUT_STMM){
782 i965_check_alloc_surface_bo(ctx, obj_surf, 1, input_fourcc, input_sampling);
783 } else if( i >= FRAME_OUT_CURRENT){
784 i965_check_alloc_surface_bo(ctx, obj_surf, output_tiling, output_fourcc, output_sampling);
787 proc_ctx->frame_store[i].surface_id = new_surface;
788 proc_ctx->frame_store[i].is_internal_surface = 1;
789 proc_ctx->frame_store[i].obj_surface = obj_surf;
792 /* alloc dndi state table */
793 dri_bo_unreference(proc_ctx->dndi_state_table.bo);
794 bo = dri_bo_alloc(i965->intel.bufmgr,
795 "vebox: dndi state Buffer",
797 proc_ctx->dndi_state_table.bo = bo;
798 dri_bo_reference(proc_ctx->dndi_state_table.bo);
800 /* alloc iecp state table */
801 dri_bo_unreference(proc_ctx->iecp_state_table.bo);
802 bo = dri_bo_alloc(i965->intel.bufmgr,
803 "vebox: iecp state Buffer",
805 proc_ctx->iecp_state_table.bo = bo;
806 dri_bo_reference(proc_ctx->iecp_state_table.bo);
808 /* alloc gamut state table */
809 dri_bo_unreference(proc_ctx->gamut_state_table.bo);
810 bo = dri_bo_alloc(i965->intel.bufmgr,
811 "vebox: gamut state Buffer",
813 proc_ctx->gamut_state_table.bo = bo;
814 dri_bo_reference(proc_ctx->gamut_state_table.bo);
816 /* alloc vertex state table */
817 dri_bo_unreference(proc_ctx->vertex_state_table.bo);
818 bo = dri_bo_alloc(i965->intel.bufmgr,
819 "vertex: iecp state Buffer",
821 proc_ctx->vertex_state_table.bo = bo;
822 dri_bo_reference(proc_ctx->vertex_state_table.bo);
826 void hsw_veb_surface_reference(VADriverContextP ctx,
827 struct intel_vebox_context *proc_ctx)
829 struct object_surface * obj_surf;
831 if (proc_ctx->surface_input_vebox_object != NULL) {
832 obj_surf = proc_ctx->surface_input_vebox_object;
834 obj_surf = proc_ctx->surface_input_object;
837 /* update the input surface */
838 proc_ctx->frame_store[FRAME_IN_CURRENT].surface_id = VA_INVALID_ID;
839 proc_ctx->frame_store[FRAME_IN_CURRENT].is_internal_surface = 0;
840 proc_ctx->frame_store[FRAME_IN_CURRENT].obj_surface = obj_surf;
842 if (proc_ctx->surface_output_vebox_object != NULL) {
843 obj_surf = proc_ctx->surface_output_vebox_object;
845 obj_surf = proc_ctx->surface_output_object;
848 /* update the output surface */
849 if (proc_ctx->filters_mask == VPP_DNDI_DN) {
850 proc_ctx->frame_store[FRAME_OUT_CURRENT_DN].surface_id = VA_INVALID_ID;
851 proc_ctx->frame_store[FRAME_OUT_CURRENT_DN].is_internal_surface = 0;
852 proc_ctx->frame_store[FRAME_OUT_CURRENT_DN].obj_surface = obj_surf;
854 proc_ctx->frame_store[FRAME_OUT_CURRENT].surface_id = VA_INVALID_ID;
855 proc_ctx->frame_store[FRAME_OUT_CURRENT].is_internal_surface = 0;
856 proc_ctx->frame_store[FRAME_OUT_CURRENT].obj_surface = obj_surf;
860 void hsw_veb_surface_unreference(VADriverContextP ctx,
861 struct intel_vebox_context *proc_ctx)
863 /* unreference the input surface */
864 proc_ctx->frame_store[FRAME_IN_CURRENT].surface_id = VA_INVALID_ID;
865 proc_ctx->frame_store[FRAME_IN_CURRENT].is_internal_surface = 0;
866 proc_ctx->frame_store[FRAME_IN_CURRENT].obj_surface = NULL;
868 /* unreference the shared output surface */
869 if (proc_ctx->filters_mask == VPP_DNDI_DN) {
870 proc_ctx->frame_store[FRAME_OUT_CURRENT_DN].surface_id = VA_INVALID_ID;
871 proc_ctx->frame_store[FRAME_OUT_CURRENT_DN].is_internal_surface = 0;
872 proc_ctx->frame_store[FRAME_OUT_CURRENT_DN].obj_surface = NULL;
874 proc_ctx->frame_store[FRAME_OUT_CURRENT].surface_id = VA_INVALID_ID;
875 proc_ctx->frame_store[FRAME_OUT_CURRENT].is_internal_surface = 0;
876 proc_ctx->frame_store[FRAME_OUT_CURRENT].obj_surface = NULL;
880 int hsw_veb_pre_format_convert(VADriverContextP ctx,
881 struct intel_vebox_context *proc_ctx)
884 struct i965_driver_data *i965 = i965_driver_data(ctx);
885 struct object_surface* obj_surf_input = proc_ctx->surface_input_object;
886 struct object_surface* obj_surf_output = proc_ctx->surface_output_object;
887 struct object_surface* obj_surf_input_vebox;
888 struct object_surface* obj_surf_output_vebox;
890 proc_ctx->width_input = obj_surf_input->orig_width;
891 proc_ctx->height_input = obj_surf_input->orig_height;
892 proc_ctx->width_output = obj_surf_output->orig_width;
893 proc_ctx->height_output = obj_surf_output->orig_height;
895 /* only partial frame is not supported to be processed */
897 assert(proc_ctx->width_input == proc_ctx->pipeline_param->surface_region->width);
898 assert(proc_ctx->height_input == proc_ctx->pipeline_param->surface_region->height);
899 assert(proc_ctx->width_output == proc_ctx->pipeline_param->output_region->width);
900 assert(proc_ctx->height_output == proc_ctx->pipeline_param->output_region->height);
903 if(proc_ctx->width_output != proc_ctx->width_input ||
904 proc_ctx->height_output != proc_ctx->height_input){
905 proc_ctx->format_convert_flags |= POST_SCALING_CONVERT;
908 /* convert the following format to NV12 format */
909 if(obj_surf_input->fourcc == VA_FOURCC('Y','V','1','2') ||
910 obj_surf_input->fourcc == VA_FOURCC('I','4','2','0') ||
911 obj_surf_input->fourcc == VA_FOURCC('I','M','C','1') ||
912 obj_surf_input->fourcc == VA_FOURCC('I','M','C','3') ||
913 obj_surf_input->fourcc == VA_FOURCC('R','G','B','A')){
915 proc_ctx->format_convert_flags |= PRE_FORMAT_CONVERT;
917 } else if(obj_surf_input->fourcc == VA_FOURCC('A','Y','U','V') ||
918 obj_surf_input->fourcc == VA_FOURCC('Y','U','Y','2') ||
919 obj_surf_input->fourcc == VA_FOURCC('N','V','1','2')){
920 // nothing to do here
922 /* not support other format as input */
926 if (proc_ctx->format_convert_flags & PRE_FORMAT_CONVERT) {
927 if(proc_ctx->surface_input_vebox_object == NULL){
928 va_status = i965_CreateSurfaces(ctx,
929 proc_ctx->width_input,
930 proc_ctx->height_input,
933 &(proc_ctx->surface_input_vebox));
934 assert(va_status == VA_STATUS_SUCCESS);
935 obj_surf_input_vebox = SURFACE(proc_ctx->surface_input_vebox);
936 assert(obj_surf_input_vebox);
938 if (obj_surf_input_vebox) {
939 proc_ctx->surface_input_vebox_object = obj_surf_input_vebox;
940 i965_check_alloc_surface_bo(ctx, obj_surf_input_vebox, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
944 vpp_surface_convert(ctx, proc_ctx->surface_input_vebox_object, proc_ctx->surface_input_object);
947 /* create one temporary NV12 surfaces for conversion*/
948 if(obj_surf_output->fourcc == VA_FOURCC('Y','V','1','2') ||
949 obj_surf_output->fourcc == VA_FOURCC('I','4','2','0') ||
950 obj_surf_output->fourcc == VA_FOURCC('I','M','C','1') ||
951 obj_surf_output->fourcc == VA_FOURCC('I','M','C','3') ||
952 obj_surf_output->fourcc == VA_FOURCC('R','G','B','A')) {
954 proc_ctx->format_convert_flags |= POST_FORMAT_CONVERT;
955 } else if(obj_surf_output->fourcc == VA_FOURCC('A','Y','U','V') ||
956 obj_surf_output->fourcc == VA_FOURCC('Y','U','Y','2') ||
957 obj_surf_output->fourcc == VA_FOURCC('N','V','1','2')){
958 /* Nothing to do here */
960 /* not support other format as input */
964 if(proc_ctx->format_convert_flags & POST_FORMAT_CONVERT ||
965 proc_ctx->format_convert_flags & POST_SCALING_CONVERT){
966 if(proc_ctx->surface_output_vebox_object == NULL){
967 va_status = i965_CreateSurfaces(ctx,
968 proc_ctx->width_input,
969 proc_ctx->height_input,
972 &(proc_ctx->surface_output_vebox));
973 assert(va_status == VA_STATUS_SUCCESS);
974 obj_surf_output_vebox = SURFACE(proc_ctx->surface_output_vebox);
975 assert(obj_surf_output_vebox);
977 if (obj_surf_output_vebox) {
978 proc_ctx->surface_output_vebox_object = obj_surf_output_vebox;
979 i965_check_alloc_surface_bo(ctx, obj_surf_output_vebox, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
984 if(proc_ctx->format_convert_flags & POST_SCALING_CONVERT){
985 if(proc_ctx->surface_output_scaled_object == NULL){
986 va_status = i965_CreateSurfaces(ctx,
987 proc_ctx->width_output,
988 proc_ctx->height_output,
991 &(proc_ctx->surface_output_scaled));
992 assert(va_status == VA_STATUS_SUCCESS);
993 obj_surf_output_vebox = SURFACE(proc_ctx->surface_output_scaled);
994 assert(obj_surf_output_vebox);
996 if (obj_surf_output_vebox) {
997 proc_ctx->surface_output_scaled_object = obj_surf_output_vebox;
998 i965_check_alloc_surface_bo(ctx, obj_surf_output_vebox, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
1006 int hsw_veb_post_format_convert(VADriverContextP ctx,
1007 struct intel_vebox_context *proc_ctx)
1009 struct object_surface *obj_surface = NULL;
1011 if(proc_ctx->filters_mask == VPP_DNDI_DN){
1012 obj_surface = proc_ctx->frame_store[FRAME_OUT_CURRENT_DN].obj_surface;
1014 obj_surface = proc_ctx->frame_store[FRAME_OUT_CURRENT].obj_surface;
1017 if(!(proc_ctx->format_convert_flags & POST_FORMAT_CONVERT) &&
1018 !(proc_ctx->format_convert_flags & POST_SCALING_CONVERT)){
1019 /* Output surface format is covered by vebox pipeline and
1020 * processed picture is already store in output surface
1021 * so nothing will be done here */
1022 } else if ((proc_ctx->format_convert_flags & POST_FORMAT_CONVERT) &&
1023 !(proc_ctx->format_convert_flags & POST_SCALING_CONVERT)){
1024 /* convert and copy NV12 to YV12/IMC3/IMC2/RGBA output*/
1025 vpp_surface_convert(ctx,proc_ctx->surface_output_object, obj_surface);
1027 } else if(proc_ctx->format_convert_flags & POST_SCALING_CONVERT) {
1028 /* scaling, convert and copy NV12 to YV12/IMC3/IMC2/RGBA output*/
1029 assert(obj_surface->fourcc == VA_FOURCC('N','V','1','2'));
1031 /* first step :surface scaling */
1032 vpp_surface_scaling(ctx,proc_ctx->surface_output_scaled_object, obj_surface);
1034 /* second step: color format convert and copy to output */
1035 obj_surface = proc_ctx->surface_output_object;
1037 if(obj_surface->fourcc == VA_FOURCC('N','V','1','2') ||
1038 obj_surface->fourcc == VA_FOURCC('Y','V','1','2') ||
1039 obj_surface->fourcc == VA_FOURCC('I','4','2','0') ||
1040 obj_surface->fourcc == VA_FOURCC('Y','U','Y','2') ||
1041 obj_surface->fourcc == VA_FOURCC('I','M','C','1') ||
1042 obj_surface->fourcc == VA_FOURCC('I','M','C','3') ||
1043 obj_surface->fourcc == VA_FOURCC('R','G','B','A')) {
1044 vpp_surface_convert(ctx, proc_ctx->surface_output_object, proc_ctx->surface_output_scaled_object);
1053 VAStatus gen75_vebox_process_picture(VADriverContextP ctx,
1054 struct intel_vebox_context *proc_ctx)
1056 struct i965_driver_data *i965 = i965_driver_data(ctx);
1058 VAProcPipelineParameterBuffer *pipe = proc_ctx->pipeline_param;
1059 VAProcFilterParameterBuffer* filter = NULL;
1060 struct object_buffer *obj_buf = NULL;
1063 for (i = 0; i < pipe->num_filters; i ++) {
1064 obj_buf = BUFFER(pipe->filters[i]);
1066 assert(obj_buf && obj_buf->buffer_store);
1068 if (!obj_buf || !obj_buf->buffer_store)
1071 filter = (VAProcFilterParameterBuffer*)obj_buf-> buffer_store->buffer;
1073 if (filter->type == VAProcFilterNoiseReduction) {
1074 proc_ctx->filters_mask |= VPP_DNDI_DN;
1075 proc_ctx->filter_dn = filter;
1076 } else if (filter->type == VAProcFilterDeinterlacing) {
1077 proc_ctx->filters_mask |= VPP_DNDI_DI;
1078 proc_ctx->filter_di = filter;
1079 } else if (filter->type == VAProcFilterColorBalance) {
1080 proc_ctx->filters_mask |= VPP_IECP_PRO_AMP;
1081 proc_ctx->filter_iecp_amp = filter;
1082 proc_ctx->filter_iecp_amp_num_elements = obj_buf->num_elements;
1086 hsw_veb_pre_format_convert(ctx, proc_ctx);
1087 hsw_veb_surface_reference(ctx, proc_ctx);
1089 if(proc_ctx->is_first_frame){
1090 hsw_veb_resource_prepare(ctx, proc_ctx);
1093 intel_batchbuffer_start_atomic_veb(proc_ctx->batch, 0x1000);
1094 intel_batchbuffer_emit_mi_flush(proc_ctx->batch);
1095 hsw_veb_surface_state(ctx, proc_ctx, INPUT_SURFACE);
1096 hsw_veb_surface_state(ctx, proc_ctx, OUTPUT_SURFACE);
1097 hsw_veb_state_table_setup(ctx, proc_ctx);
1099 hsw_veb_state_command(ctx, proc_ctx);
1100 hsw_veb_dndi_iecp_command(ctx, proc_ctx);
1101 intel_batchbuffer_end_atomic(proc_ctx->batch);
1102 intel_batchbuffer_flush(proc_ctx->batch);
1104 hsw_veb_post_format_convert(ctx, proc_ctx);
1105 hsw_veb_surface_unreference(ctx, proc_ctx);
1108 if(proc_ctx->is_first_frame)
1109 proc_ctx->is_first_frame = 0;
1111 return VA_STATUS_SUCCESS;
1114 return VA_STATUS_ERROR_INVALID_PARAMETER;
1117 void gen75_vebox_context_destroy(VADriverContextP ctx,
1118 struct intel_vebox_context *proc_ctx)
1122 if(proc_ctx->surface_input_vebox != VA_INVALID_ID){
1123 i965_DestroySurfaces(ctx, &proc_ctx->surface_input_vebox, 1);
1124 proc_ctx->surface_input_vebox = VA_INVALID_ID;
1125 proc_ctx->surface_input_vebox_object = NULL;
1128 if(proc_ctx->surface_output_vebox != VA_INVALID_ID){
1129 i965_DestroySurfaces(ctx, &proc_ctx->surface_output_vebox, 1);
1130 proc_ctx->surface_output_vebox = VA_INVALID_ID;
1131 proc_ctx->surface_output_vebox_object = NULL;
1134 if(proc_ctx->surface_output_scaled != VA_INVALID_ID){
1135 i965_DestroySurfaces(ctx, &proc_ctx->surface_output_scaled, 1);
1136 proc_ctx->surface_output_scaled = VA_INVALID_ID;
1137 proc_ctx->surface_output_scaled_object = NULL;
1140 for(i = 0; i < FRAME_STORE_SUM; i ++) {
1141 if (proc_ctx->frame_store[i].is_internal_surface == 1) {
1142 assert(proc_ctx->frame_store[i].surface_id != VA_INVALID_ID);
1144 if (proc_ctx->frame_store[i].surface_id != VA_INVALID_ID)
1145 i965_DestroySurfaces(ctx, &proc_ctx->frame_store[i].surface_id, 1);
1148 proc_ctx->frame_store[i].surface_id = VA_INVALID_ID;
1149 proc_ctx->frame_store[i].is_internal_surface = 0;
1150 proc_ctx->frame_store[i].obj_surface = NULL;
1153 /* dndi state table */
1154 dri_bo_unreference(proc_ctx->dndi_state_table.bo);
1155 proc_ctx->dndi_state_table.bo = NULL;
1157 /* iecp state table */
1158 dri_bo_unreference(proc_ctx->iecp_state_table.bo);
1159 proc_ctx->dndi_state_table.bo = NULL;
1161 /* gamut statu table */
1162 dri_bo_unreference(proc_ctx->gamut_state_table.bo);
1163 proc_ctx->gamut_state_table.bo = NULL;
1165 /* vertex state table */
1166 dri_bo_unreference(proc_ctx->vertex_state_table.bo);
1167 proc_ctx->vertex_state_table.bo = NULL;
1169 intel_batchbuffer_free(proc_ctx->batch);
1174 struct intel_vebox_context * gen75_vebox_context_init(VADriverContextP ctx)
1176 struct intel_driver_data *intel = intel_driver_data(ctx);
1177 struct intel_vebox_context *proc_context = calloc(1, sizeof(struct intel_vebox_context));
1180 proc_context->batch = intel_batchbuffer_new(intel, I915_EXEC_VEBOX, 0);
1181 memset(proc_context->frame_store, 0, sizeof(VEBFrameStore)*FRAME_STORE_SUM);
1183 for (i = 0; i < FRAME_STORE_SUM; i ++) {
1184 proc_context->frame_store[i].surface_id = VA_INVALID_ID;
1185 proc_context->frame_store[i].is_internal_surface = 0;
1186 proc_context->frame_store[i].obj_surface = NULL;
1189 proc_context->filters_mask = 0;
1190 proc_context->is_first_frame = 1;
1191 proc_context->surface_output_object = NULL;
1192 proc_context->surface_input_object = NULL;
1193 proc_context->surface_input_vebox = VA_INVALID_ID;
1194 proc_context->surface_input_vebox_object = NULL;
1195 proc_context->surface_output_vebox = VA_INVALID_ID;
1196 proc_context->surface_output_vebox_object = NULL;
1197 proc_context->surface_output_scaled = VA_INVALID_ID;
1198 proc_context->surface_output_scaled_object = NULL;
1199 proc_context->filters_mask = 0;
1200 proc_context->format_convert_flags = 0;
1202 return proc_context;