2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Zhou Chang <chang.zhou@intel.com>
26 * Xiang, Haihao <haihao.xiang@intel.com>
35 #include "intel_batchbuffer.h"
36 #include "i965_defines.h"
37 #include "i965_structs.h"
38 #include "i965_drv_video.h"
39 #include "i965_encoder.h"
40 #include "i965_encoder_utils.h"
44 #define SURFACE_STATE_PADDED_SIZE MAX(SURFACE_STATE_PADDED_SIZE_GEN6, SURFACE_STATE_PADDED_SIZE_GEN7)
45 #define SURFACE_STATE_OFFSET(index) (SURFACE_STATE_PADDED_SIZE * index)
46 #define BINDING_TABLE_OFFSET(index) (SURFACE_STATE_OFFSET(MAX_MEDIA_SURFACES_GEN6) + sizeof(unsigned int) * index)
49 gen6_mfc_pipe_buf_addr_state(VADriverContextP ctx,
50 struct intel_encoder_context *encoder_context);
52 gen6_mfc_bsp_buf_base_addr_state(VADriverContextP ctx,
53 struct intel_encoder_context *encoder_context);
55 gen6_mfc_init(VADriverContextP ctx,
56 struct encode_state *encode_state,
57 struct intel_encoder_context *encoder_context);
60 gen6_mfc_run(VADriverContextP ctx,
61 struct encode_state *encode_state,
62 struct intel_encoder_context *encoder_context);
65 gen6_mfc_stop(VADriverContextP ctx,
66 struct encode_state *encode_state,
67 struct intel_encoder_context *encoder_context,
68 int *encoded_bits_size);
71 gen6_mfc_avc_encode_picture(VADriverContextP ctx,
72 struct encode_state *encode_state,
73 struct intel_encoder_context *encoder_context);
75 static const uint32_t gen7_mfc_batchbuffer_avc_intra[][4] = {
76 #include "shaders/utils/mfc_batchbuffer_avc_intra.g7b"
79 static const uint32_t gen7_mfc_batchbuffer_avc_inter[][4] = {
80 #include "shaders/utils/mfc_batchbuffer_avc_inter.g7b"
83 static struct i965_kernel gen7_mfc_kernels[] = {
85 "MFC AVC INTRA BATCHBUFFER ",
86 MFC_BATCHBUFFER_AVC_INTRA,
87 gen7_mfc_batchbuffer_avc_intra,
88 sizeof(gen7_mfc_batchbuffer_avc_intra),
93 "MFC AVC INTER BATCHBUFFER ",
94 MFC_BATCHBUFFER_AVC_INTER,
95 gen7_mfc_batchbuffer_avc_inter,
96 sizeof(gen7_mfc_batchbuffer_avc_inter),
102 gen7_mfc_pipe_mode_select(VADriverContextP ctx,
104 struct intel_encoder_context *encoder_context)
106 struct intel_batchbuffer *batch = encoder_context->base.batch;
107 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
109 assert(standard_select == MFX_FORMAT_MPEG2 ||
110 standard_select == MFX_FORMAT_AVC);
112 BEGIN_BCS_BATCH(batch, 5);
114 OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2));
116 (MFX_LONG_MODE << 17) | /* Must be long format for encoder */
117 (MFD_MODE_VLD << 15) | /* VLD mode */
118 (1 << 10) | /* Stream-Out Enable */
119 ((!!mfc_context->post_deblocking_output.bo) << 9) | /* Post Deblocking Output */
120 ((!!mfc_context->pre_deblocking_output.bo) << 8) | /* Pre Deblocking Output */
121 (0 << 8) | /* Pre Deblocking Output */
122 (0 << 5) | /* not in stitch mode */
123 (1 << 4) | /* encoding mode */
124 (standard_select << 0)); /* standard select: avc or mpeg2 */
126 (0 << 7) | /* expand NOA bus flag */
127 (0 << 6) | /* disable slice-level clock gating */
128 (0 << 5) | /* disable clock gating for NOA */
129 (0 << 4) | /* terminate if AVC motion and POC table error occurs */
130 (0 << 3) | /* terminate if AVC mbdata error occurs */
131 (0 << 2) | /* terminate if AVC CABAC/CAVLC decode error occurs */
134 OUT_BCS_BATCH(batch, 0);
135 OUT_BCS_BATCH(batch, 0);
137 ADVANCE_BCS_BATCH(batch);
141 gen7_mfc_surface_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
143 struct intel_batchbuffer *batch = encoder_context->base.batch;
144 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
146 BEGIN_BCS_BATCH(batch, 6);
148 OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
149 OUT_BCS_BATCH(batch, 0);
151 ((mfc_context->surface_state.height - 1) << 18) |
152 ((mfc_context->surface_state.width - 1) << 4));
154 (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
155 (1 << 27) | /* must be 1 for interleave U/V, hardware requirement */
156 (0 << 22) | /* surface object control state, FIXME??? */
157 ((mfc_context->surface_state.w_pitch - 1) << 3) | /* pitch */
158 (0 << 2) | /* must be 0 for interleave U/V */
159 (1 << 1) | /* must be tiled */
160 (I965_TILEWALK_YMAJOR << 0)); /* tile walk, TILEWALK_YMAJOR */
162 (0 << 16) | /* must be 0 for interleave U/V */
163 (mfc_context->surface_state.h_pitch)); /* y offset for U(cb) */
164 OUT_BCS_BATCH(batch, 0);
166 ADVANCE_BCS_BATCH(batch);
170 gen7_mfc_ind_obj_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
172 struct intel_batchbuffer *batch = encoder_context->base.batch;
173 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
174 struct gen6_vme_context *vme_context = encoder_context->vme_context;
176 BEGIN_BCS_BATCH(batch, 11);
178 OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
179 OUT_BCS_BATCH(batch, 0);
180 OUT_BCS_BATCH(batch, 0);
181 /* MFX Indirect MV Object Base Address */
182 OUT_BCS_RELOC(batch, vme_context->vme_output.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
183 OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
184 OUT_BCS_BATCH(batch, 0);
185 OUT_BCS_BATCH(batch, 0);
186 OUT_BCS_BATCH(batch, 0);
187 OUT_BCS_BATCH(batch, 0);
188 /*MFC Indirect PAK-BSE Object Base Address for Encoder*/
190 mfc_context->mfc_indirect_pak_bse_object.bo,
191 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
194 mfc_context->mfc_indirect_pak_bse_object.bo,
195 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
196 mfc_context->mfc_indirect_pak_bse_object.end_offset);
198 ADVANCE_BCS_BATCH(batch);
202 gen7_mfc_avc_img_state(VADriverContextP ctx, struct encode_state *encode_state,
203 struct intel_encoder_context *encoder_context)
205 struct intel_batchbuffer *batch = encoder_context->base.batch;
206 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
207 VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
209 int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
210 int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
212 BEGIN_BCS_BATCH(batch, 16);
214 OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (16 - 2));
217 ((width_in_mbs * height_in_mbs - 1) & 0xFFFF));
219 ((height_in_mbs - 1) << 16) |
220 ((width_in_mbs - 1) << 0));
223 (0 << 24) | /* Second Chroma QP Offset */
224 (0 << 16) | /* Chroma QP Offset */
225 (0 << 14) | /* Max-bit conformance Intra flag */
226 (0 << 13) | /* Max Macroblock size conformance Inter flag */
227 (pPicParameter->pic_fields.bits.weighted_pred_flag << 12) | /*Weighted_Pred_Flag */
228 (pPicParameter->pic_fields.bits.weighted_bipred_idc << 10) | /* Weighted_BiPred_Idc */
229 (0 << 8) | /* FIXME: Image Structure */
230 (0 << 0)); /* Current Decoed Image Frame Store ID, reserved in Encode mode */
232 (0 << 16) | /* Mininum Frame size */
233 (0 << 15) | /* Disable reading of Macroblock Status Buffer */
234 (0 << 14) | /* Load BitStream Pointer only once, 1 slic 1 frame */
235 (0 << 13) | /* CABAC 0 word insertion test enable */
236 (1 << 12) | /* MVUnpackedEnable,compliant to DXVA */
237 (1 << 10) | /* Chroma Format IDC, 4:2:0 */
238 (0 << 9) | /* FIXME: MbMvFormatFlag */
239 (pPicParameter->pic_fields.bits.entropy_coding_mode_flag << 7) | /*0:CAVLC encoding mode,1:CABAC*/
240 (0 << 6) | /* Only valid for VLD decoding mode */
241 (0 << 5) | /* Constrained Intra Predition Flag, from PPS */
242 (0 << 4) | /* Direct 8x8 inference flag */
243 (pPicParameter->pic_fields.bits.transform_8x8_mode_flag << 3) | /*8x8 or 4x4 IDCT Transform Mode Flag*/
244 (1 << 2) | /* Frame MB only flag */
245 (0 << 1) | /* MBAFF mode is in active */
246 (0 << 0)); /* Field picture flag */
247 /*DW5 trequllis quantization */
248 OUT_BCS_BATCH(batch, 0); /* Mainly about MB rate control and debug, just ignoring */
249 OUT_BCS_BATCH(batch, /* Inter and Intra Conformance Max size limit */
250 (0xBB8 << 16) | /* InterMbMaxSz */
251 (0xEE8)); /* IntraMbMaxSz */
253 OUT_BCS_BATCH(batch, 0); /* Reserved */
254 OUT_BCS_BATCH(batch, 0); /* Slice QP Delta for bitrate control */
255 OUT_BCS_BATCH(batch, 0); /* Slice QP Delta for bitrate control */
256 /* DW10 frame bit setting */
257 OUT_BCS_BATCH(batch, 0x8C000000);
258 OUT_BCS_BATCH(batch, 0x00010000);
259 OUT_BCS_BATCH(batch, 0);
260 /* DW13 Ref setting */
261 OUT_BCS_BATCH(batch, 0x02010100);
262 OUT_BCS_BATCH(batch, 0);
263 OUT_BCS_BATCH(batch, 0);
265 ADVANCE_BCS_BATCH(batch);
269 gen7_mfc_qm_state(VADriverContextP ctx,
273 struct intel_encoder_context *encoder_context)
275 struct intel_batchbuffer *batch = encoder_context->base.batch;
276 unsigned int qm_buffer[16];
278 assert(qm_length <= 16);
279 assert(sizeof(*qm) == 4);
280 memcpy(qm_buffer, qm, qm_length * 4);
282 BEGIN_BCS_BATCH(batch, 18);
283 OUT_BCS_BATCH(batch, MFX_QM_STATE | (18 - 2));
284 OUT_BCS_BATCH(batch, qm_type << 0);
285 intel_batchbuffer_data(batch, qm_buffer, 16 * 4);
286 ADVANCE_BCS_BATCH(batch);
290 gen7_mfc_avc_qm_state(VADriverContextP ctx,
291 struct encode_state *encode_state,
292 struct intel_encoder_context *encoder_context)
294 unsigned int qm[16] = {
295 0x10101010, 0x10101010, 0x10101010, 0x10101010,
296 0x10101010, 0x10101010, 0x10101010, 0x10101010,
297 0x10101010, 0x10101010, 0x10101010, 0x10101010,
298 0x10101010, 0x10101010, 0x10101010, 0x10101010
301 gen7_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm, 12, encoder_context);
302 gen7_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm, 12, encoder_context);
303 gen7_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm, 16, encoder_context);
304 gen7_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm, 16, encoder_context);
308 gen7_mfc_fqm_state(VADriverContextP ctx,
312 struct intel_encoder_context *encoder_context)
314 struct intel_batchbuffer *batch = encoder_context->base.batch;
315 unsigned int fqm_buffer[32];
317 assert(fqm_length <= 32);
318 assert(sizeof(*fqm) == 4);
319 memcpy(fqm_buffer, fqm, fqm_length * 4);
321 BEGIN_BCS_BATCH(batch, 34);
322 OUT_BCS_BATCH(batch, MFX_FQM_STATE | (34 - 2));
323 OUT_BCS_BATCH(batch, fqm_type << 0);
324 intel_batchbuffer_data(batch, fqm_buffer, 32 * 4);
325 ADVANCE_BCS_BATCH(batch);
329 gen7_mfc_avc_fqm_state(VADriverContextP ctx,
330 struct encode_state *encode_state,
331 struct intel_encoder_context *encoder_context)
333 unsigned int qm[32] = {
334 0x10001000, 0x10001000, 0x10001000, 0x10001000,
335 0x10001000, 0x10001000, 0x10001000, 0x10001000,
336 0x10001000, 0x10001000, 0x10001000, 0x10001000,
337 0x10001000, 0x10001000, 0x10001000, 0x10001000,
338 0x10001000, 0x10001000, 0x10001000, 0x10001000,
339 0x10001000, 0x10001000, 0x10001000, 0x10001000,
340 0x10001000, 0x10001000, 0x10001000, 0x10001000,
341 0x10001000, 0x10001000, 0x10001000, 0x10001000
344 gen7_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm, 24, encoder_context);
345 gen7_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm, 24, encoder_context);
346 gen7_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm, 32, encoder_context);
347 gen7_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm, 32, encoder_context);
351 gen7_mfc_avc_insert_object(VADriverContextP ctx, struct intel_encoder_context *encoder_context,
352 unsigned int *insert_data, int lenght_in_dws, int data_bits_in_last_dw,
353 int skip_emul_byte_count, int is_last_header, int is_end_of_slice, int emulation_flag,
354 struct intel_batchbuffer *batch)
357 batch = encoder_context->base.batch;
359 BEGIN_BCS_BATCH(batch, lenght_in_dws + 2);
361 OUT_BCS_BATCH(batch, MFX_INSERT_OBJECT | (lenght_in_dws + 2 - 2));
363 (0 << 16) | /* always start at offset 0 */
364 (data_bits_in_last_dw << 8) |
365 (skip_emul_byte_count << 4) |
366 (!!emulation_flag << 3) |
367 ((!!is_last_header) << 2) |
368 ((!!is_end_of_slice) << 1) |
369 (0 << 0)); /* FIXME: ??? */
370 intel_batchbuffer_data(batch, insert_data, lenght_in_dws * 4);
372 ADVANCE_BCS_BATCH(batch);
376 va_to_gen7_mpeg2_picture_type[3] = {
383 gen7_mfc_mpeg2_pic_state(VADriverContextP ctx,
384 struct intel_encoder_context *encoder_context,
385 struct encode_state *encode_state)
387 struct intel_batchbuffer *batch = encoder_context->base.batch;
388 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
389 VAEncPictureParameterBufferMPEG2 *pic_param;
390 int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
391 int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
392 VAEncSliceParameterBufferMPEG2 *slice_param = NULL;
394 assert(encode_state->pic_param_ext && encode_state->pic_param_ext->buffer);
395 pic_param = (VAEncPictureParameterBufferMPEG2 *)encode_state->pic_param_ext->buffer;
396 slice_param = (VAEncSliceParameterBufferMPEG2 *)encode_state->slice_params_ext[0]->buffer;
398 BEGIN_BCS_BATCH(batch, 13);
399 OUT_BCS_BATCH(batch, MFX_MPEG2_PIC_STATE | (13 - 2));
401 (pic_param->f_code[1][1] & 0xf) << 28 | /* f_code[1][1] */
402 (pic_param->f_code[1][0] & 0xf) << 24 | /* f_code[1][0] */
403 (pic_param->f_code[0][1] & 0xf) << 20 | /* f_code[0][1] */
404 (pic_param->f_code[0][0] & 0xf) << 16 | /* f_code[0][0] */
405 pic_param->picture_coding_extension.bits.intra_dc_precision << 14 |
406 pic_param->picture_coding_extension.bits.picture_structure << 12 |
407 pic_param->picture_coding_extension.bits.top_field_first << 11 |
408 pic_param->picture_coding_extension.bits.frame_pred_frame_dct << 10 |
409 pic_param->picture_coding_extension.bits.concealment_motion_vectors << 9 |
410 pic_param->picture_coding_extension.bits.q_scale_type << 8 |
411 pic_param->picture_coding_extension.bits.intra_vlc_format << 7 |
412 pic_param->picture_coding_extension.bits.alternate_scan << 6);
414 0 << 14 | /* LoadSlicePointerFlag, 0 means only loading bitstream pointer once */
415 va_to_gen7_mpeg2_picture_type[pic_param->picture_type] << 9 |
418 1 << 31 | /* slice concealment */
419 (height_in_mbs - 1) << 16 |
422 if (slice_param && slice_param->quantiser_scale_code >= 14)
423 OUT_BCS_BATCH(batch, (3 << 1) | (1 << 4) | (5 << 8) | (1 << 12));
425 OUT_BCS_BATCH(batch, 0);
427 OUT_BCS_BATCH(batch, 0);
429 0xFFF << 16 | /* InterMBMaxSize */
430 0xFFF << 0 | /* IntraMBMaxSize */
432 OUT_BCS_BATCH(batch, 0);
433 OUT_BCS_BATCH(batch, 0);
434 OUT_BCS_BATCH(batch, 0);
435 OUT_BCS_BATCH(batch, 0);
436 OUT_BCS_BATCH(batch, 0);
437 OUT_BCS_BATCH(batch, 0);
438 ADVANCE_BCS_BATCH(batch);
442 gen7_mfc_mpeg2_qm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
444 unsigned char intra_qm[64] = {
445 8, 16, 19, 22, 26, 27, 29, 34,
446 16, 16, 22, 24, 27, 29, 34, 37,
447 19, 22, 26, 27, 29, 34, 34, 38,
448 22, 22, 26, 27, 29, 34, 37, 40,
449 22, 26, 27, 29, 32, 35, 40, 48,
450 26, 27, 29, 32, 35, 40, 48, 58,
451 26, 27, 29, 34, 38, 46, 56, 69,
452 27, 29, 35, 38, 46, 56, 69, 83
455 unsigned char non_intra_qm[64] = {
456 16, 16, 16, 16, 16, 16, 16, 16,
457 16, 16, 16, 16, 16, 16, 16, 16,
458 16, 16, 16, 16, 16, 16, 16, 16,
459 16, 16, 16, 16, 16, 16, 16, 16,
460 16, 16, 16, 16, 16, 16, 16, 16,
461 16, 16, 16, 16, 16, 16, 16, 16,
462 16, 16, 16, 16, 16, 16, 16, 16,
463 16, 16, 16, 16, 16, 16, 16, 16
466 gen7_mfc_qm_state(ctx, MFX_QM_MPEG_INTRA_QUANTIZER_MATRIX, (unsigned int *)intra_qm, 16, encoder_context);
467 gen7_mfc_qm_state(ctx, MFX_QM_MPEG_NON_INTRA_QUANTIZER_MATRIX, (unsigned int *)non_intra_qm, 16, encoder_context);
471 gen7_mfc_mpeg2_fqm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
473 unsigned short intra_fqm[64] = {
474 65536 / 0x8, 65536 / 0x10, 65536 / 0x13, 65536 / 0x16, 65536 / 0x16, 65536 / 0x1a, 65536 / 0x1a, 65536 / 0x1b,
475 65536 / 0x10, 65536 / 0x10, 65536 / 0x16, 65536 / 0x16, 65536 / 0x1a, 65536 / 0x1b, 65536 / 0x1b, 65536 / 0x1d,
476 65536 / 0x13, 65536 / 0x16, 65536 / 0x1a, 65536 / 0x1a, 65536 / 0x1b, 65536 / 0x1d, 65536 / 0x1d, 65536 / 0x23,
477 65536 / 0x16, 65536 / 0x18, 65536 / 0x1b, 65536 / 0x1b, 65536 / 0x13, 65536 / 0x20, 65536 / 0x22, 65536 / 0x26,
478 65536 / 0x1a, 65536 / 0x1b, 65536 / 0x13, 65536 / 0x13, 65536 / 0x20, 65536 / 0x23, 65536 / 0x26, 65536 / 0x2e,
479 65536 / 0x1b, 65536 / 0x1d, 65536 / 0x22, 65536 / 0x22, 65536 / 0x23, 65536 / 0x28, 65536 / 0x2e, 65536 / 0x38,
480 65536 / 0x1d, 65536 / 0x22, 65536 / 0x22, 65536 / 0x25, 65536 / 0x28, 65536 / 0x30, 65536 / 0x38, 65536 / 0x45,
481 65536 / 0x22, 65536 / 0x25, 65536 / 0x26, 65536 / 0x28, 65536 / 0x30, 65536 / 0x3a, 65536 / 0x45, 65536 / 0x53,
484 unsigned short non_intra_fqm[64] = {
485 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000,
486 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000,
487 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000,
488 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000,
489 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000,
490 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000,
491 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000,
492 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000,
495 gen7_mfc_fqm_state(ctx, MFX_QM_MPEG_INTRA_QUANTIZER_MATRIX, (unsigned int *)intra_fqm, 32, encoder_context);
496 gen7_mfc_fqm_state(ctx, MFX_QM_MPEG_NON_INTRA_QUANTIZER_MATRIX, (unsigned int *)non_intra_fqm, 32, encoder_context);
500 gen7_mfc_mpeg2_slicegroup_state(VADriverContextP ctx,
501 struct intel_encoder_context *encoder_context,
503 int next_x, int next_y,
504 int is_fisrt_slice_group,
505 int is_last_slice_group,
508 struct intel_batchbuffer *batch)
510 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
513 batch = encoder_context->base.batch;
515 BEGIN_BCS_BATCH(batch, 8);
517 OUT_BCS_BATCH(batch, MFC_MPEG2_SLICEGROUP_STATE | (8 - 2));
519 0 << 31 | /* MbRateCtrlFlag */
520 !!is_last_slice_group << 19 | /* IsLastSliceGrp */
521 1 << 17 | /* Insert Header before the first slice group data */
522 1 << 16 | /* SliceData PresentFlag: always 1 */
523 1 << 15 | /* TailPresentFlag: always 1 */
524 0 << 14 | /* FirstSliceHdrDisabled: slice header for each slice */
525 !!intra_slice << 13 | /* IntraSlice */
526 !!intra_slice << 12 | /* IntraSliceFlag */
534 OUT_BCS_BATCH(batch, qp); /* FIXME: SliceGroupQp */
535 /* bitstream pointer is only loaded once for the first slice of a frame when
536 * LoadSlicePointerFlag is 0
538 OUT_BCS_BATCH(batch, mfc_context->mfc_indirect_pak_bse_object.offset);
539 OUT_BCS_BATCH(batch, 0); /* FIXME: */
540 OUT_BCS_BATCH(batch, 0); /* FIXME: CorrectPoints */
541 OUT_BCS_BATCH(batch, 0); /* FIXME: CVxxx */
543 ADVANCE_BCS_BATCH(batch);
547 gen7_mfc_mpeg2_pak_object_intra(VADriverContextP ctx,
548 struct intel_encoder_context *encoder_context,
550 int first_mb_in_slice,
551 int last_mb_in_slice,
552 int first_mb_in_slice_group,
553 int last_mb_in_slice_group,
556 int coded_block_pattern,
557 unsigned char target_size_in_word,
558 unsigned char max_size_in_word,
559 struct intel_batchbuffer *batch)
561 int len_in_dwords = 9;
564 batch = encoder_context->base.batch;
566 BEGIN_BCS_BATCH(batch, len_in_dwords);
568 OUT_BCS_BATCH(batch, MFC_MPEG2_PAK_OBJECT | (len_in_dwords - 2));
570 0 << 24 | /* PackedMvNum */
571 0 << 20 | /* MvFormat */
572 7 << 17 | /* CbpDcY/CbpDcU/CbpDcV */
573 0 << 15 | /* TransformFlag: frame DCT */
574 0 << 14 | /* FieldMbFlag */
575 1 << 13 | /* IntraMbFlag */
576 mb_type << 8 | /* MbType: Intra */
577 0 << 2 | /* SkipMbFlag */
578 0 << 0 | /* InterMbMode */
580 OUT_BCS_BATCH(batch, y << 16 | x);
582 max_size_in_word << 24 |
583 target_size_in_word << 16 |
584 coded_block_pattern << 6 | /* CBP */
587 last_mb_in_slice << 31 |
588 first_mb_in_slice << 30 |
589 0 << 27 | /* EnableCoeffClamp */
590 last_mb_in_slice_group << 26 |
591 0 << 25 | /* MbSkipConvDisable */
592 first_mb_in_slice_group << 24 |
593 0 << 16 | /* MvFieldSelect */
596 OUT_BCS_BATCH(batch, 0); /* MV[0][0] */
597 OUT_BCS_BATCH(batch, 0); /* MV[1][0] */
598 OUT_BCS_BATCH(batch, 0); /* MV[0][1] */
599 OUT_BCS_BATCH(batch, 0); /* MV[1][1] */
601 ADVANCE_BCS_BATCH(batch);
603 return len_in_dwords;
606 #define MV_OFFSET_IN_WORD 112
608 static struct _mv_ranges {
609 int low; /* in the unit of 1/2 pixel */
610 int high; /* in the unit of 1/2 pixel */
625 mpeg2_motion_vector(int mv, int pos, int display_max, int f_code)
627 if (mv + pos * 16 * 2 < 0 ||
628 mv + (pos + 1) * 16 * 2 > display_max * 2)
631 if (f_code > 0 && f_code < 10) {
632 if (mv < mv_ranges[f_code].low)
633 mv = mv_ranges[f_code].low;
635 if (mv > mv_ranges[f_code].high)
636 mv = mv_ranges[f_code].high;
643 gen7_mfc_mpeg2_pak_object_inter(VADriverContextP ctx,
644 struct encode_state *encode_state,
645 struct intel_encoder_context *encoder_context,
647 int width_in_mbs, int height_in_mbs,
649 int first_mb_in_slice,
650 int last_mb_in_slice,
651 int first_mb_in_slice_group,
652 int last_mb_in_slice_group,
654 unsigned char target_size_in_word,
655 unsigned char max_size_in_word,
656 struct intel_batchbuffer *batch)
658 VAEncPictureParameterBufferMPEG2 *pic_param = (VAEncPictureParameterBufferMPEG2 *)encode_state->pic_param_ext->buffer;
659 int len_in_dwords = 9;
660 short *mvptr, mvx0, mvy0, mvx1, mvy1;
663 batch = encoder_context->base.batch;
665 mvptr = (short *)msg;
666 mvx0 = mpeg2_motion_vector(mvptr[0] / 2, x, width_in_mbs * 16, pic_param->f_code[0][0]);
667 mvy0 = mpeg2_motion_vector(mvptr[1] / 2, y, height_in_mbs * 16, pic_param->f_code[0][0]);
668 mvx1 = mpeg2_motion_vector(mvptr[2] / 2, x, width_in_mbs * 16, pic_param->f_code[1][0]);
669 mvy1 = mpeg2_motion_vector(mvptr[3] / 2, y, height_in_mbs * 16, pic_param->f_code[1][0]);
671 BEGIN_BCS_BATCH(batch, len_in_dwords);
673 OUT_BCS_BATCH(batch, MFC_MPEG2_PAK_OBJECT | (len_in_dwords - 2));
675 2 << 24 | /* PackedMvNum */
676 7 << 20 | /* MvFormat */
677 7 << 17 | /* CbpDcY/CbpDcU/CbpDcV */
678 0 << 15 | /* TransformFlag: frame DCT */
679 0 << 14 | /* FieldMbFlag */
680 0 << 13 | /* IntraMbFlag */
681 1 << 8 | /* MbType: Frame-based */
682 0 << 2 | /* SkipMbFlag */
683 0 << 0 | /* InterMbMode */
685 OUT_BCS_BATCH(batch, y << 16 | x);
687 max_size_in_word << 24 |
688 target_size_in_word << 16 |
689 0x3f << 6 | /* CBP */
692 last_mb_in_slice << 31 |
693 first_mb_in_slice << 30 |
694 0 << 27 | /* EnableCoeffClamp */
695 last_mb_in_slice_group << 26 |
696 0 << 25 | /* MbSkipConvDisable */
697 first_mb_in_slice_group << 24 |
698 0 << 16 | /* MvFieldSelect */
702 OUT_BCS_BATCH(batch, (mvx0 & 0xFFFF) | mvy0 << 16); /* MV[0][0] */
703 OUT_BCS_BATCH(batch, (mvx1 & 0xFFFF) | mvy1 << 16); /* MV[1][0] */
704 OUT_BCS_BATCH(batch, 0); /* MV[0][1] */
705 OUT_BCS_BATCH(batch, 0); /* MV[1][1] */
707 ADVANCE_BCS_BATCH(batch);
709 return len_in_dwords;
713 gen7_mfc_mpeg2_pipeline_header_programing(VADriverContextP ctx,
714 struct encode_state *encode_state,
715 struct intel_encoder_context *encoder_context,
716 struct intel_batchbuffer *slice_batch)
718 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
719 int idx = va_enc_packed_type_to_idx(VAEncPackedHeaderMPEG2_SPS);
721 if (encode_state->packed_header_data[idx]) {
722 VAEncPackedHeaderParameterBuffer *param = NULL;
723 unsigned int *header_data = (unsigned int *)encode_state->packed_header_data[idx]->buffer;
724 unsigned int length_in_bits;
726 assert(encode_state->packed_header_param[idx]);
727 param = (VAEncPackedHeaderParameterBuffer *)encode_state->packed_header_param[idx]->buffer;
728 length_in_bits = param->bit_length;
730 mfc_context->insert_object(ctx,
733 ALIGN(length_in_bits, 32) >> 5,
734 length_in_bits & 0x1f,
735 5, /* FIXME: check it */
738 0, /* Needn't insert emulation bytes for MPEG-2 */
742 idx = va_enc_packed_type_to_idx(VAEncPackedHeaderMPEG2_PPS);
744 if (encode_state->packed_header_data[idx]) {
745 VAEncPackedHeaderParameterBuffer *param = NULL;
746 unsigned int *header_data = (unsigned int *)encode_state->packed_header_data[idx]->buffer;
747 unsigned int length_in_bits;
749 assert(encode_state->packed_header_param[idx]);
750 param = (VAEncPackedHeaderParameterBuffer *)encode_state->packed_header_param[idx]->buffer;
751 length_in_bits = param->bit_length;
753 mfc_context->insert_object(ctx,
756 ALIGN(length_in_bits, 32) >> 5,
757 length_in_bits & 0x1f,
758 5, /* FIXME: check it */
761 0, /* Needn't insert emulation bytes for MPEG-2 */
767 gen7_mfc_mpeg2_pipeline_slice_group(VADriverContextP ctx,
768 struct encode_state *encode_state,
769 struct intel_encoder_context *encoder_context,
771 VAEncSliceParameterBufferMPEG2 *next_slice_group_param,
772 struct intel_batchbuffer *slice_batch)
774 struct gen6_vme_context *vme_context = encoder_context->vme_context;
775 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
776 VAEncSequenceParameterBufferMPEG2 *seq_param = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer;
777 VAEncSliceParameterBufferMPEG2 *slice_param = NULL;
778 unsigned char tail_delimiter[] = {MPEG2_DELIMITER0, MPEG2_DELIMITER1, MPEG2_DELIMITER2, MPEG2_DELIMITER3, MPEG2_DELIMITER4, 0, 0, 0};
779 unsigned char section_delimiter[] = {0x0, 0x0, 0x0, 0x0};
780 int width_in_mbs = ALIGN(seq_param->picture_width, 16) / 16;
781 int height_in_mbs = ALIGN(seq_param->picture_height, 16) / 16;
783 int h_start_pos, v_start_pos, h_next_start_pos, v_next_start_pos;
784 unsigned int *msg = NULL;
785 unsigned char *msg_ptr = NULL;
787 slice_param = (VAEncSliceParameterBufferMPEG2 *)encode_state->slice_params_ext[slice_index]->buffer;
788 h_start_pos = slice_param->macroblock_address % width_in_mbs;
789 v_start_pos = slice_param->macroblock_address / width_in_mbs;
790 assert(h_start_pos + slice_param->num_macroblocks <= width_in_mbs);
792 dri_bo_map(vme_context->vme_output.bo , 0);
793 msg_ptr = (unsigned char *)vme_context->vme_output.bo->virtual;
795 if (next_slice_group_param) {
796 h_next_start_pos = next_slice_group_param->macroblock_address % width_in_mbs;
797 v_next_start_pos = next_slice_group_param->macroblock_address / width_in_mbs;
799 h_next_start_pos = 0;
800 v_next_start_pos = height_in_mbs;
803 gen7_mfc_mpeg2_slicegroup_state(ctx,
810 next_slice_group_param == NULL,
811 slice_param->is_intra_slice,
812 slice_param->quantiser_scale_code,
815 if (slice_index == 0)
816 gen7_mfc_mpeg2_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch);
818 /* Insert '00' to make sure the header is valid */
819 mfc_context->insert_object(ctx,
821 (unsigned int*)section_delimiter,
823 8, /* 8bits in the last DWORD */
830 for (i = 0; i < encode_state->slice_params_ext[slice_index]->num_elements; i++) {
831 /* PAK for each macroblocks */
832 for (j = 0; j < slice_param->num_macroblocks; j++) {
833 int h_pos = (slice_param->macroblock_address + j) % width_in_mbs;
834 int v_pos = (slice_param->macroblock_address + j) / width_in_mbs;
835 int first_mb_in_slice = (j == 0);
836 int last_mb_in_slice = (j == slice_param->num_macroblocks - 1);
837 int first_mb_in_slice_group = (i == 0 && j == 0);
838 int last_mb_in_slice_group = (i == encode_state->slice_params_ext[slice_index]->num_elements - 1 &&
839 j == slice_param->num_macroblocks - 1);
841 if (slice_param->is_intra_slice) {
842 gen7_mfc_mpeg2_pak_object_intra(ctx,
847 first_mb_in_slice_group,
848 last_mb_in_slice_group,
850 slice_param->quantiser_scale_code,
856 msg = (unsigned int *)(msg_ptr + (slice_param->macroblock_address + j) * vme_context->vme_output.size_block);
858 if (msg[32] & INTRA_MB_FLAG_MASK) {
859 gen7_mfc_mpeg2_pak_object_intra(ctx,
864 first_mb_in_slice_group,
865 last_mb_in_slice_group,
867 slice_param->quantiser_scale_code,
874 gen7_mfc_mpeg2_pak_object_inter(ctx,
878 width_in_mbs, height_in_mbs,
882 first_mb_in_slice_group,
883 last_mb_in_slice_group,
884 slice_param->quantiser_scale_code,
895 dri_bo_unmap(vme_context->vme_output.bo);
898 if (next_slice_group_param == NULL) { /* end of a picture */
899 mfc_context->insert_object(ctx,
901 (unsigned int *)tail_delimiter,
903 8, /* 8bits in the last DWORD */
909 } else { /* end of a lsice group */
910 mfc_context->insert_object(ctx,
912 (unsigned int *)section_delimiter,
914 8, /* 8bits in the last DWORD */
924 * A batch buffer for all slices, including slice state,
925 * slice insert object and slice pak object commands
929 gen7_mfc_mpeg2_software_slice_batchbuffer(VADriverContextP ctx,
930 struct encode_state *encode_state,
931 struct intel_encoder_context *encoder_context)
933 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
934 struct intel_batchbuffer *batch;
935 VAEncSliceParameterBufferMPEG2 *next_slice_group_param = NULL;
939 batch = mfc_context->aux_batchbuffer;
940 batch_bo = batch->buffer;
942 for (i = 0; i < encode_state->num_slice_params_ext; i++) {
943 if (i == encode_state->num_slice_params_ext - 1)
944 next_slice_group_param = NULL;
946 next_slice_group_param = (VAEncSliceParameterBufferMPEG2 *)encode_state->slice_params_ext[i + 1]->buffer;
948 gen7_mfc_mpeg2_pipeline_slice_group(ctx, encode_state, encoder_context, i, next_slice_group_param, batch);
951 intel_batchbuffer_align(batch, 8);
953 BEGIN_BCS_BATCH(batch, 2);
954 OUT_BCS_BATCH(batch, 0);
955 OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_END);
956 ADVANCE_BCS_BATCH(batch);
958 dri_bo_reference(batch_bo);
959 intel_batchbuffer_free(batch);
960 mfc_context->aux_batchbuffer = NULL;
966 gen7_mfc_mpeg2_pipeline_picture_programing(VADriverContextP ctx,
967 struct encode_state *encode_state,
968 struct intel_encoder_context *encoder_context)
970 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
972 mfc_context->pipe_mode_select(ctx, MFX_FORMAT_MPEG2, encoder_context);
973 mfc_context->set_surface_state(ctx, encoder_context);
974 mfc_context->ind_obj_base_addr_state(ctx, encoder_context);
975 gen6_mfc_pipe_buf_addr_state(ctx, encoder_context);
976 gen6_mfc_bsp_buf_base_addr_state(ctx, encoder_context);
977 gen7_mfc_mpeg2_pic_state(ctx, encoder_context, encode_state);
978 gen7_mfc_mpeg2_qm_state(ctx, encoder_context);
979 gen7_mfc_mpeg2_fqm_state(ctx, encoder_context);
983 gen7_mfc_mpeg2_pipeline_programing(VADriverContextP ctx,
984 struct encode_state *encode_state,
985 struct intel_encoder_context *encoder_context)
987 struct intel_batchbuffer *batch = encoder_context->base.batch;
988 dri_bo *slice_batch_bo;
990 slice_batch_bo = gen7_mfc_mpeg2_software_slice_batchbuffer(ctx, encode_state, encoder_context);
993 intel_batchbuffer_start_atomic_bcs(batch, 0x4000);
994 intel_batchbuffer_emit_mi_flush(batch);
996 // picture level programing
997 gen7_mfc_mpeg2_pipeline_picture_programing(ctx, encode_state, encoder_context);
999 BEGIN_BCS_BATCH(batch, 2);
1000 OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8));
1001 OUT_BCS_RELOC(batch,
1003 I915_GEM_DOMAIN_COMMAND, 0,
1005 ADVANCE_BCS_BATCH(batch);
1008 intel_batchbuffer_end_atomic(batch);
1010 dri_bo_unreference(slice_batch_bo);
1014 gen7_mfc_mpeg2_prepare(VADriverContextP ctx,
1015 struct encode_state *encode_state,
1016 struct intel_encoder_context *encoder_context)
1018 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1019 struct object_surface *obj_surface;
1020 struct object_buffer *obj_buffer;
1021 struct i965_coded_buffer_segment *coded_buffer_segment;
1022 VAStatus vaStatus = VA_STATUS_SUCCESS;
1026 /* reconstructed surface */
1027 obj_surface = encode_state->reconstructed_object;
1028 i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
1029 mfc_context->pre_deblocking_output.bo = obj_surface->bo;
1030 dri_bo_reference(mfc_context->pre_deblocking_output.bo);
1031 mfc_context->surface_state.width = obj_surface->orig_width;
1032 mfc_context->surface_state.height = obj_surface->orig_height;
1033 mfc_context->surface_state.w_pitch = obj_surface->width;
1034 mfc_context->surface_state.h_pitch = obj_surface->height;
1036 /* forward reference */
1037 obj_surface = encode_state->reference_objects[0];
1039 if (obj_surface && obj_surface->bo) {
1040 mfc_context->reference_surfaces[0].bo = obj_surface->bo;
1041 dri_bo_reference(mfc_context->reference_surfaces[0].bo);
1043 mfc_context->reference_surfaces[0].bo = NULL;
1045 /* backward reference */
1046 obj_surface = encode_state->reference_objects[1];
1048 if (obj_surface && obj_surface->bo) {
1049 mfc_context->reference_surfaces[1].bo = obj_surface->bo;
1050 dri_bo_reference(mfc_context->reference_surfaces[1].bo);
1052 mfc_context->reference_surfaces[1].bo = mfc_context->reference_surfaces[0].bo;
1054 if (mfc_context->reference_surfaces[1].bo)
1055 dri_bo_reference(mfc_context->reference_surfaces[1].bo);
1058 for (i = 2; i < ARRAY_ELEMS(mfc_context->reference_surfaces); i++) {
1059 mfc_context->reference_surfaces[i].bo = mfc_context->reference_surfaces[i & 1].bo;
1061 if (mfc_context->reference_surfaces[i].bo)
1062 dri_bo_reference(mfc_context->reference_surfaces[i].bo);
1065 /* input YUV surface */
1066 obj_surface = encode_state->input_yuv_object;
1067 mfc_context->uncompressed_picture_source.bo = obj_surface->bo;
1068 dri_bo_reference(mfc_context->uncompressed_picture_source.bo);
1071 obj_buffer = encode_state->coded_buf_object;
1072 bo = obj_buffer->buffer_store->bo;
1073 mfc_context->mfc_indirect_pak_bse_object.bo = bo;
1074 mfc_context->mfc_indirect_pak_bse_object.offset = I965_CODEDBUFFER_HEADER_SIZE;
1075 mfc_context->mfc_indirect_pak_bse_object.end_offset = ALIGN(obj_buffer->size_element - 0x1000, 0x1000);
1076 dri_bo_reference(mfc_context->mfc_indirect_pak_bse_object.bo);
1078 /* set the internal flag to 0 to indicate the coded size is unknown */
1080 coded_buffer_segment = (struct i965_coded_buffer_segment *)bo->virtual;
1081 coded_buffer_segment->mapped = 0;
1082 coded_buffer_segment->codec = encoder_context->codec;
1089 gen7_mfc_mpeg2_encode_picture(VADriverContextP ctx,
1090 struct encode_state *encode_state,
1091 struct intel_encoder_context *encoder_context)
1093 gen6_mfc_init(ctx, encode_state, encoder_context);
1094 gen7_mfc_mpeg2_prepare(ctx, encode_state, encoder_context);
1095 /*Programing bcs pipeline*/
1096 gen7_mfc_mpeg2_pipeline_programing(ctx, encode_state, encoder_context);
1097 gen6_mfc_run(ctx, encode_state, encoder_context);
1099 return VA_STATUS_SUCCESS;
1103 gen7_mfc_pipeline(VADriverContextP ctx,
1105 struct encode_state *encode_state,
1106 struct intel_encoder_context *encoder_context)
1111 case VAProfileH264ConstrainedBaseline:
1112 case VAProfileH264Main:
1113 case VAProfileH264High:
1114 vaStatus = gen6_mfc_avc_encode_picture(ctx, encode_state, encoder_context);
1117 case VAProfileMPEG2Simple:
1118 case VAProfileMPEG2Main:
1119 vaStatus = gen7_mfc_mpeg2_encode_picture(ctx, encode_state, encoder_context);
1122 /* FIXME: add for other profile */
1124 vaStatus = VA_STATUS_ERROR_UNSUPPORTED_PROFILE;
1132 gen7_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
1134 struct gen6_mfc_context *mfc_context = calloc(1, sizeof(struct gen6_mfc_context));
1139 mfc_context->gpe_context.surface_state_binding_table.length = (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6;
1141 mfc_context->gpe_context.idrt.max_entries = MAX_GPE_KERNELS;
1142 mfc_context->gpe_context.idrt.entry_size = sizeof(struct gen6_interface_descriptor_data);
1144 mfc_context->gpe_context.curbe.length = 32 * 4;
1146 mfc_context->gpe_context.vfe_state.max_num_threads = 60 - 1;
1147 mfc_context->gpe_context.vfe_state.num_urb_entries = 16;
1148 mfc_context->gpe_context.vfe_state.gpgpu_mode = 0;
1149 mfc_context->gpe_context.vfe_state.urb_entry_size = 59 - 1;
1150 mfc_context->gpe_context.vfe_state.curbe_allocation_size = 37 - 1;
1152 i965_gpe_load_kernels(ctx,
1153 &mfc_context->gpe_context,
1157 mfc_context->pipe_mode_select = gen7_mfc_pipe_mode_select;
1158 mfc_context->set_surface_state = gen7_mfc_surface_state;
1159 mfc_context->ind_obj_base_addr_state = gen7_mfc_ind_obj_base_addr_state;
1160 mfc_context->avc_img_state = gen7_mfc_avc_img_state;
1161 mfc_context->avc_qm_state = gen7_mfc_avc_qm_state;
1162 mfc_context->avc_fqm_state = gen7_mfc_avc_fqm_state;
1163 mfc_context->insert_object = gen7_mfc_avc_insert_object;
1164 mfc_context->buffer_suface_setup = gen7_gpe_buffer_suface_setup;
1166 encoder_context->mfc_context = mfc_context;
1167 encoder_context->mfc_context_destroy = gen6_mfc_context_destroy;
1168 encoder_context->mfc_pipeline = gen7_mfc_pipeline;
1169 encoder_context->mfc_brc_prepare = intel_mfc_brc_prepare;