src/gen7_mfd.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Xiang Haihao <haihao.xiang@intel.com>
  26  *
  27  */
  28
  29 #include "sysdeps.h"
  30
  31 #include <va/va_dec_jpeg.h>
  32
  33 #include "intel_batchbuffer.h"
  34 #include "intel_driver.h"
  35 #include "i965_defines.h"
  36 #include "i965_drv_video.h"
  37 #include "i965_decoder_utils.h"
  38
  39 #include "gen7_mfd.h"
  40 #include "intel_media.h"
  41
  42 static const uint32_t zigzag_direct[64] = {
  43     0,   1,  8, 16,  9,  2,  3, 10,
  44     17, 24, 32, 25, 18, 11,  4,  5,
  45     12, 19, 26, 33, 40, 48, 41, 34,
  46     27, 20, 13,  6,  7, 14, 21, 28,
  47     35, 42, 49, 56, 57, 50, 43, 36,
  48     29, 22, 15, 23, 30, 37, 44, 51,
  49     58, 59, 52, 45, 38, 31, 39, 46,
  50     53, 60, 61, 54, 47, 55, 62, 63
  51 };
  52
  53 static void
  54 gen7_mfd_init_avc_surface(VADriverContextP ctx,
  55                           VAPictureParameterBufferH264 *pic_param,
  56                           struct object_surface *obj_surface)
  57 {
  58     struct i965_driver_data *i965 = i965_driver_data(ctx);
  59     GenAvcSurface *gen7_avc_surface = obj_surface->private_data;
  60     int width_in_mbs, height_in_mbs;
  61
  62     obj_surface->free_private_data = gen_free_avc_surface;
  63     width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
  64     height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; /* frame height */
  65
  66     if (!gen7_avc_surface) {
  67         gen7_avc_surface = calloc(sizeof(GenAvcSurface), 1);
  68         assert(gen7_avc_surface);
  69         gen7_avc_surface->base.frame_store_id = -1;
  70         assert((obj_surface->size & 0x3f) == 0);
  71         obj_surface->private_data = gen7_avc_surface;
  72     }
  73
  74     gen7_avc_surface->dmv_bottom_flag = (pic_param->pic_fields.bits.field_pic_flag &&
  75                                          !pic_param->seq_fields.bits.direct_8x8_inference_flag);
  76
  77     if (gen7_avc_surface->dmv_top == NULL) {
  78         gen7_avc_surface->dmv_top = dri_bo_alloc(i965->intel.bufmgr,
  79                                                  "direct mv w/r buffer",
  80                                                  width_in_mbs * (height_in_mbs + 1) * 64,
  81                                                  0x1000);
  82         assert(gen7_avc_surface->dmv_top);
  83     }
  84
  85     if (gen7_avc_surface->dmv_bottom_flag &&
  86         gen7_avc_surface->dmv_bottom == NULL) {
  87         gen7_avc_surface->dmv_bottom = dri_bo_alloc(i965->intel.bufmgr,
  88                                                     "direct mv w/r buffer",
  89                                                     width_in_mbs * (height_in_mbs + 1) * 64,
  90                                                     0x1000);
  91         assert(gen7_avc_surface->dmv_bottom);
  92     }
  93 }
  94
  95 static void
  96 gen7_mfd_pipe_mode_select(VADriverContextP ctx,
  97                           struct decode_state *decode_state,
  98                           int standard_select,
  99                           struct gen7_mfd_context *gen7_mfd_context)
 100 {
 101     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 102
 103     assert(standard_select == MFX_FORMAT_MPEG2 ||
 104            standard_select == MFX_FORMAT_AVC ||
 105            standard_select == MFX_FORMAT_VC1 ||
 106            standard_select == MFX_FORMAT_JPEG);
 107
 108     BEGIN_BCS_BATCH(batch, 5);
 109     OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2));
 110     OUT_BCS_BATCH(batch,
 111                   (MFX_LONG_MODE << 17) | /* Currently only support long format */
 112                   (MFD_MODE_VLD << 15) | /* VLD mode */
 113                   (0 << 10) | /* disable Stream-Out */
 114                   (gen7_mfd_context->post_deblocking_output.valid << 9)  | /* Post Deblocking Output */
 115                   (gen7_mfd_context->pre_deblocking_output.valid << 8)  | /* Pre Deblocking Output */
 116                   (0 << 5)  | /* not in stitch mode */
 117                   (MFX_CODEC_DECODE << 4)  | /* decoding mode */
 118                   (standard_select << 0));
 119     OUT_BCS_BATCH(batch,
 120                   (0 << 4)  | /* terminate if AVC motion and POC table error occurs */
 121                   (0 << 3)  | /* terminate if AVC mbdata error occurs */
 122                   (0 << 2)  | /* terminate if AVC CABAC/CAVLC decode error occurs */
 123                   (0 << 1)  |
 124                   (0 << 0));
 125     OUT_BCS_BATCH(batch, 0); /* pic status/error report id */
 126     OUT_BCS_BATCH(batch, 0); /* reserved */
 127     ADVANCE_BCS_BATCH(batch);
 128 }
 129
 130 static void
 131 gen7_mfd_surface_state(VADriverContextP ctx,
 132                        struct decode_state *decode_state,
 133                        int standard_select,
 134                        struct gen7_mfd_context *gen7_mfd_context)
 135 {
 136     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 137     struct object_surface *obj_surface = decode_state->render_object;
 138     unsigned int y_cb_offset;
 139     unsigned int y_cr_offset;
 140     unsigned int surface_format;
 141
 142     assert(obj_surface);
 143
 144     y_cb_offset = obj_surface->y_cb_offset;
 145     y_cr_offset = obj_surface->y_cr_offset;
 146
 147     surface_format = obj_surface->fourcc == VA_FOURCC_Y800 ?
 148                      MFX_SURFACE_MONOCHROME : MFX_SURFACE_PLANAR_420_8;
 149
 150     BEGIN_BCS_BATCH(batch, 6);
 151     OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
 152     OUT_BCS_BATCH(batch, 0);
 153     OUT_BCS_BATCH(batch,
 154                   ((obj_surface->orig_height - 1) << 18) |
 155                   ((obj_surface->orig_width - 1) << 4));
 156     OUT_BCS_BATCH(batch,
 157                   (surface_format << 28) | /* 420 planar YUV surface */
 158                   ((standard_select != MFX_FORMAT_JPEG) << 27) | /* interleave chroma, set to 0 for JPEG */
 159                   (0 << 22) | /* surface object control state, ignored */
 160                   ((obj_surface->width - 1) << 3) | /* pitch */
 161                   (0 << 2)  | /* must be 0 */
 162                   (1 << 1)  | /* must be tiled */
 163                   (I965_TILEWALK_YMAJOR << 0));  /* tile walk, must be 1 */
 164     OUT_BCS_BATCH(batch,
 165                   (0 << 16) | /* X offset for U(Cb), must be 0 */
 166                   (y_cb_offset << 0)); /* Y offset for U(Cb) */
 167     OUT_BCS_BATCH(batch,
 168                   (0 << 16) | /* X offset for V(Cr), must be 0 */
 169                   ((standard_select == MFX_FORMAT_JPEG ? y_cr_offset : 0) << 0)); /* Y offset for V(Cr), must be 0 for video codec, non-zoro for JPEG */
 170     ADVANCE_BCS_BATCH(batch);
 171 }
 172
 173 static void
 174 gen7_mfd_pipe_buf_addr_state(VADriverContextP ctx,
 175                              struct decode_state *decode_state,
 176                              int standard_select,
 177                              struct gen7_mfd_context *gen7_mfd_context)
 178 {
 179     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 180     int i;
 181
 182     BEGIN_BCS_BATCH(batch, 24);
 183     OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
 184     if (gen7_mfd_context->pre_deblocking_output.valid)
 185         OUT_BCS_RELOC(batch, gen7_mfd_context->pre_deblocking_output.bo,
 186                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 187                       0);
 188     else
 189         OUT_BCS_BATCH(batch, 0);
 190
 191     if (gen7_mfd_context->post_deblocking_output.valid)
 192         OUT_BCS_RELOC(batch, gen7_mfd_context->post_deblocking_output.bo,
 193                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 194                       0);
 195     else
 196         OUT_BCS_BATCH(batch, 0);
 197
 198     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
 199     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
 200
 201     if (gen7_mfd_context->intra_row_store_scratch_buffer.valid)
 202         OUT_BCS_RELOC(batch, gen7_mfd_context->intra_row_store_scratch_buffer.bo,
 203                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 204                       0);
 205     else
 206         OUT_BCS_BATCH(batch, 0);
 207
 208     if (gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid)
 209         OUT_BCS_RELOC(batch, gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo,
 210                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 211                       0);
 212     else
 213         OUT_BCS_BATCH(batch, 0);
 214
 215     /* DW 7..22 */
 216     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
 217         struct object_surface *obj_surface;
 218
 219         if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID &&
 220             gen7_mfd_context->reference_surface[i].obj_surface &&
 221             gen7_mfd_context->reference_surface[i].obj_surface->bo) {
 222             obj_surface = gen7_mfd_context->reference_surface[i].obj_surface;
 223
 224             OUT_BCS_RELOC(batch, obj_surface->bo,
 225                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 226                           0);
 227         } else {
 228             OUT_BCS_BATCH(batch, 0);
 229         }
 230     }
 231
 232     OUT_BCS_BATCH(batch, 0);   /* ignore DW23 for decoding */
 233     ADVANCE_BCS_BATCH(batch);
 234 }
 235
 236 static void
 237 gen7_mfd_ind_obj_base_addr_state(VADriverContextP ctx,
 238                                  dri_bo *slice_data_bo,
 239                                  int standard_select,
 240                                  struct gen7_mfd_context *gen7_mfd_context)
 241 {
 242     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 243
 244     BEGIN_BCS_BATCH(batch, 11);
 245     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
 246     OUT_BCS_RELOC(batch, slice_data_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); /* MFX Indirect Bitstream Object Base Address */
 247     OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
 248     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 249     OUT_BCS_BATCH(batch, 0);
 250     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 251     OUT_BCS_BATCH(batch, 0);
 252     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 253     OUT_BCS_BATCH(batch, 0);
 254     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 255     OUT_BCS_BATCH(batch, 0);
 256     ADVANCE_BCS_BATCH(batch);
 257 }
 258
 259 static void
 260 gen7_mfd_bsp_buf_base_addr_state(VADriverContextP ctx,
 261                                  struct decode_state *decode_state,
 262                                  int standard_select,
 263                                  struct gen7_mfd_context *gen7_mfd_context)
 264 {
 265     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 266
 267     BEGIN_BCS_BATCH(batch, 4);
 268     OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
 269
 270     if (gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid)
 271         OUT_BCS_RELOC(batch, gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo,
 272                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 273                       0);
 274     else
 275         OUT_BCS_BATCH(batch, 0);
 276
 277     if (gen7_mfd_context->mpr_row_store_scratch_buffer.valid)
 278         OUT_BCS_RELOC(batch, gen7_mfd_context->mpr_row_store_scratch_buffer.bo,
 279                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 280                       0);
 281     else
 282         OUT_BCS_BATCH(batch, 0);
 283
 284     if (gen7_mfd_context->bitplane_read_buffer.valid)
 285         OUT_BCS_RELOC(batch, gen7_mfd_context->bitplane_read_buffer.bo,
 286                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 287                       0);
 288     else
 289         OUT_BCS_BATCH(batch, 0);
 290
 291     ADVANCE_BCS_BATCH(batch);
 292 }
 293
 294 static void
 295 gen7_mfd_qm_state(VADriverContextP ctx,
 296                   int qm_type,
 297                   unsigned char *qm,
 298                   int qm_length,
 299                   struct gen7_mfd_context *gen7_mfd_context)
 300 {
 301     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 302     unsigned int qm_buffer[16];
 303
 304     assert(qm_length <= 16 * 4);
 305     memcpy(qm_buffer, qm, qm_length);
 306
 307     BEGIN_BCS_BATCH(batch, 18);
 308     OUT_BCS_BATCH(batch, MFX_QM_STATE | (18 - 2));
 309     OUT_BCS_BATCH(batch, qm_type << 0);
 310     intel_batchbuffer_data(batch, qm_buffer, 16 * 4);
 311     ADVANCE_BCS_BATCH(batch);
 312 }
 313
 314 static void
 315 gen7_mfd_avc_img_state(VADriverContextP ctx,
 316                        struct decode_state *decode_state,
 317                        struct gen7_mfd_context *gen7_mfd_context)
 318 {
 319     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 320     int img_struct;
 321     int mbaff_frame_flag;
 322     unsigned int width_in_mbs, height_in_mbs;
 323     VAPictureParameterBufferH264 *pic_param;
 324
 325     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 326     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 327
 328     if (pic_param->CurrPic.flags & VA_PICTURE_H264_TOP_FIELD)
 329         img_struct = 1;
 330     else if (pic_param->CurrPic.flags & VA_PICTURE_H264_BOTTOM_FIELD)
 331         img_struct = 3;
 332     else
 333         img_struct = 0;
 334
 335     if ((img_struct & 0x1) == 0x1) {
 336         assert(pic_param->pic_fields.bits.field_pic_flag == 0x1);
 337     } else {
 338         assert(pic_param->pic_fields.bits.field_pic_flag == 0x0);
 339     }
 340
 341     if (pic_param->seq_fields.bits.frame_mbs_only_flag) { /* a frame containing only frame macroblocks */
 342         assert(pic_param->seq_fields.bits.mb_adaptive_frame_field_flag == 0);
 343         assert(pic_param->pic_fields.bits.field_pic_flag == 0);
 344     } else {
 345         assert(pic_param->seq_fields.bits.direct_8x8_inference_flag == 1); /* see H.264 spec */
 346     }
 347
 348     mbaff_frame_flag = (pic_param->seq_fields.bits.mb_adaptive_frame_field_flag &&
 349                         !pic_param->pic_fields.bits.field_pic_flag);
 350
 351     width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
 352     height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; /* frame height */
 353
 354     /* MFX unit doesn't support 4:2:2 and 4:4:4 picture */
 355     assert(pic_param->seq_fields.bits.chroma_format_idc == 0 || /* monochrome picture */
 356            pic_param->seq_fields.bits.chroma_format_idc == 1);  /* 4:2:0 */
 357     assert(pic_param->seq_fields.bits.residual_colour_transform_flag == 0); /* only available for 4:4:4 */
 358
 359     BEGIN_BCS_BATCH(batch, 16);
 360     OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (16 - 2));
 361     OUT_BCS_BATCH(batch,
 362                   (width_in_mbs * height_in_mbs - 1));
 363     OUT_BCS_BATCH(batch,
 364                   ((height_in_mbs - 1) << 16) |
 365                   ((width_in_mbs - 1) << 0));
 366     OUT_BCS_BATCH(batch,
 367                   ((pic_param->second_chroma_qp_index_offset & 0x1f) << 24) |
 368                   ((pic_param->chroma_qp_index_offset & 0x1f) << 16) |
 369                   (0 << 14) | /* Max-bit conformance Intra flag ??? FIXME */
 370                   (0 << 13) | /* Max Macroblock size conformance Inter flag ??? FIXME */
 371                   (pic_param->pic_fields.bits.weighted_pred_flag << 12) | /* differ from GEN6 */
 372                   (pic_param->pic_fields.bits.weighted_bipred_idc << 10) |
 373                   (img_struct << 8));
 374     OUT_BCS_BATCH(batch,
 375                   (pic_param->seq_fields.bits.chroma_format_idc << 10) |
 376                   (pic_param->pic_fields.bits.entropy_coding_mode_flag << 7) |
 377                   ((!pic_param->pic_fields.bits.reference_pic_flag) << 6) |
 378                   (pic_param->pic_fields.bits.constrained_intra_pred_flag << 5) |
 379                   (pic_param->seq_fields.bits.direct_8x8_inference_flag << 4) |
 380                   (pic_param->pic_fields.bits.transform_8x8_mode_flag << 3) |
 381                   (pic_param->seq_fields.bits.frame_mbs_only_flag << 2) |
 382                   (mbaff_frame_flag << 1) |
 383                   (pic_param->pic_fields.bits.field_pic_flag << 0));
 384     OUT_BCS_BATCH(batch, 0);
 385     OUT_BCS_BATCH(batch, 0);
 386     OUT_BCS_BATCH(batch, 0);
 387     OUT_BCS_BATCH(batch, 0);
 388     OUT_BCS_BATCH(batch, 0);
 389     OUT_BCS_BATCH(batch, 0);
 390     OUT_BCS_BATCH(batch, 0);
 391     OUT_BCS_BATCH(batch, 0);
 392     OUT_BCS_BATCH(batch, 0);
 393     OUT_BCS_BATCH(batch, 0);
 394     OUT_BCS_BATCH(batch, 0);
 395     ADVANCE_BCS_BATCH(batch);
 396 }
 397
 398 static void
 399 gen7_mfd_avc_qm_state(VADriverContextP ctx,
 400                       struct decode_state *decode_state,
 401                       struct gen7_mfd_context *gen7_mfd_context)
 402 {
 403     VAIQMatrixBufferH264 *iq_matrix;
 404     VAPictureParameterBufferH264 *pic_param;
 405
 406     if (decode_state->iq_matrix && decode_state->iq_matrix->buffer)
 407         iq_matrix = (VAIQMatrixBufferH264 *)decode_state->iq_matrix->buffer;
 408     else
 409         iq_matrix = &gen7_mfd_context->iq_matrix.h264;
 410
 411     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 412     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 413
 414     gen7_mfd_qm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, &iq_matrix->ScalingList4x4[0][0], 3 * 16, gen7_mfd_context);
 415     gen7_mfd_qm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, &iq_matrix->ScalingList4x4[3][0], 3 * 16, gen7_mfd_context);
 416
 417     if (pic_param->pic_fields.bits.transform_8x8_mode_flag) {
 418         gen7_mfd_qm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, &iq_matrix->ScalingList8x8[0][0], 64, gen7_mfd_context);
 419         gen7_mfd_qm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, &iq_matrix->ScalingList8x8[1][0], 64, gen7_mfd_context);
 420     }
 421 }
 422
 423 static void
 424 gen7_mfd_avc_directmode_state(VADriverContextP ctx,
 425                               struct decode_state *decode_state,
 426                               VAPictureParameterBufferH264 *pic_param,
 427                               VASliceParameterBufferH264 *slice_param,
 428                               struct gen7_mfd_context *gen7_mfd_context)
 429 {
 430     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 431     struct object_surface *obj_surface;
 432     GenAvcSurface *gen7_avc_surface;
 433     VAPictureH264 *va_pic;
 434     int i;
 435
 436     BEGIN_BCS_BATCH(batch, 69);
 437     OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
 438
 439     /* reference surfaces 0..15 */
 440     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
 441         if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID &&
 442             gen7_mfd_context->reference_surface[i].obj_surface &&
 443             gen7_mfd_context->reference_surface[i].obj_surface->private_data) {
 444
 445             obj_surface = gen7_mfd_context->reference_surface[i].obj_surface;
 446             gen7_avc_surface = obj_surface->private_data;
 447             OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
 448                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 449                           0);
 450
 451             if (gen7_avc_surface->dmv_bottom_flag == 1)
 452                 OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_bottom,
 453                               I915_GEM_DOMAIN_INSTRUCTION, 0,
 454                               0);
 455             else
 456                 OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
 457                               I915_GEM_DOMAIN_INSTRUCTION, 0,
 458                               0);
 459         } else {
 460             OUT_BCS_BATCH(batch, 0);
 461             OUT_BCS_BATCH(batch, 0);
 462         }
 463     }
 464
 465     /* the current decoding frame/field */
 466     va_pic = &pic_param->CurrPic;
 467     obj_surface = decode_state->render_object;
 468     assert(obj_surface->bo && obj_surface->private_data);
 469     gen7_avc_surface = obj_surface->private_data;
 470
 471     OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
 472                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 473                   0);
 474
 475     if (gen7_avc_surface->dmv_bottom_flag == 1)
 476         OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_bottom,
 477                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 478                       0);
 479     else
 480         OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
 481                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 482                       0);
 483
 484     /* POC List */
 485     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
 486         obj_surface = gen7_mfd_context->reference_surface[i].obj_surface;
 487
 488         if (obj_surface) {
 489             const VAPictureH264 * const va_pic = avc_find_picture(
 490                                                      obj_surface->base.id, pic_param->ReferenceFrames,
 491                                                      ARRAY_ELEMS(pic_param->ReferenceFrames));
 492
 493             assert(va_pic != NULL);
 494             OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
 495             OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
 496         } else {
 497             OUT_BCS_BATCH(batch, 0);
 498             OUT_BCS_BATCH(batch, 0);
 499         }
 500     }
 501
 502     va_pic = &pic_param->CurrPic;
 503     OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
 504     OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
 505
 506     ADVANCE_BCS_BATCH(batch);
 507 }
 508
 509 static void
 510 gen7_mfd_avc_phantom_slice_first(VADriverContextP ctx,
 511                                  VAPictureParameterBufferH264 *pic_param,
 512                                  VASliceParameterBufferH264 *next_slice_param,
 513                                  struct gen7_mfd_context *gen7_mfd_context)
 514 {
 515     gen6_mfd_avc_phantom_slice(ctx, pic_param, next_slice_param, gen7_mfd_context->base.batch);
 516 }
 517
 518 static void
 519 gen7_mfd_avc_slice_state(VADriverContextP ctx,
 520                          VAPictureParameterBufferH264 *pic_param,
 521                          VASliceParameterBufferH264 *slice_param,
 522                          VASliceParameterBufferH264 *next_slice_param,
 523                          struct gen7_mfd_context *gen7_mfd_context)
 524 {
 525     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 526     int width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
 527     int height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1;
 528     int slice_hor_pos, slice_ver_pos, next_slice_hor_pos, next_slice_ver_pos;
 529     int num_ref_idx_l0, num_ref_idx_l1;
 530     int mbaff_picture = (!pic_param->pic_fields.bits.field_pic_flag &&
 531                          pic_param->seq_fields.bits.mb_adaptive_frame_field_flag);
 532     int first_mb_in_slice = 0, first_mb_in_next_slice = 0;
 533     int slice_type;
 534
 535     if (slice_param->slice_type == SLICE_TYPE_I ||
 536         slice_param->slice_type == SLICE_TYPE_SI) {
 537         slice_type = SLICE_TYPE_I;
 538     } else if (slice_param->slice_type == SLICE_TYPE_P ||
 539                slice_param->slice_type == SLICE_TYPE_SP) {
 540         slice_type = SLICE_TYPE_P;
 541     } else {
 542         assert(slice_param->slice_type == SLICE_TYPE_B);
 543         slice_type = SLICE_TYPE_B;
 544     }
 545
 546     if (slice_type == SLICE_TYPE_I) {
 547         assert(slice_param->num_ref_idx_l0_active_minus1 == 0);
 548         assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
 549         num_ref_idx_l0 = 0;
 550         num_ref_idx_l1 = 0;
 551     } else if (slice_type == SLICE_TYPE_P) {
 552         assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
 553         num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
 554         num_ref_idx_l1 = 0;
 555     } else {
 556         num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
 557         num_ref_idx_l1 = slice_param->num_ref_idx_l1_active_minus1 + 1;
 558     }
 559
 560     first_mb_in_slice = slice_param->first_mb_in_slice;
 561     slice_hor_pos = first_mb_in_slice % width_in_mbs;
 562     slice_ver_pos = first_mb_in_slice / width_in_mbs;
 563
 564     if (mbaff_picture)
 565         slice_ver_pos = slice_ver_pos << 1;
 566
 567     if (next_slice_param) {
 568         first_mb_in_next_slice = next_slice_param->first_mb_in_slice;
 569         next_slice_hor_pos = first_mb_in_next_slice % width_in_mbs;
 570         next_slice_ver_pos = first_mb_in_next_slice / width_in_mbs;
 571
 572         if (mbaff_picture)
 573             next_slice_ver_pos = next_slice_ver_pos << 1;
 574     } else {
 575         next_slice_hor_pos = 0;
 576         next_slice_ver_pos = height_in_mbs / (1 + !!pic_param->pic_fields.bits.field_pic_flag);
 577     }
 578
 579     BEGIN_BCS_BATCH(batch, 11); /* FIXME: is it 10??? */
 580     OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2));
 581     OUT_BCS_BATCH(batch, slice_type);
 582     OUT_BCS_BATCH(batch,
 583                   (num_ref_idx_l1 << 24) |
 584                   (num_ref_idx_l0 << 16) |
 585                   (slice_param->chroma_log2_weight_denom << 8) |
 586                   (slice_param->luma_log2_weight_denom << 0));
 587     OUT_BCS_BATCH(batch,
 588                   (slice_param->direct_spatial_mv_pred_flag << 29) |
 589                   (slice_param->disable_deblocking_filter_idc << 27) |
 590                   (slice_param->cabac_init_idc << 24) |
 591                   ((pic_param->pic_init_qp_minus26 + 26 + slice_param->slice_qp_delta) << 16) |
 592                   ((slice_param->slice_beta_offset_div2 & 0xf) << 8) |
 593                   ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0));
 594     OUT_BCS_BATCH(batch,
 595                   (slice_ver_pos << 24) |
 596                   (slice_hor_pos << 16) |
 597                   (first_mb_in_slice << 0));
 598     OUT_BCS_BATCH(batch,
 599                   (next_slice_ver_pos << 16) |
 600                   (next_slice_hor_pos << 0));
 601     OUT_BCS_BATCH(batch,
 602                   (next_slice_param == NULL) << 19); /* last slice flag */
 603     OUT_BCS_BATCH(batch, 0);
 604     OUT_BCS_BATCH(batch, 0);
 605     OUT_BCS_BATCH(batch, 0);
 606     OUT_BCS_BATCH(batch, 0);
 607     ADVANCE_BCS_BATCH(batch);
 608 }
 609
 610 static inline void
 611 gen7_mfd_avc_ref_idx_state(VADriverContextP ctx,
 612                            VAPictureParameterBufferH264 *pic_param,
 613                            VASliceParameterBufferH264 *slice_param,
 614                            struct gen7_mfd_context *gen7_mfd_context)
 615 {
 616     gen6_send_avc_ref_idx_state(
 617         gen7_mfd_context->base.batch,
 618         slice_param,
 619         gen7_mfd_context->reference_surface
 620     );
 621 }
 622
 623 static void
 624 gen7_mfd_avc_weightoffset_state(VADriverContextP ctx,
 625                                 VAPictureParameterBufferH264 *pic_param,
 626                                 VASliceParameterBufferH264 *slice_param,
 627                                 struct gen7_mfd_context *gen7_mfd_context)
 628 {
 629     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 630     int i, j, num_weight_offset_table = 0;
 631     short weightoffsets[32 * 6];
 632
 633     if ((slice_param->slice_type == SLICE_TYPE_P ||
 634          slice_param->slice_type == SLICE_TYPE_SP) &&
 635         (pic_param->pic_fields.bits.weighted_pred_flag == 1)) {
 636         num_weight_offset_table = 1;
 637     }
 638
 639     if ((slice_param->slice_type == SLICE_TYPE_B) &&
 640         (pic_param->pic_fields.bits.weighted_bipred_idc == 1)) {
 641         num_weight_offset_table = 2;
 642     }
 643
 644     for (i = 0; i < num_weight_offset_table; i++) {
 645         BEGIN_BCS_BATCH(batch, 98);
 646         OUT_BCS_BATCH(batch, MFX_AVC_WEIGHTOFFSET_STATE | (98 - 2));
 647         OUT_BCS_BATCH(batch, i);
 648
 649         if (i == 0) {
 650             for (j = 0; j < 32; j++) {
 651                 weightoffsets[j * 6 + 0] = slice_param->luma_weight_l0[j];
 652                 weightoffsets[j * 6 + 1] = slice_param->luma_offset_l0[j];
 653                 weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l0[j][0];
 654                 weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l0[j][0];
 655                 weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l0[j][1];
 656                 weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l0[j][1];
 657             }
 658         } else {
 659             for (j = 0; j < 32; j++) {
 660                 weightoffsets[j * 6 + 0] = slice_param->luma_weight_l1[j];
 661                 weightoffsets[j * 6 + 1] = slice_param->luma_offset_l1[j];
 662                 weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l1[j][0];
 663                 weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l1[j][0];
 664                 weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l1[j][1];
 665                 weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l1[j][1];
 666             }
 667         }
 668
 669         intel_batchbuffer_data(batch, weightoffsets, sizeof(weightoffsets));
 670         ADVANCE_BCS_BATCH(batch);
 671     }
 672 }
 673
 674 static void
 675 gen7_mfd_avc_bsd_object(VADriverContextP ctx,
 676                         VAPictureParameterBufferH264 *pic_param,
 677                         VASliceParameterBufferH264 *slice_param,
 678                         dri_bo *slice_data_bo,
 679                         VASliceParameterBufferH264 *next_slice_param,
 680                         struct gen7_mfd_context *gen7_mfd_context)
 681 {
 682     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 683     unsigned int slice_data_bit_offset;
 684
 685     slice_data_bit_offset = avc_get_first_mb_bit_offset(
 686                                 slice_data_bo,
 687                                 slice_param,
 688                                 pic_param->pic_fields.bits.entropy_coding_mode_flag
 689                             );
 690
 691     /* the input bitsteam format on GEN7 differs from GEN6 */
 692     BEGIN_BCS_BATCH(batch, 6);
 693     OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2));
 694     OUT_BCS_BATCH(batch,
 695                   (slice_param->slice_data_size - slice_param->slice_data_offset));
 696     OUT_BCS_BATCH(batch, slice_param->slice_data_offset);
 697     OUT_BCS_BATCH(batch,
 698                   (0 << 31) |
 699                   (0 << 14) |
 700                   (0 << 12) |
 701                   (0 << 10) |
 702                   (0 << 8));
 703     OUT_BCS_BATCH(batch,
 704                   ((slice_data_bit_offset >> 3) << 16) |
 705                   (1 << 7)  |
 706                   (0 << 5)  |
 707                   (0 << 4)  |
 708                   ((next_slice_param == NULL) << 3) | /* LastSlice Flag */
 709                   (slice_data_bit_offset & 0x7));
 710     OUT_BCS_BATCH(batch, 0);
 711     ADVANCE_BCS_BATCH(batch);
 712 }
 713
 714 static inline void
 715 gen7_mfd_avc_context_init(
 716     VADriverContextP         ctx,
 717     struct gen7_mfd_context *gen7_mfd_context
 718 )
 719 {
 720     /* Initialize flat scaling lists */
 721     avc_gen_default_iq_matrix(&gen7_mfd_context->iq_matrix.h264);
 722 }
 723
 724 static void
 725 gen7_mfd_avc_decode_init(VADriverContextP ctx,
 726                          struct decode_state *decode_state,
 727                          struct gen7_mfd_context *gen7_mfd_context)
 728 {
 729     VAPictureParameterBufferH264 *pic_param;
 730     VASliceParameterBufferH264 *slice_param;
 731     struct i965_driver_data *i965 = i965_driver_data(ctx);
 732     struct object_surface *obj_surface;
 733     dri_bo *bo;
 734     int i, j, enable_avc_ildb = 0;
 735     unsigned int width_in_mbs, height_in_mbs;
 736
 737     for (j = 0; j < decode_state->num_slice_params && enable_avc_ildb == 0; j++) {
 738         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
 739         slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
 740
 741         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
 742             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
 743             assert((slice_param->slice_type == SLICE_TYPE_I) ||
 744                    (slice_param->slice_type == SLICE_TYPE_SI) ||
 745                    (slice_param->slice_type == SLICE_TYPE_P) ||
 746                    (slice_param->slice_type == SLICE_TYPE_SP) ||
 747                    (slice_param->slice_type == SLICE_TYPE_B));
 748
 749             if (slice_param->disable_deblocking_filter_idc != 1) {
 750                 enable_avc_ildb = 1;
 751                 break;
 752             }
 753
 754             slice_param++;
 755         }
 756     }
 757
 758     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 759     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 760     intel_update_avc_frame_store_index(ctx, decode_state, pic_param,
 761                                        gen7_mfd_context->reference_surface, &gen7_mfd_context->fs_ctx);
 762     width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
 763     height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1;
 764     assert(width_in_mbs > 0 && width_in_mbs <= 256); /* 4K */
 765     assert(height_in_mbs > 0 && height_in_mbs <= 256);
 766
 767     /* Current decoded picture */
 768     obj_surface = decode_state->render_object;
 769     if (pic_param->pic_fields.bits.reference_pic_flag)
 770         obj_surface->flags |= SURFACE_REFERENCED;
 771     else
 772         obj_surface->flags &= ~SURFACE_REFERENCED;
 773
 774     avc_ensure_surface_bo(ctx, decode_state, obj_surface, pic_param);
 775     gen7_mfd_init_avc_surface(ctx, pic_param, obj_surface);
 776
 777     dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo);
 778     gen7_mfd_context->post_deblocking_output.bo = obj_surface->bo;
 779     dri_bo_reference(gen7_mfd_context->post_deblocking_output.bo);
 780     gen7_mfd_context->post_deblocking_output.valid = enable_avc_ildb;
 781
 782     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
 783     gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
 784     dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
 785     gen7_mfd_context->pre_deblocking_output.valid = !enable_avc_ildb;
 786
 787     dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo);
 788     bo = dri_bo_alloc(i965->intel.bufmgr,
 789                       "intra row store",
 790                       width_in_mbs * 64,
 791                       0x1000);
 792     assert(bo);
 793     gen7_mfd_context->intra_row_store_scratch_buffer.bo = bo;
 794     gen7_mfd_context->intra_row_store_scratch_buffer.valid = 1;
 795
 796     dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
 797     bo = dri_bo_alloc(i965->intel.bufmgr,
 798                       "deblocking filter row store",
 799                       width_in_mbs * 64 * 4,
 800                       0x1000);
 801     assert(bo);
 802     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
 803     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1;
 804
 805     dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
 806     bo = dri_bo_alloc(i965->intel.bufmgr,
 807                       "bsd mpc row store",
 808                       width_in_mbs * 64 * 2,
 809                       0x1000);
 810     assert(bo);
 811     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
 812     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
 813
 814     dri_bo_unreference(gen7_mfd_context->mpr_row_store_scratch_buffer.bo);
 815     bo = dri_bo_alloc(i965->intel.bufmgr,
 816                       "mpr row store",
 817                       width_in_mbs * 64 * 2,
 818                       0x1000);
 819     assert(bo);
 820     gen7_mfd_context->mpr_row_store_scratch_buffer.bo = bo;
 821     gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 1;
 822
 823     gen7_mfd_context->bitplane_read_buffer.valid = 0;
 824 }
 825
 826 static void
 827 gen7_mfd_avc_decode_picture(VADriverContextP ctx,
 828                             struct decode_state *decode_state,
 829                             struct gen7_mfd_context *gen7_mfd_context)
 830 {
 831     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 832     VAPictureParameterBufferH264 *pic_param;
 833     VASliceParameterBufferH264 *slice_param, *next_slice_param, *next_slice_group_param;
 834     dri_bo *slice_data_bo;
 835     int i, j;
 836
 837     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 838     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 839     gen7_mfd_avc_decode_init(ctx, decode_state, gen7_mfd_context);
 840
 841     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
 842     intel_batchbuffer_emit_mi_flush(batch);
 843     gen7_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
 844     gen7_mfd_surface_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
 845     gen7_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
 846     gen7_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
 847     gen7_mfd_avc_qm_state(ctx, decode_state, gen7_mfd_context);
 848     gen7_mfd_avc_img_state(ctx, decode_state, gen7_mfd_context);
 849
 850     for (j = 0; j < decode_state->num_slice_params; j++) {
 851         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
 852         slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
 853         slice_data_bo = decode_state->slice_datas[j]->bo;
 854         gen7_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_AVC, gen7_mfd_context);
 855
 856         if (j == decode_state->num_slice_params - 1)
 857             next_slice_group_param = NULL;
 858         else
 859             next_slice_group_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j + 1]->buffer;
 860
 861         if (j == 0 && slice_param->first_mb_in_slice)
 862             gen7_mfd_avc_phantom_slice_first(ctx, pic_param, slice_param, gen7_mfd_context);
 863
 864         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
 865             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
 866             assert((slice_param->slice_type == SLICE_TYPE_I) ||
 867                    (slice_param->slice_type == SLICE_TYPE_SI) ||
 868                    (slice_param->slice_type == SLICE_TYPE_P) ||
 869                    (slice_param->slice_type == SLICE_TYPE_SP) ||
 870                    (slice_param->slice_type == SLICE_TYPE_B));
 871
 872             if (i < decode_state->slice_params[j]->num_elements - 1)
 873                 next_slice_param = slice_param + 1;
 874             else
 875                 next_slice_param = next_slice_group_param;
 876
 877             gen7_mfd_avc_directmode_state(ctx, decode_state, pic_param, slice_param, gen7_mfd_context);
 878             gen7_mfd_avc_ref_idx_state(ctx, pic_param, slice_param, gen7_mfd_context);
 879             gen7_mfd_avc_weightoffset_state(ctx, pic_param, slice_param, gen7_mfd_context);
 880             gen7_mfd_avc_slice_state(ctx, pic_param, slice_param, next_slice_param, gen7_mfd_context);
 881             gen7_mfd_avc_bsd_object(ctx, pic_param, slice_param, slice_data_bo, next_slice_param, gen7_mfd_context);
 882             slice_param++;
 883         }
 884     }
 885
 886     intel_batchbuffer_end_atomic(batch);
 887     intel_batchbuffer_flush(batch);
 888 }
 889
 890 static void
 891 gen7_mfd_mpeg2_decode_init(VADriverContextP ctx,
 892                            struct decode_state *decode_state,
 893                            struct gen7_mfd_context *gen7_mfd_context)
 894 {
 895     VAPictureParameterBufferMPEG2 *pic_param;
 896     struct i965_driver_data *i965 = i965_driver_data(ctx);
 897     struct object_surface *obj_surface;
 898     dri_bo *bo;
 899     unsigned int width_in_mbs;
 900
 901     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 902     pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
 903     width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16;
 904
 905     mpeg2_set_reference_surfaces(
 906         ctx,
 907         gen7_mfd_context->reference_surface,
 908         decode_state,
 909         pic_param
 910     );
 911
 912     /* Current decoded picture */
 913     obj_surface = decode_state->render_object;
 914     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
 915
 916     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
 917     gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
 918     dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
 919     gen7_mfd_context->pre_deblocking_output.valid = 1;
 920
 921     dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
 922     bo = dri_bo_alloc(i965->intel.bufmgr,
 923                       "bsd mpc row store",
 924                       width_in_mbs * 96,
 925                       0x1000);
 926     assert(bo);
 927     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
 928     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
 929
 930     gen7_mfd_context->post_deblocking_output.valid = 0;
 931     gen7_mfd_context->intra_row_store_scratch_buffer.valid = 0;
 932     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 0;
 933     gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
 934     gen7_mfd_context->bitplane_read_buffer.valid = 0;
 935 }
 936
 937 static void
 938 gen7_mfd_mpeg2_pic_state(VADriverContextP ctx,
 939                          struct decode_state *decode_state,
 940                          struct gen7_mfd_context *gen7_mfd_context)
 941 {
 942     struct i965_driver_data * const i965 = i965_driver_data(ctx);
 943     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 944     VAPictureParameterBufferMPEG2 *pic_param;
 945     unsigned int slice_concealment_disable_bit = 0;
 946
 947     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 948     pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
 949
 950     if (IS_HASWELL(i965->intel.device_info)) {
 951         /* XXX: disable concealment for now */
 952         slice_concealment_disable_bit = 1;
 953     }
 954
 955     BEGIN_BCS_BATCH(batch, 13);
 956     OUT_BCS_BATCH(batch, MFX_MPEG2_PIC_STATE | (13 - 2));
 957     OUT_BCS_BATCH(batch,
 958                   (pic_param->f_code & 0xf) << 28 | /* f_code[1][1] */
 959                   ((pic_param->f_code >> 4) & 0xf) << 24 | /* f_code[1][0] */
 960                   ((pic_param->f_code >> 8) & 0xf) << 20 | /* f_code[0][1] */
 961                   ((pic_param->f_code >> 12) & 0xf) << 16 | /* f_code[0][0] */
 962                   pic_param->picture_coding_extension.bits.intra_dc_precision << 14 |
 963                   pic_param->picture_coding_extension.bits.picture_structure << 12 |
 964                   pic_param->picture_coding_extension.bits.top_field_first << 11 |
 965                   pic_param->picture_coding_extension.bits.frame_pred_frame_dct << 10 |
 966                   pic_param->picture_coding_extension.bits.concealment_motion_vectors << 9 |
 967                   pic_param->picture_coding_extension.bits.q_scale_type << 8 |
 968                   pic_param->picture_coding_extension.bits.intra_vlc_format << 7 |
 969                   pic_param->picture_coding_extension.bits.alternate_scan << 6);
 970     OUT_BCS_BATCH(batch,
 971                   pic_param->picture_coding_type << 9);
 972     OUT_BCS_BATCH(batch,
 973                   (slice_concealment_disable_bit << 31) |
 974                   ((ALIGN(pic_param->vertical_size, 16) / 16) - 1) << 16 |
 975                   ((ALIGN(pic_param->horizontal_size, 16) / 16) - 1));
 976     OUT_BCS_BATCH(batch, 0);
 977     OUT_BCS_BATCH(batch, 0);
 978     OUT_BCS_BATCH(batch, 0);
 979     OUT_BCS_BATCH(batch, 0);
 980     OUT_BCS_BATCH(batch, 0);
 981     OUT_BCS_BATCH(batch, 0);
 982     OUT_BCS_BATCH(batch, 0);
 983     OUT_BCS_BATCH(batch, 0);
 984     OUT_BCS_BATCH(batch, 0);
 985     ADVANCE_BCS_BATCH(batch);
 986 }
 987
 988 static void
 989 gen7_mfd_mpeg2_qm_state(VADriverContextP ctx,
 990                         struct decode_state *decode_state,
 991                         struct gen7_mfd_context *gen7_mfd_context)
 992 {
 993     VAIQMatrixBufferMPEG2 * const gen_iq_matrix = &gen7_mfd_context->iq_matrix.mpeg2;
 994     int i, j;
 995
 996     /* Update internal QM state */
 997     if (decode_state->iq_matrix && decode_state->iq_matrix->buffer) {
 998         VAIQMatrixBufferMPEG2 * const iq_matrix =
 999             (VAIQMatrixBufferMPEG2 *)decode_state->iq_matrix->buffer;
1000
1001         if (gen_iq_matrix->load_intra_quantiser_matrix == -1 ||
1002             iq_matrix->load_intra_quantiser_matrix) {
1003             gen_iq_matrix->load_intra_quantiser_matrix =
1004                 iq_matrix->load_intra_quantiser_matrix;
1005             if (iq_matrix->load_intra_quantiser_matrix) {
1006                 for (j = 0; j < 64; j++)
1007                     gen_iq_matrix->intra_quantiser_matrix[zigzag_direct[j]] =
1008                         iq_matrix->intra_quantiser_matrix[j];
1009             }
1010         }
1011
1012         if (gen_iq_matrix->load_non_intra_quantiser_matrix == -1 ||
1013             iq_matrix->load_non_intra_quantiser_matrix) {
1014             gen_iq_matrix->load_non_intra_quantiser_matrix =
1015                 iq_matrix->load_non_intra_quantiser_matrix;
1016             if (iq_matrix->load_non_intra_quantiser_matrix) {
1017                 for (j = 0; j < 64; j++)
1018                     gen_iq_matrix->non_intra_quantiser_matrix[zigzag_direct[j]] =
1019                         iq_matrix->non_intra_quantiser_matrix[j];
1020             }
1021         }
1022     }
1023
1024     /* Commit QM state to HW */
1025     for (i = 0; i < 2; i++) {
1026         unsigned char *qm = NULL;
1027         int qm_type;
1028
1029         if (i == 0) {
1030             if (gen_iq_matrix->load_intra_quantiser_matrix) {
1031                 qm = gen_iq_matrix->intra_quantiser_matrix;
1032                 qm_type = MFX_QM_MPEG_INTRA_QUANTIZER_MATRIX;
1033             }
1034         } else {
1035             if (gen_iq_matrix->load_non_intra_quantiser_matrix) {
1036                 qm = gen_iq_matrix->non_intra_quantiser_matrix;
1037                 qm_type = MFX_QM_MPEG_NON_INTRA_QUANTIZER_MATRIX;
1038             }
1039         }
1040
1041         if (!qm)
1042             continue;
1043
1044         gen7_mfd_qm_state(ctx, qm_type, qm, 64, gen7_mfd_context);
1045     }
1046 }
1047
1048 uint32_t mpeg2_get_slice_data_length(dri_bo *slice_data_bo, VASliceParameterBufferMPEG2 *slice_param)
1049 {
1050     uint8_t *buf;
1051     uint32_t buf_offset = slice_param->slice_data_offset + (slice_param->macroblock_offset >> 3);
1052     uint32_t buf_size = slice_param->slice_data_size - (slice_param->macroblock_offset >> 3);
1053     uint32_t i = 0;
1054
1055     dri_bo_map(slice_data_bo, 0);
1056     buf = (uint8_t *)slice_data_bo->virtual + buf_offset;
1057
1058     if (buf_size < 4)
1059         return buf_size;
1060
1061     while (i <= (buf_size - 4)) {
1062         if (buf[i + 2] > 1) {
1063             i += 3;
1064         } else if (buf[i + 1]) {
1065             i += 2;
1066         } else if (buf[i] || buf[i + 2] != 1) {
1067             i++;
1068         } else {
1069             break;
1070         }
1071     }
1072
1073     if (i <= (buf_size - 4))
1074         buf_size = i;
1075
1076     dri_bo_unmap(slice_data_bo);
1077     return buf_size;
1078 }
1079
1080 static void
1081 gen7_mfd_mpeg2_bsd_object(VADriverContextP ctx,
1082                           VAPictureParameterBufferMPEG2 *pic_param,
1083                           VASliceParameterBufferMPEG2 *slice_param,
1084                           dri_bo *slice_data_bo,
1085                           VASliceParameterBufferMPEG2 *next_slice_param,
1086                           struct gen7_mfd_context *gen7_mfd_context)
1087 {
1088     struct i965_driver_data * const i965 = i965_driver_data(ctx);
1089     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1090     unsigned int width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16;
1091     int mb_count, vpos0, hpos0, vpos1, hpos1, is_field_pic_wa, is_field_pic = 0;
1092
1093     if (pic_param->picture_coding_extension.bits.picture_structure == MPEG_TOP_FIELD ||
1094         pic_param->picture_coding_extension.bits.picture_structure == MPEG_BOTTOM_FIELD)
1095         is_field_pic = 1;
1096     is_field_pic_wa = is_field_pic &&
1097                       gen7_mfd_context->wa_mpeg2_slice_vertical_position > 0;
1098
1099     vpos0 = slice_param->slice_vertical_position / (1 + is_field_pic_wa);
1100     hpos0 = slice_param->slice_horizontal_position;
1101
1102     if (next_slice_param == NULL) {
1103         vpos1 = ALIGN(pic_param->vertical_size, 16) / 16 / (1 + is_field_pic);
1104         hpos1 = 0;
1105     } else {
1106         vpos1 = next_slice_param->slice_vertical_position / (1 + is_field_pic_wa);
1107         hpos1 = next_slice_param->slice_horizontal_position;
1108     }
1109
1110     mb_count = (vpos1 * width_in_mbs + hpos1) - (vpos0 * width_in_mbs + hpos0);
1111
1112     BEGIN_BCS_BATCH(batch, 5);
1113     OUT_BCS_BATCH(batch, MFD_MPEG2_BSD_OBJECT | (5 - 2));
1114     OUT_BCS_BATCH(batch,
1115                   mpeg2_get_slice_data_length(slice_data_bo, slice_param));
1116     OUT_BCS_BATCH(batch,
1117                   slice_param->slice_data_offset + (slice_param->macroblock_offset >> 3));
1118     OUT_BCS_BATCH(batch,
1119                   hpos0 << 24 |
1120                   vpos0 << 16 |
1121                   mb_count << 8 |
1122                   (next_slice_param == NULL) << 5 |
1123                   (next_slice_param == NULL) << 3 |
1124                   (slice_param->macroblock_offset & 0x7));
1125     OUT_BCS_BATCH(batch,
1126                   (slice_param->quantiser_scale_code << 24) |
1127                   (IS_HASWELL(i965->intel.device_info) ? (vpos1 << 8 | hpos1) : 0));
1128     ADVANCE_BCS_BATCH(batch);
1129 }
1130
1131 static void
1132 gen7_mfd_mpeg2_decode_picture(VADriverContextP ctx,
1133                               struct decode_state *decode_state,
1134                               struct gen7_mfd_context *gen7_mfd_context)
1135 {
1136     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1137     VAPictureParameterBufferMPEG2 *pic_param;
1138     VASliceParameterBufferMPEG2 *slice_param, *next_slice_param, *next_slice_group_param;
1139     dri_bo *slice_data_bo;
1140     int i, j;
1141
1142     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1143     pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
1144
1145     gen7_mfd_mpeg2_decode_init(ctx, decode_state, gen7_mfd_context);
1146     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
1147     intel_batchbuffer_emit_mi_flush(batch);
1148     gen7_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1149     gen7_mfd_surface_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1150     gen7_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1151     gen7_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1152     gen7_mfd_mpeg2_pic_state(ctx, decode_state, gen7_mfd_context);
1153     gen7_mfd_mpeg2_qm_state(ctx, decode_state, gen7_mfd_context);
1154
1155     if (gen7_mfd_context->wa_mpeg2_slice_vertical_position < 0)
1156         gen7_mfd_context->wa_mpeg2_slice_vertical_position =
1157             mpeg2_wa_slice_vertical_position(decode_state, pic_param);
1158
1159     for (j = 0; j < decode_state->num_slice_params; j++) {
1160         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
1161         slice_param = (VASliceParameterBufferMPEG2 *)decode_state->slice_params[j]->buffer;
1162         slice_data_bo = decode_state->slice_datas[j]->bo;
1163         gen7_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_MPEG2, gen7_mfd_context);
1164
1165         if (j == decode_state->num_slice_params - 1)
1166             next_slice_group_param = NULL;
1167         else
1168             next_slice_group_param = (VASliceParameterBufferMPEG2 *)decode_state->slice_params[j + 1]->buffer;
1169
1170         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
1171             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
1172
1173             if (i < decode_state->slice_params[j]->num_elements - 1)
1174                 next_slice_param = slice_param + 1;
1175             else
1176                 next_slice_param = next_slice_group_param;
1177
1178             gen7_mfd_mpeg2_bsd_object(ctx, pic_param, slice_param, slice_data_bo, next_slice_param, gen7_mfd_context);
1179             slice_param++;
1180         }
1181     }
1182
1183     intel_batchbuffer_end_atomic(batch);
1184     intel_batchbuffer_flush(batch);
1185 }
1186
1187 static const int va_to_gen7_vc1_mv[4] = {
1188     1, /* 1-MV */
1189     2, /* 1-MV half-pel */
1190     3, /* 1-MV half-pef bilinear */
1191     0, /* Mixed MV */
1192 };
1193
1194 static const int b_picture_scale_factor[21] = {
1195     128, 85,  170, 64,  192,
1196     51,  102, 153, 204, 43,
1197     215, 37,  74,  111, 148,
1198     185, 222, 32,  96,  160,
1199     224,
1200 };
1201
1202 static const int va_to_gen7_vc1_condover[3] = {
1203     0,
1204     2,
1205     3
1206 };
1207
1208 static const int va_to_gen7_vc1_profile[4] = {
1209     GEN7_VC1_SIMPLE_PROFILE,
1210     GEN7_VC1_MAIN_PROFILE,
1211     GEN7_VC1_RESERVED_PROFILE,
1212     GEN7_VC1_ADVANCED_PROFILE
1213 };
1214
1215 static const int fptype_to_picture_type[8][2] = {
1216     {GEN7_VC1_I_PICTURE, GEN7_VC1_I_PICTURE},
1217     {GEN7_VC1_I_PICTURE, GEN7_VC1_P_PICTURE},
1218     {GEN7_VC1_P_PICTURE, GEN7_VC1_I_PICTURE},
1219     {GEN7_VC1_P_PICTURE, GEN7_VC1_P_PICTURE},
1220     {GEN7_VC1_B_PICTURE, GEN7_VC1_B_PICTURE},
1221     {GEN7_VC1_B_PICTURE, GEN7_VC1_BI_PICTURE},
1222     {GEN7_VC1_BI_PICTURE, GEN7_VC1_B_PICTURE},
1223     {GEN7_VC1_BI_PICTURE, GEN7_VC1_BI_PICTURE}
1224 };
1225
1226 static void
1227 gen7_mfd_free_vc1_surface(void **data)
1228 {
1229     struct gen7_vc1_surface *gen7_vc1_surface = *data;
1230
1231     if (!gen7_vc1_surface)
1232         return;
1233
1234     dri_bo_unreference(gen7_vc1_surface->dmv_top);
1235     dri_bo_unreference(gen7_vc1_surface->dmv_bottom);
1236     free(gen7_vc1_surface);
1237     *data = NULL;
1238 }
1239
1240 static void
1241 gen7_mfd_init_vc1_surface(VADriverContextP ctx,
1242                           VAPictureParameterBufferVC1 *pic_param,
1243                           struct object_surface *obj_surface)
1244 {
1245     struct i965_driver_data *i965 = i965_driver_data(ctx);
1246     struct gen7_vc1_surface *gen7_vc1_surface = obj_surface->private_data;
1247     int height_in_mbs;
1248     int picture_type;
1249     int is_first_field = 1;
1250
1251     if (!pic_param->sequence_fields.bits.interlace ||
1252         (pic_param->picture_fields.bits.frame_coding_mode < 2)) { /* Progressive or Frame-Interlace */
1253         picture_type = pic_param->picture_fields.bits.picture_type;
1254     } else {/* Field-Interlace */
1255         is_first_field = pic_param->picture_fields.bits.is_first_field;
1256         picture_type = fptype_to_picture_type[pic_param->picture_fields.bits.picture_type][!is_first_field];
1257     }
1258
1259     obj_surface->free_private_data = gen7_mfd_free_vc1_surface;
1260
1261     if (!gen7_vc1_surface) {
1262         gen7_vc1_surface = calloc(sizeof(struct gen7_vc1_surface), 1);
1263         assert(gen7_vc1_surface);
1264         assert((obj_surface->size & 0x3f) == 0);
1265         obj_surface->private_data = gen7_vc1_surface;
1266     }
1267
1268     if (!pic_param->sequence_fields.bits.interlace ||
1269         pic_param->picture_fields.bits.frame_coding_mode < 2 || /* Progressive or Frame-Interlace */
1270         is_first_field) {
1271         gen7_vc1_surface->picture_type_top = 0;
1272         gen7_vc1_surface->picture_type_bottom = 0;
1273         gen7_vc1_surface->intensity_compensation = 0;
1274         gen7_vc1_surface->luma_scale = 0;
1275         gen7_vc1_surface->luma_shift = 0;
1276     }
1277
1278     if (!pic_param->sequence_fields.bits.interlace ||
1279         pic_param->picture_fields.bits.frame_coding_mode < 2) { /* Progressive or Frame-Interlace */
1280         gen7_vc1_surface->picture_type = picture_type;
1281         gen7_vc1_surface->picture_type_top = picture_type;
1282         gen7_vc1_surface->picture_type_bottom = picture_type;
1283     } else if (pic_param->picture_fields.bits.top_field_first ^ is_first_field)
1284         gen7_vc1_surface->picture_type_bottom = picture_type;
1285     else
1286         gen7_vc1_surface->picture_type_top = picture_type;
1287
1288     if (gen7_vc1_surface->dmv_top == NULL) {
1289         height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16;
1290         gen7_vc1_surface->dmv_top = dri_bo_alloc(i965->intel.bufmgr,
1291                                              "direct mv w/r buffer",
1292                                              128 * height_in_mbs * 64,
1293                                              0x1000);
1294     }
1295
1296     if (pic_param->sequence_fields.bits.interlace &&
1297         gen7_vc1_surface->dmv_bottom == NULL) {
1298         height_in_mbs = ALIGN(pic_param->coded_height, 32) / 32;
1299         gen7_vc1_surface->dmv_bottom = dri_bo_alloc(i965->intel.bufmgr,
1300                                              "direct mv w/r buffer",
1301                                              128 * height_in_mbs * 64,
1302                                              0x1000);
1303     }
1304 }
1305
1306 static void
1307 gen7_mfd_vc1_decode_init(VADriverContextP ctx,
1308                          struct decode_state *decode_state,
1309                          struct gen7_mfd_context *gen7_mfd_context)
1310 {
1311     VAPictureParameterBufferVC1 *pic_param;
1312     struct i965_driver_data *i965 = i965_driver_data(ctx);
1313     struct object_surface *obj_surface;
1314     dri_bo *bo;
1315     int width_in_mbs;
1316     int picture_type;
1317     int intensity_compensation;
1318     int is_first_field = 1;
1319
1320     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1321     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1322     width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1323     intensity_compensation = (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation);
1324
1325     if (!pic_param->sequence_fields.bits.interlace ||
1326         (pic_param->picture_fields.bits.frame_coding_mode < 2)) { /* Progressive or Frame-Interlace */
1327         picture_type = pic_param->picture_fields.bits.picture_type;
1328     } else {/* Field-Interlace */
1329         is_first_field = pic_param->picture_fields.bits.is_first_field;
1330         picture_type = fptype_to_picture_type[pic_param->picture_fields.bits.picture_type][!is_first_field];
1331     }
1332
1333     intel_update_vc1_frame_store_index(ctx,
1334                                        decode_state,
1335                                        pic_param,
1336                                        gen7_mfd_context->reference_surface);
1337
1338     /* Forward reference picture */
1339     obj_surface = decode_state->reference_objects[0];
1340     if (pic_param->forward_reference_picture != VA_INVALID_ID &&
1341         obj_surface &&
1342         obj_surface->private_data) {
1343         if (picture_type == 1 && intensity_compensation) { /* P picture */
1344             struct gen7_vc1_surface *gen7_vc1_surface = obj_surface->private_data;
1345
1346             gen7_vc1_surface->intensity_compensation = intensity_compensation;
1347             gen7_vc1_surface->luma_scale = pic_param->luma_scale;
1348             gen7_vc1_surface->luma_shift = pic_param->luma_shift;
1349         }
1350     }
1351
1352     /* Current decoded picture */
1353     obj_surface = decode_state->render_object;
1354     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
1355     gen7_mfd_init_vc1_surface(ctx, pic_param, obj_surface);
1356
1357     dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo);
1358     gen7_mfd_context->post_deblocking_output.bo = obj_surface->bo;
1359     dri_bo_reference(gen7_mfd_context->post_deblocking_output.bo);
1360
1361     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
1362     gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
1363     dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
1364
1365     if (picture_type == GEN7_VC1_SKIPPED_PICTURE) {
1366         gen7_mfd_context->post_deblocking_output.valid = 0;
1367         gen7_mfd_context->pre_deblocking_output.valid = 1;
1368     } else {
1369         gen7_mfd_context->post_deblocking_output.valid = pic_param->entrypoint_fields.bits.loopfilter;
1370         gen7_mfd_context->pre_deblocking_output.valid = !pic_param->entrypoint_fields.bits.loopfilter;
1371     }
1372
1373     dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo);
1374     bo = dri_bo_alloc(i965->intel.bufmgr,
1375                       "intra row store",
1376                       width_in_mbs * 64,
1377                       0x1000);
1378     assert(bo);
1379     gen7_mfd_context->intra_row_store_scratch_buffer.bo = bo;
1380     gen7_mfd_context->intra_row_store_scratch_buffer.valid = 1;
1381
1382     dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
1383     bo = dri_bo_alloc(i965->intel.bufmgr,
1384                       "deblocking filter row store",
1385                       width_in_mbs * 7 * 64,
1386                       0x1000);
1387     assert(bo);
1388     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
1389     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1;
1390
1391     dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
1392     bo = dri_bo_alloc(i965->intel.bufmgr,
1393                       "bsd mpc row store",
1394                       width_in_mbs * 96,
1395                       0x1000);
1396     assert(bo);
1397     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
1398     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
1399
1400     gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
1401
1402     if (picture_type == GEN7_VC1_SKIPPED_PICTURE)
1403         gen7_mfd_context->bitplane_read_buffer.valid = 1;
1404     else
1405         gen7_mfd_context->bitplane_read_buffer.valid = !!(pic_param->bitplane_present.value & 0x7f);
1406     dri_bo_unreference(gen7_mfd_context->bitplane_read_buffer.bo);
1407
1408     if (gen7_mfd_context->bitplane_read_buffer.valid) {
1409         int width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1410         int height_in_mbs;
1411         int bitplane_width = ALIGN(width_in_mbs, 2) / 2;
1412         int src_w, src_h;
1413         uint8_t *src = NULL, *dst = NULL;
1414
1415         if (!pic_param->sequence_fields.bits.interlace ||
1416             (pic_param->picture_fields.bits.frame_coding_mode < 2)) /* Progressive or Frame-Interlace */
1417             height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16;
1418         else /* Field-Interlace */
1419             height_in_mbs = ALIGN(pic_param->coded_height, 32) / 32;
1420
1421         bo = dri_bo_alloc(i965->intel.bufmgr,
1422                           "VC-1 Bitplane",
1423                           bitplane_width * height_in_mbs,
1424                           0x1000);
1425         assert(bo);
1426         gen7_mfd_context->bitplane_read_buffer.bo = bo;
1427
1428         dri_bo_map(bo, True);
1429         assert(bo->virtual);
1430         dst = bo->virtual;
1431
1432         if (picture_type == GEN7_VC1_SKIPPED_PICTURE) {
1433             for (src_h = 0; src_h < height_in_mbs; src_h++) {
1434                 for (src_w = 0; src_w < width_in_mbs; src_w++) {
1435                     int dst_index;
1436                     uint8_t src_value = 0x2;
1437
1438                     dst_index = src_w / 2;
1439                     dst[dst_index] = ((dst[dst_index] >> 4) | (src_value << 4));
1440                 }
1441
1442                 if (src_w & 1)
1443                     dst[src_w / 2] >>= 4;
1444
1445                 dst += bitplane_width;
1446             }
1447         } else {
1448             assert(decode_state->bit_plane->buffer);
1449             src = decode_state->bit_plane->buffer;
1450
1451             for (src_h = 0; src_h < height_in_mbs; src_h++) {
1452                 for (src_w = 0; src_w < width_in_mbs; src_w++) {
1453                     int src_index, dst_index;
1454                     int src_shift;
1455                     uint8_t src_value;
1456
1457                     src_index = (src_h * width_in_mbs + src_w) / 2;
1458                     src_shift = !((src_h * width_in_mbs + src_w) & 1) * 4;
1459                     src_value = ((src[src_index] >> src_shift) & 0xf);
1460
1461                     dst_index = src_w / 2;
1462                     dst[dst_index] = ((dst[dst_index] >> 4) | (src_value << 4));
1463                 }
1464
1465                 if (src_w & 1)
1466                     dst[src_w / 2] >>= 4;
1467
1468                 dst += bitplane_width;
1469             }
1470         }
1471
1472         dri_bo_unmap(bo);
1473     } else
1474         gen7_mfd_context->bitplane_read_buffer.bo = NULL;
1475 }
1476
1477 static void
1478 gen7_mfd_vc1_pic_state(VADriverContextP ctx,
1479                        struct decode_state *decode_state,
1480                        struct gen7_mfd_context *gen7_mfd_context)
1481 {
1482     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1483     VAPictureParameterBufferVC1 *pic_param;
1484     struct object_surface *obj_surface;
1485     struct gen7_vc1_surface *gen7_vc1_surface;
1486     int alt_pquant_config = 0, alt_pquant_edge_mask = 0, alt_pq;
1487     int dquant, dquantfrm, dqprofile, dqdbedge, dqsbedge, dqbilevel;
1488     int unified_mv_mode = 0;
1489     int ref_field_pic_polarity = 0;
1490     int scale_factor = 0;
1491     int trans_ac_y = 0;
1492     int dmv_surface_valid = 0;
1493     int frfd = 0;
1494     int brfd = 0;
1495     int fcm = 0;
1496     int picture_type;
1497     int ptype;
1498     int profile;
1499     int overlap = 0;
1500     int interpolation_mode = 0;
1501     int height_in_mbs;
1502     int is_first_field = 1;
1503     int loopfilter = 0;
1504     int bitplane_present;
1505     int forward_mb = 0, mv_type_mb = 0, skip_mb = 0, direct_mb = 0;
1506     int overflags = 0, ac_pred = 0, field_tx = 0;
1507
1508     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1509     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1510
1511     if (!pic_param->sequence_fields.bits.interlace ||
1512         (pic_param->picture_fields.bits.frame_coding_mode < 2)) { /* Progressive or Frame-Interlace */
1513         picture_type = pic_param->picture_fields.bits.picture_type;
1514         height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16;
1515     } else {/* Field-Interlace */
1516         is_first_field = pic_param->picture_fields.bits.is_first_field;
1517         picture_type = fptype_to_picture_type[pic_param->picture_fields.bits.picture_type][!is_first_field];
1518         height_in_mbs = ALIGN(pic_param->coded_height, 32) / 32;
1519     }
1520
1521     profile = va_to_gen7_vc1_profile[pic_param->sequence_fields.bits.profile];
1522     dquant = pic_param->pic_quantizer_fields.bits.dquant;
1523     dquantfrm = pic_param->pic_quantizer_fields.bits.dq_frame;
1524     dqprofile = pic_param->pic_quantizer_fields.bits.dq_profile;
1525     dqdbedge = pic_param->pic_quantizer_fields.bits.dq_db_edge;
1526     dqsbedge = pic_param->pic_quantizer_fields.bits.dq_sb_edge;
1527     dqbilevel = pic_param->pic_quantizer_fields.bits.dq_binary_level;
1528     alt_pq = pic_param->pic_quantizer_fields.bits.alt_pic_quantizer;
1529
1530     if (dquant == 0) {
1531         alt_pquant_config = 0;
1532         alt_pquant_edge_mask = 0;
1533     } else if (dquant == 2) {
1534         alt_pquant_config = 1;
1535         alt_pquant_edge_mask = 0xf;
1536     } else {
1537         assert(dquant == 1);
1538         if (dquantfrm == 0) {
1539             alt_pquant_config = 0;
1540             alt_pquant_edge_mask = 0;
1541             alt_pq = 0;
1542         } else {
1543             assert(dquantfrm == 1);
1544             alt_pquant_config = 1;
1545
1546             switch (dqprofile) {
1547             case 3:
1548                 if (dqbilevel == 0) {
1549                     alt_pquant_config = 2;
1550                     alt_pquant_edge_mask = 0;
1551                 } else {
1552                     assert(dqbilevel == 1);
1553                     alt_pquant_config = 3;
1554                     alt_pquant_edge_mask = 0;
1555                 }
1556                 break;
1557
1558             case 0:
1559                 alt_pquant_edge_mask = 0xf;
1560                 break;
1561
1562             case 1:
1563                 if (dqdbedge == 3)
1564                     alt_pquant_edge_mask = 0x9;
1565                 else
1566                     alt_pquant_edge_mask = (0x3 << dqdbedge);
1567
1568                 break;
1569
1570             case 2:
1571                 alt_pquant_edge_mask = (0x1 << dqsbedge);
1572                 break;
1573
1574             default:
1575                 assert(0);
1576             }
1577         }
1578     }
1579
1580     if ((!pic_param->sequence_fields.bits.interlace ||
1581          pic_param->picture_fields.bits.frame_coding_mode != 1) && /* Progressive or Field-Interlace */
1582         (picture_type == GEN7_VC1_P_PICTURE ||
1583          picture_type == GEN7_VC1_B_PICTURE)) {
1584         if (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation) {
1585             assert(pic_param->mv_fields.bits.mv_mode2 < 4);
1586             unified_mv_mode = va_to_gen7_vc1_mv[pic_param->mv_fields.bits.mv_mode2];
1587         } else {
1588             assert(pic_param->mv_fields.bits.mv_mode < 4);
1589             unified_mv_mode = va_to_gen7_vc1_mv[pic_param->mv_fields.bits.mv_mode];
1590         }
1591     }
1592
1593     if (pic_param->sequence_fields.bits.interlace &&
1594         pic_param->picture_fields.bits.frame_coding_mode == 2 && /* Field-Interlace */
1595         picture_type == GEN7_VC1_P_PICTURE &&
1596         !pic_param->reference_fields.bits.num_reference_pictures) {
1597         if (pic_param->reference_fields.bits.reference_field_pic_indicator == 0) {
1598             ref_field_pic_polarity = is_first_field ?
1599                                         pic_param->picture_fields.bits.top_field_first :
1600                                         !pic_param->picture_fields.bits.top_field_first;
1601         } else {
1602             ref_field_pic_polarity = is_first_field ?
1603                                         !pic_param->picture_fields.bits.top_field_first :
1604                                         pic_param->picture_fields.bits.top_field_first;
1605         }
1606     }
1607
1608     if (pic_param->b_picture_fraction < 21)
1609         scale_factor = b_picture_scale_factor[pic_param->b_picture_fraction];
1610
1611     if (picture_type == GEN7_VC1_SKIPPED_PICTURE) {
1612         ptype = GEN7_VC1_P_PICTURE;
1613         bitplane_present = 1;
1614     } else {
1615         ptype = pic_param->picture_fields.bits.picture_type;
1616         bitplane_present = !!(pic_param->bitplane_present.value & 0x7f);
1617         forward_mb = pic_param->raw_coding.flags.forward_mb;
1618         mv_type_mb = pic_param->raw_coding.flags.mv_type_mb;
1619         skip_mb = pic_param->raw_coding.flags.skip_mb;
1620         direct_mb = pic_param->raw_coding.flags.direct_mb;
1621         overflags = pic_param->raw_coding.flags.overflags;
1622         ac_pred = pic_param->raw_coding.flags.ac_pred;
1623         field_tx = pic_param->raw_coding.flags.field_tx;
1624         loopfilter = pic_param->entrypoint_fields.bits.loopfilter;
1625     }
1626
1627     if (picture_type == GEN7_VC1_I_PICTURE || picture_type == GEN7_VC1_BI_PICTURE) /* I picture */
1628         trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx2;
1629     else {
1630         trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx1;
1631         /*
1632          * 8.3.6.2.1 Transform Type Selection
1633          * If variable-sized transform coding is not enabled,
1634          * then the 8x8 transform shall be used for all blocks.
1635          * it is also MFX_VC1_PIC_STATE requirement.
1636          */
1637         if (pic_param->transform_fields.bits.variable_sized_transform_flag == 0) {
1638             pic_param->transform_fields.bits.mb_level_transform_type_flag   = 1;
1639             pic_param->transform_fields.bits.frame_level_transform_type     = 0;
1640         }
1641     }
1642
1643     if (picture_type == GEN7_VC1_B_PICTURE) {
1644         obj_surface = decode_state->reference_objects[1];
1645
1646         if (pic_param->backward_reference_picture != VA_INVALID_ID &&
1647             obj_surface)
1648             gen7_vc1_surface = (struct gen7_vc1_surface *)(obj_surface->private_data);
1649         else
1650             gen7_vc1_surface = NULL;
1651
1652         if (gen7_vc1_surface) {
1653             if (pic_param->sequence_fields.bits.interlace &&
1654                 pic_param->picture_fields.bits.frame_coding_mode == 2 && /* Field-Interlace */
1655                 pic_param->picture_fields.bits.top_field_first ^ is_first_field) {
1656                 if (gen7_vc1_surface->picture_type_bottom == GEN7_VC1_P_PICTURE)
1657                     dmv_surface_valid = 1;
1658             } else if (gen7_vc1_surface->picture_type_top == GEN7_VC1_P_PICTURE)
1659                 dmv_surface_valid = 1;
1660         }
1661     }
1662
1663     assert(pic_param->picture_fields.bits.frame_coding_mode < 3);
1664
1665     if (pic_param->sequence_fields.bits.interlace) {
1666         if (!pic_param->picture_fields.bits.top_field_first)
1667             fcm = 3;
1668         else
1669             fcm = pic_param->picture_fields.bits.frame_coding_mode;
1670     }
1671
1672     if (pic_param->sequence_fields.bits.interlace &&
1673         pic_param->picture_fields.bits.frame_coding_mode == 2) { /* Field-Interlace */
1674         if (picture_type == GEN7_VC1_I_PICTURE ||
1675              picture_type == GEN7_VC1_P_PICTURE) {
1676             gen7_vc1_surface = (struct gen7_vc1_surface *)(decode_state->render_object->private_data);
1677
1678             if (is_first_field)
1679                 gen7_vc1_surface->reference_distance = pic_param->reference_fields.bits.reference_distance;
1680
1681             frfd = gen7_vc1_surface->reference_distance;
1682         } else if (picture_type == GEN7_VC1_B_PICTURE) {
1683             obj_surface = decode_state->reference_objects[1];
1684
1685             if (pic_param->backward_reference_picture != VA_INVALID_ID &&
1686                 obj_surface)
1687                 gen7_vc1_surface = (struct gen7_vc1_surface *)(obj_surface->private_data);
1688             else
1689                 gen7_vc1_surface = NULL;
1690
1691             if (gen7_vc1_surface) {
1692                 frfd = (scale_factor * gen7_vc1_surface->reference_distance) >> 8;
1693
1694                 brfd = gen7_vc1_surface->reference_distance - frfd - 1;
1695                 if (brfd < 0)
1696                     brfd = 0;
1697             }
1698         }
1699     }
1700
1701     if (pic_param->sequence_fields.bits.overlap) {
1702         if (profile == GEN7_VC1_ADVANCED_PROFILE) {
1703             if (picture_type == GEN7_VC1_P_PICTURE &&
1704                 pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9) {
1705                 overlap = 1;
1706             }
1707             if (picture_type == GEN7_VC1_I_PICTURE ||
1708                 picture_type == GEN7_VC1_BI_PICTURE) {
1709                 if (pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9) {
1710                     overlap = 1;
1711                 } else if (pic_param->conditional_overlap_flag == 1 || /* all block boundaries */
1712                            pic_param->conditional_overlap_flag == 2) { /* coded by OVERFLAGSMB bitplane */
1713                     overlap = 1;
1714                 }
1715             }
1716         } else {
1717             if (pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9 &&
1718                 picture_type != GEN7_VC1_B_PICTURE) {
1719                 overlap = 1;
1720             }
1721         }
1722     }
1723
1724     if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPelBilinear ||
1725         (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation &&
1726          pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPelBilinear))
1727         interpolation_mode = 8 | pic_param->fast_uvmc_flag;
1728     else
1729         interpolation_mode = 0 | pic_param->fast_uvmc_flag;
1730
1731     BEGIN_BCS_BATCH(batch, 6);
1732     OUT_BCS_BATCH(batch, MFD_VC1_LONG_PIC_STATE | (6 - 2));
1733     OUT_BCS_BATCH(batch,
1734                   ((height_in_mbs - 1) << 16) |
1735                   ((ALIGN(pic_param->coded_width, 16) / 16) - 1));
1736     OUT_BCS_BATCH(batch,
1737                   ((ALIGN(pic_param->coded_width, 16) / 16 + 1) / 2 - 1) << 24 |
1738                   dmv_surface_valid << 15 |
1739                   (pic_param->pic_quantizer_fields.bits.quantizer == 0) << 14 | /* implicit quantizer */
1740                   pic_param->rounding_control << 13 |
1741                   pic_param->sequence_fields.bits.syncmarker << 12 |
1742                   interpolation_mode << 8 |
1743                   0 << 7 | /* FIXME: scale up or down ??? */
1744                   pic_param->range_reduction_frame << 6 |
1745                   loopfilter << 5 |
1746                   overlap << 4 |
1747                   !is_first_field << 3 |
1748                   (pic_param->sequence_fields.bits.profile == 3) << 0);
1749     OUT_BCS_BATCH(batch,
1750                   va_to_gen7_vc1_condover[pic_param->conditional_overlap_flag] << 29 |
1751                   ptype << 26 |
1752                   fcm << 24 |
1753                   alt_pq << 16 |
1754                   pic_param->pic_quantizer_fields.bits.pic_quantizer_scale << 8 |
1755                   scale_factor << 0);
1756     OUT_BCS_BATCH(batch,
1757                   unified_mv_mode << 28 |
1758                   pic_param->mv_fields.bits.four_mv_switch << 27 |
1759                   pic_param->fast_uvmc_flag << 26 |
1760                   ref_field_pic_polarity << 25 |
1761                   pic_param->reference_fields.bits.num_reference_pictures << 24 |
1762                   brfd << 20 |
1763                   frfd << 16 |
1764                   pic_param->mv_fields.bits.extended_dmv_range << 10 |
1765                   pic_param->mv_fields.bits.extended_mv_range << 8 |
1766                   alt_pquant_edge_mask << 4 |
1767                   alt_pquant_config << 2 |
1768                   pic_param->pic_quantizer_fields.bits.half_qp << 1 |
1769                   pic_param->pic_quantizer_fields.bits.pic_quantizer_type << 0);
1770     OUT_BCS_BATCH(batch,
1771                   bitplane_present << 31 |
1772                   forward_mb << 30 |
1773                   mv_type_mb << 29 |
1774                   skip_mb << 28 |
1775                   direct_mb << 27 |
1776                   overflags << 26 |
1777                   ac_pred << 25 |
1778                   field_tx << 24 |
1779                   pic_param->mv_fields.bits.mv_table << 20 |
1780                   pic_param->mv_fields.bits.four_mv_block_pattern_table << 18 |
1781                   pic_param->mv_fields.bits.two_mv_block_pattern_table << 16 |
1782                   pic_param->transform_fields.bits.frame_level_transform_type << 12 |
1783                   pic_param->transform_fields.bits.mb_level_transform_type_flag << 11 |
1784                   pic_param->mb_mode_table << 8 |
1785                   trans_ac_y << 6 |
1786                   pic_param->transform_fields.bits.transform_ac_codingset_idx1 << 4 |
1787                   pic_param->transform_fields.bits.intra_transform_dc_table << 3 |
1788                   pic_param->cbp_table << 0);
1789     ADVANCE_BCS_BATCH(batch);
1790 }
1791
1792 static void
1793 gen7_mfd_vc1_pred_pipe_state(VADriverContextP ctx,
1794                              struct decode_state *decode_state,
1795                              struct gen7_mfd_context *gen7_mfd_context)
1796 {
1797     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1798     VAPictureParameterBufferVC1 *pic_param;
1799     int picture_type;
1800     int is_first_field = 1;
1801     int intensitycomp_single_fwd = 0;
1802     int luma_scale1 = 0;
1803     int luma_shift1 = 0;
1804     int replication_mode = 0;
1805
1806     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1807     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1808
1809     if (!pic_param->sequence_fields.bits.interlace ||
1810         (pic_param->picture_fields.bits.frame_coding_mode < 2)) { /* Progressive or Frame-Interlace */
1811         picture_type = pic_param->picture_fields.bits.picture_type;
1812     } else {/* Field-Interlace */
1813         is_first_field = pic_param->picture_fields.bits.is_first_field;
1814         picture_type = fptype_to_picture_type[pic_param->picture_fields.bits.picture_type][!is_first_field];
1815     }
1816
1817     if (gen7_mfd_context->reference_surface[0].surface_id != VA_INVALID_ID) {
1818         if (picture_type == 1 || picture_type == 2) { /* P/B picture */
1819             struct gen7_vc1_surface *gen7_vc1_surface = gen7_mfd_context->reference_surface[0].obj_surface->private_data;
1820             if (gen7_vc1_surface) {
1821                 intensitycomp_single_fwd = gen7_vc1_surface->intensity_compensation;
1822                 luma_scale1 = gen7_vc1_surface->luma_scale;
1823                 luma_shift1 = gen7_vc1_surface->luma_shift;
1824             }
1825         }
1826     }
1827
1828     if (pic_param->sequence_fields.bits.interlace &&
1829         pic_param->picture_fields.bits.frame_coding_mode > 0) { /* Frame-Interlace or Field-Interlace */
1830         if (picture_type == GEN7_VC1_P_PICTURE)
1831             replication_mode = 0x5;
1832         else if (picture_type == GEN7_VC1_B_PICTURE)
1833             replication_mode = 0xf;
1834     }
1835
1836     BEGIN_BCS_BATCH(batch, 6);
1837     OUT_BCS_BATCH(batch, MFX_VC1_PRED_PIPE_STATE | (6 - 2));
1838     OUT_BCS_BATCH(batch,
1839                   0 << 14 | /* FIXME: double ??? */
1840                   0 << 12 |
1841                   intensitycomp_single_fwd << 10 |
1842                   0 << 8 |
1843                   replication_mode << 4 |
1844                   0);
1845     OUT_BCS_BATCH(batch,
1846                   luma_shift1 << 16 |
1847                   luma_scale1 << 0);
1848     OUT_BCS_BATCH(batch, 0);
1849     OUT_BCS_BATCH(batch, 0);
1850     OUT_BCS_BATCH(batch, 0);
1851     ADVANCE_BCS_BATCH(batch);
1852 }
1853
1854
1855 static void
1856 gen7_mfd_vc1_directmode_state(VADriverContextP ctx,
1857                               struct decode_state *decode_state,
1858                               struct gen7_mfd_context *gen7_mfd_context)
1859 {
1860     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1861     VAPictureParameterBufferVC1 *pic_param;
1862     struct object_surface *obj_surface;
1863     dri_bo *dmv_read_buffer = NULL, *dmv_write_buffer = NULL;
1864     int picture_type;
1865     int is_first_field = 1;
1866
1867     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1868
1869     if (!pic_param->sequence_fields.bits.interlace ||
1870         (pic_param->picture_fields.bits.frame_coding_mode < 2)) { /* Progressive or Frame-Interlace */
1871         picture_type = pic_param->picture_fields.bits.picture_type;
1872     } else {/* Field-Interlace */
1873         is_first_field = pic_param->picture_fields.bits.is_first_field;
1874         picture_type = fptype_to_picture_type[pic_param->picture_fields.bits.picture_type][!is_first_field];
1875     }
1876
1877    if (picture_type == GEN7_VC1_P_PICTURE ||
1878         picture_type == GEN7_VC1_SKIPPED_PICTURE) {
1879         obj_surface = decode_state->render_object;
1880
1881         if (pic_param->sequence_fields.bits.interlace &&
1882             (pic_param->picture_fields.bits.frame_coding_mode == 2) && /* Field-Interlace */
1883             (pic_param->picture_fields.bits.top_field_first ^ is_first_field))
1884             dmv_write_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv_bottom;
1885         else
1886             dmv_write_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv_top;
1887     }
1888
1889     if (picture_type == GEN7_VC1_B_PICTURE) {
1890         obj_surface = decode_state->reference_objects[1];
1891         if (pic_param->backward_reference_picture != VA_INVALID_ID &&
1892             obj_surface &&
1893             obj_surface->private_data) {
1894
1895             if (pic_param->sequence_fields.bits.interlace &&
1896                 (pic_param->picture_fields.bits.frame_coding_mode == 2) && /* Field-Interlace */
1897                 (pic_param->picture_fields.bits.top_field_first ^ is_first_field))
1898                 dmv_read_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv_bottom;
1899             else
1900                 dmv_read_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv_top;
1901         }
1902     }
1903
1904     BEGIN_BCS_BATCH(batch, 3);
1905     OUT_BCS_BATCH(batch, MFX_VC1_DIRECTMODE_STATE | (3 - 2));
1906
1907     if (dmv_write_buffer)
1908         OUT_BCS_RELOC(batch, dmv_write_buffer,
1909                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
1910                       0);
1911     else
1912         OUT_BCS_BATCH(batch, 0);
1913
1914     if (dmv_read_buffer)
1915         OUT_BCS_RELOC(batch, dmv_read_buffer,
1916                       I915_GEM_DOMAIN_INSTRUCTION, 0,
1917                       0);
1918     else
1919         OUT_BCS_BATCH(batch, 0);
1920
1921     ADVANCE_BCS_BATCH(batch);
1922 }
1923
1924 static int
1925 gen7_mfd_vc1_get_macroblock_bit_offset(uint8_t *buf, int in_slice_data_bit_offset, int profile)
1926 {
1927     int out_slice_data_bit_offset;
1928     int slice_header_size = in_slice_data_bit_offset / 8;
1929     int i, j;
1930
1931     if (profile != 3)
1932         out_slice_data_bit_offset = in_slice_data_bit_offset;
1933     else {
1934         for (i = 0, j = 0; i < slice_header_size; i++, j++) {
1935             if (!buf[j] && !buf[j + 1] && buf[j + 2] == 3 && buf[j + 3] < 4) {
1936                 if (i < slice_header_size - 1)
1937                     i++, j += 2;
1938                 else {
1939                     buf[j + 2] = buf[j + 1];
1940                     j++;
1941                 }
1942             }
1943         }
1944
1945         out_slice_data_bit_offset = 8 * j + in_slice_data_bit_offset % 8;
1946     }
1947
1948     return out_slice_data_bit_offset;
1949 }
1950
1951 static void
1952 gen7_mfd_vc1_bsd_object(VADriverContextP ctx,
1953                         VAPictureParameterBufferVC1 *pic_param,
1954                         VASliceParameterBufferVC1 *slice_param,
1955                         VASliceParameterBufferVC1 *next_slice_param,
1956                         dri_bo *slice_data_bo,
1957                         struct gen7_mfd_context *gen7_mfd_context)
1958 {
1959     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1960     int next_slice_start_vert_pos;
1961     int macroblock_offset;
1962     uint8_t *slice_data = NULL;
1963
1964     dri_bo_map(slice_data_bo, True);
1965     slice_data = (uint8_t *)(slice_data_bo->virtual + slice_param->slice_data_offset);
1966     macroblock_offset = gen7_mfd_vc1_get_macroblock_bit_offset(slice_data,
1967                                                                slice_param->macroblock_offset,
1968                                                                pic_param->sequence_fields.bits.profile);
1969     dri_bo_unmap(slice_data_bo);
1970
1971     if (next_slice_param)
1972         next_slice_start_vert_pos = next_slice_param->slice_vertical_position;
1973     else if (!pic_param->sequence_fields.bits.interlace ||
1974              pic_param->picture_fields.bits.frame_coding_mode < 2) /* Progressive or Frame-Interlace */
1975         next_slice_start_vert_pos = ALIGN(pic_param->coded_height, 16) / 16;
1976     else /* Field-Interlace */
1977         next_slice_start_vert_pos = ALIGN(pic_param->coded_height, 32) / 32;
1978
1979     BEGIN_BCS_BATCH(batch, 5);
1980     OUT_BCS_BATCH(batch, MFD_VC1_BSD_OBJECT | (5 - 2));
1981     OUT_BCS_BATCH(batch,
1982                   slice_param->slice_data_size - (macroblock_offset >> 3));
1983     OUT_BCS_BATCH(batch,
1984                   slice_param->slice_data_offset + (macroblock_offset >> 3));
1985     OUT_BCS_BATCH(batch,
1986                   slice_param->slice_vertical_position << 16 |
1987                   next_slice_start_vert_pos << 0);
1988     OUT_BCS_BATCH(batch,
1989                   (macroblock_offset & 0x7));
1990     ADVANCE_BCS_BATCH(batch);
1991 }
1992
1993 static void
1994 gen7_mfd_vc1_decode_picture(VADriverContextP ctx,
1995                             struct decode_state *decode_state,
1996                             struct gen7_mfd_context *gen7_mfd_context)
1997 {
1998     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1999     VAPictureParameterBufferVC1 *pic_param;
2000     VASliceParameterBufferVC1 *slice_param, *next_slice_param, *next_slice_group_param;
2001     dri_bo *slice_data_bo;
2002     int i, j;
2003
2004     assert(decode_state->pic_param && decode_state->pic_param->buffer);
2005     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
2006
2007     gen7_mfd_vc1_decode_init(ctx, decode_state, gen7_mfd_context);
2008     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
2009     intel_batchbuffer_emit_mi_flush(batch);
2010     gen7_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
2011     gen7_mfd_surface_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
2012     gen7_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
2013     gen7_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
2014     gen7_mfd_vc1_pic_state(ctx, decode_state, gen7_mfd_context);
2015     gen7_mfd_vc1_pred_pipe_state(ctx, decode_state, gen7_mfd_context);
2016     gen7_mfd_vc1_directmode_state(ctx, decode_state, gen7_mfd_context);
2017
2018     for (j = 0; j < decode_state->num_slice_params; j++) {
2019         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
2020         slice_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j]->buffer;
2021         slice_data_bo = decode_state->slice_datas[j]->bo;
2022         gen7_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_VC1, gen7_mfd_context);
2023
2024         if (j == decode_state->num_slice_params - 1)
2025             next_slice_group_param = NULL;
2026         else
2027             next_slice_group_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j + 1]->buffer;
2028
2029         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
2030             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
2031
2032             if (i < decode_state->slice_params[j]->num_elements - 1)
2033                 next_slice_param = slice_param + 1;
2034             else
2035                 next_slice_param = next_slice_group_param;
2036
2037             gen7_mfd_vc1_bsd_object(ctx, pic_param, slice_param, next_slice_param, slice_data_bo, gen7_mfd_context);
2038             slice_param++;
2039         }
2040     }
2041
2042     intel_batchbuffer_end_atomic(batch);
2043     intel_batchbuffer_flush(batch);
2044 }
2045
2046 static void
2047 gen7_mfd_jpeg_decode_init(VADriverContextP ctx,
2048                           struct decode_state *decode_state,
2049                           struct gen7_mfd_context *gen7_mfd_context)
2050 {
2051     struct object_surface *obj_surface;
2052     VAPictureParameterBufferJPEGBaseline *pic_param;
2053     int subsampling = SUBSAMPLE_YUV420;
2054     int fourcc = VA_FOURCC_IMC3;
2055
2056     pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
2057
2058     if (pic_param->num_components == 1) {
2059         subsampling = SUBSAMPLE_YUV400;
2060         fourcc = VA_FOURCC_Y800;
2061     } else if (pic_param->num_components == 3) {
2062         int h1 = pic_param->components[0].h_sampling_factor;
2063         int h2 = pic_param->components[1].h_sampling_factor;
2064         int h3 = pic_param->components[2].h_sampling_factor;
2065         int v1 = pic_param->components[0].v_sampling_factor;
2066         int v2 = pic_param->components[1].v_sampling_factor;
2067         int v3 = pic_param->components[2].v_sampling_factor;
2068
2069         if (h1 == 2 * h2 && h2 == h3 &&
2070             v1 == 2 * v2 && v2 == v3) {
2071             subsampling = SUBSAMPLE_YUV420;
2072             fourcc = VA_FOURCC_IMC3;
2073         } else if (h1 == 2 * h2  && h2 == h3 &&
2074                    v1 == v2 && v2 == v3) {
2075             subsampling = SUBSAMPLE_YUV422H;
2076             fourcc = VA_FOURCC_422H;
2077         } else if (h1 == h2 && h2 == h3 &&
2078                    v1 == v2  && v2 == v3) {
2079             subsampling = SUBSAMPLE_YUV444;
2080             fourcc = VA_FOURCC_444P;
2081         } else if (h1 == 4 * h2 && h2 ==  h3 &&
2082                    v1 == v2 && v2 == v3) {
2083             subsampling = SUBSAMPLE_YUV411;
2084             fourcc = VA_FOURCC_411P;
2085         } else if (h1 == h2 && h2 == h3 &&
2086                    v1 == 2 * v2 && v2 == v3) {
2087             subsampling = SUBSAMPLE_YUV422V;
2088             fourcc = VA_FOURCC_422V;
2089         } else
2090             assert(0);
2091     } else {
2092         assert(0);
2093     }
2094
2095     /* Current decoded picture */
2096     obj_surface = decode_state->render_object;
2097     i965_check_alloc_surface_bo(ctx, obj_surface, 1, fourcc, subsampling);
2098
2099     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
2100     gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
2101     dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
2102     gen7_mfd_context->pre_deblocking_output.valid = 1;
2103
2104     gen7_mfd_context->post_deblocking_output.bo = NULL;
2105     gen7_mfd_context->post_deblocking_output.valid = 0;
2106
2107     gen7_mfd_context->intra_row_store_scratch_buffer.bo = NULL;
2108     gen7_mfd_context->intra_row_store_scratch_buffer.valid = 0;
2109
2110     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
2111     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 0;
2112
2113     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
2114     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 0;
2115
2116     gen7_mfd_context->mpr_row_store_scratch_buffer.bo = NULL;
2117     gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
2118
2119     gen7_mfd_context->bitplane_read_buffer.bo = NULL;
2120     gen7_mfd_context->bitplane_read_buffer.valid = 0;
2121 }
2122
2123 static const int va_to_gen7_jpeg_rotation[4] = {
2124     GEN7_JPEG_ROTATION_0,
2125     GEN7_JPEG_ROTATION_90,
2126     GEN7_JPEG_ROTATION_180,
2127     GEN7_JPEG_ROTATION_270
2128 };
2129
2130 static void
2131 gen7_mfd_jpeg_pic_state(VADriverContextP ctx,
2132                         struct decode_state *decode_state,
2133                         struct gen7_mfd_context *gen7_mfd_context)
2134 {
2135     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2136     VAPictureParameterBufferJPEGBaseline *pic_param;
2137     int chroma_type = GEN7_YUV420;
2138     int frame_width_in_blks;
2139     int frame_height_in_blks;
2140
2141     assert(decode_state->pic_param && decode_state->pic_param->buffer);
2142     pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
2143
2144     if (pic_param->num_components == 1)
2145         chroma_type = GEN7_YUV400;
2146     else if (pic_param->num_components == 3) {
2147         int h1 = pic_param->components[0].h_sampling_factor;
2148         int h2 = pic_param->components[1].h_sampling_factor;
2149         int h3 = pic_param->components[2].h_sampling_factor;
2150         int v1 = pic_param->components[0].v_sampling_factor;
2151         int v2 = pic_param->components[1].v_sampling_factor;
2152         int v3 = pic_param->components[2].v_sampling_factor;
2153
2154         if (h1 == 2 * h2 && h2 == h3 &&
2155             v1 == 2 * v2 && v2 == v3)
2156             chroma_type = GEN7_YUV420;
2157         else if (h1 == 2 && h2 == 1 && h3 == 1 &&
2158                  v1 == 1 && v2 == 1 && v3 == 1)
2159             chroma_type = GEN7_YUV422H_2Y;
2160         else if (h1 == h2 && h2 == h3 &&
2161                  v1 == v2 && v2 == v3)
2162             chroma_type = GEN7_YUV444;
2163         else if (h1 == 4 * h2 && h2 == h3 &&
2164                  v1 == v2 && v2 == v3)
2165             chroma_type = GEN7_YUV411;
2166         else if (h1 == 1 && h2 == 1 && h3 == 1 &&
2167                  v1 == 2 && v2 == 1 && v3 == 1)
2168             chroma_type = GEN7_YUV422V_2Y;
2169         else if (h1 == 2 && h2 == 1 && h3 == 1 &&
2170                  v1 == 2 && v2 == 2 && v3 == 2)
2171             chroma_type = GEN7_YUV422H_4Y;
2172         else if (h2 == 2 && h2 == 2 && h3 == 2 &&
2173                  v1 == 2 && v2 == 1 && v3 == 1)
2174             chroma_type = GEN7_YUV422V_4Y;
2175         else
2176             assert(0);
2177     }
2178
2179     if (chroma_type == GEN7_YUV400 ||
2180         chroma_type == GEN7_YUV444 ||
2181         chroma_type == GEN7_YUV422V_2Y) {
2182         frame_width_in_blks = ((pic_param->picture_width + 7) / 8);
2183         frame_height_in_blks = ((pic_param->picture_height + 7) / 8);
2184     } else if (chroma_type == GEN7_YUV411) {
2185         frame_width_in_blks = ((pic_param->picture_width + 31) / 32) * 4;
2186         frame_height_in_blks = ((pic_param->picture_height + 31) / 32) * 4;
2187     } else {
2188         frame_width_in_blks = ((pic_param->picture_width + 15) / 16) * 2;
2189         frame_height_in_blks = ((pic_param->picture_height + 15) / 16) * 2;
2190     }
2191
2192     BEGIN_BCS_BATCH(batch, 3);
2193     OUT_BCS_BATCH(batch, MFX_JPEG_PIC_STATE | (3 - 2));
2194     OUT_BCS_BATCH(batch,
2195                   (va_to_gen7_jpeg_rotation[0] << 4) |    /* without rotation */
2196                   (chroma_type << 0));
2197     OUT_BCS_BATCH(batch,
2198                   ((frame_height_in_blks - 1) << 16) |   /* FrameHeightInBlks */
2199                   ((frame_width_in_blks - 1) << 0));    /* FrameWidthInBlks */
2200     ADVANCE_BCS_BATCH(batch);
2201 }
2202
2203 static const int va_to_gen7_jpeg_hufftable[2] = {
2204     MFX_HUFFTABLE_ID_Y,
2205     MFX_HUFFTABLE_ID_UV
2206 };
2207
2208 static void
2209 gen7_mfd_jpeg_huff_table_state(VADriverContextP ctx,
2210                                struct decode_state *decode_state,
2211                                struct gen7_mfd_context *gen7_mfd_context,
2212                                int num_tables)
2213 {
2214     VAHuffmanTableBufferJPEGBaseline *huffman_table;
2215     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2216     int index;
2217
2218     if (!decode_state->huffman_table || !decode_state->huffman_table->buffer)
2219         return;
2220
2221     huffman_table = (VAHuffmanTableBufferJPEGBaseline *)decode_state->huffman_table->buffer;
2222
2223     for (index = 0; index < num_tables; index++) {
2224         int id = va_to_gen7_jpeg_hufftable[index];
2225         if (!huffman_table->load_huffman_table[index])
2226             continue;
2227         BEGIN_BCS_BATCH(batch, 53);
2228         OUT_BCS_BATCH(batch, MFX_JPEG_HUFF_TABLE_STATE | (53 - 2));
2229         OUT_BCS_BATCH(batch, id);
2230         intel_batchbuffer_data(batch, huffman_table->huffman_table[index].num_dc_codes, 12);
2231         intel_batchbuffer_data(batch, huffman_table->huffman_table[index].dc_values, 12);
2232         intel_batchbuffer_data(batch, huffman_table->huffman_table[index].num_ac_codes, 16);
2233         intel_batchbuffer_data(batch, huffman_table->huffman_table[index].ac_values, 164);
2234         ADVANCE_BCS_BATCH(batch);
2235     }
2236 }
2237
2238 static const int va_to_gen7_jpeg_qm[5] = {
2239     -1,
2240     MFX_QM_JPEG_LUMA_Y_QUANTIZER_MATRIX,
2241     MFX_QM_JPEG_CHROMA_CB_QUANTIZER_MATRIX,
2242     MFX_QM_JPEG_CHROMA_CR_QUANTIZER_MATRIX,
2243     MFX_QM_JPEG_ALPHA_QUANTIZER_MATRIX
2244 };
2245
2246 static void
2247 gen7_mfd_jpeg_qm_state(VADriverContextP ctx,
2248                        struct decode_state *decode_state,
2249                        struct gen7_mfd_context *gen7_mfd_context)
2250 {
2251     VAPictureParameterBufferJPEGBaseline *pic_param;
2252     VAIQMatrixBufferJPEGBaseline *iq_matrix;
2253     int index;
2254
2255     if (!decode_state->iq_matrix || !decode_state->iq_matrix->buffer)
2256         return;
2257
2258     iq_matrix = (VAIQMatrixBufferJPEGBaseline *)decode_state->iq_matrix->buffer;
2259     pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
2260
2261     assert(pic_param->num_components <= 3);
2262
2263     for (index = 0; index < pic_param->num_components; index++) {
2264         int id = pic_param->components[index].component_id - pic_param->components[0].component_id + 1;
2265         int qm_type;
2266         unsigned char *qm = iq_matrix->quantiser_table[pic_param->components[index].quantiser_table_selector];
2267         unsigned char raster_qm[64];
2268         int j;
2269
2270         if (id > 4 || id < 1)
2271             continue;
2272
2273         if (!iq_matrix->load_quantiser_table[pic_param->components[index].quantiser_table_selector])
2274             continue;
2275
2276         qm_type = va_to_gen7_jpeg_qm[id];
2277
2278         for (j = 0; j < 64; j++)
2279             raster_qm[zigzag_direct[j]] = qm[j];
2280
2281         gen7_mfd_qm_state(ctx, qm_type, raster_qm, 64, gen7_mfd_context);
2282     }
2283 }
2284
2285 static void
2286 gen7_mfd_jpeg_bsd_object(VADriverContextP ctx,
2287                          VAPictureParameterBufferJPEGBaseline *pic_param,
2288                          VASliceParameterBufferJPEGBaseline *slice_param,
2289                          VASliceParameterBufferJPEGBaseline *next_slice_param,
2290                          dri_bo *slice_data_bo,
2291                          struct gen7_mfd_context *gen7_mfd_context)
2292 {
2293     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2294     int scan_component_mask = 0;
2295     int i;
2296
2297     assert(slice_param->num_components > 0);
2298     assert(slice_param->num_components < 4);
2299     assert(slice_param->num_components <= pic_param->num_components);
2300
2301     for (i = 0; i < slice_param->num_components; i++) {
2302         switch (slice_param->components[i].component_selector - pic_param->components[0].component_id + 1) {
2303         case 1:
2304             scan_component_mask |= (1 << 0);
2305             break;
2306         case 2:
2307             scan_component_mask |= (1 << 1);
2308             break;
2309         case 3:
2310             scan_component_mask |= (1 << 2);
2311             break;
2312         default:
2313             assert(0);
2314             break;
2315         }
2316     }
2317
2318     BEGIN_BCS_BATCH(batch, 6);
2319     OUT_BCS_BATCH(batch, MFD_JPEG_BSD_OBJECT | (6 - 2));
2320     OUT_BCS_BATCH(batch,
2321                   slice_param->slice_data_size);
2322     OUT_BCS_BATCH(batch,
2323                   slice_param->slice_data_offset);
2324     OUT_BCS_BATCH(batch,
2325                   slice_param->slice_horizontal_position << 16 |
2326                   slice_param->slice_vertical_position << 0);
2327     OUT_BCS_BATCH(batch,
2328                   ((slice_param->num_components != 1) << 30) |  /* interleaved */
2329                   (scan_component_mask << 27) |                 /* scan components */
2330                   (0 << 26) |   /* disable interrupt allowed */
2331                   (slice_param->num_mcus << 0));                /* MCU count */
2332     OUT_BCS_BATCH(batch,
2333                   (slice_param->restart_interval << 0));    /* RestartInterval */
2334     ADVANCE_BCS_BATCH(batch);
2335 }
2336
2337 /* Workaround for JPEG decoding on Ivybridge */
2338
2339 static struct {
2340     int width;
2341     int height;
2342     unsigned char data[32];
2343     int data_size;
2344     int data_bit_offset;
2345     int qp;
2346 } gen7_jpeg_wa_clip = {
2347     16,
2348     16,
2349     {
2350         0x65, 0xb8, 0x40, 0x32, 0x13, 0xfd, 0x06, 0x6c,
2351         0xfc, 0x0a, 0x50, 0x71, 0x5c, 0x00
2352     },
2353     14,
2354     40,
2355     28,
2356 };
2357
2358 static void
2359 gen7_jpeg_wa_init(VADriverContextP ctx,
2360                   struct gen7_mfd_context *gen7_mfd_context)
2361 {
2362     struct i965_driver_data *i965 = i965_driver_data(ctx);
2363     VAStatus status;
2364     struct object_surface *obj_surface;
2365
2366     if (gen7_mfd_context->jpeg_wa_surface_id != VA_INVALID_SURFACE)
2367         i965_DestroySurfaces(ctx,
2368                              &gen7_mfd_context->jpeg_wa_surface_id,
2369                              1);
2370
2371     status = i965_CreateSurfaces(ctx,
2372                                  gen7_jpeg_wa_clip.width,
2373                                  gen7_jpeg_wa_clip.height,
2374                                  VA_RT_FORMAT_YUV420,
2375                                  1,
2376                                  &gen7_mfd_context->jpeg_wa_surface_id);
2377     assert(status == VA_STATUS_SUCCESS);
2378
2379     obj_surface = SURFACE(gen7_mfd_context->jpeg_wa_surface_id);
2380     assert(obj_surface);
2381     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
2382     gen7_mfd_context->jpeg_wa_surface_object = obj_surface;
2383
2384     if (!gen7_mfd_context->jpeg_wa_slice_data_bo) {
2385         gen7_mfd_context->jpeg_wa_slice_data_bo = dri_bo_alloc(i965->intel.bufmgr,
2386                                                                "JPEG WA data",
2387                                                                0x1000,
2388                                                                0x1000);
2389         dri_bo_subdata(gen7_mfd_context->jpeg_wa_slice_data_bo,
2390                        0,
2391                        gen7_jpeg_wa_clip.data_size,
2392                        gen7_jpeg_wa_clip.data);
2393     }
2394 }
2395
2396 static void
2397 gen7_jpeg_wa_pipe_mode_select(VADriverContextP ctx,
2398                               struct gen7_mfd_context *gen7_mfd_context)
2399 {
2400     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2401
2402     BEGIN_BCS_BATCH(batch, 5);
2403     OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2));
2404     OUT_BCS_BATCH(batch,
2405                   (MFX_LONG_MODE << 17) | /* Currently only support long format */
2406                   (MFD_MODE_VLD << 15) | /* VLD mode */
2407                   (0 << 10) | /* disable Stream-Out */
2408                   (0 << 9)  | /* Post Deblocking Output */
2409                   (1 << 8)  | /* Pre Deblocking Output */
2410                   (0 << 5)  | /* not in stitch mode */
2411                   (MFX_CODEC_DECODE << 4)  | /* decoding mode */
2412                   (MFX_FORMAT_AVC << 0));
2413     OUT_BCS_BATCH(batch,
2414                   (0 << 4)  | /* terminate if AVC motion and POC table error occurs */
2415                   (0 << 3)  | /* terminate if AVC mbdata error occurs */
2416                   (0 << 2)  | /* terminate if AVC CABAC/CAVLC decode error occurs */
2417                   (0 << 1)  |
2418                   (0 << 0));
2419     OUT_BCS_BATCH(batch, 0); /* pic status/error report id */
2420     OUT_BCS_BATCH(batch, 0); /* reserved */
2421     ADVANCE_BCS_BATCH(batch);
2422 }
2423
2424 static void
2425 gen7_jpeg_wa_surface_state(VADriverContextP ctx,
2426                            struct gen7_mfd_context *gen7_mfd_context)
2427 {
2428     struct object_surface *obj_surface = gen7_mfd_context->jpeg_wa_surface_object;
2429     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2430
2431     BEGIN_BCS_BATCH(batch, 6);
2432     OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
2433     OUT_BCS_BATCH(batch, 0);
2434     OUT_BCS_BATCH(batch,
2435                   ((obj_surface->orig_width - 1) << 18) |
2436                   ((obj_surface->orig_height - 1) << 4));
2437     OUT_BCS_BATCH(batch,
2438                   (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
2439                   (1 << 27) | /* interleave chroma, set to 0 for JPEG */
2440                   (0 << 22) | /* surface object control state, ignored */
2441                   ((obj_surface->width - 1) << 3) | /* pitch */
2442                   (0 << 2)  | /* must be 0 */
2443                   (1 << 1)  | /* must be tiled */
2444                   (I965_TILEWALK_YMAJOR << 0));  /* tile walk, must be 1 */
2445     OUT_BCS_BATCH(batch,
2446                   (0 << 16) | /* X offset for U(Cb), must be 0 */
2447                   (obj_surface->y_cb_offset << 0)); /* Y offset for U(Cb) */
2448     OUT_BCS_BATCH(batch,
2449                   (0 << 16) | /* X offset for V(Cr), must be 0 */
2450                   (0 << 0)); /* Y offset for V(Cr), must be 0 for video codec, non-zoro for JPEG */
2451     ADVANCE_BCS_BATCH(batch);
2452 }
2453
2454 static void
2455 gen7_jpeg_wa_pipe_buf_addr_state(VADriverContextP ctx,
2456                                  struct gen7_mfd_context *gen7_mfd_context)
2457 {
2458     struct i965_driver_data *i965 = i965_driver_data(ctx);
2459     struct object_surface *obj_surface = gen7_mfd_context->jpeg_wa_surface_object;
2460     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2461     dri_bo *intra_bo;
2462     int i;
2463
2464     intra_bo = dri_bo_alloc(i965->intel.bufmgr,
2465                             "intra row store",
2466                             128 * 64,
2467                             0x1000);
2468
2469     BEGIN_BCS_BATCH(batch, 24);
2470     OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
2471     OUT_BCS_RELOC(batch,
2472                   obj_surface->bo,
2473                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2474                   0);
2475
2476     OUT_BCS_BATCH(batch, 0); /* post deblocking */
2477
2478     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
2479     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
2480
2481     OUT_BCS_RELOC(batch,
2482                   intra_bo,
2483                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2484                   0);
2485
2486     OUT_BCS_BATCH(batch, 0);
2487
2488     /* DW 7..22 */
2489     for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
2490         OUT_BCS_BATCH(batch, 0);
2491     }
2492
2493     OUT_BCS_BATCH(batch, 0);   /* ignore DW23 for decoding */
2494     ADVANCE_BCS_BATCH(batch);
2495
2496     dri_bo_unreference(intra_bo);
2497 }
2498
2499 static void
2500 gen7_jpeg_wa_bsp_buf_base_addr_state(VADriverContextP ctx,
2501                                      struct gen7_mfd_context *gen7_mfd_context)
2502 {
2503     struct i965_driver_data *i965 = i965_driver_data(ctx);
2504     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2505     dri_bo *bsd_mpc_bo, *mpr_bo;
2506
2507     bsd_mpc_bo = dri_bo_alloc(i965->intel.bufmgr,
2508                               "bsd mpc row store",
2509                               11520, /* 1.5 * 120 * 64 */
2510                               0x1000);
2511
2512     mpr_bo = dri_bo_alloc(i965->intel.bufmgr,
2513                           "mpr row store",
2514                           7680, /* 1. 0 * 120 * 64 */
2515                           0x1000);
2516
2517     BEGIN_BCS_BATCH(batch, 4);
2518     OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
2519
2520     OUT_BCS_RELOC(batch,
2521                   bsd_mpc_bo,
2522                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2523                   0);
2524
2525     OUT_BCS_RELOC(batch,
2526                   mpr_bo,
2527                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2528                   0);
2529     OUT_BCS_BATCH(batch, 0);
2530
2531     ADVANCE_BCS_BATCH(batch);
2532
2533     dri_bo_unreference(bsd_mpc_bo);
2534     dri_bo_unreference(mpr_bo);
2535 }
2536
2537 static void
2538 gen7_jpeg_wa_avc_qm_state(VADriverContextP ctx,
2539                           struct gen7_mfd_context *gen7_mfd_context)
2540 {
2541
2542 }
2543
2544 static void
2545 gen7_jpeg_wa_avc_img_state(VADriverContextP ctx,
2546                            struct gen7_mfd_context *gen7_mfd_context)
2547 {
2548     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2549     int img_struct = 0;
2550     int mbaff_frame_flag = 0;
2551     unsigned int width_in_mbs = 1, height_in_mbs = 1;
2552
2553     BEGIN_BCS_BATCH(batch, 16);
2554     OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (16 - 2));
2555     OUT_BCS_BATCH(batch,
2556                   (width_in_mbs * height_in_mbs - 1));
2557     OUT_BCS_BATCH(batch,
2558                   ((height_in_mbs - 1) << 16) |
2559                   ((width_in_mbs - 1) << 0));
2560     OUT_BCS_BATCH(batch,
2561                   (0 << 24) |
2562                   (0 << 16) |
2563                   (0 << 14) |
2564                   (0 << 13) |
2565                   (0 << 12) | /* differ from GEN6 */
2566                   (0 << 10) |
2567                   (img_struct << 8));
2568     OUT_BCS_BATCH(batch,
2569                   (1 << 10) | /* 4:2:0 */
2570                   (1 << 7) |  /* CABAC */
2571                   (0 << 6) |
2572                   (0 << 5) |
2573                   (0 << 4) |
2574                   (0 << 3) |
2575                   (1 << 2) |
2576                   (mbaff_frame_flag << 1) |
2577                   (0 << 0));
2578     OUT_BCS_BATCH(batch, 0);
2579     OUT_BCS_BATCH(batch, 0);
2580     OUT_BCS_BATCH(batch, 0);
2581     OUT_BCS_BATCH(batch, 0);
2582     OUT_BCS_BATCH(batch, 0);
2583     OUT_BCS_BATCH(batch, 0);
2584     OUT_BCS_BATCH(batch, 0);
2585     OUT_BCS_BATCH(batch, 0);
2586     OUT_BCS_BATCH(batch, 0);
2587     OUT_BCS_BATCH(batch, 0);
2588     OUT_BCS_BATCH(batch, 0);
2589     ADVANCE_BCS_BATCH(batch);
2590 }
2591
2592 static void
2593 gen7_jpeg_wa_avc_directmode_state(VADriverContextP ctx,
2594                                   struct gen7_mfd_context *gen7_mfd_context)
2595 {
2596     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2597     int i;
2598
2599     BEGIN_BCS_BATCH(batch, 69);
2600     OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
2601
2602     /* reference surfaces 0..15 */
2603     for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
2604         OUT_BCS_BATCH(batch, 0); /* top */
2605         OUT_BCS_BATCH(batch, 0); /* bottom */
2606     }
2607
2608     /* the current decoding frame/field */
2609     OUT_BCS_BATCH(batch, 0); /* top */
2610     OUT_BCS_BATCH(batch, 0); /* bottom */
2611
2612     /* POC List */
2613     for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
2614         OUT_BCS_BATCH(batch, 0);
2615         OUT_BCS_BATCH(batch, 0);
2616     }
2617
2618     OUT_BCS_BATCH(batch, 0);
2619     OUT_BCS_BATCH(batch, 0);
2620
2621     ADVANCE_BCS_BATCH(batch);
2622 }
2623
2624 static void
2625 gen7_jpeg_wa_ind_obj_base_addr_state(VADriverContextP ctx,
2626                                      struct gen7_mfd_context *gen7_mfd_context)
2627 {
2628     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2629
2630     BEGIN_BCS_BATCH(batch, 11);
2631     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
2632     OUT_BCS_RELOC(batch,
2633                   gen7_mfd_context->jpeg_wa_slice_data_bo,
2634                   I915_GEM_DOMAIN_INSTRUCTION, 0,
2635                   0);
2636     OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
2637     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
2638     OUT_BCS_BATCH(batch, 0);
2639     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
2640     OUT_BCS_BATCH(batch, 0);
2641     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
2642     OUT_BCS_BATCH(batch, 0);
2643     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
2644     OUT_BCS_BATCH(batch, 0);
2645     ADVANCE_BCS_BATCH(batch);
2646 }
2647
2648 static void
2649 gen7_jpeg_wa_avc_bsd_object(VADriverContextP ctx,
2650                             struct gen7_mfd_context *gen7_mfd_context)
2651 {
2652     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2653
2654     /* the input bitsteam format on GEN7 differs from GEN6 */
2655     BEGIN_BCS_BATCH(batch, 6);
2656     OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2));
2657     OUT_BCS_BATCH(batch, gen7_jpeg_wa_clip.data_size);
2658     OUT_BCS_BATCH(batch, 0);
2659     OUT_BCS_BATCH(batch,
2660                   (0 << 31) |
2661                   (0 << 14) |
2662                   (0 << 12) |
2663                   (0 << 10) |
2664                   (0 << 8));
2665     OUT_BCS_BATCH(batch,
2666                   ((gen7_jpeg_wa_clip.data_bit_offset >> 3) << 16) |
2667                   (0 << 5)  |
2668                   (0 << 4)  |
2669                   (1 << 3) | /* LastSlice Flag */
2670                   (gen7_jpeg_wa_clip.data_bit_offset & 0x7));
2671     OUT_BCS_BATCH(batch, 0);
2672     ADVANCE_BCS_BATCH(batch);
2673 }
2674
2675 static void
2676 gen7_jpeg_wa_avc_slice_state(VADriverContextP ctx,
2677                              struct gen7_mfd_context *gen7_mfd_context)
2678 {
2679     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2680     int slice_hor_pos = 0, slice_ver_pos = 0, next_slice_hor_pos = 0, next_slice_ver_pos = 1;
2681     int num_ref_idx_l0 = 0, num_ref_idx_l1 = 0;
2682     int first_mb_in_slice = 0;
2683     int slice_type = SLICE_TYPE_I;
2684
2685     BEGIN_BCS_BATCH(batch, 11);
2686     OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2));
2687     OUT_BCS_BATCH(batch, slice_type);
2688     OUT_BCS_BATCH(batch,
2689                   (num_ref_idx_l1 << 24) |
2690                   (num_ref_idx_l0 << 16) |
2691                   (0 << 8) |
2692                   (0 << 0));
2693     OUT_BCS_BATCH(batch,
2694                   (0 << 29) |
2695                   (1 << 27) |   /* disable Deblocking */
2696                   (0 << 24) |
2697                   (gen7_jpeg_wa_clip.qp << 16) |
2698                   (0 << 8) |
2699                   (0 << 0));
2700     OUT_BCS_BATCH(batch,
2701                   (slice_ver_pos << 24) |
2702                   (slice_hor_pos << 16) |
2703                   (first_mb_in_slice << 0));
2704     OUT_BCS_BATCH(batch,
2705                   (next_slice_ver_pos << 16) |
2706                   (next_slice_hor_pos << 0));
2707     OUT_BCS_BATCH(batch, (1 << 19)); /* last slice flag */
2708     OUT_BCS_BATCH(batch, 0);
2709     OUT_BCS_BATCH(batch, 0);
2710     OUT_BCS_BATCH(batch, 0);
2711     OUT_BCS_BATCH(batch, 0);
2712     ADVANCE_BCS_BATCH(batch);
2713 }
2714
2715 static void
2716 gen7_mfd_jpeg_wa(VADriverContextP ctx,
2717                  struct gen7_mfd_context *gen7_mfd_context)
2718 {
2719     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2720     gen7_jpeg_wa_init(ctx, gen7_mfd_context);
2721     intel_batchbuffer_emit_mi_flush(batch);
2722     gen7_jpeg_wa_pipe_mode_select(ctx, gen7_mfd_context);
2723     gen7_jpeg_wa_surface_state(ctx, gen7_mfd_context);
2724     gen7_jpeg_wa_pipe_buf_addr_state(ctx, gen7_mfd_context);
2725     gen7_jpeg_wa_bsp_buf_base_addr_state(ctx, gen7_mfd_context);
2726     gen7_jpeg_wa_avc_qm_state(ctx, gen7_mfd_context);
2727     gen7_jpeg_wa_avc_img_state(ctx, gen7_mfd_context);
2728     gen7_jpeg_wa_ind_obj_base_addr_state(ctx, gen7_mfd_context);
2729
2730     gen7_jpeg_wa_avc_directmode_state(ctx, gen7_mfd_context);
2731     gen7_jpeg_wa_avc_slice_state(ctx, gen7_mfd_context);
2732     gen7_jpeg_wa_avc_bsd_object(ctx, gen7_mfd_context);
2733 }
2734
2735 void
2736 gen7_mfd_jpeg_decode_picture(VADriverContextP ctx,
2737                              struct decode_state *decode_state,
2738                              struct gen7_mfd_context *gen7_mfd_context)
2739 {
2740     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2741     VAPictureParameterBufferJPEGBaseline *pic_param;
2742     VASliceParameterBufferJPEGBaseline *slice_param, *next_slice_param, *next_slice_group_param;
2743     dri_bo *slice_data_bo;
2744     int i, j, max_selector = 0;
2745
2746     assert(decode_state->pic_param && decode_state->pic_param->buffer);
2747     pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
2748
2749     /* Currently only support Baseline DCT */
2750     gen7_mfd_jpeg_decode_init(ctx, decode_state, gen7_mfd_context);
2751     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
2752     gen7_mfd_jpeg_wa(ctx, gen7_mfd_context);
2753     intel_batchbuffer_emit_mi_flush(batch);
2754     gen7_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_JPEG, gen7_mfd_context);
2755     gen7_mfd_surface_state(ctx, decode_state, MFX_FORMAT_JPEG, gen7_mfd_context);
2756     gen7_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_JPEG, gen7_mfd_context);
2757     gen7_mfd_jpeg_pic_state(ctx, decode_state, gen7_mfd_context);
2758     gen7_mfd_jpeg_qm_state(ctx, decode_state, gen7_mfd_context);
2759
2760     for (j = 0; j < decode_state->num_slice_params; j++) {
2761         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
2762         slice_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j]->buffer;
2763         slice_data_bo = decode_state->slice_datas[j]->bo;
2764         gen7_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_JPEG, gen7_mfd_context);
2765
2766         if (j == decode_state->num_slice_params - 1)
2767             next_slice_group_param = NULL;
2768         else
2769             next_slice_group_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j + 1]->buffer;
2770
2771         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
2772             int component;
2773
2774             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
2775
2776             if (i < decode_state->slice_params[j]->num_elements - 1)
2777                 next_slice_param = slice_param + 1;
2778             else
2779                 next_slice_param = next_slice_group_param;
2780
2781             for (component = 0; component < slice_param->num_components; component++) {
2782                 if (max_selector < slice_param->components[component].dc_table_selector)
2783                     max_selector = slice_param->components[component].dc_table_selector;
2784
2785                 if (max_selector < slice_param->components[component].ac_table_selector)
2786                     max_selector = slice_param->components[component].ac_table_selector;
2787             }
2788
2789             slice_param++;
2790         }
2791     }
2792
2793     assert(max_selector < 2);
2794     gen7_mfd_jpeg_huff_table_state(ctx, decode_state, gen7_mfd_context, max_selector + 1);
2795
2796     for (j = 0; j < decode_state->num_slice_params; j++) {
2797         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
2798         slice_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j]->buffer;
2799         slice_data_bo = decode_state->slice_datas[j]->bo;
2800         gen7_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_JPEG, gen7_mfd_context);
2801
2802         if (j == decode_state->num_slice_params - 1)
2803             next_slice_group_param = NULL;
2804         else
2805             next_slice_group_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j + 1]->buffer;
2806
2807         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
2808             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
2809
2810             if (i < decode_state->slice_params[j]->num_elements - 1)
2811                 next_slice_param = slice_param + 1;
2812             else
2813                 next_slice_param = next_slice_group_param;
2814
2815             gen7_mfd_jpeg_bsd_object(ctx, pic_param, slice_param, next_slice_param, slice_data_bo, gen7_mfd_context);
2816             slice_param++;
2817         }
2818     }
2819
2820     intel_batchbuffer_end_atomic(batch);
2821     intel_batchbuffer_flush(batch);
2822 }
2823
2824 static VAStatus
2825 gen7_mfd_decode_picture(VADriverContextP ctx,
2826                         VAProfile profile,
2827                         union codec_state *codec_state,
2828                         struct hw_context *hw_context)
2829
2830 {
2831     struct gen7_mfd_context *gen7_mfd_context = (struct gen7_mfd_context *)hw_context;
2832     struct decode_state *decode_state = &codec_state->decode;
2833     VAStatus vaStatus;
2834
2835     assert(gen7_mfd_context);
2836
2837     vaStatus = intel_decoder_sanity_check_input(ctx, profile, decode_state);
2838
2839     if (vaStatus != VA_STATUS_SUCCESS)
2840         goto out;
2841
2842     gen7_mfd_context->wa_mpeg2_slice_vertical_position = -1;
2843
2844     switch (profile) {
2845     case VAProfileMPEG2Simple:
2846     case VAProfileMPEG2Main:
2847         gen7_mfd_mpeg2_decode_picture(ctx, decode_state, gen7_mfd_context);
2848         break;
2849
2850     case VAProfileH264ConstrainedBaseline:
2851     case VAProfileH264Main:
2852     case VAProfileH264High:
2853     case VAProfileH264StereoHigh:
2854         gen7_mfd_avc_decode_picture(ctx, decode_state, gen7_mfd_context);
2855         break;
2856
2857     case VAProfileVC1Simple:
2858     case VAProfileVC1Main:
2859     case VAProfileVC1Advanced:
2860         gen7_mfd_vc1_decode_picture(ctx, decode_state, gen7_mfd_context);
2861         break;
2862
2863     case VAProfileJPEGBaseline:
2864         gen7_mfd_jpeg_decode_picture(ctx, decode_state, gen7_mfd_context);
2865         break;
2866
2867     default:
2868         assert(0);
2869         break;
2870     }
2871
2872     vaStatus = VA_STATUS_SUCCESS;
2873
2874 out:
2875     return vaStatus;
2876 }
2877
2878 static void
2879 gen7_mfd_context_destroy(void *hw_context)
2880 {
2881     VADriverContextP ctx;
2882     struct gen7_mfd_context *gen7_mfd_context = (struct gen7_mfd_context *)hw_context;
2883
2884     ctx = (VADriverContextP)(gen7_mfd_context->driver_context);
2885
2886     dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo);
2887     gen7_mfd_context->post_deblocking_output.bo = NULL;
2888
2889     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
2890     gen7_mfd_context->pre_deblocking_output.bo = NULL;
2891
2892     dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo);
2893     gen7_mfd_context->intra_row_store_scratch_buffer.bo = NULL;
2894
2895     dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
2896     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
2897
2898     dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
2899     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
2900
2901     dri_bo_unreference(gen7_mfd_context->mpr_row_store_scratch_buffer.bo);
2902     gen7_mfd_context->mpr_row_store_scratch_buffer.bo = NULL;
2903
2904     dri_bo_unreference(gen7_mfd_context->bitplane_read_buffer.bo);
2905     gen7_mfd_context->bitplane_read_buffer.bo = NULL;
2906
2907     dri_bo_unreference(gen7_mfd_context->jpeg_wa_slice_data_bo);
2908
2909     if (gen7_mfd_context->jpeg_wa_surface_id != VA_INVALID_SURFACE) {
2910         i965_DestroySurfaces(ctx,
2911                              &gen7_mfd_context->jpeg_wa_surface_id,
2912                              1);
2913         gen7_mfd_context->jpeg_wa_surface_object = NULL;
2914     }
2915
2916     intel_batchbuffer_free(gen7_mfd_context->base.batch);
2917     free(gen7_mfd_context);
2918 }
2919
2920 static void gen7_mfd_mpeg2_context_init(VADriverContextP ctx,
2921                                         struct gen7_mfd_context *gen7_mfd_context)
2922 {
2923     gen7_mfd_context->iq_matrix.mpeg2.load_intra_quantiser_matrix = -1;
2924     gen7_mfd_context->iq_matrix.mpeg2.load_non_intra_quantiser_matrix = -1;
2925     gen7_mfd_context->iq_matrix.mpeg2.load_chroma_intra_quantiser_matrix = -1;
2926     gen7_mfd_context->iq_matrix.mpeg2.load_chroma_non_intra_quantiser_matrix = -1;
2927 }
2928
2929 struct hw_context *
2930 gen7_dec_hw_context_init(VADriverContextP ctx, struct object_config *obj_config)
2931 {
2932     struct intel_driver_data *intel = intel_driver_data(ctx);
2933     struct gen7_mfd_context *gen7_mfd_context = calloc(1, sizeof(struct gen7_mfd_context));
2934     int i;
2935
2936     assert(gen7_mfd_context);
2937     gen7_mfd_context->base.destroy = gen7_mfd_context_destroy;
2938     gen7_mfd_context->base.run = gen7_mfd_decode_picture;
2939     gen7_mfd_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER, 0);
2940
2941     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
2942         gen7_mfd_context->reference_surface[i].surface_id = VA_INVALID_ID;
2943         gen7_mfd_context->reference_surface[i].frame_store_id = -1;
2944         gen7_mfd_context->reference_surface[i].obj_surface = NULL;
2945     }
2946
2947     gen7_mfd_context->jpeg_wa_surface_id = VA_INVALID_SURFACE;
2948     gen7_mfd_context->jpeg_wa_surface_object = NULL;
2949
2950     switch (obj_config->profile) {
2951     case VAProfileMPEG2Simple:
2952     case VAProfileMPEG2Main:
2953         gen7_mfd_mpeg2_context_init(ctx, gen7_mfd_context);
2954         break;
2955
2956     case VAProfileH264ConstrainedBaseline:
2957     case VAProfileH264Main:
2958     case VAProfileH264High:
2959     case VAProfileH264StereoHigh:
2960         gen7_mfd_avc_context_init(ctx, gen7_mfd_context);
2961         break;
2962     default:
2963         break;
2964     }
2965
2966     gen7_mfd_context->driver_context = ctx;
2967     return (struct hw_context *)gen7_mfd_context;
2968 }