2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Xiang Haihao <haihao.xiang@intel.com>
31 #include <va/va_dec_jpeg.h>
33 #include "intel_batchbuffer.h"
34 #include "intel_driver.h"
35 #include "i965_defines.h"
36 #include "i965_drv_video.h"
37 #include "i965_decoder_utils.h"
40 #include "intel_media.h"
42 static const uint32_t zigzag_direct[64] = {
43 0, 1, 8, 16, 9, 2, 3, 10,
44 17, 24, 32, 25, 18, 11, 4, 5,
45 12, 19, 26, 33, 40, 48, 41, 34,
46 27, 20, 13, 6, 7, 14, 21, 28,
47 35, 42, 49, 56, 57, 50, 43, 36,
48 29, 22, 15, 23, 30, 37, 44, 51,
49 58, 59, 52, 45, 38, 31, 39, 46,
50 53, 60, 61, 54, 47, 55, 62, 63
54 gen7_mfd_init_avc_surface(VADriverContextP ctx,
55 VAPictureParameterBufferH264 *pic_param,
56 struct object_surface *obj_surface)
58 struct i965_driver_data *i965 = i965_driver_data(ctx);
59 GenAvcSurface *gen7_avc_surface = obj_surface->private_data;
60 int width_in_mbs, height_in_mbs;
62 obj_surface->free_private_data = gen_free_avc_surface;
63 width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
64 height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; /* frame height */
66 if (!gen7_avc_surface) {
67 gen7_avc_surface = calloc(sizeof(GenAvcSurface), 1);
68 assert(gen7_avc_surface);
69 gen7_avc_surface->base.frame_store_id = -1;
70 assert((obj_surface->size & 0x3f) == 0);
71 obj_surface->private_data = gen7_avc_surface;
74 gen7_avc_surface->dmv_bottom_flag = (pic_param->pic_fields.bits.field_pic_flag &&
75 !pic_param->seq_fields.bits.direct_8x8_inference_flag);
77 if (gen7_avc_surface->dmv_top == NULL) {
78 gen7_avc_surface->dmv_top = dri_bo_alloc(i965->intel.bufmgr,
79 "direct mv w/r buffer",
80 width_in_mbs * (height_in_mbs + 1) * 64,
82 assert(gen7_avc_surface->dmv_top);
85 if (gen7_avc_surface->dmv_bottom_flag &&
86 gen7_avc_surface->dmv_bottom == NULL) {
87 gen7_avc_surface->dmv_bottom = dri_bo_alloc(i965->intel.bufmgr,
88 "direct mv w/r buffer",
89 width_in_mbs * (height_in_mbs + 1) * 64,
91 assert(gen7_avc_surface->dmv_bottom);
96 gen7_mfd_pipe_mode_select(VADriverContextP ctx,
97 struct decode_state *decode_state,
99 struct gen7_mfd_context *gen7_mfd_context)
101 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
103 assert(standard_select == MFX_FORMAT_MPEG2 ||
104 standard_select == MFX_FORMAT_AVC ||
105 standard_select == MFX_FORMAT_VC1 ||
106 standard_select == MFX_FORMAT_JPEG);
108 BEGIN_BCS_BATCH(batch, 5);
109 OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2));
111 (MFX_LONG_MODE << 17) | /* Currently only support long format */
112 (MFD_MODE_VLD << 15) | /* VLD mode */
113 (0 << 10) | /* disable Stream-Out */
114 (gen7_mfd_context->post_deblocking_output.valid << 9) | /* Post Deblocking Output */
115 (gen7_mfd_context->pre_deblocking_output.valid << 8) | /* Pre Deblocking Output */
116 (0 << 5) | /* not in stitch mode */
117 (MFX_CODEC_DECODE << 4) | /* decoding mode */
118 (standard_select << 0));
120 (0 << 4) | /* terminate if AVC motion and POC table error occurs */
121 (0 << 3) | /* terminate if AVC mbdata error occurs */
122 (0 << 2) | /* terminate if AVC CABAC/CAVLC decode error occurs */
125 OUT_BCS_BATCH(batch, 0); /* pic status/error report id */
126 OUT_BCS_BATCH(batch, 0); /* reserved */
127 ADVANCE_BCS_BATCH(batch);
131 gen7_mfd_surface_state(VADriverContextP ctx,
132 struct decode_state *decode_state,
134 struct gen7_mfd_context *gen7_mfd_context)
136 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
137 struct object_surface *obj_surface = decode_state->render_object;
138 unsigned int y_cb_offset;
139 unsigned int y_cr_offset;
140 unsigned int surface_format;
144 y_cb_offset = obj_surface->y_cb_offset;
145 y_cr_offset = obj_surface->y_cr_offset;
147 surface_format = obj_surface->fourcc == VA_FOURCC_Y800 ?
148 MFX_SURFACE_MONOCHROME : MFX_SURFACE_PLANAR_420_8;
150 BEGIN_BCS_BATCH(batch, 6);
151 OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
152 OUT_BCS_BATCH(batch, 0);
154 ((obj_surface->orig_height - 1) << 18) |
155 ((obj_surface->orig_width - 1) << 4));
157 (surface_format << 28) | /* 420 planar YUV surface */
158 ((standard_select != MFX_FORMAT_JPEG) << 27) | /* interleave chroma, set to 0 for JPEG */
159 (0 << 22) | /* surface object control state, ignored */
160 ((obj_surface->width - 1) << 3) | /* pitch */
161 (0 << 2) | /* must be 0 */
162 (1 << 1) | /* must be tiled */
163 (I965_TILEWALK_YMAJOR << 0)); /* tile walk, must be 1 */
165 (0 << 16) | /* X offset for U(Cb), must be 0 */
166 (y_cb_offset << 0)); /* Y offset for U(Cb) */
168 (0 << 16) | /* X offset for V(Cr), must be 0 */
169 ((standard_select == MFX_FORMAT_JPEG ? y_cr_offset : 0) << 0)); /* Y offset for V(Cr), must be 0 for video codec, non-zoro for JPEG */
170 ADVANCE_BCS_BATCH(batch);
174 gen7_mfd_pipe_buf_addr_state(VADriverContextP ctx,
175 struct decode_state *decode_state,
177 struct gen7_mfd_context *gen7_mfd_context)
179 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
182 BEGIN_BCS_BATCH(batch, 24);
183 OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
184 if (gen7_mfd_context->pre_deblocking_output.valid)
185 OUT_BCS_RELOC(batch, gen7_mfd_context->pre_deblocking_output.bo,
186 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
189 OUT_BCS_BATCH(batch, 0);
191 if (gen7_mfd_context->post_deblocking_output.valid)
192 OUT_BCS_RELOC(batch, gen7_mfd_context->post_deblocking_output.bo,
193 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
196 OUT_BCS_BATCH(batch, 0);
198 OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
199 OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
201 if (gen7_mfd_context->intra_row_store_scratch_buffer.valid)
202 OUT_BCS_RELOC(batch, gen7_mfd_context->intra_row_store_scratch_buffer.bo,
203 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
206 OUT_BCS_BATCH(batch, 0);
208 if (gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid)
209 OUT_BCS_RELOC(batch, gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo,
210 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
213 OUT_BCS_BATCH(batch, 0);
216 for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
217 struct object_surface *obj_surface;
219 if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID &&
220 gen7_mfd_context->reference_surface[i].obj_surface &&
221 gen7_mfd_context->reference_surface[i].obj_surface->bo) {
222 obj_surface = gen7_mfd_context->reference_surface[i].obj_surface;
224 OUT_BCS_RELOC(batch, obj_surface->bo,
225 I915_GEM_DOMAIN_INSTRUCTION, 0,
228 OUT_BCS_BATCH(batch, 0);
232 OUT_BCS_BATCH(batch, 0); /* ignore DW23 for decoding */
233 ADVANCE_BCS_BATCH(batch);
237 gen7_mfd_ind_obj_base_addr_state(VADriverContextP ctx,
238 dri_bo *slice_data_bo,
240 struct gen7_mfd_context *gen7_mfd_context)
242 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
244 BEGIN_BCS_BATCH(batch, 11);
245 OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
246 OUT_BCS_RELOC(batch, slice_data_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); /* MFX Indirect Bitstream Object Base Address */
247 OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
248 OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
249 OUT_BCS_BATCH(batch, 0);
250 OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
251 OUT_BCS_BATCH(batch, 0);
252 OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
253 OUT_BCS_BATCH(batch, 0);
254 OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
255 OUT_BCS_BATCH(batch, 0);
256 ADVANCE_BCS_BATCH(batch);
260 gen7_mfd_bsp_buf_base_addr_state(VADriverContextP ctx,
261 struct decode_state *decode_state,
263 struct gen7_mfd_context *gen7_mfd_context)
265 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
267 BEGIN_BCS_BATCH(batch, 4);
268 OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
270 if (gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid)
271 OUT_BCS_RELOC(batch, gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo,
272 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
275 OUT_BCS_BATCH(batch, 0);
277 if (gen7_mfd_context->mpr_row_store_scratch_buffer.valid)
278 OUT_BCS_RELOC(batch, gen7_mfd_context->mpr_row_store_scratch_buffer.bo,
279 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
282 OUT_BCS_BATCH(batch, 0);
284 if (gen7_mfd_context->bitplane_read_buffer.valid)
285 OUT_BCS_RELOC(batch, gen7_mfd_context->bitplane_read_buffer.bo,
286 I915_GEM_DOMAIN_INSTRUCTION, 0,
289 OUT_BCS_BATCH(batch, 0);
291 ADVANCE_BCS_BATCH(batch);
295 gen7_mfd_qm_state(VADriverContextP ctx,
299 struct gen7_mfd_context *gen7_mfd_context)
301 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
302 unsigned int qm_buffer[16];
304 assert(qm_length <= 16 * 4);
305 memcpy(qm_buffer, qm, qm_length);
307 BEGIN_BCS_BATCH(batch, 18);
308 OUT_BCS_BATCH(batch, MFX_QM_STATE | (18 - 2));
309 OUT_BCS_BATCH(batch, qm_type << 0);
310 intel_batchbuffer_data(batch, qm_buffer, 16 * 4);
311 ADVANCE_BCS_BATCH(batch);
315 gen7_mfd_avc_img_state(VADriverContextP ctx,
316 struct decode_state *decode_state,
317 struct gen7_mfd_context *gen7_mfd_context)
319 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
321 int mbaff_frame_flag;
322 unsigned int width_in_mbs, height_in_mbs;
323 VAPictureParameterBufferH264 *pic_param;
325 assert(decode_state->pic_param && decode_state->pic_param->buffer);
326 pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
328 if (pic_param->CurrPic.flags & VA_PICTURE_H264_TOP_FIELD)
330 else if (pic_param->CurrPic.flags & VA_PICTURE_H264_BOTTOM_FIELD)
335 if ((img_struct & 0x1) == 0x1) {
336 assert(pic_param->pic_fields.bits.field_pic_flag == 0x1);
338 assert(pic_param->pic_fields.bits.field_pic_flag == 0x0);
341 if (pic_param->seq_fields.bits.frame_mbs_only_flag) { /* a frame containing only frame macroblocks */
342 assert(pic_param->seq_fields.bits.mb_adaptive_frame_field_flag == 0);
343 assert(pic_param->pic_fields.bits.field_pic_flag == 0);
345 assert(pic_param->seq_fields.bits.direct_8x8_inference_flag == 1); /* see H.264 spec */
348 mbaff_frame_flag = (pic_param->seq_fields.bits.mb_adaptive_frame_field_flag &&
349 !pic_param->pic_fields.bits.field_pic_flag);
351 width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
352 height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; /* frame height */
354 /* MFX unit doesn't support 4:2:2 and 4:4:4 picture */
355 assert(pic_param->seq_fields.bits.chroma_format_idc == 0 || /* monochrome picture */
356 pic_param->seq_fields.bits.chroma_format_idc == 1); /* 4:2:0 */
357 assert(pic_param->seq_fields.bits.residual_colour_transform_flag == 0); /* only available for 4:4:4 */
359 BEGIN_BCS_BATCH(batch, 16);
360 OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (16 - 2));
362 (width_in_mbs * height_in_mbs - 1));
364 ((height_in_mbs - 1) << 16) |
365 ((width_in_mbs - 1) << 0));
367 ((pic_param->second_chroma_qp_index_offset & 0x1f) << 24) |
368 ((pic_param->chroma_qp_index_offset & 0x1f) << 16) |
369 (0 << 14) | /* Max-bit conformance Intra flag ??? FIXME */
370 (0 << 13) | /* Max Macroblock size conformance Inter flag ??? FIXME */
371 (pic_param->pic_fields.bits.weighted_pred_flag << 12) | /* differ from GEN6 */
372 (pic_param->pic_fields.bits.weighted_bipred_idc << 10) |
375 (pic_param->seq_fields.bits.chroma_format_idc << 10) |
376 (pic_param->pic_fields.bits.entropy_coding_mode_flag << 7) |
377 ((!pic_param->pic_fields.bits.reference_pic_flag) << 6) |
378 (pic_param->pic_fields.bits.constrained_intra_pred_flag << 5) |
379 (pic_param->seq_fields.bits.direct_8x8_inference_flag << 4) |
380 (pic_param->pic_fields.bits.transform_8x8_mode_flag << 3) |
381 (pic_param->seq_fields.bits.frame_mbs_only_flag << 2) |
382 (mbaff_frame_flag << 1) |
383 (pic_param->pic_fields.bits.field_pic_flag << 0));
384 OUT_BCS_BATCH(batch, 0);
385 OUT_BCS_BATCH(batch, 0);
386 OUT_BCS_BATCH(batch, 0);
387 OUT_BCS_BATCH(batch, 0);
388 OUT_BCS_BATCH(batch, 0);
389 OUT_BCS_BATCH(batch, 0);
390 OUT_BCS_BATCH(batch, 0);
391 OUT_BCS_BATCH(batch, 0);
392 OUT_BCS_BATCH(batch, 0);
393 OUT_BCS_BATCH(batch, 0);
394 OUT_BCS_BATCH(batch, 0);
395 ADVANCE_BCS_BATCH(batch);
399 gen7_mfd_avc_qm_state(VADriverContextP ctx,
400 struct decode_state *decode_state,
401 struct gen7_mfd_context *gen7_mfd_context)
403 VAIQMatrixBufferH264 *iq_matrix;
404 VAPictureParameterBufferH264 *pic_param;
406 if (decode_state->iq_matrix && decode_state->iq_matrix->buffer)
407 iq_matrix = (VAIQMatrixBufferH264 *)decode_state->iq_matrix->buffer;
409 iq_matrix = &gen7_mfd_context->iq_matrix.h264;
411 assert(decode_state->pic_param && decode_state->pic_param->buffer);
412 pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
414 gen7_mfd_qm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, &iq_matrix->ScalingList4x4[0][0], 3 * 16, gen7_mfd_context);
415 gen7_mfd_qm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, &iq_matrix->ScalingList4x4[3][0], 3 * 16, gen7_mfd_context);
417 if (pic_param->pic_fields.bits.transform_8x8_mode_flag) {
418 gen7_mfd_qm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, &iq_matrix->ScalingList8x8[0][0], 64, gen7_mfd_context);
419 gen7_mfd_qm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, &iq_matrix->ScalingList8x8[1][0], 64, gen7_mfd_context);
424 gen7_mfd_avc_directmode_state(VADriverContextP ctx,
425 struct decode_state *decode_state,
426 VAPictureParameterBufferH264 *pic_param,
427 VASliceParameterBufferH264 *slice_param,
428 struct gen7_mfd_context *gen7_mfd_context)
430 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
431 struct object_surface *obj_surface;
432 GenAvcSurface *gen7_avc_surface;
433 VAPictureH264 *va_pic;
436 BEGIN_BCS_BATCH(batch, 69);
437 OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
439 /* reference surfaces 0..15 */
440 for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
441 if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID &&
442 gen7_mfd_context->reference_surface[i].obj_surface &&
443 gen7_mfd_context->reference_surface[i].obj_surface->private_data) {
445 obj_surface = gen7_mfd_context->reference_surface[i].obj_surface;
446 gen7_avc_surface = obj_surface->private_data;
447 OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
448 I915_GEM_DOMAIN_INSTRUCTION, 0,
451 if (gen7_avc_surface->dmv_bottom_flag == 1)
452 OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_bottom,
453 I915_GEM_DOMAIN_INSTRUCTION, 0,
456 OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
457 I915_GEM_DOMAIN_INSTRUCTION, 0,
460 OUT_BCS_BATCH(batch, 0);
461 OUT_BCS_BATCH(batch, 0);
465 /* the current decoding frame/field */
466 va_pic = &pic_param->CurrPic;
467 obj_surface = decode_state->render_object;
468 assert(obj_surface->bo && obj_surface->private_data);
469 gen7_avc_surface = obj_surface->private_data;
471 OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
472 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
475 if (gen7_avc_surface->dmv_bottom_flag == 1)
476 OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_bottom,
477 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
480 OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
481 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
485 for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
486 obj_surface = gen7_mfd_context->reference_surface[i].obj_surface;
489 const VAPictureH264 * const va_pic = avc_find_picture(
490 obj_surface->base.id, pic_param->ReferenceFrames,
491 ARRAY_ELEMS(pic_param->ReferenceFrames));
493 assert(va_pic != NULL);
494 OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
495 OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
497 OUT_BCS_BATCH(batch, 0);
498 OUT_BCS_BATCH(batch, 0);
502 va_pic = &pic_param->CurrPic;
503 OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
504 OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
506 ADVANCE_BCS_BATCH(batch);
510 gen7_mfd_avc_phantom_slice_first(VADriverContextP ctx,
511 VAPictureParameterBufferH264 *pic_param,
512 VASliceParameterBufferH264 *next_slice_param,
513 struct gen7_mfd_context *gen7_mfd_context)
515 gen6_mfd_avc_phantom_slice(ctx, pic_param, next_slice_param, gen7_mfd_context->base.batch);
519 gen7_mfd_avc_slice_state(VADriverContextP ctx,
520 VAPictureParameterBufferH264 *pic_param,
521 VASliceParameterBufferH264 *slice_param,
522 VASliceParameterBufferH264 *next_slice_param,
523 struct gen7_mfd_context *gen7_mfd_context)
525 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
526 int width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
527 int height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1;
528 int slice_hor_pos, slice_ver_pos, next_slice_hor_pos, next_slice_ver_pos;
529 int num_ref_idx_l0, num_ref_idx_l1;
530 int mbaff_picture = (!pic_param->pic_fields.bits.field_pic_flag &&
531 pic_param->seq_fields.bits.mb_adaptive_frame_field_flag);
532 int first_mb_in_slice = 0, first_mb_in_next_slice = 0;
535 if (slice_param->slice_type == SLICE_TYPE_I ||
536 slice_param->slice_type == SLICE_TYPE_SI) {
537 slice_type = SLICE_TYPE_I;
538 } else if (slice_param->slice_type == SLICE_TYPE_P ||
539 slice_param->slice_type == SLICE_TYPE_SP) {
540 slice_type = SLICE_TYPE_P;
542 assert(slice_param->slice_type == SLICE_TYPE_B);
543 slice_type = SLICE_TYPE_B;
546 if (slice_type == SLICE_TYPE_I) {
547 assert(slice_param->num_ref_idx_l0_active_minus1 == 0);
548 assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
551 } else if (slice_type == SLICE_TYPE_P) {
552 assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
553 num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
556 num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
557 num_ref_idx_l1 = slice_param->num_ref_idx_l1_active_minus1 + 1;
560 first_mb_in_slice = slice_param->first_mb_in_slice;
561 slice_hor_pos = first_mb_in_slice % width_in_mbs;
562 slice_ver_pos = first_mb_in_slice / width_in_mbs;
565 slice_ver_pos = slice_ver_pos << 1;
567 if (next_slice_param) {
568 first_mb_in_next_slice = next_slice_param->first_mb_in_slice;
569 next_slice_hor_pos = first_mb_in_next_slice % width_in_mbs;
570 next_slice_ver_pos = first_mb_in_next_slice / width_in_mbs;
573 next_slice_ver_pos = next_slice_ver_pos << 1;
575 next_slice_hor_pos = 0;
576 next_slice_ver_pos = height_in_mbs / (1 + !!pic_param->pic_fields.bits.field_pic_flag);
579 BEGIN_BCS_BATCH(batch, 11); /* FIXME: is it 10??? */
580 OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2));
581 OUT_BCS_BATCH(batch, slice_type);
583 (num_ref_idx_l1 << 24) |
584 (num_ref_idx_l0 << 16) |
585 (slice_param->chroma_log2_weight_denom << 8) |
586 (slice_param->luma_log2_weight_denom << 0));
588 (slice_param->direct_spatial_mv_pred_flag << 29) |
589 (slice_param->disable_deblocking_filter_idc << 27) |
590 (slice_param->cabac_init_idc << 24) |
591 ((pic_param->pic_init_qp_minus26 + 26 + slice_param->slice_qp_delta) << 16) |
592 ((slice_param->slice_beta_offset_div2 & 0xf) << 8) |
593 ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0));
595 (slice_ver_pos << 24) |
596 (slice_hor_pos << 16) |
597 (first_mb_in_slice << 0));
599 (next_slice_ver_pos << 16) |
600 (next_slice_hor_pos << 0));
602 (next_slice_param == NULL) << 19); /* last slice flag */
603 OUT_BCS_BATCH(batch, 0);
604 OUT_BCS_BATCH(batch, 0);
605 OUT_BCS_BATCH(batch, 0);
606 OUT_BCS_BATCH(batch, 0);
607 ADVANCE_BCS_BATCH(batch);
611 gen7_mfd_avc_ref_idx_state(VADriverContextP ctx,
612 VAPictureParameterBufferH264 *pic_param,
613 VASliceParameterBufferH264 *slice_param,
614 struct gen7_mfd_context *gen7_mfd_context)
616 gen6_send_avc_ref_idx_state(
617 gen7_mfd_context->base.batch,
619 gen7_mfd_context->reference_surface
624 gen7_mfd_avc_weightoffset_state(VADriverContextP ctx,
625 VAPictureParameterBufferH264 *pic_param,
626 VASliceParameterBufferH264 *slice_param,
627 struct gen7_mfd_context *gen7_mfd_context)
629 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
630 int i, j, num_weight_offset_table = 0;
631 short weightoffsets[32 * 6];
633 if ((slice_param->slice_type == SLICE_TYPE_P ||
634 slice_param->slice_type == SLICE_TYPE_SP) &&
635 (pic_param->pic_fields.bits.weighted_pred_flag == 1)) {
636 num_weight_offset_table = 1;
639 if ((slice_param->slice_type == SLICE_TYPE_B) &&
640 (pic_param->pic_fields.bits.weighted_bipred_idc == 1)) {
641 num_weight_offset_table = 2;
644 for (i = 0; i < num_weight_offset_table; i++) {
645 BEGIN_BCS_BATCH(batch, 98);
646 OUT_BCS_BATCH(batch, MFX_AVC_WEIGHTOFFSET_STATE | (98 - 2));
647 OUT_BCS_BATCH(batch, i);
650 for (j = 0; j < 32; j++) {
651 weightoffsets[j * 6 + 0] = slice_param->luma_weight_l0[j];
652 weightoffsets[j * 6 + 1] = slice_param->luma_offset_l0[j];
653 weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l0[j][0];
654 weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l0[j][0];
655 weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l0[j][1];
656 weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l0[j][1];
659 for (j = 0; j < 32; j++) {
660 weightoffsets[j * 6 + 0] = slice_param->luma_weight_l1[j];
661 weightoffsets[j * 6 + 1] = slice_param->luma_offset_l1[j];
662 weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l1[j][0];
663 weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l1[j][0];
664 weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l1[j][1];
665 weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l1[j][1];
669 intel_batchbuffer_data(batch, weightoffsets, sizeof(weightoffsets));
670 ADVANCE_BCS_BATCH(batch);
675 gen7_mfd_avc_bsd_object(VADriverContextP ctx,
676 VAPictureParameterBufferH264 *pic_param,
677 VASliceParameterBufferH264 *slice_param,
678 dri_bo *slice_data_bo,
679 VASliceParameterBufferH264 *next_slice_param,
680 struct gen7_mfd_context *gen7_mfd_context)
682 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
683 unsigned int slice_data_bit_offset;
685 slice_data_bit_offset = avc_get_first_mb_bit_offset(
688 pic_param->pic_fields.bits.entropy_coding_mode_flag
691 /* the input bitsteam format on GEN7 differs from GEN6 */
692 BEGIN_BCS_BATCH(batch, 6);
693 OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2));
695 (slice_param->slice_data_size - slice_param->slice_data_offset));
696 OUT_BCS_BATCH(batch, slice_param->slice_data_offset);
704 ((slice_data_bit_offset >> 3) << 16) |
708 ((next_slice_param == NULL) << 3) | /* LastSlice Flag */
709 (slice_data_bit_offset & 0x7));
710 OUT_BCS_BATCH(batch, 0);
711 ADVANCE_BCS_BATCH(batch);
715 gen7_mfd_avc_context_init(
716 VADriverContextP ctx,
717 struct gen7_mfd_context *gen7_mfd_context
720 /* Initialize flat scaling lists */
721 avc_gen_default_iq_matrix(&gen7_mfd_context->iq_matrix.h264);
725 gen7_mfd_avc_decode_init(VADriverContextP ctx,
726 struct decode_state *decode_state,
727 struct gen7_mfd_context *gen7_mfd_context)
729 VAPictureParameterBufferH264 *pic_param;
730 VASliceParameterBufferH264 *slice_param;
731 struct i965_driver_data *i965 = i965_driver_data(ctx);
732 struct object_surface *obj_surface;
734 int i, j, enable_avc_ildb = 0;
735 unsigned int width_in_mbs, height_in_mbs;
737 for (j = 0; j < decode_state->num_slice_params && enable_avc_ildb == 0; j++) {
738 assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
739 slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
741 for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
742 assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
743 assert((slice_param->slice_type == SLICE_TYPE_I) ||
744 (slice_param->slice_type == SLICE_TYPE_SI) ||
745 (slice_param->slice_type == SLICE_TYPE_P) ||
746 (slice_param->slice_type == SLICE_TYPE_SP) ||
747 (slice_param->slice_type == SLICE_TYPE_B));
749 if (slice_param->disable_deblocking_filter_idc != 1) {
758 assert(decode_state->pic_param && decode_state->pic_param->buffer);
759 pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
760 intel_update_avc_frame_store_index(ctx, decode_state, pic_param,
761 gen7_mfd_context->reference_surface, &gen7_mfd_context->fs_ctx);
762 width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
763 height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1;
764 assert(width_in_mbs > 0 && width_in_mbs <= 256); /* 4K */
765 assert(height_in_mbs > 0 && height_in_mbs <= 256);
767 /* Current decoded picture */
768 obj_surface = decode_state->render_object;
769 if (pic_param->pic_fields.bits.reference_pic_flag)
770 obj_surface->flags |= SURFACE_REFERENCED;
772 obj_surface->flags &= ~SURFACE_REFERENCED;
774 avc_ensure_surface_bo(ctx, decode_state, obj_surface, pic_param);
775 gen7_mfd_init_avc_surface(ctx, pic_param, obj_surface);
777 dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo);
778 gen7_mfd_context->post_deblocking_output.bo = obj_surface->bo;
779 dri_bo_reference(gen7_mfd_context->post_deblocking_output.bo);
780 gen7_mfd_context->post_deblocking_output.valid = enable_avc_ildb;
782 dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
783 gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
784 dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
785 gen7_mfd_context->pre_deblocking_output.valid = !enable_avc_ildb;
787 dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo);
788 bo = dri_bo_alloc(i965->intel.bufmgr,
793 gen7_mfd_context->intra_row_store_scratch_buffer.bo = bo;
794 gen7_mfd_context->intra_row_store_scratch_buffer.valid = 1;
796 dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
797 bo = dri_bo_alloc(i965->intel.bufmgr,
798 "deblocking filter row store",
799 width_in_mbs * 64 * 4,
802 gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
803 gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1;
805 dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
806 bo = dri_bo_alloc(i965->intel.bufmgr,
808 width_in_mbs * 64 * 2,
811 gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
812 gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
814 dri_bo_unreference(gen7_mfd_context->mpr_row_store_scratch_buffer.bo);
815 bo = dri_bo_alloc(i965->intel.bufmgr,
817 width_in_mbs * 64 * 2,
820 gen7_mfd_context->mpr_row_store_scratch_buffer.bo = bo;
821 gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 1;
823 gen7_mfd_context->bitplane_read_buffer.valid = 0;
827 gen7_mfd_avc_decode_picture(VADriverContextP ctx,
828 struct decode_state *decode_state,
829 struct gen7_mfd_context *gen7_mfd_context)
831 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
832 VAPictureParameterBufferH264 *pic_param;
833 VASliceParameterBufferH264 *slice_param, *next_slice_param, *next_slice_group_param;
834 dri_bo *slice_data_bo;
837 assert(decode_state->pic_param && decode_state->pic_param->buffer);
838 pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
839 gen7_mfd_avc_decode_init(ctx, decode_state, gen7_mfd_context);
841 intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
842 intel_batchbuffer_emit_mi_flush(batch);
843 gen7_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
844 gen7_mfd_surface_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
845 gen7_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
846 gen7_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
847 gen7_mfd_avc_qm_state(ctx, decode_state, gen7_mfd_context);
848 gen7_mfd_avc_img_state(ctx, decode_state, gen7_mfd_context);
850 for (j = 0; j < decode_state->num_slice_params; j++) {
851 assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
852 slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
853 slice_data_bo = decode_state->slice_datas[j]->bo;
854 gen7_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_AVC, gen7_mfd_context);
856 if (j == decode_state->num_slice_params - 1)
857 next_slice_group_param = NULL;
859 next_slice_group_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j + 1]->buffer;
861 if (j == 0 && slice_param->first_mb_in_slice)
862 gen7_mfd_avc_phantom_slice_first(ctx, pic_param, slice_param, gen7_mfd_context);
864 for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
865 assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
866 assert((slice_param->slice_type == SLICE_TYPE_I) ||
867 (slice_param->slice_type == SLICE_TYPE_SI) ||
868 (slice_param->slice_type == SLICE_TYPE_P) ||
869 (slice_param->slice_type == SLICE_TYPE_SP) ||
870 (slice_param->slice_type == SLICE_TYPE_B));
872 if (i < decode_state->slice_params[j]->num_elements - 1)
873 next_slice_param = slice_param + 1;
875 next_slice_param = next_slice_group_param;
877 gen7_mfd_avc_directmode_state(ctx, decode_state, pic_param, slice_param, gen7_mfd_context);
878 gen7_mfd_avc_ref_idx_state(ctx, pic_param, slice_param, gen7_mfd_context);
879 gen7_mfd_avc_weightoffset_state(ctx, pic_param, slice_param, gen7_mfd_context);
880 gen7_mfd_avc_slice_state(ctx, pic_param, slice_param, next_slice_param, gen7_mfd_context);
881 gen7_mfd_avc_bsd_object(ctx, pic_param, slice_param, slice_data_bo, next_slice_param, gen7_mfd_context);
886 intel_batchbuffer_end_atomic(batch);
887 intel_batchbuffer_flush(batch);
891 gen7_mfd_mpeg2_decode_init(VADriverContextP ctx,
892 struct decode_state *decode_state,
893 struct gen7_mfd_context *gen7_mfd_context)
895 VAPictureParameterBufferMPEG2 *pic_param;
896 struct i965_driver_data *i965 = i965_driver_data(ctx);
897 struct object_surface *obj_surface;
899 unsigned int width_in_mbs;
901 assert(decode_state->pic_param && decode_state->pic_param->buffer);
902 pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
903 width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16;
905 mpeg2_set_reference_surfaces(
907 gen7_mfd_context->reference_surface,
912 /* Current decoded picture */
913 obj_surface = decode_state->render_object;
914 i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
916 dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
917 gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
918 dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
919 gen7_mfd_context->pre_deblocking_output.valid = 1;
921 dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
922 bo = dri_bo_alloc(i965->intel.bufmgr,
927 gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
928 gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
930 gen7_mfd_context->post_deblocking_output.valid = 0;
931 gen7_mfd_context->intra_row_store_scratch_buffer.valid = 0;
932 gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 0;
933 gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
934 gen7_mfd_context->bitplane_read_buffer.valid = 0;
938 gen7_mfd_mpeg2_pic_state(VADriverContextP ctx,
939 struct decode_state *decode_state,
940 struct gen7_mfd_context *gen7_mfd_context)
942 struct i965_driver_data * const i965 = i965_driver_data(ctx);
943 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
944 VAPictureParameterBufferMPEG2 *pic_param;
945 unsigned int slice_concealment_disable_bit = 0;
947 assert(decode_state->pic_param && decode_state->pic_param->buffer);
948 pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
950 if (IS_HASWELL(i965->intel.device_info)) {
951 /* XXX: disable concealment for now */
952 slice_concealment_disable_bit = 1;
955 BEGIN_BCS_BATCH(batch, 13);
956 OUT_BCS_BATCH(batch, MFX_MPEG2_PIC_STATE | (13 - 2));
958 (pic_param->f_code & 0xf) << 28 | /* f_code[1][1] */
959 ((pic_param->f_code >> 4) & 0xf) << 24 | /* f_code[1][0] */
960 ((pic_param->f_code >> 8) & 0xf) << 20 | /* f_code[0][1] */
961 ((pic_param->f_code >> 12) & 0xf) << 16 | /* f_code[0][0] */
962 pic_param->picture_coding_extension.bits.intra_dc_precision << 14 |
963 pic_param->picture_coding_extension.bits.picture_structure << 12 |
964 pic_param->picture_coding_extension.bits.top_field_first << 11 |
965 pic_param->picture_coding_extension.bits.frame_pred_frame_dct << 10 |
966 pic_param->picture_coding_extension.bits.concealment_motion_vectors << 9 |
967 pic_param->picture_coding_extension.bits.q_scale_type << 8 |
968 pic_param->picture_coding_extension.bits.intra_vlc_format << 7 |
969 pic_param->picture_coding_extension.bits.alternate_scan << 6);
971 pic_param->picture_coding_type << 9);
973 (slice_concealment_disable_bit << 31) |
974 ((ALIGN(pic_param->vertical_size, 16) / 16) - 1) << 16 |
975 ((ALIGN(pic_param->horizontal_size, 16) / 16) - 1));
976 OUT_BCS_BATCH(batch, 0);
977 OUT_BCS_BATCH(batch, 0);
978 OUT_BCS_BATCH(batch, 0);
979 OUT_BCS_BATCH(batch, 0);
980 OUT_BCS_BATCH(batch, 0);
981 OUT_BCS_BATCH(batch, 0);
982 OUT_BCS_BATCH(batch, 0);
983 OUT_BCS_BATCH(batch, 0);
984 OUT_BCS_BATCH(batch, 0);
985 ADVANCE_BCS_BATCH(batch);
989 gen7_mfd_mpeg2_qm_state(VADriverContextP ctx,
990 struct decode_state *decode_state,
991 struct gen7_mfd_context *gen7_mfd_context)
993 VAIQMatrixBufferMPEG2 * const gen_iq_matrix = &gen7_mfd_context->iq_matrix.mpeg2;
996 /* Update internal QM state */
997 if (decode_state->iq_matrix && decode_state->iq_matrix->buffer) {
998 VAIQMatrixBufferMPEG2 * const iq_matrix =
999 (VAIQMatrixBufferMPEG2 *)decode_state->iq_matrix->buffer;
1001 if (gen_iq_matrix->load_intra_quantiser_matrix == -1 ||
1002 iq_matrix->load_intra_quantiser_matrix) {
1003 gen_iq_matrix->load_intra_quantiser_matrix =
1004 iq_matrix->load_intra_quantiser_matrix;
1005 if (iq_matrix->load_intra_quantiser_matrix) {
1006 for (j = 0; j < 64; j++)
1007 gen_iq_matrix->intra_quantiser_matrix[zigzag_direct[j]] =
1008 iq_matrix->intra_quantiser_matrix[j];
1012 if (gen_iq_matrix->load_non_intra_quantiser_matrix == -1 ||
1013 iq_matrix->load_non_intra_quantiser_matrix) {
1014 gen_iq_matrix->load_non_intra_quantiser_matrix =
1015 iq_matrix->load_non_intra_quantiser_matrix;
1016 if (iq_matrix->load_non_intra_quantiser_matrix) {
1017 for (j = 0; j < 64; j++)
1018 gen_iq_matrix->non_intra_quantiser_matrix[zigzag_direct[j]] =
1019 iq_matrix->non_intra_quantiser_matrix[j];
1024 /* Commit QM state to HW */
1025 for (i = 0; i < 2; i++) {
1026 unsigned char *qm = NULL;
1030 if (gen_iq_matrix->load_intra_quantiser_matrix) {
1031 qm = gen_iq_matrix->intra_quantiser_matrix;
1032 qm_type = MFX_QM_MPEG_INTRA_QUANTIZER_MATRIX;
1035 if (gen_iq_matrix->load_non_intra_quantiser_matrix) {
1036 qm = gen_iq_matrix->non_intra_quantiser_matrix;
1037 qm_type = MFX_QM_MPEG_NON_INTRA_QUANTIZER_MATRIX;
1044 gen7_mfd_qm_state(ctx, qm_type, qm, 64, gen7_mfd_context);
1048 uint32_t mpeg2_get_slice_data_length(dri_bo *slice_data_bo, VASliceParameterBufferMPEG2 *slice_param)
1051 uint32_t buf_offset = slice_param->slice_data_offset + (slice_param->macroblock_offset >> 3);
1052 uint32_t buf_size = slice_param->slice_data_size - (slice_param->macroblock_offset >> 3);
1055 dri_bo_map(slice_data_bo, 0);
1056 buf = (uint8_t *)slice_data_bo->virtual + buf_offset;
1061 while (i <= (buf_size - 4)) {
1062 if (buf[i + 2] > 1) {
1064 } else if (buf[i + 1]) {
1066 } else if (buf[i] || buf[i + 2] != 1) {
1073 if (i <= (buf_size - 4))
1076 dri_bo_unmap(slice_data_bo);
1081 gen7_mfd_mpeg2_bsd_object(VADriverContextP ctx,
1082 VAPictureParameterBufferMPEG2 *pic_param,
1083 VASliceParameterBufferMPEG2 *slice_param,
1084 dri_bo *slice_data_bo,
1085 VASliceParameterBufferMPEG2 *next_slice_param,
1086 struct gen7_mfd_context *gen7_mfd_context)
1088 struct i965_driver_data * const i965 = i965_driver_data(ctx);
1089 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1090 unsigned int width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16;
1091 int mb_count, vpos0, hpos0, vpos1, hpos1, is_field_pic_wa, is_field_pic = 0;
1093 if (pic_param->picture_coding_extension.bits.picture_structure == MPEG_TOP_FIELD ||
1094 pic_param->picture_coding_extension.bits.picture_structure == MPEG_BOTTOM_FIELD)
1096 is_field_pic_wa = is_field_pic &&
1097 gen7_mfd_context->wa_mpeg2_slice_vertical_position > 0;
1099 vpos0 = slice_param->slice_vertical_position / (1 + is_field_pic_wa);
1100 hpos0 = slice_param->slice_horizontal_position;
1102 if (next_slice_param == NULL) {
1103 vpos1 = ALIGN(pic_param->vertical_size, 16) / 16 / (1 + is_field_pic);
1106 vpos1 = next_slice_param->slice_vertical_position / (1 + is_field_pic_wa);
1107 hpos1 = next_slice_param->slice_horizontal_position;
1110 mb_count = (vpos1 * width_in_mbs + hpos1) - (vpos0 * width_in_mbs + hpos0);
1112 BEGIN_BCS_BATCH(batch, 5);
1113 OUT_BCS_BATCH(batch, MFD_MPEG2_BSD_OBJECT | (5 - 2));
1114 OUT_BCS_BATCH(batch,
1115 mpeg2_get_slice_data_length(slice_data_bo, slice_param));
1116 OUT_BCS_BATCH(batch,
1117 slice_param->slice_data_offset + (slice_param->macroblock_offset >> 3));
1118 OUT_BCS_BATCH(batch,
1122 (next_slice_param == NULL) << 5 |
1123 (next_slice_param == NULL) << 3 |
1124 (slice_param->macroblock_offset & 0x7));
1125 OUT_BCS_BATCH(batch,
1126 (slice_param->quantiser_scale_code << 24) |
1127 (IS_HASWELL(i965->intel.device_info) ? (vpos1 << 8 | hpos1) : 0));
1128 ADVANCE_BCS_BATCH(batch);
1132 gen7_mfd_mpeg2_decode_picture(VADriverContextP ctx,
1133 struct decode_state *decode_state,
1134 struct gen7_mfd_context *gen7_mfd_context)
1136 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1137 VAPictureParameterBufferMPEG2 *pic_param;
1138 VASliceParameterBufferMPEG2 *slice_param, *next_slice_param, *next_slice_group_param;
1139 dri_bo *slice_data_bo;
1142 assert(decode_state->pic_param && decode_state->pic_param->buffer);
1143 pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
1145 gen7_mfd_mpeg2_decode_init(ctx, decode_state, gen7_mfd_context);
1146 intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
1147 intel_batchbuffer_emit_mi_flush(batch);
1148 gen7_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1149 gen7_mfd_surface_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1150 gen7_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1151 gen7_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1152 gen7_mfd_mpeg2_pic_state(ctx, decode_state, gen7_mfd_context);
1153 gen7_mfd_mpeg2_qm_state(ctx, decode_state, gen7_mfd_context);
1155 if (gen7_mfd_context->wa_mpeg2_slice_vertical_position < 0)
1156 gen7_mfd_context->wa_mpeg2_slice_vertical_position =
1157 mpeg2_wa_slice_vertical_position(decode_state, pic_param);
1159 for (j = 0; j < decode_state->num_slice_params; j++) {
1160 assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
1161 slice_param = (VASliceParameterBufferMPEG2 *)decode_state->slice_params[j]->buffer;
1162 slice_data_bo = decode_state->slice_datas[j]->bo;
1163 gen7_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_MPEG2, gen7_mfd_context);
1165 if (j == decode_state->num_slice_params - 1)
1166 next_slice_group_param = NULL;
1168 next_slice_group_param = (VASliceParameterBufferMPEG2 *)decode_state->slice_params[j + 1]->buffer;
1170 for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
1171 assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
1173 if (i < decode_state->slice_params[j]->num_elements - 1)
1174 next_slice_param = slice_param + 1;
1176 next_slice_param = next_slice_group_param;
1178 gen7_mfd_mpeg2_bsd_object(ctx, pic_param, slice_param, slice_data_bo, next_slice_param, gen7_mfd_context);
1183 intel_batchbuffer_end_atomic(batch);
1184 intel_batchbuffer_flush(batch);
1187 static const int va_to_gen7_vc1_mv[4] = {
1189 2, /* 1-MV half-pel */
1190 3, /* 1-MV half-pef bilinear */
1194 static const int b_picture_scale_factor[21] = {
1195 128, 85, 170, 64, 192,
1196 51, 102, 153, 204, 43,
1197 215, 37, 74, 111, 148,
1198 185, 222, 32, 96, 160,
1202 static const int va_to_gen7_vc1_condover[3] = {
1208 static const int va_to_gen7_vc1_profile[4] = {
1209 GEN7_VC1_SIMPLE_PROFILE,
1210 GEN7_VC1_MAIN_PROFILE,
1211 GEN7_VC1_RESERVED_PROFILE,
1212 GEN7_VC1_ADVANCED_PROFILE
1216 gen7_mfd_free_vc1_surface(void **data)
1218 struct gen7_vc1_surface *gen7_vc1_surface = *data;
1220 if (!gen7_vc1_surface)
1223 dri_bo_unreference(gen7_vc1_surface->dmv);
1224 free(gen7_vc1_surface);
1229 gen7_mfd_init_vc1_surface(VADriverContextP ctx,
1230 VAPictureParameterBufferVC1 *pic_param,
1231 struct object_surface *obj_surface)
1233 struct i965_driver_data *i965 = i965_driver_data(ctx);
1234 struct gen7_vc1_surface *gen7_vc1_surface = obj_surface->private_data;
1235 int height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16;
1237 obj_surface->free_private_data = gen7_mfd_free_vc1_surface;
1239 if (!gen7_vc1_surface) {
1240 gen7_vc1_surface = calloc(sizeof(struct gen7_vc1_surface), 1);
1241 assert(gen7_vc1_surface);
1242 assert((obj_surface->size & 0x3f) == 0);
1243 obj_surface->private_data = gen7_vc1_surface;
1246 gen7_vc1_surface->picture_type = pic_param->picture_fields.bits.picture_type;
1247 gen7_vc1_surface->intensity_compensation = 0;
1248 gen7_vc1_surface->luma_scale = 0;
1249 gen7_vc1_surface->luma_shift = 0;
1251 if (gen7_vc1_surface->dmv == NULL) {
1252 gen7_vc1_surface->dmv = dri_bo_alloc(i965->intel.bufmgr,
1253 "direct mv w/r buffer",
1254 128 * height_in_mbs * 64,
1260 gen7_mfd_vc1_decode_init(VADriverContextP ctx,
1261 struct decode_state *decode_state,
1262 struct gen7_mfd_context *gen7_mfd_context)
1264 VAPictureParameterBufferVC1 *pic_param;
1265 struct i965_driver_data *i965 = i965_driver_data(ctx);
1266 struct object_surface *obj_surface;
1270 int intensity_compensation;
1272 assert(decode_state->pic_param && decode_state->pic_param->buffer);
1273 pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1274 width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1275 picture_type = pic_param->picture_fields.bits.picture_type;
1276 intensity_compensation = (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation);
1278 intel_update_vc1_frame_store_index(ctx,
1281 gen7_mfd_context->reference_surface);
1283 /* Forward reference picture */
1284 obj_surface = decode_state->reference_objects[0];
1285 if (pic_param->forward_reference_picture != VA_INVALID_ID &&
1287 obj_surface->private_data) {
1288 if (picture_type == 1 && intensity_compensation) { /* P picture */
1289 struct gen7_vc1_surface *gen7_vc1_surface = obj_surface->private_data;
1291 gen7_vc1_surface->intensity_compensation = intensity_compensation;
1292 gen7_vc1_surface->luma_scale = pic_param->luma_scale;
1293 gen7_vc1_surface->luma_shift = pic_param->luma_shift;
1297 /* Current decoded picture */
1298 obj_surface = decode_state->render_object;
1299 i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
1300 gen7_mfd_init_vc1_surface(ctx, pic_param, obj_surface);
1302 dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo);
1303 gen7_mfd_context->post_deblocking_output.bo = obj_surface->bo;
1304 dri_bo_reference(gen7_mfd_context->post_deblocking_output.bo);
1306 dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
1307 gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
1308 dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
1310 if (picture_type == GEN7_VC1_SKIPPED_PICTURE) {
1311 gen7_mfd_context->post_deblocking_output.valid = 0;
1312 gen7_mfd_context->pre_deblocking_output.valid = 1;
1314 gen7_mfd_context->post_deblocking_output.valid = pic_param->entrypoint_fields.bits.loopfilter;
1315 gen7_mfd_context->pre_deblocking_output.valid = !pic_param->entrypoint_fields.bits.loopfilter;
1318 dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo);
1319 bo = dri_bo_alloc(i965->intel.bufmgr,
1324 gen7_mfd_context->intra_row_store_scratch_buffer.bo = bo;
1325 gen7_mfd_context->intra_row_store_scratch_buffer.valid = 1;
1327 dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
1328 bo = dri_bo_alloc(i965->intel.bufmgr,
1329 "deblocking filter row store",
1330 width_in_mbs * 7 * 64,
1333 gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
1334 gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1;
1336 dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
1337 bo = dri_bo_alloc(i965->intel.bufmgr,
1338 "bsd mpc row store",
1342 gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
1343 gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
1345 gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
1347 if (picture_type == GEN7_VC1_SKIPPED_PICTURE)
1348 gen7_mfd_context->bitplane_read_buffer.valid = 1;
1350 gen7_mfd_context->bitplane_read_buffer.valid = !!(pic_param->bitplane_present.value & 0x7f);
1351 dri_bo_unreference(gen7_mfd_context->bitplane_read_buffer.bo);
1353 if (gen7_mfd_context->bitplane_read_buffer.valid) {
1354 int width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1355 int height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16;
1356 int bitplane_width = ALIGN(width_in_mbs, 2) / 2;
1358 uint8_t *src = NULL, *dst = NULL;
1360 bo = dri_bo_alloc(i965->intel.bufmgr,
1362 bitplane_width * height_in_mbs,
1365 gen7_mfd_context->bitplane_read_buffer.bo = bo;
1367 dri_bo_map(bo, True);
1368 assert(bo->virtual);
1371 if (picture_type == GEN7_VC1_SKIPPED_PICTURE) {
1372 for (src_h = 0; src_h < height_in_mbs; src_h++) {
1373 for (src_w = 0; src_w < width_in_mbs; src_w++) {
1375 uint8_t src_value = 0x2;
1377 dst_index = src_w / 2;
1378 dst[dst_index] = ((dst[dst_index] >> 4) | (src_value << 4));
1382 dst[src_w / 2] >>= 4;
1384 dst += bitplane_width;
1387 assert(decode_state->bit_plane->buffer);
1388 src = decode_state->bit_plane->buffer;
1390 for (src_h = 0; src_h < height_in_mbs; src_h++) {
1391 for (src_w = 0; src_w < width_in_mbs; src_w++) {
1392 int src_index, dst_index;
1396 src_index = (src_h * width_in_mbs + src_w) / 2;
1397 src_shift = !((src_h * width_in_mbs + src_w) & 1) * 4;
1398 src_value = ((src[src_index] >> src_shift) & 0xf);
1400 dst_index = src_w / 2;
1401 dst[dst_index] = ((dst[dst_index] >> 4) | (src_value << 4));
1405 dst[src_w / 2] >>= 4;
1407 dst += bitplane_width;
1413 gen7_mfd_context->bitplane_read_buffer.bo = NULL;
1417 gen7_mfd_vc1_pic_state(VADriverContextP ctx,
1418 struct decode_state *decode_state,
1419 struct gen7_mfd_context *gen7_mfd_context)
1421 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1422 VAPictureParameterBufferVC1 *pic_param;
1423 struct object_surface *obj_surface;
1424 int alt_pquant_config = 0, alt_pquant_edge_mask = 0, alt_pq;
1425 int dquant, dquantfrm, dqprofile, dqdbedge, dqsbedge, dqbilevel;
1426 int unified_mv_mode;
1427 int ref_field_pic_polarity = 0;
1428 int scale_factor = 0;
1430 int dmv_surface_valid = 0;
1437 int interpolation_mode = 0;
1439 int bitplane_present;
1440 int forward_mb = 0, mv_type_mb = 0, skip_mb = 0, direct_mb = 0;
1441 int overflags = 0, ac_pred = 0, field_tx = 0;
1443 assert(decode_state->pic_param && decode_state->pic_param->buffer);
1444 pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1446 picture_type = pic_param->picture_fields.bits.picture_type;
1448 profile = va_to_gen7_vc1_profile[pic_param->sequence_fields.bits.profile];
1449 dquant = pic_param->pic_quantizer_fields.bits.dquant;
1450 dquantfrm = pic_param->pic_quantizer_fields.bits.dq_frame;
1451 dqprofile = pic_param->pic_quantizer_fields.bits.dq_profile;
1452 dqdbedge = pic_param->pic_quantizer_fields.bits.dq_db_edge;
1453 dqsbedge = pic_param->pic_quantizer_fields.bits.dq_sb_edge;
1454 dqbilevel = pic_param->pic_quantizer_fields.bits.dq_binary_level;
1455 alt_pq = pic_param->pic_quantizer_fields.bits.alt_pic_quantizer;
1458 alt_pquant_config = 0;
1459 alt_pquant_edge_mask = 0;
1460 } else if (dquant == 2) {
1461 alt_pquant_config = 1;
1462 alt_pquant_edge_mask = 0xf;
1464 assert(dquant == 1);
1465 if (dquantfrm == 0) {
1466 alt_pquant_config = 0;
1467 alt_pquant_edge_mask = 0;
1470 assert(dquantfrm == 1);
1471 alt_pquant_config = 1;
1473 switch (dqprofile) {
1475 if (dqbilevel == 0) {
1476 alt_pquant_config = 2;
1477 alt_pquant_edge_mask = 0;
1479 assert(dqbilevel == 1);
1480 alt_pquant_config = 3;
1481 alt_pquant_edge_mask = 0;
1486 alt_pquant_edge_mask = 0xf;
1491 alt_pquant_edge_mask = 0x9;
1493 alt_pquant_edge_mask = (0x3 << dqdbedge);
1498 alt_pquant_edge_mask = (0x1 << dqsbedge);
1507 if (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation) {
1508 assert(pic_param->mv_fields.bits.mv_mode2 < 4);
1509 unified_mv_mode = va_to_gen7_vc1_mv[pic_param->mv_fields.bits.mv_mode2];
1511 assert(pic_param->mv_fields.bits.mv_mode < 4);
1512 unified_mv_mode = va_to_gen7_vc1_mv[pic_param->mv_fields.bits.mv_mode];
1515 if (pic_param->sequence_fields.bits.interlace == 1 &&
1516 pic_param->picture_fields.bits.frame_coding_mode != 0) { /* frame-interlace or field-interlace */
1517 /* FIXME: calculate reference field picture polarity */
1519 ref_field_pic_polarity = 0;
1522 if (pic_param->b_picture_fraction < 21)
1523 scale_factor = b_picture_scale_factor[pic_param->b_picture_fraction];
1525 if (picture_type == GEN7_VC1_SKIPPED_PICTURE) {
1526 ptype = GEN7_VC1_P_PICTURE;
1527 bitplane_present = 1;
1529 ptype = pic_param->picture_fields.bits.picture_type;
1530 bitplane_present = !!(pic_param->bitplane_present.value & 0x7f);
1531 forward_mb = pic_param->raw_coding.flags.forward_mb;
1532 mv_type_mb = pic_param->raw_coding.flags.mv_type_mb;
1533 skip_mb = pic_param->raw_coding.flags.skip_mb;
1534 direct_mb = pic_param->raw_coding.flags.direct_mb;
1535 overflags = pic_param->raw_coding.flags.overflags;
1536 ac_pred = pic_param->raw_coding.flags.ac_pred;
1537 field_tx = pic_param->raw_coding.flags.field_tx;
1538 loopfilter = pic_param->entrypoint_fields.bits.loopfilter;
1541 if (picture_type == GEN7_VC1_I_PICTURE || picture_type == GEN7_VC1_BI_PICTURE) /* I picture */
1542 trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx2;
1544 trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx1;
1546 * 8.3.6.2.1 Transform Type Selection
1547 * If variable-sized transform coding is not enabled,
1548 * then the 8x8 transform shall be used for all blocks.
1549 * it is also MFX_VC1_PIC_STATE requirement.
1551 if (pic_param->transform_fields.bits.variable_sized_transform_flag == 0) {
1552 pic_param->transform_fields.bits.mb_level_transform_type_flag = 1;
1553 pic_param->transform_fields.bits.frame_level_transform_type = 0;
1557 if (picture_type == GEN7_VC1_B_PICTURE) {
1558 struct gen7_vc1_surface *gen7_vc1_surface = NULL;
1560 obj_surface = decode_state->reference_objects[1];
1563 gen7_vc1_surface = obj_surface->private_data;
1565 if (gen7_vc1_surface &&
1566 gen7_vc1_surface->picture_type == GEN7_VC1_P_PICTURE)
1567 dmv_surface_valid = 1;
1570 assert(pic_param->picture_fields.bits.frame_coding_mode < 3);
1572 if (pic_param->picture_fields.bits.frame_coding_mode < 2)
1573 fcm = pic_param->picture_fields.bits.frame_coding_mode;
1575 if (pic_param->picture_fields.bits.top_field_first)
1581 if (picture_type == GEN7_VC1_B_PICTURE) { /* B picture */
1582 brfd = pic_param->reference_fields.bits.reference_distance;
1583 brfd = (scale_factor * brfd) >> 8;
1584 brfd = pic_param->reference_fields.bits.reference_distance - brfd - 1;
1590 if (pic_param->sequence_fields.bits.overlap) {
1591 if (profile == GEN7_VC1_ADVANCED_PROFILE) {
1592 if (picture_type == GEN7_VC1_P_PICTURE &&
1593 pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9) {
1596 if (picture_type == GEN7_VC1_I_PICTURE ||
1597 picture_type == GEN7_VC1_BI_PICTURE) {
1598 if (pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9) {
1600 } else if (pic_param->conditional_overlap_flag == 1 || /* all block boundaries */
1601 pic_param->conditional_overlap_flag == 2) { /* coded by OVERFLAGSMB bitplane */
1606 if (pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9 &&
1607 picture_type != GEN7_VC1_B_PICTURE) {
1613 assert(pic_param->conditional_overlap_flag < 3);
1614 assert(pic_param->mv_fields.bits.mv_table < 4); /* FIXME: interlace mode */
1616 if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPelBilinear ||
1617 (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation &&
1618 pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPelBilinear))
1619 interpolation_mode = 9; /* Half-pel bilinear */
1620 else if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPel ||
1621 (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation &&
1622 pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPel))
1623 interpolation_mode = 1; /* Half-pel bicubic */
1625 interpolation_mode = 0; /* Quarter-pel bicubic */
1627 BEGIN_BCS_BATCH(batch, 6);
1628 OUT_BCS_BATCH(batch, MFD_VC1_LONG_PIC_STATE | (6 - 2));
1629 OUT_BCS_BATCH(batch,
1630 (((ALIGN(pic_param->coded_height, 16) / 16) - 1) << 16) |
1631 ((ALIGN(pic_param->coded_width, 16) / 16) - 1));
1632 OUT_BCS_BATCH(batch,
1633 ((ALIGN(pic_param->coded_width, 16) / 16 + 1) / 2 - 1) << 24 |
1634 dmv_surface_valid << 15 |
1635 (pic_param->pic_quantizer_fields.bits.quantizer == 0) << 14 | /* implicit quantizer */
1636 pic_param->rounding_control << 13 |
1637 pic_param->sequence_fields.bits.syncmarker << 12 |
1638 interpolation_mode << 8 |
1639 0 << 7 | /* FIXME: scale up or down ??? */
1640 pic_param->range_reduction_frame << 6 |
1643 !pic_param->picture_fields.bits.is_first_field << 3 |
1644 (pic_param->sequence_fields.bits.profile == 3) << 0);
1645 OUT_BCS_BATCH(batch,
1646 va_to_gen7_vc1_condover[pic_param->conditional_overlap_flag] << 29 |
1650 pic_param->pic_quantizer_fields.bits.pic_quantizer_scale << 8 |
1652 OUT_BCS_BATCH(batch,
1653 unified_mv_mode << 28 |
1654 pic_param->mv_fields.bits.four_mv_switch << 27 |
1655 pic_param->fast_uvmc_flag << 26 |
1656 ref_field_pic_polarity << 25 |
1657 pic_param->reference_fields.bits.num_reference_pictures << 24 |
1658 pic_param->reference_fields.bits.reference_distance << 20 |
1659 pic_param->reference_fields.bits.reference_distance << 16 | /* FIXME: ??? */
1660 pic_param->mv_fields.bits.extended_dmv_range << 10 |
1661 pic_param->mv_fields.bits.extended_mv_range << 8 |
1662 alt_pquant_edge_mask << 4 |
1663 alt_pquant_config << 2 |
1664 pic_param->pic_quantizer_fields.bits.half_qp << 1 |
1665 pic_param->pic_quantizer_fields.bits.pic_quantizer_type << 0);
1666 OUT_BCS_BATCH(batch,
1667 bitplane_present << 31 |
1675 pic_param->mv_fields.bits.mv_table << 20 |
1676 pic_param->mv_fields.bits.four_mv_block_pattern_table << 18 |
1677 pic_param->mv_fields.bits.two_mv_block_pattern_table << 16 |
1678 pic_param->transform_fields.bits.frame_level_transform_type << 12 |
1679 pic_param->transform_fields.bits.mb_level_transform_type_flag << 11 |
1680 pic_param->mb_mode_table << 8 |
1682 pic_param->transform_fields.bits.transform_ac_codingset_idx1 << 4 |
1683 pic_param->transform_fields.bits.intra_transform_dc_table << 3 |
1684 pic_param->cbp_table << 0);
1685 ADVANCE_BCS_BATCH(batch);
1689 gen7_mfd_vc1_pred_pipe_state(VADriverContextP ctx,
1690 struct decode_state *decode_state,
1691 struct gen7_mfd_context *gen7_mfd_context)
1693 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1694 VAPictureParameterBufferVC1 *pic_param;
1696 int intensitycomp_single_fwd = 0;
1697 int luma_scale1 = 0;
1698 int luma_shift1 = 0;
1700 assert(decode_state->pic_param && decode_state->pic_param->buffer);
1701 pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1702 picture_type = pic_param->picture_fields.bits.picture_type;
1704 if (gen7_mfd_context->reference_surface[0].surface_id != VA_INVALID_ID) {
1705 if (picture_type == 1 || picture_type == 2) { /* P/B picture */
1706 struct gen7_vc1_surface *gen7_vc1_surface = gen7_mfd_context->reference_surface[0].obj_surface->private_data;
1707 if (gen7_vc1_surface) {
1708 intensitycomp_single_fwd = gen7_vc1_surface->intensity_compensation;
1709 luma_scale1 = gen7_vc1_surface->luma_scale;
1710 luma_shift1 = gen7_vc1_surface->luma_shift;
1715 BEGIN_BCS_BATCH(batch, 6);
1716 OUT_BCS_BATCH(batch, MFX_VC1_PRED_PIPE_STATE | (6 - 2));
1717 OUT_BCS_BATCH(batch,
1718 0 << 14 | /* FIXME: double ??? */
1720 intensitycomp_single_fwd << 10 |
1722 0 << 4 | /* FIXME: interlace mode */
1724 OUT_BCS_BATCH(batch,
1727 OUT_BCS_BATCH(batch, 0);
1728 OUT_BCS_BATCH(batch, 0);
1729 OUT_BCS_BATCH(batch, 0);
1730 ADVANCE_BCS_BATCH(batch);
1735 gen7_mfd_vc1_directmode_state(VADriverContextP ctx,
1736 struct decode_state *decode_state,
1737 struct gen7_mfd_context *gen7_mfd_context)
1739 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1740 VAPictureParameterBufferVC1 *pic_param;
1741 struct object_surface *obj_surface;
1742 dri_bo *dmv_read_buffer = NULL, *dmv_write_buffer = NULL;
1745 pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1746 picture_type = pic_param->picture_fields.bits.picture_type;
1748 if (picture_type == GEN7_VC1_P_PICTURE ||
1749 picture_type == GEN7_VC1_SKIPPED_PICTURE) {
1750 obj_surface = decode_state->render_object;
1751 dmv_write_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv;
1754 if (picture_type == GEN7_VC1_B_PICTURE) {
1755 obj_surface = decode_state->reference_objects[1];
1756 if (pic_param->backward_reference_picture != VA_INVALID_ID &&
1758 dmv_read_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv;
1762 BEGIN_BCS_BATCH(batch, 3);
1763 OUT_BCS_BATCH(batch, MFX_VC1_DIRECTMODE_STATE | (3 - 2));
1765 if (dmv_write_buffer)
1766 OUT_BCS_RELOC(batch, dmv_write_buffer,
1767 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
1770 OUT_BCS_BATCH(batch, 0);
1772 if (dmv_read_buffer)
1773 OUT_BCS_RELOC(batch, dmv_read_buffer,
1774 I915_GEM_DOMAIN_INSTRUCTION, 0,
1777 OUT_BCS_BATCH(batch, 0);
1779 ADVANCE_BCS_BATCH(batch);
1783 gen7_mfd_vc1_get_macroblock_bit_offset(uint8_t *buf, int in_slice_data_bit_offset, int profile)
1785 int out_slice_data_bit_offset;
1786 int slice_header_size = in_slice_data_bit_offset / 8;
1790 out_slice_data_bit_offset = in_slice_data_bit_offset;
1792 for (i = 0, j = 0; i < slice_header_size; i++, j++) {
1793 if (!buf[j] && !buf[j + 1] && buf[j + 2] == 3 && buf[j + 3] < 4) {
1794 if (i < slice_header_size - 1)
1797 buf[j + 2] = buf[j + 1];
1803 out_slice_data_bit_offset = 8 * j + in_slice_data_bit_offset % 8;
1806 return out_slice_data_bit_offset;
1810 gen7_mfd_vc1_bsd_object(VADriverContextP ctx,
1811 VAPictureParameterBufferVC1 *pic_param,
1812 VASliceParameterBufferVC1 *slice_param,
1813 VASliceParameterBufferVC1 *next_slice_param,
1814 dri_bo *slice_data_bo,
1815 struct gen7_mfd_context *gen7_mfd_context)
1817 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1818 int next_slice_start_vert_pos;
1819 int macroblock_offset;
1820 uint8_t *slice_data = NULL;
1822 dri_bo_map(slice_data_bo, True);
1823 slice_data = (uint8_t *)(slice_data_bo->virtual + slice_param->slice_data_offset);
1824 macroblock_offset = gen7_mfd_vc1_get_macroblock_bit_offset(slice_data,
1825 slice_param->macroblock_offset,
1826 pic_param->sequence_fields.bits.profile);
1827 dri_bo_unmap(slice_data_bo);
1829 if (next_slice_param)
1830 next_slice_start_vert_pos = next_slice_param->slice_vertical_position;
1832 next_slice_start_vert_pos = ALIGN(pic_param->coded_height, 16) / 16;
1834 BEGIN_BCS_BATCH(batch, 5);
1835 OUT_BCS_BATCH(batch, MFD_VC1_BSD_OBJECT | (5 - 2));
1836 OUT_BCS_BATCH(batch,
1837 slice_param->slice_data_size - (macroblock_offset >> 3));
1838 OUT_BCS_BATCH(batch,
1839 slice_param->slice_data_offset + (macroblock_offset >> 3));
1840 OUT_BCS_BATCH(batch,
1841 slice_param->slice_vertical_position << 16 |
1842 next_slice_start_vert_pos << 0);
1843 OUT_BCS_BATCH(batch,
1844 (macroblock_offset & 0x7));
1845 ADVANCE_BCS_BATCH(batch);
1849 gen7_mfd_vc1_decode_picture(VADriverContextP ctx,
1850 struct decode_state *decode_state,
1851 struct gen7_mfd_context *gen7_mfd_context)
1853 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1854 VAPictureParameterBufferVC1 *pic_param;
1855 VASliceParameterBufferVC1 *slice_param, *next_slice_param, *next_slice_group_param;
1856 dri_bo *slice_data_bo;
1859 assert(decode_state->pic_param && decode_state->pic_param->buffer);
1860 pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1862 gen7_mfd_vc1_decode_init(ctx, decode_state, gen7_mfd_context);
1863 intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
1864 intel_batchbuffer_emit_mi_flush(batch);
1865 gen7_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
1866 gen7_mfd_surface_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
1867 gen7_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
1868 gen7_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
1869 gen7_mfd_vc1_pic_state(ctx, decode_state, gen7_mfd_context);
1870 gen7_mfd_vc1_pred_pipe_state(ctx, decode_state, gen7_mfd_context);
1871 gen7_mfd_vc1_directmode_state(ctx, decode_state, gen7_mfd_context);
1873 for (j = 0; j < decode_state->num_slice_params; j++) {
1874 assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
1875 slice_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j]->buffer;
1876 slice_data_bo = decode_state->slice_datas[j]->bo;
1877 gen7_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_VC1, gen7_mfd_context);
1879 if (j == decode_state->num_slice_params - 1)
1880 next_slice_group_param = NULL;
1882 next_slice_group_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j + 1]->buffer;
1884 for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
1885 assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
1887 if (i < decode_state->slice_params[j]->num_elements - 1)
1888 next_slice_param = slice_param + 1;
1890 next_slice_param = next_slice_group_param;
1892 gen7_mfd_vc1_bsd_object(ctx, pic_param, slice_param, next_slice_param, slice_data_bo, gen7_mfd_context);
1897 intel_batchbuffer_end_atomic(batch);
1898 intel_batchbuffer_flush(batch);
1902 gen7_mfd_jpeg_decode_init(VADriverContextP ctx,
1903 struct decode_state *decode_state,
1904 struct gen7_mfd_context *gen7_mfd_context)
1906 struct object_surface *obj_surface;
1907 VAPictureParameterBufferJPEGBaseline *pic_param;
1908 int subsampling = SUBSAMPLE_YUV420;
1909 int fourcc = VA_FOURCC_IMC3;
1911 pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
1913 if (pic_param->num_components == 1) {
1914 subsampling = SUBSAMPLE_YUV400;
1915 fourcc = VA_FOURCC_Y800;
1916 } else if (pic_param->num_components == 3) {
1917 int h1 = pic_param->components[0].h_sampling_factor;
1918 int h2 = pic_param->components[1].h_sampling_factor;
1919 int h3 = pic_param->components[2].h_sampling_factor;
1920 int v1 = pic_param->components[0].v_sampling_factor;
1921 int v2 = pic_param->components[1].v_sampling_factor;
1922 int v3 = pic_param->components[2].v_sampling_factor;
1924 if (h1 == 2 * h2 && h2 == h3 &&
1925 v1 == 2 * v2 && v2 == v3) {
1926 subsampling = SUBSAMPLE_YUV420;
1927 fourcc = VA_FOURCC_IMC3;
1928 } else if (h1 == 2 * h2 && h2 == h3 &&
1929 v1 == v2 && v2 == v3) {
1930 subsampling = SUBSAMPLE_YUV422H;
1931 fourcc = VA_FOURCC_422H;
1932 } else if (h1 == h2 && h2 == h3 &&
1933 v1 == v2 && v2 == v3) {
1934 subsampling = SUBSAMPLE_YUV444;
1935 fourcc = VA_FOURCC_444P;
1936 } else if (h1 == 4 * h2 && h2 == h3 &&
1937 v1 == v2 && v2 == v3) {
1938 subsampling = SUBSAMPLE_YUV411;
1939 fourcc = VA_FOURCC_411P;
1940 } else if (h1 == h2 && h2 == h3 &&
1941 v1 == 2 * v2 && v2 == v3) {
1942 subsampling = SUBSAMPLE_YUV422V;
1943 fourcc = VA_FOURCC_422V;
1950 /* Current decoded picture */
1951 obj_surface = decode_state->render_object;
1952 i965_check_alloc_surface_bo(ctx, obj_surface, 1, fourcc, subsampling);
1954 dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
1955 gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
1956 dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
1957 gen7_mfd_context->pre_deblocking_output.valid = 1;
1959 gen7_mfd_context->post_deblocking_output.bo = NULL;
1960 gen7_mfd_context->post_deblocking_output.valid = 0;
1962 gen7_mfd_context->intra_row_store_scratch_buffer.bo = NULL;
1963 gen7_mfd_context->intra_row_store_scratch_buffer.valid = 0;
1965 gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
1966 gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 0;
1968 gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
1969 gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 0;
1971 gen7_mfd_context->mpr_row_store_scratch_buffer.bo = NULL;
1972 gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
1974 gen7_mfd_context->bitplane_read_buffer.bo = NULL;
1975 gen7_mfd_context->bitplane_read_buffer.valid = 0;
1978 static const int va_to_gen7_jpeg_rotation[4] = {
1979 GEN7_JPEG_ROTATION_0,
1980 GEN7_JPEG_ROTATION_90,
1981 GEN7_JPEG_ROTATION_180,
1982 GEN7_JPEG_ROTATION_270
1986 gen7_mfd_jpeg_pic_state(VADriverContextP ctx,
1987 struct decode_state *decode_state,
1988 struct gen7_mfd_context *gen7_mfd_context)
1990 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1991 VAPictureParameterBufferJPEGBaseline *pic_param;
1992 int chroma_type = GEN7_YUV420;
1993 int frame_width_in_blks;
1994 int frame_height_in_blks;
1996 assert(decode_state->pic_param && decode_state->pic_param->buffer);
1997 pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
1999 if (pic_param->num_components == 1)
2000 chroma_type = GEN7_YUV400;
2001 else if (pic_param->num_components == 3) {
2002 int h1 = pic_param->components[0].h_sampling_factor;
2003 int h2 = pic_param->components[1].h_sampling_factor;
2004 int h3 = pic_param->components[2].h_sampling_factor;
2005 int v1 = pic_param->components[0].v_sampling_factor;
2006 int v2 = pic_param->components[1].v_sampling_factor;
2007 int v3 = pic_param->components[2].v_sampling_factor;
2009 if (h1 == 2 * h2 && h2 == h3 &&
2010 v1 == 2 * v2 && v2 == v3)
2011 chroma_type = GEN7_YUV420;
2012 else if (h1 == 2 && h2 == 1 && h3 == 1 &&
2013 v1 == 1 && v2 == 1 && v3 == 1)
2014 chroma_type = GEN7_YUV422H_2Y;
2015 else if (h1 == h2 && h2 == h3 &&
2016 v1 == v2 && v2 == v3)
2017 chroma_type = GEN7_YUV444;
2018 else if (h1 == 4 * h2 && h2 == h3 &&
2019 v1 == v2 && v2 == v3)
2020 chroma_type = GEN7_YUV411;
2021 else if (h1 == 1 && h2 == 1 && h3 == 1 &&
2022 v1 == 2 && v2 == 1 && v3 == 1)
2023 chroma_type = GEN7_YUV422V_2Y;
2024 else if (h1 == 2 && h2 == 1 && h3 == 1 &&
2025 v1 == 2 && v2 == 2 && v3 == 2)
2026 chroma_type = GEN7_YUV422H_4Y;
2027 else if (h2 == 2 && h2 == 2 && h3 == 2 &&
2028 v1 == 2 && v2 == 1 && v3 == 1)
2029 chroma_type = GEN7_YUV422V_4Y;
2034 if (chroma_type == GEN7_YUV400 ||
2035 chroma_type == GEN7_YUV444 ||
2036 chroma_type == GEN7_YUV422V_2Y) {
2037 frame_width_in_blks = ((pic_param->picture_width + 7) / 8);
2038 frame_height_in_blks = ((pic_param->picture_height + 7) / 8);
2039 } else if (chroma_type == GEN7_YUV411) {
2040 frame_width_in_blks = ((pic_param->picture_width + 31) / 32) * 4;
2041 frame_height_in_blks = ((pic_param->picture_height + 31) / 32) * 4;
2043 frame_width_in_blks = ((pic_param->picture_width + 15) / 16) * 2;
2044 frame_height_in_blks = ((pic_param->picture_height + 15) / 16) * 2;
2047 BEGIN_BCS_BATCH(batch, 3);
2048 OUT_BCS_BATCH(batch, MFX_JPEG_PIC_STATE | (3 - 2));
2049 OUT_BCS_BATCH(batch,
2050 (va_to_gen7_jpeg_rotation[0] << 4) | /* without rotation */
2051 (chroma_type << 0));
2052 OUT_BCS_BATCH(batch,
2053 ((frame_height_in_blks - 1) << 16) | /* FrameHeightInBlks */
2054 ((frame_width_in_blks - 1) << 0)); /* FrameWidthInBlks */
2055 ADVANCE_BCS_BATCH(batch);
2058 static const int va_to_gen7_jpeg_hufftable[2] = {
2064 gen7_mfd_jpeg_huff_table_state(VADriverContextP ctx,
2065 struct decode_state *decode_state,
2066 struct gen7_mfd_context *gen7_mfd_context,
2069 VAHuffmanTableBufferJPEGBaseline *huffman_table;
2070 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2073 if (!decode_state->huffman_table || !decode_state->huffman_table->buffer)
2076 huffman_table = (VAHuffmanTableBufferJPEGBaseline *)decode_state->huffman_table->buffer;
2078 for (index = 0; index < num_tables; index++) {
2079 int id = va_to_gen7_jpeg_hufftable[index];
2080 if (!huffman_table->load_huffman_table[index])
2082 BEGIN_BCS_BATCH(batch, 53);
2083 OUT_BCS_BATCH(batch, MFX_JPEG_HUFF_TABLE_STATE | (53 - 2));
2084 OUT_BCS_BATCH(batch, id);
2085 intel_batchbuffer_data(batch, huffman_table->huffman_table[index].num_dc_codes, 12);
2086 intel_batchbuffer_data(batch, huffman_table->huffman_table[index].dc_values, 12);
2087 intel_batchbuffer_data(batch, huffman_table->huffman_table[index].num_ac_codes, 16);
2088 intel_batchbuffer_data(batch, huffman_table->huffman_table[index].ac_values, 164);
2089 ADVANCE_BCS_BATCH(batch);
2093 static const int va_to_gen7_jpeg_qm[5] = {
2095 MFX_QM_JPEG_LUMA_Y_QUANTIZER_MATRIX,
2096 MFX_QM_JPEG_CHROMA_CB_QUANTIZER_MATRIX,
2097 MFX_QM_JPEG_CHROMA_CR_QUANTIZER_MATRIX,
2098 MFX_QM_JPEG_ALPHA_QUANTIZER_MATRIX
2102 gen7_mfd_jpeg_qm_state(VADriverContextP ctx,
2103 struct decode_state *decode_state,
2104 struct gen7_mfd_context *gen7_mfd_context)
2106 VAPictureParameterBufferJPEGBaseline *pic_param;
2107 VAIQMatrixBufferJPEGBaseline *iq_matrix;
2110 if (!decode_state->iq_matrix || !decode_state->iq_matrix->buffer)
2113 iq_matrix = (VAIQMatrixBufferJPEGBaseline *)decode_state->iq_matrix->buffer;
2114 pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
2116 assert(pic_param->num_components <= 3);
2118 for (index = 0; index < pic_param->num_components; index++) {
2119 int id = pic_param->components[index].component_id - pic_param->components[0].component_id + 1;
2121 unsigned char *qm = iq_matrix->quantiser_table[pic_param->components[index].quantiser_table_selector];
2122 unsigned char raster_qm[64];
2125 if (id > 4 || id < 1)
2128 if (!iq_matrix->load_quantiser_table[pic_param->components[index].quantiser_table_selector])
2131 qm_type = va_to_gen7_jpeg_qm[id];
2133 for (j = 0; j < 64; j++)
2134 raster_qm[zigzag_direct[j]] = qm[j];
2136 gen7_mfd_qm_state(ctx, qm_type, raster_qm, 64, gen7_mfd_context);
2141 gen7_mfd_jpeg_bsd_object(VADriverContextP ctx,
2142 VAPictureParameterBufferJPEGBaseline *pic_param,
2143 VASliceParameterBufferJPEGBaseline *slice_param,
2144 VASliceParameterBufferJPEGBaseline *next_slice_param,
2145 dri_bo *slice_data_bo,
2146 struct gen7_mfd_context *gen7_mfd_context)
2148 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2149 int scan_component_mask = 0;
2152 assert(slice_param->num_components > 0);
2153 assert(slice_param->num_components < 4);
2154 assert(slice_param->num_components <= pic_param->num_components);
2156 for (i = 0; i < slice_param->num_components; i++) {
2157 switch (slice_param->components[i].component_selector - pic_param->components[0].component_id + 1) {
2159 scan_component_mask |= (1 << 0);
2162 scan_component_mask |= (1 << 1);
2165 scan_component_mask |= (1 << 2);
2173 BEGIN_BCS_BATCH(batch, 6);
2174 OUT_BCS_BATCH(batch, MFD_JPEG_BSD_OBJECT | (6 - 2));
2175 OUT_BCS_BATCH(batch,
2176 slice_param->slice_data_size);
2177 OUT_BCS_BATCH(batch,
2178 slice_param->slice_data_offset);
2179 OUT_BCS_BATCH(batch,
2180 slice_param->slice_horizontal_position << 16 |
2181 slice_param->slice_vertical_position << 0);
2182 OUT_BCS_BATCH(batch,
2183 ((slice_param->num_components != 1) << 30) | /* interleaved */
2184 (scan_component_mask << 27) | /* scan components */
2185 (0 << 26) | /* disable interrupt allowed */
2186 (slice_param->num_mcus << 0)); /* MCU count */
2187 OUT_BCS_BATCH(batch,
2188 (slice_param->restart_interval << 0)); /* RestartInterval */
2189 ADVANCE_BCS_BATCH(batch);
2192 /* Workaround for JPEG decoding on Ivybridge */
2197 unsigned char data[32];
2199 int data_bit_offset;
2201 } gen7_jpeg_wa_clip = {
2205 0x65, 0xb8, 0x40, 0x32, 0x13, 0xfd, 0x06, 0x6c,
2206 0xfc, 0x0a, 0x50, 0x71, 0x5c, 0x00
2214 gen7_jpeg_wa_init(VADriverContextP ctx,
2215 struct gen7_mfd_context *gen7_mfd_context)
2217 struct i965_driver_data *i965 = i965_driver_data(ctx);
2219 struct object_surface *obj_surface;
2221 if (gen7_mfd_context->jpeg_wa_surface_id != VA_INVALID_SURFACE)
2222 i965_DestroySurfaces(ctx,
2223 &gen7_mfd_context->jpeg_wa_surface_id,
2226 status = i965_CreateSurfaces(ctx,
2227 gen7_jpeg_wa_clip.width,
2228 gen7_jpeg_wa_clip.height,
2229 VA_RT_FORMAT_YUV420,
2231 &gen7_mfd_context->jpeg_wa_surface_id);
2232 assert(status == VA_STATUS_SUCCESS);
2234 obj_surface = SURFACE(gen7_mfd_context->jpeg_wa_surface_id);
2235 assert(obj_surface);
2236 i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
2237 gen7_mfd_context->jpeg_wa_surface_object = obj_surface;
2239 if (!gen7_mfd_context->jpeg_wa_slice_data_bo) {
2240 gen7_mfd_context->jpeg_wa_slice_data_bo = dri_bo_alloc(i965->intel.bufmgr,
2244 dri_bo_subdata(gen7_mfd_context->jpeg_wa_slice_data_bo,
2246 gen7_jpeg_wa_clip.data_size,
2247 gen7_jpeg_wa_clip.data);
2252 gen7_jpeg_wa_pipe_mode_select(VADriverContextP ctx,
2253 struct gen7_mfd_context *gen7_mfd_context)
2255 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2257 BEGIN_BCS_BATCH(batch, 5);
2258 OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2));
2259 OUT_BCS_BATCH(batch,
2260 (MFX_LONG_MODE << 17) | /* Currently only support long format */
2261 (MFD_MODE_VLD << 15) | /* VLD mode */
2262 (0 << 10) | /* disable Stream-Out */
2263 (0 << 9) | /* Post Deblocking Output */
2264 (1 << 8) | /* Pre Deblocking Output */
2265 (0 << 5) | /* not in stitch mode */
2266 (MFX_CODEC_DECODE << 4) | /* decoding mode */
2267 (MFX_FORMAT_AVC << 0));
2268 OUT_BCS_BATCH(batch,
2269 (0 << 4) | /* terminate if AVC motion and POC table error occurs */
2270 (0 << 3) | /* terminate if AVC mbdata error occurs */
2271 (0 << 2) | /* terminate if AVC CABAC/CAVLC decode error occurs */
2274 OUT_BCS_BATCH(batch, 0); /* pic status/error report id */
2275 OUT_BCS_BATCH(batch, 0); /* reserved */
2276 ADVANCE_BCS_BATCH(batch);
2280 gen7_jpeg_wa_surface_state(VADriverContextP ctx,
2281 struct gen7_mfd_context *gen7_mfd_context)
2283 struct object_surface *obj_surface = gen7_mfd_context->jpeg_wa_surface_object;
2284 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2286 BEGIN_BCS_BATCH(batch, 6);
2287 OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
2288 OUT_BCS_BATCH(batch, 0);
2289 OUT_BCS_BATCH(batch,
2290 ((obj_surface->orig_width - 1) << 18) |
2291 ((obj_surface->orig_height - 1) << 4));
2292 OUT_BCS_BATCH(batch,
2293 (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
2294 (1 << 27) | /* interleave chroma, set to 0 for JPEG */
2295 (0 << 22) | /* surface object control state, ignored */
2296 ((obj_surface->width - 1) << 3) | /* pitch */
2297 (0 << 2) | /* must be 0 */
2298 (1 << 1) | /* must be tiled */
2299 (I965_TILEWALK_YMAJOR << 0)); /* tile walk, must be 1 */
2300 OUT_BCS_BATCH(batch,
2301 (0 << 16) | /* X offset for U(Cb), must be 0 */
2302 (obj_surface->y_cb_offset << 0)); /* Y offset for U(Cb) */
2303 OUT_BCS_BATCH(batch,
2304 (0 << 16) | /* X offset for V(Cr), must be 0 */
2305 (0 << 0)); /* Y offset for V(Cr), must be 0 for video codec, non-zoro for JPEG */
2306 ADVANCE_BCS_BATCH(batch);
2310 gen7_jpeg_wa_pipe_buf_addr_state(VADriverContextP ctx,
2311 struct gen7_mfd_context *gen7_mfd_context)
2313 struct i965_driver_data *i965 = i965_driver_data(ctx);
2314 struct object_surface *obj_surface = gen7_mfd_context->jpeg_wa_surface_object;
2315 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2319 intra_bo = dri_bo_alloc(i965->intel.bufmgr,
2324 BEGIN_BCS_BATCH(batch, 24);
2325 OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
2326 OUT_BCS_RELOC(batch,
2328 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2331 OUT_BCS_BATCH(batch, 0); /* post deblocking */
2333 OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
2334 OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
2336 OUT_BCS_RELOC(batch,
2338 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2341 OUT_BCS_BATCH(batch, 0);
2344 for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
2345 OUT_BCS_BATCH(batch, 0);
2348 OUT_BCS_BATCH(batch, 0); /* ignore DW23 for decoding */
2349 ADVANCE_BCS_BATCH(batch);
2351 dri_bo_unreference(intra_bo);
2355 gen7_jpeg_wa_bsp_buf_base_addr_state(VADriverContextP ctx,
2356 struct gen7_mfd_context *gen7_mfd_context)
2358 struct i965_driver_data *i965 = i965_driver_data(ctx);
2359 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2360 dri_bo *bsd_mpc_bo, *mpr_bo;
2362 bsd_mpc_bo = dri_bo_alloc(i965->intel.bufmgr,
2363 "bsd mpc row store",
2364 11520, /* 1.5 * 120 * 64 */
2367 mpr_bo = dri_bo_alloc(i965->intel.bufmgr,
2369 7680, /* 1. 0 * 120 * 64 */
2372 BEGIN_BCS_BATCH(batch, 4);
2373 OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
2375 OUT_BCS_RELOC(batch,
2377 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2380 OUT_BCS_RELOC(batch,
2382 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2384 OUT_BCS_BATCH(batch, 0);
2386 ADVANCE_BCS_BATCH(batch);
2388 dri_bo_unreference(bsd_mpc_bo);
2389 dri_bo_unreference(mpr_bo);
2393 gen7_jpeg_wa_avc_qm_state(VADriverContextP ctx,
2394 struct gen7_mfd_context *gen7_mfd_context)
2400 gen7_jpeg_wa_avc_img_state(VADriverContextP ctx,
2401 struct gen7_mfd_context *gen7_mfd_context)
2403 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2405 int mbaff_frame_flag = 0;
2406 unsigned int width_in_mbs = 1, height_in_mbs = 1;
2408 BEGIN_BCS_BATCH(batch, 16);
2409 OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (16 - 2));
2410 OUT_BCS_BATCH(batch,
2411 (width_in_mbs * height_in_mbs - 1));
2412 OUT_BCS_BATCH(batch,
2413 ((height_in_mbs - 1) << 16) |
2414 ((width_in_mbs - 1) << 0));
2415 OUT_BCS_BATCH(batch,
2420 (0 << 12) | /* differ from GEN6 */
2423 OUT_BCS_BATCH(batch,
2424 (1 << 10) | /* 4:2:0 */
2425 (1 << 7) | /* CABAC */
2431 (mbaff_frame_flag << 1) |
2433 OUT_BCS_BATCH(batch, 0);
2434 OUT_BCS_BATCH(batch, 0);
2435 OUT_BCS_BATCH(batch, 0);
2436 OUT_BCS_BATCH(batch, 0);
2437 OUT_BCS_BATCH(batch, 0);
2438 OUT_BCS_BATCH(batch, 0);
2439 OUT_BCS_BATCH(batch, 0);
2440 OUT_BCS_BATCH(batch, 0);
2441 OUT_BCS_BATCH(batch, 0);
2442 OUT_BCS_BATCH(batch, 0);
2443 OUT_BCS_BATCH(batch, 0);
2444 ADVANCE_BCS_BATCH(batch);
2448 gen7_jpeg_wa_avc_directmode_state(VADriverContextP ctx,
2449 struct gen7_mfd_context *gen7_mfd_context)
2451 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2454 BEGIN_BCS_BATCH(batch, 69);
2455 OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
2457 /* reference surfaces 0..15 */
2458 for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
2459 OUT_BCS_BATCH(batch, 0); /* top */
2460 OUT_BCS_BATCH(batch, 0); /* bottom */
2463 /* the current decoding frame/field */
2464 OUT_BCS_BATCH(batch, 0); /* top */
2465 OUT_BCS_BATCH(batch, 0); /* bottom */
2468 for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
2469 OUT_BCS_BATCH(batch, 0);
2470 OUT_BCS_BATCH(batch, 0);
2473 OUT_BCS_BATCH(batch, 0);
2474 OUT_BCS_BATCH(batch, 0);
2476 ADVANCE_BCS_BATCH(batch);
2480 gen7_jpeg_wa_ind_obj_base_addr_state(VADriverContextP ctx,
2481 struct gen7_mfd_context *gen7_mfd_context)
2483 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2485 BEGIN_BCS_BATCH(batch, 11);
2486 OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
2487 OUT_BCS_RELOC(batch,
2488 gen7_mfd_context->jpeg_wa_slice_data_bo,
2489 I915_GEM_DOMAIN_INSTRUCTION, 0,
2491 OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
2492 OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
2493 OUT_BCS_BATCH(batch, 0);
2494 OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
2495 OUT_BCS_BATCH(batch, 0);
2496 OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
2497 OUT_BCS_BATCH(batch, 0);
2498 OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
2499 OUT_BCS_BATCH(batch, 0);
2500 ADVANCE_BCS_BATCH(batch);
2504 gen7_jpeg_wa_avc_bsd_object(VADriverContextP ctx,
2505 struct gen7_mfd_context *gen7_mfd_context)
2507 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2509 /* the input bitsteam format on GEN7 differs from GEN6 */
2510 BEGIN_BCS_BATCH(batch, 6);
2511 OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2));
2512 OUT_BCS_BATCH(batch, gen7_jpeg_wa_clip.data_size);
2513 OUT_BCS_BATCH(batch, 0);
2514 OUT_BCS_BATCH(batch,
2520 OUT_BCS_BATCH(batch,
2521 ((gen7_jpeg_wa_clip.data_bit_offset >> 3) << 16) |
2524 (1 << 3) | /* LastSlice Flag */
2525 (gen7_jpeg_wa_clip.data_bit_offset & 0x7));
2526 OUT_BCS_BATCH(batch, 0);
2527 ADVANCE_BCS_BATCH(batch);
2531 gen7_jpeg_wa_avc_slice_state(VADriverContextP ctx,
2532 struct gen7_mfd_context *gen7_mfd_context)
2534 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2535 int slice_hor_pos = 0, slice_ver_pos = 0, next_slice_hor_pos = 0, next_slice_ver_pos = 1;
2536 int num_ref_idx_l0 = 0, num_ref_idx_l1 = 0;
2537 int first_mb_in_slice = 0;
2538 int slice_type = SLICE_TYPE_I;
2540 BEGIN_BCS_BATCH(batch, 11);
2541 OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2));
2542 OUT_BCS_BATCH(batch, slice_type);
2543 OUT_BCS_BATCH(batch,
2544 (num_ref_idx_l1 << 24) |
2545 (num_ref_idx_l0 << 16) |
2548 OUT_BCS_BATCH(batch,
2550 (1 << 27) | /* disable Deblocking */
2552 (gen7_jpeg_wa_clip.qp << 16) |
2555 OUT_BCS_BATCH(batch,
2556 (slice_ver_pos << 24) |
2557 (slice_hor_pos << 16) |
2558 (first_mb_in_slice << 0));
2559 OUT_BCS_BATCH(batch,
2560 (next_slice_ver_pos << 16) |
2561 (next_slice_hor_pos << 0));
2562 OUT_BCS_BATCH(batch, (1 << 19)); /* last slice flag */
2563 OUT_BCS_BATCH(batch, 0);
2564 OUT_BCS_BATCH(batch, 0);
2565 OUT_BCS_BATCH(batch, 0);
2566 OUT_BCS_BATCH(batch, 0);
2567 ADVANCE_BCS_BATCH(batch);
2571 gen7_mfd_jpeg_wa(VADriverContextP ctx,
2572 struct gen7_mfd_context *gen7_mfd_context)
2574 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2575 gen7_jpeg_wa_init(ctx, gen7_mfd_context);
2576 intel_batchbuffer_emit_mi_flush(batch);
2577 gen7_jpeg_wa_pipe_mode_select(ctx, gen7_mfd_context);
2578 gen7_jpeg_wa_surface_state(ctx, gen7_mfd_context);
2579 gen7_jpeg_wa_pipe_buf_addr_state(ctx, gen7_mfd_context);
2580 gen7_jpeg_wa_bsp_buf_base_addr_state(ctx, gen7_mfd_context);
2581 gen7_jpeg_wa_avc_qm_state(ctx, gen7_mfd_context);
2582 gen7_jpeg_wa_avc_img_state(ctx, gen7_mfd_context);
2583 gen7_jpeg_wa_ind_obj_base_addr_state(ctx, gen7_mfd_context);
2585 gen7_jpeg_wa_avc_directmode_state(ctx, gen7_mfd_context);
2586 gen7_jpeg_wa_avc_slice_state(ctx, gen7_mfd_context);
2587 gen7_jpeg_wa_avc_bsd_object(ctx, gen7_mfd_context);
2591 gen7_mfd_jpeg_decode_picture(VADriverContextP ctx,
2592 struct decode_state *decode_state,
2593 struct gen7_mfd_context *gen7_mfd_context)
2595 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2596 VAPictureParameterBufferJPEGBaseline *pic_param;
2597 VASliceParameterBufferJPEGBaseline *slice_param, *next_slice_param, *next_slice_group_param;
2598 dri_bo *slice_data_bo;
2599 int i, j, max_selector = 0;
2601 assert(decode_state->pic_param && decode_state->pic_param->buffer);
2602 pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
2604 /* Currently only support Baseline DCT */
2605 gen7_mfd_jpeg_decode_init(ctx, decode_state, gen7_mfd_context);
2606 intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
2607 gen7_mfd_jpeg_wa(ctx, gen7_mfd_context);
2608 intel_batchbuffer_emit_mi_flush(batch);
2609 gen7_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_JPEG, gen7_mfd_context);
2610 gen7_mfd_surface_state(ctx, decode_state, MFX_FORMAT_JPEG, gen7_mfd_context);
2611 gen7_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_JPEG, gen7_mfd_context);
2612 gen7_mfd_jpeg_pic_state(ctx, decode_state, gen7_mfd_context);
2613 gen7_mfd_jpeg_qm_state(ctx, decode_state, gen7_mfd_context);
2615 for (j = 0; j < decode_state->num_slice_params; j++) {
2616 assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
2617 slice_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j]->buffer;
2618 slice_data_bo = decode_state->slice_datas[j]->bo;
2619 gen7_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_JPEG, gen7_mfd_context);
2621 if (j == decode_state->num_slice_params - 1)
2622 next_slice_group_param = NULL;
2624 next_slice_group_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j + 1]->buffer;
2626 for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
2629 assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
2631 if (i < decode_state->slice_params[j]->num_elements - 1)
2632 next_slice_param = slice_param + 1;
2634 next_slice_param = next_slice_group_param;
2636 for (component = 0; component < slice_param->num_components; component++) {
2637 if (max_selector < slice_param->components[component].dc_table_selector)
2638 max_selector = slice_param->components[component].dc_table_selector;
2640 if (max_selector < slice_param->components[component].ac_table_selector)
2641 max_selector = slice_param->components[component].ac_table_selector;
2648 assert(max_selector < 2);
2649 gen7_mfd_jpeg_huff_table_state(ctx, decode_state, gen7_mfd_context, max_selector + 1);
2651 for (j = 0; j < decode_state->num_slice_params; j++) {
2652 assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
2653 slice_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j]->buffer;
2654 slice_data_bo = decode_state->slice_datas[j]->bo;
2655 gen7_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_JPEG, gen7_mfd_context);
2657 if (j == decode_state->num_slice_params - 1)
2658 next_slice_group_param = NULL;
2660 next_slice_group_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j + 1]->buffer;
2662 for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
2663 assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
2665 if (i < decode_state->slice_params[j]->num_elements - 1)
2666 next_slice_param = slice_param + 1;
2668 next_slice_param = next_slice_group_param;
2670 gen7_mfd_jpeg_bsd_object(ctx, pic_param, slice_param, next_slice_param, slice_data_bo, gen7_mfd_context);
2675 intel_batchbuffer_end_atomic(batch);
2676 intel_batchbuffer_flush(batch);
2680 gen7_mfd_decode_picture(VADriverContextP ctx,
2682 union codec_state *codec_state,
2683 struct hw_context *hw_context)
2686 struct gen7_mfd_context *gen7_mfd_context = (struct gen7_mfd_context *)hw_context;
2687 struct decode_state *decode_state = &codec_state->decode;
2690 assert(gen7_mfd_context);
2692 vaStatus = intel_decoder_sanity_check_input(ctx, profile, decode_state);
2694 if (vaStatus != VA_STATUS_SUCCESS)
2697 gen7_mfd_context->wa_mpeg2_slice_vertical_position = -1;
2700 case VAProfileMPEG2Simple:
2701 case VAProfileMPEG2Main:
2702 gen7_mfd_mpeg2_decode_picture(ctx, decode_state, gen7_mfd_context);
2705 case VAProfileH264ConstrainedBaseline:
2706 case VAProfileH264Main:
2707 case VAProfileH264High:
2708 case VAProfileH264StereoHigh:
2709 gen7_mfd_avc_decode_picture(ctx, decode_state, gen7_mfd_context);
2712 case VAProfileVC1Simple:
2713 case VAProfileVC1Main:
2714 case VAProfileVC1Advanced:
2715 gen7_mfd_vc1_decode_picture(ctx, decode_state, gen7_mfd_context);
2718 case VAProfileJPEGBaseline:
2719 gen7_mfd_jpeg_decode_picture(ctx, decode_state, gen7_mfd_context);
2727 vaStatus = VA_STATUS_SUCCESS;
2734 gen7_mfd_context_destroy(void *hw_context)
2736 VADriverContextP ctx;
2737 struct gen7_mfd_context *gen7_mfd_context = (struct gen7_mfd_context *)hw_context;
2739 ctx = (VADriverContextP)(gen7_mfd_context->driver_context);
2741 dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo);
2742 gen7_mfd_context->post_deblocking_output.bo = NULL;
2744 dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
2745 gen7_mfd_context->pre_deblocking_output.bo = NULL;
2747 dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo);
2748 gen7_mfd_context->intra_row_store_scratch_buffer.bo = NULL;
2750 dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
2751 gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
2753 dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
2754 gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
2756 dri_bo_unreference(gen7_mfd_context->mpr_row_store_scratch_buffer.bo);
2757 gen7_mfd_context->mpr_row_store_scratch_buffer.bo = NULL;
2759 dri_bo_unreference(gen7_mfd_context->bitplane_read_buffer.bo);
2760 gen7_mfd_context->bitplane_read_buffer.bo = NULL;
2762 dri_bo_unreference(gen7_mfd_context->jpeg_wa_slice_data_bo);
2764 if (gen7_mfd_context->jpeg_wa_surface_id != VA_INVALID_SURFACE) {
2765 i965_DestroySurfaces(ctx,
2766 &gen7_mfd_context->jpeg_wa_surface_id,
2768 gen7_mfd_context->jpeg_wa_surface_object = NULL;
2771 intel_batchbuffer_free(gen7_mfd_context->base.batch);
2772 free(gen7_mfd_context);
2775 static void gen7_mfd_mpeg2_context_init(VADriverContextP ctx,
2776 struct gen7_mfd_context *gen7_mfd_context)
2778 gen7_mfd_context->iq_matrix.mpeg2.load_intra_quantiser_matrix = -1;
2779 gen7_mfd_context->iq_matrix.mpeg2.load_non_intra_quantiser_matrix = -1;
2780 gen7_mfd_context->iq_matrix.mpeg2.load_chroma_intra_quantiser_matrix = -1;
2781 gen7_mfd_context->iq_matrix.mpeg2.load_chroma_non_intra_quantiser_matrix = -1;
2785 gen7_dec_hw_context_init(VADriverContextP ctx, struct object_config *obj_config)
2787 struct intel_driver_data *intel = intel_driver_data(ctx);
2788 struct gen7_mfd_context *gen7_mfd_context = calloc(1, sizeof(struct gen7_mfd_context));
2791 assert(gen7_mfd_context);
2792 gen7_mfd_context->base.destroy = gen7_mfd_context_destroy;
2793 gen7_mfd_context->base.run = gen7_mfd_decode_picture;
2794 gen7_mfd_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER, 0);
2796 for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
2797 gen7_mfd_context->reference_surface[i].surface_id = VA_INVALID_ID;
2798 gen7_mfd_context->reference_surface[i].frame_store_id = -1;
2799 gen7_mfd_context->reference_surface[i].obj_surface = NULL;
2802 gen7_mfd_context->jpeg_wa_surface_id = VA_INVALID_SURFACE;
2803 gen7_mfd_context->jpeg_wa_surface_object = NULL;
2805 switch (obj_config->profile) {
2806 case VAProfileMPEG2Simple:
2807 case VAProfileMPEG2Main:
2808 gen7_mfd_mpeg2_context_init(ctx, gen7_mfd_context);
2811 case VAProfileH264ConstrainedBaseline:
2812 case VAProfileH264Main:
2813 case VAProfileH264High:
2814 case VAProfileH264StereoHigh:
2815 gen7_mfd_avc_context_init(ctx, gen7_mfd_context);
2821 gen7_mfd_context->driver_context = ctx;
2822 return (struct hw_context *)gen7_mfd_context;