src/gen7_mfd.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Xiang Haihao <haihao.xiang@intel.com>
  26  *
  27  */
  28
  29 #include "sysdeps.h"
  30
  31 #include <va/va_dec_jpeg.h>
  32
  33 #include "intel_batchbuffer.h"
  34 #include "intel_driver.h"
  35 #include "i965_defines.h"
  36 #include "i965_drv_video.h"
  37 #include "i965_decoder_utils.h"
  38
  39 #include "gen7_mfd.h"
  40 #include "intel_media.h"
  41
  42 static const uint32_t zigzag_direct[64] = {
  43     0,   1,  8, 16,  9,  2,  3, 10,
  44     17, 24, 32, 25, 18, 11,  4,  5,
  45     12, 19, 26, 33, 40, 48, 41, 34,
  46     27, 20, 13,  6,  7, 14, 21, 28,
  47     35, 42, 49, 56, 57, 50, 43, 36,
  48     29, 22, 15, 23, 30, 37, 44, 51,
  49     58, 59, 52, 45, 38, 31, 39, 46,
  50     53, 60, 61, 54, 47, 55, 62, 63
  51 };
  52
  53 static void
  54 gen7_mfd_init_avc_surface(VADriverContextP ctx,
  55                           VAPictureParameterBufferH264 *pic_param,
  56                           struct object_surface *obj_surface)
  57 {
  58     struct i965_driver_data *i965 = i965_driver_data(ctx);
  59     GenAvcSurface *gen7_avc_surface = obj_surface->private_data;
  60     int width_in_mbs, height_in_mbs;
  61
  62     obj_surface->free_private_data = gen_free_avc_surface;
  63     width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
  64     height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; /* frame height */
  65
  66     if (!gen7_avc_surface) {
  67         gen7_avc_surface = calloc(sizeof(GenAvcSurface), 1);
  68         assert(gen7_avc_surface);
  69         gen7_avc_surface->base.frame_store_id = -1;
  70         assert((obj_surface->size & 0x3f) == 0);
  71         obj_surface->private_data = gen7_avc_surface;
  72     }
  73
  74     gen7_avc_surface->dmv_bottom_flag = (pic_param->pic_fields.bits.field_pic_flag &&
  75                                          !pic_param->seq_fields.bits.direct_8x8_inference_flag);
  76
  77     if (gen7_avc_surface->dmv_top == NULL) {
  78         gen7_avc_surface->dmv_top = dri_bo_alloc(i965->intel.bufmgr,
  79                                                  "direct mv w/r buffer",
  80                                                  width_in_mbs * (height_in_mbs + 1) * 64,
  81                                                  0x1000);
  82         assert(gen7_avc_surface->dmv_top);
  83     }
  84
  85     if (gen7_avc_surface->dmv_bottom_flag &&
  86         gen7_avc_surface->dmv_bottom == NULL) {
  87         gen7_avc_surface->dmv_bottom = dri_bo_alloc(i965->intel.bufmgr,
  88                                                     "direct mv w/r buffer",
  89                                                     width_in_mbs * (height_in_mbs + 1) * 64,
  90                                                     0x1000);
  91         assert(gen7_avc_surface->dmv_bottom);
  92     }
  93 }
  94
  95 static void
  96 gen7_mfd_pipe_mode_select(VADriverContextP ctx,
  97                           struct decode_state *decode_state,
  98                           int standard_select,
  99                           struct gen7_mfd_context *gen7_mfd_context)
 100 {
 101     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 102
 103     assert(standard_select == MFX_FORMAT_MPEG2 ||
 104            standard_select == MFX_FORMAT_AVC ||
 105            standard_select == MFX_FORMAT_VC1 ||
 106            standard_select == MFX_FORMAT_JPEG);
 107
 108     BEGIN_BCS_BATCH(batch, 5);
 109     OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2));
 110     OUT_BCS_BATCH(batch,
 111                   (MFX_LONG_MODE << 17) | /* Currently only support long format */
 112                   (MFD_MODE_VLD << 15) | /* VLD mode */
 113                   (0 << 10) | /* disable Stream-Out */
 114                   (gen7_mfd_context->post_deblocking_output.valid << 9)  | /* Post Deblocking Output */
 115                   (gen7_mfd_context->pre_deblocking_output.valid << 8)  | /* Pre Deblocking Output */
 116                   (0 << 5)  | /* not in stitch mode */
 117                   (MFX_CODEC_DECODE << 4)  | /* decoding mode */
 118                   (standard_select << 0));
 119     OUT_BCS_BATCH(batch,
 120                   (0 << 4)  | /* terminate if AVC motion and POC table error occurs */
 121                   (0 << 3)  | /* terminate if AVC mbdata error occurs */
 122                   (0 << 2)  | /* terminate if AVC CABAC/CAVLC decode error occurs */
 123                   (0 << 1)  |
 124                   (0 << 0));
 125     OUT_BCS_BATCH(batch, 0); /* pic status/error report id */
 126     OUT_BCS_BATCH(batch, 0); /* reserved */
 127     ADVANCE_BCS_BATCH(batch);
 128 }
 129
 130 static void
 131 gen7_mfd_surface_state(VADriverContextP ctx,
 132                        struct decode_state *decode_state,
 133                        int standard_select,
 134                        struct gen7_mfd_context *gen7_mfd_context)
 135 {
 136     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 137     struct object_surface *obj_surface = decode_state->render_object;
 138     unsigned int y_cb_offset;
 139     unsigned int y_cr_offset;
 140     unsigned int surface_format;
 141
 142     assert(obj_surface);
 143
 144     y_cb_offset = obj_surface->y_cb_offset;
 145     y_cr_offset = obj_surface->y_cr_offset;
 146
 147     surface_format = obj_surface->fourcc == VA_FOURCC_Y800 ?
 148                      MFX_SURFACE_MONOCHROME : MFX_SURFACE_PLANAR_420_8;
 149
 150     BEGIN_BCS_BATCH(batch, 6);
 151     OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
 152     OUT_BCS_BATCH(batch, 0);
 153     OUT_BCS_BATCH(batch,
 154                   ((obj_surface->orig_height - 1) << 18) |
 155                   ((obj_surface->orig_width - 1) << 4));
 156     OUT_BCS_BATCH(batch,
 157                   (surface_format << 28) | /* 420 planar YUV surface */
 158                   ((standard_select != MFX_FORMAT_JPEG) << 27) | /* interleave chroma, set to 0 for JPEG */
 159                   (0 << 22) | /* surface object control state, ignored */
 160                   ((obj_surface->width - 1) << 3) | /* pitch */
 161                   (0 << 2)  | /* must be 0 */
 162                   (1 << 1)  | /* must be tiled */
 163                   (I965_TILEWALK_YMAJOR << 0));  /* tile walk, must be 1 */
 164     OUT_BCS_BATCH(batch,
 165                   (0 << 16) | /* X offset for U(Cb), must be 0 */
 166                   (y_cb_offset << 0)); /* Y offset for U(Cb) */
 167     OUT_BCS_BATCH(batch,
 168                   (0 << 16) | /* X offset for V(Cr), must be 0 */
 169                   ((standard_select == MFX_FORMAT_JPEG ? y_cr_offset : 0) << 0)); /* Y offset for V(Cr), must be 0 for video codec, non-zoro for JPEG */
 170     ADVANCE_BCS_BATCH(batch);
 171 }
 172
 173 static void
 174 gen7_mfd_pipe_buf_addr_state(VADriverContextP ctx,
 175                              struct decode_state *decode_state,
 176                              int standard_select,
 177                              struct gen7_mfd_context *gen7_mfd_context)
 178 {
 179     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 180     int i;
 181
 182     BEGIN_BCS_BATCH(batch, 24);
 183     OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
 184     if (gen7_mfd_context->pre_deblocking_output.valid)
 185         OUT_BCS_RELOC(batch, gen7_mfd_context->pre_deblocking_output.bo,
 186                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 187                       0);
 188     else
 189         OUT_BCS_BATCH(batch, 0);
 190
 191     if (gen7_mfd_context->post_deblocking_output.valid)
 192         OUT_BCS_RELOC(batch, gen7_mfd_context->post_deblocking_output.bo,
 193                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 194                       0);
 195     else
 196         OUT_BCS_BATCH(batch, 0);
 197
 198     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
 199     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
 200
 201     if (gen7_mfd_context->intra_row_store_scratch_buffer.valid)
 202         OUT_BCS_RELOC(batch, gen7_mfd_context->intra_row_store_scratch_buffer.bo,
 203                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 204                       0);
 205     else
 206         OUT_BCS_BATCH(batch, 0);
 207
 208     if (gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid)
 209         OUT_BCS_RELOC(batch, gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo,
 210                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 211                       0);
 212     else
 213         OUT_BCS_BATCH(batch, 0);
 214
 215     /* DW 7..22 */
 216     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
 217         struct object_surface *obj_surface;
 218
 219         if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID &&
 220             gen7_mfd_context->reference_surface[i].obj_surface &&
 221             gen7_mfd_context->reference_surface[i].obj_surface->bo) {
 222             obj_surface = gen7_mfd_context->reference_surface[i].obj_surface;
 223
 224             OUT_BCS_RELOC(batch, obj_surface->bo,
 225                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 226                           0);
 227         } else {
 228             OUT_BCS_BATCH(batch, 0);
 229         }
 230     }
 231
 232     OUT_BCS_BATCH(batch, 0);   /* ignore DW23 for decoding */
 233     ADVANCE_BCS_BATCH(batch);
 234 }
 235
 236 static void
 237 gen7_mfd_ind_obj_base_addr_state(VADriverContextP ctx,
 238                                  dri_bo *slice_data_bo,
 239                                  int standard_select,
 240                                  struct gen7_mfd_context *gen7_mfd_context)
 241 {
 242     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 243
 244     BEGIN_BCS_BATCH(batch, 11);
 245     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
 246     OUT_BCS_RELOC(batch, slice_data_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); /* MFX Indirect Bitstream Object Base Address */
 247     OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
 248     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 249     OUT_BCS_BATCH(batch, 0);
 250     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 251     OUT_BCS_BATCH(batch, 0);
 252     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 253     OUT_BCS_BATCH(batch, 0);
 254     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 255     OUT_BCS_BATCH(batch, 0);
 256     ADVANCE_BCS_BATCH(batch);
 257 }
 258
 259 static void
 260 gen7_mfd_bsp_buf_base_addr_state(VADriverContextP ctx,
 261                                  struct decode_state *decode_state,
 262                                  int standard_select,
 263                                  struct gen7_mfd_context *gen7_mfd_context)
 264 {
 265     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 266
 267     BEGIN_BCS_BATCH(batch, 4);
 268     OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
 269
 270     if (gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid)
 271         OUT_BCS_RELOC(batch, gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo,
 272                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 273                       0);
 274     else
 275         OUT_BCS_BATCH(batch, 0);
 276
 277     if (gen7_mfd_context->mpr_row_store_scratch_buffer.valid)
 278         OUT_BCS_RELOC(batch, gen7_mfd_context->mpr_row_store_scratch_buffer.bo,
 279                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 280                       0);
 281     else
 282         OUT_BCS_BATCH(batch, 0);
 283
 284     if (gen7_mfd_context->bitplane_read_buffer.valid)
 285         OUT_BCS_RELOC(batch, gen7_mfd_context->bitplane_read_buffer.bo,
 286                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 287                       0);
 288     else
 289         OUT_BCS_BATCH(batch, 0);
 290
 291     ADVANCE_BCS_BATCH(batch);
 292 }
 293
 294 static void
 295 gen7_mfd_qm_state(VADriverContextP ctx,
 296                   int qm_type,
 297                   unsigned char *qm,
 298                   int qm_length,
 299                   struct gen7_mfd_context *gen7_mfd_context)
 300 {
 301     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 302     unsigned int qm_buffer[16];
 303
 304     assert(qm_length <= 16 * 4);
 305     memcpy(qm_buffer, qm, qm_length);
 306
 307     BEGIN_BCS_BATCH(batch, 18);
 308     OUT_BCS_BATCH(batch, MFX_QM_STATE | (18 - 2));
 309     OUT_BCS_BATCH(batch, qm_type << 0);
 310     intel_batchbuffer_data(batch, qm_buffer, 16 * 4);
 311     ADVANCE_BCS_BATCH(batch);
 312 }
 313
 314 static void
 315 gen7_mfd_avc_img_state(VADriverContextP ctx,
 316                        struct decode_state *decode_state,
 317                        struct gen7_mfd_context *gen7_mfd_context)
 318 {
 319     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 320     int img_struct;
 321     int mbaff_frame_flag;
 322     unsigned int width_in_mbs, height_in_mbs;
 323     VAPictureParameterBufferH264 *pic_param;
 324
 325     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 326     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 327
 328     if (pic_param->CurrPic.flags & VA_PICTURE_H264_TOP_FIELD)
 329         img_struct = 1;
 330     else if (pic_param->CurrPic.flags & VA_PICTURE_H264_BOTTOM_FIELD)
 331         img_struct = 3;
 332     else
 333         img_struct = 0;
 334
 335     if ((img_struct & 0x1) == 0x1) {
 336         assert(pic_param->pic_fields.bits.field_pic_flag == 0x1);
 337     } else {
 338         assert(pic_param->pic_fields.bits.field_pic_flag == 0x0);
 339     }
 340
 341     if (pic_param->seq_fields.bits.frame_mbs_only_flag) { /* a frame containing only frame macroblocks */
 342         assert(pic_param->seq_fields.bits.mb_adaptive_frame_field_flag == 0);
 343         assert(pic_param->pic_fields.bits.field_pic_flag == 0);
 344     } else {
 345         assert(pic_param->seq_fields.bits.direct_8x8_inference_flag == 1); /* see H.264 spec */
 346     }
 347
 348     mbaff_frame_flag = (pic_param->seq_fields.bits.mb_adaptive_frame_field_flag &&
 349                         !pic_param->pic_fields.bits.field_pic_flag);
 350
 351     width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
 352     height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; /* frame height */
 353
 354     /* MFX unit doesn't support 4:2:2 and 4:4:4 picture */
 355     assert(pic_param->seq_fields.bits.chroma_format_idc == 0 || /* monochrome picture */
 356            pic_param->seq_fields.bits.chroma_format_idc == 1);  /* 4:2:0 */
 357     assert(pic_param->seq_fields.bits.residual_colour_transform_flag == 0); /* only available for 4:4:4 */
 358
 359     BEGIN_BCS_BATCH(batch, 16);
 360     OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (16 - 2));
 361     OUT_BCS_BATCH(batch,
 362                   (width_in_mbs * height_in_mbs - 1));
 363     OUT_BCS_BATCH(batch,
 364                   ((height_in_mbs - 1) << 16) |
 365                   ((width_in_mbs - 1) << 0));
 366     OUT_BCS_BATCH(batch,
 367                   ((pic_param->second_chroma_qp_index_offset & 0x1f) << 24) |
 368                   ((pic_param->chroma_qp_index_offset & 0x1f) << 16) |
 369                   (0 << 14) | /* Max-bit conformance Intra flag ??? FIXME */
 370                   (0 << 13) | /* Max Macroblock size conformance Inter flag ??? FIXME */
 371                   (pic_param->pic_fields.bits.weighted_pred_flag << 12) | /* differ from GEN6 */
 372                   (pic_param->pic_fields.bits.weighted_bipred_idc << 10) |
 373                   (img_struct << 8));
 374     OUT_BCS_BATCH(batch,
 375                   (pic_param->seq_fields.bits.chroma_format_idc << 10) |
 376                   (pic_param->pic_fields.bits.entropy_coding_mode_flag << 7) |
 377                   ((!pic_param->pic_fields.bits.reference_pic_flag) << 6) |
 378                   (pic_param->pic_fields.bits.constrained_intra_pred_flag << 5) |
 379                   (pic_param->seq_fields.bits.direct_8x8_inference_flag << 4) |
 380                   (pic_param->pic_fields.bits.transform_8x8_mode_flag << 3) |
 381                   (pic_param->seq_fields.bits.frame_mbs_only_flag << 2) |
 382                   (mbaff_frame_flag << 1) |
 383                   (pic_param->pic_fields.bits.field_pic_flag << 0));
 384     OUT_BCS_BATCH(batch, 0);
 385     OUT_BCS_BATCH(batch, 0);
 386     OUT_BCS_BATCH(batch, 0);
 387     OUT_BCS_BATCH(batch, 0);
 388     OUT_BCS_BATCH(batch, 0);
 389     OUT_BCS_BATCH(batch, 0);
 390     OUT_BCS_BATCH(batch, 0);
 391     OUT_BCS_BATCH(batch, 0);
 392     OUT_BCS_BATCH(batch, 0);
 393     OUT_BCS_BATCH(batch, 0);
 394     OUT_BCS_BATCH(batch, 0);
 395     ADVANCE_BCS_BATCH(batch);
 396 }
 397
 398 static void
 399 gen7_mfd_avc_qm_state(VADriverContextP ctx,
 400                       struct decode_state *decode_state,
 401                       struct gen7_mfd_context *gen7_mfd_context)
 402 {
 403     VAIQMatrixBufferH264 *iq_matrix;
 404     VAPictureParameterBufferH264 *pic_param;
 405
 406     if (decode_state->iq_matrix && decode_state->iq_matrix->buffer)
 407         iq_matrix = (VAIQMatrixBufferH264 *)decode_state->iq_matrix->buffer;
 408     else
 409         iq_matrix = &gen7_mfd_context->iq_matrix.h264;
 410
 411     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 412     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 413
 414     gen7_mfd_qm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, &iq_matrix->ScalingList4x4[0][0], 3 * 16, gen7_mfd_context);
 415     gen7_mfd_qm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, &iq_matrix->ScalingList4x4[3][0], 3 * 16, gen7_mfd_context);
 416
 417     if (pic_param->pic_fields.bits.transform_8x8_mode_flag) {
 418         gen7_mfd_qm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, &iq_matrix->ScalingList8x8[0][0], 64, gen7_mfd_context);
 419         gen7_mfd_qm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, &iq_matrix->ScalingList8x8[1][0], 64, gen7_mfd_context);
 420     }
 421 }
 422
 423 static void
 424 gen7_mfd_avc_directmode_state(VADriverContextP ctx,
 425                               struct decode_state *decode_state,
 426                               VAPictureParameterBufferH264 *pic_param,
 427                               VASliceParameterBufferH264 *slice_param,
 428                               struct gen7_mfd_context *gen7_mfd_context)
 429 {
 430     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 431     struct object_surface *obj_surface;
 432     GenAvcSurface *gen7_avc_surface;
 433     VAPictureH264 *va_pic;
 434     int i;
 435
 436     BEGIN_BCS_BATCH(batch, 69);
 437     OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
 438
 439     /* reference surfaces 0..15 */
 440     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
 441         if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID &&
 442             gen7_mfd_context->reference_surface[i].obj_surface &&
 443             gen7_mfd_context->reference_surface[i].obj_surface->private_data) {
 444
 445             obj_surface = gen7_mfd_context->reference_surface[i].obj_surface;
 446             gen7_avc_surface = obj_surface->private_data;
 447             OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
 448                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 449                           0);
 450
 451             if (gen7_avc_surface->dmv_bottom_flag == 1)
 452                 OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_bottom,
 453                               I915_GEM_DOMAIN_INSTRUCTION, 0,
 454                               0);
 455             else
 456                 OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
 457                               I915_GEM_DOMAIN_INSTRUCTION, 0,
 458                               0);
 459         } else {
 460             OUT_BCS_BATCH(batch, 0);
 461             OUT_BCS_BATCH(batch, 0);
 462         }
 463     }
 464
 465     /* the current decoding frame/field */
 466     va_pic = &pic_param->CurrPic;
 467     obj_surface = decode_state->render_object;
 468     assert(obj_surface->bo && obj_surface->private_data);
 469     gen7_avc_surface = obj_surface->private_data;
 470
 471     OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
 472                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 473                   0);
 474
 475     if (gen7_avc_surface->dmv_bottom_flag == 1)
 476         OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_bottom,
 477                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 478                       0);
 479     else
 480         OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
 481                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 482                       0);
 483
 484     /* POC List */
 485     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
 486         obj_surface = gen7_mfd_context->reference_surface[i].obj_surface;
 487
 488         if (obj_surface) {
 489             const VAPictureH264 * const va_pic = avc_find_picture(
 490                                                      obj_surface->base.id, pic_param->ReferenceFrames,
 491                                                      ARRAY_ELEMS(pic_param->ReferenceFrames));
 492
 493             assert(va_pic != NULL);
 494             OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
 495             OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
 496         } else {
 497             OUT_BCS_BATCH(batch, 0);
 498             OUT_BCS_BATCH(batch, 0);
 499         }
 500     }
 501
 502     va_pic = &pic_param->CurrPic;
 503     OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
 504     OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
 505
 506     ADVANCE_BCS_BATCH(batch);
 507 }
 508
 509 static void
 510 gen7_mfd_avc_phantom_slice_first(VADriverContextP ctx,
 511                                  VAPictureParameterBufferH264 *pic_param,
 512                                  VASliceParameterBufferH264 *next_slice_param,
 513                                  struct gen7_mfd_context *gen7_mfd_context)
 514 {
 515     gen6_mfd_avc_phantom_slice(ctx, pic_param, next_slice_param, gen7_mfd_context->base.batch);
 516 }
 517
 518 static void
 519 gen7_mfd_avc_slice_state(VADriverContextP ctx,
 520                          VAPictureParameterBufferH264 *pic_param,
 521                          VASliceParameterBufferH264 *slice_param,
 522                          VASliceParameterBufferH264 *next_slice_param,
 523                          struct gen7_mfd_context *gen7_mfd_context)
 524 {
 525     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 526     int width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
 527     int height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1;
 528     int slice_hor_pos, slice_ver_pos, next_slice_hor_pos, next_slice_ver_pos;
 529     int num_ref_idx_l0, num_ref_idx_l1;
 530     int mbaff_picture = (!pic_param->pic_fields.bits.field_pic_flag &&
 531                          pic_param->seq_fields.bits.mb_adaptive_frame_field_flag);
 532     int first_mb_in_slice = 0, first_mb_in_next_slice = 0;
 533     int slice_type;
 534
 535     if (slice_param->slice_type == SLICE_TYPE_I ||
 536         slice_param->slice_type == SLICE_TYPE_SI) {
 537         slice_type = SLICE_TYPE_I;
 538     } else if (slice_param->slice_type == SLICE_TYPE_P ||
 539                slice_param->slice_type == SLICE_TYPE_SP) {
 540         slice_type = SLICE_TYPE_P;
 541     } else {
 542         assert(slice_param->slice_type == SLICE_TYPE_B);
 543         slice_type = SLICE_TYPE_B;
 544     }
 545
 546     if (slice_type == SLICE_TYPE_I) {
 547         assert(slice_param->num_ref_idx_l0_active_minus1 == 0);
 548         assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
 549         num_ref_idx_l0 = 0;
 550         num_ref_idx_l1 = 0;
 551     } else if (slice_type == SLICE_TYPE_P) {
 552         assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
 553         num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
 554         num_ref_idx_l1 = 0;
 555     } else {
 556         num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
 557         num_ref_idx_l1 = slice_param->num_ref_idx_l1_active_minus1 + 1;
 558     }
 559
 560     first_mb_in_slice = slice_param->first_mb_in_slice;
 561     slice_hor_pos = first_mb_in_slice % width_in_mbs;
 562     slice_ver_pos = first_mb_in_slice / width_in_mbs;
 563
 564     if (mbaff_picture)
 565         slice_ver_pos = slice_ver_pos << 1;
 566
 567     if (next_slice_param) {
 568         first_mb_in_next_slice = next_slice_param->first_mb_in_slice;
 569         next_slice_hor_pos = first_mb_in_next_slice % width_in_mbs;
 570         next_slice_ver_pos = first_mb_in_next_slice / width_in_mbs;
 571
 572         if (mbaff_picture)
 573             next_slice_ver_pos = next_slice_ver_pos << 1;
 574     } else {
 575         next_slice_hor_pos = 0;
 576         next_slice_ver_pos = height_in_mbs / (1 + !!pic_param->pic_fields.bits.field_pic_flag);
 577     }
 578
 579     BEGIN_BCS_BATCH(batch, 11); /* FIXME: is it 10??? */
 580     OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2));
 581     OUT_BCS_BATCH(batch, slice_type);
 582     OUT_BCS_BATCH(batch,
 583                   (num_ref_idx_l1 << 24) |
 584                   (num_ref_idx_l0 << 16) |
 585                   (slice_param->chroma_log2_weight_denom << 8) |
 586                   (slice_param->luma_log2_weight_denom << 0));
 587     OUT_BCS_BATCH(batch,
 588                   (slice_param->direct_spatial_mv_pred_flag << 29) |
 589                   (slice_param->disable_deblocking_filter_idc << 27) |
 590                   (slice_param->cabac_init_idc << 24) |
 591                   ((pic_param->pic_init_qp_minus26 + 26 + slice_param->slice_qp_delta) << 16) |
 592                   ((slice_param->slice_beta_offset_div2 & 0xf) << 8) |
 593                   ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0));
 594     OUT_BCS_BATCH(batch,
 595                   (slice_ver_pos << 24) |
 596                   (slice_hor_pos << 16) |
 597                   (first_mb_in_slice << 0));
 598     OUT_BCS_BATCH(batch,
 599                   (next_slice_ver_pos << 16) |
 600                   (next_slice_hor_pos << 0));
 601     OUT_BCS_BATCH(batch,
 602                   (next_slice_param == NULL) << 19); /* last slice flag */
 603     OUT_BCS_BATCH(batch, 0);
 604     OUT_BCS_BATCH(batch, 0);
 605     OUT_BCS_BATCH(batch, 0);
 606     OUT_BCS_BATCH(batch, 0);
 607     ADVANCE_BCS_BATCH(batch);
 608 }
 609
 610 static inline void
 611 gen7_mfd_avc_ref_idx_state(VADriverContextP ctx,
 612                            VAPictureParameterBufferH264 *pic_param,
 613                            VASliceParameterBufferH264 *slice_param,
 614                            struct gen7_mfd_context *gen7_mfd_context)
 615 {
 616     gen6_send_avc_ref_idx_state(
 617         gen7_mfd_context->base.batch,
 618         slice_param,
 619         gen7_mfd_context->reference_surface
 620     );
 621 }
 622
 623 static void
 624 gen7_mfd_avc_weightoffset_state(VADriverContextP ctx,
 625                                 VAPictureParameterBufferH264 *pic_param,
 626                                 VASliceParameterBufferH264 *slice_param,
 627                                 struct gen7_mfd_context *gen7_mfd_context)
 628 {
 629     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 630     int i, j, num_weight_offset_table = 0;
 631     short weightoffsets[32 * 6];
 632
 633     if ((slice_param->slice_type == SLICE_TYPE_P ||
 634          slice_param->slice_type == SLICE_TYPE_SP) &&
 635         (pic_param->pic_fields.bits.weighted_pred_flag == 1)) {
 636         num_weight_offset_table = 1;
 637     }
 638
 639     if ((slice_param->slice_type == SLICE_TYPE_B) &&
 640         (pic_param->pic_fields.bits.weighted_bipred_idc == 1)) {
 641         num_weight_offset_table = 2;
 642     }
 643
 644     for (i = 0; i < num_weight_offset_table; i++) {
 645         BEGIN_BCS_BATCH(batch, 98);
 646         OUT_BCS_BATCH(batch, MFX_AVC_WEIGHTOFFSET_STATE | (98 - 2));
 647         OUT_BCS_BATCH(batch, i);
 648
 649         if (i == 0) {
 650             for (j = 0; j < 32; j++) {
 651                 weightoffsets[j * 6 + 0] = slice_param->luma_weight_l0[j];
 652                 weightoffsets[j * 6 + 1] = slice_param->luma_offset_l0[j];
 653                 weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l0[j][0];
 654                 weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l0[j][0];
 655                 weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l0[j][1];
 656                 weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l0[j][1];
 657             }
 658         } else {
 659             for (j = 0; j < 32; j++) {
 660                 weightoffsets[j * 6 + 0] = slice_param->luma_weight_l1[j];
 661                 weightoffsets[j * 6 + 1] = slice_param->luma_offset_l1[j];
 662                 weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l1[j][0];
 663                 weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l1[j][0];
 664                 weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l1[j][1];
 665                 weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l1[j][1];
 666             }
 667         }
 668
 669         intel_batchbuffer_data(batch, weightoffsets, sizeof(weightoffsets));
 670         ADVANCE_BCS_BATCH(batch);
 671     }
 672 }
 673
 674 static void
 675 gen7_mfd_avc_bsd_object(VADriverContextP ctx,
 676                         VAPictureParameterBufferH264 *pic_param,
 677                         VASliceParameterBufferH264 *slice_param,
 678                         dri_bo *slice_data_bo,
 679                         VASliceParameterBufferH264 *next_slice_param,
 680                         struct gen7_mfd_context *gen7_mfd_context)
 681 {
 682     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 683     unsigned int slice_data_bit_offset;
 684
 685     slice_data_bit_offset = avc_get_first_mb_bit_offset(
 686                                 slice_data_bo,
 687                                 slice_param,
 688                                 pic_param->pic_fields.bits.entropy_coding_mode_flag
 689                             );
 690
 691     /* the input bitsteam format on GEN7 differs from GEN6 */
 692     BEGIN_BCS_BATCH(batch, 6);
 693     OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2));
 694     OUT_BCS_BATCH(batch,
 695                   (slice_param->slice_data_size - slice_param->slice_data_offset));
 696     OUT_BCS_BATCH(batch, slice_param->slice_data_offset);
 697     OUT_BCS_BATCH(batch,
 698                   (0 << 31) |
 699                   (0 << 14) |
 700                   (0 << 12) |
 701                   (0 << 10) |
 702                   (0 << 8));
 703     OUT_BCS_BATCH(batch,
 704                   ((slice_data_bit_offset >> 3) << 16) |
 705                   (1 << 7)  |
 706                   (0 << 5)  |
 707                   (0 << 4)  |
 708                   ((next_slice_param == NULL) << 3) | /* LastSlice Flag */
 709                   (slice_data_bit_offset & 0x7));
 710     OUT_BCS_BATCH(batch, 0);
 711     ADVANCE_BCS_BATCH(batch);
 712 }
 713
 714 static inline void
 715 gen7_mfd_avc_context_init(
 716     VADriverContextP         ctx,
 717     struct gen7_mfd_context *gen7_mfd_context
 718 )
 719 {
 720     /* Initialize flat scaling lists */
 721     avc_gen_default_iq_matrix(&gen7_mfd_context->iq_matrix.h264);
 722 }
 723
 724 static void
 725 gen7_mfd_avc_decode_init(VADriverContextP ctx,
 726                          struct decode_state *decode_state,
 727                          struct gen7_mfd_context *gen7_mfd_context)
 728 {
 729     VAPictureParameterBufferH264 *pic_param;
 730     VASliceParameterBufferH264 *slice_param;
 731     struct i965_driver_data *i965 = i965_driver_data(ctx);
 732     struct object_surface *obj_surface;
 733     dri_bo *bo;
 734     int i, j, enable_avc_ildb = 0;
 735     unsigned int width_in_mbs, height_in_mbs;
 736
 737     for (j = 0; j < decode_state->num_slice_params && enable_avc_ildb == 0; j++) {
 738         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
 739         slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
 740
 741         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
 742             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
 743             assert((slice_param->slice_type == SLICE_TYPE_I) ||
 744                    (slice_param->slice_type == SLICE_TYPE_SI) ||
 745                    (slice_param->slice_type == SLICE_TYPE_P) ||
 746                    (slice_param->slice_type == SLICE_TYPE_SP) ||
 747                    (slice_param->slice_type == SLICE_TYPE_B));
 748
 749             if (slice_param->disable_deblocking_filter_idc != 1) {
 750                 enable_avc_ildb = 1;
 751                 break;
 752             }
 753
 754             slice_param++;
 755         }
 756     }
 757
 758     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 759     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 760     intel_update_avc_frame_store_index(ctx, decode_state, pic_param,
 761                                        gen7_mfd_context->reference_surface, &gen7_mfd_context->fs_ctx);
 762     width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
 763     height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1;
 764     assert(width_in_mbs > 0 && width_in_mbs <= 256); /* 4K */
 765     assert(height_in_mbs > 0 && height_in_mbs <= 256);
 766
 767     /* Current decoded picture */
 768     obj_surface = decode_state->render_object;
 769     if (pic_param->pic_fields.bits.reference_pic_flag)
 770         obj_surface->flags |= SURFACE_REFERENCED;
 771     else
 772         obj_surface->flags &= ~SURFACE_REFERENCED;
 773
 774     avc_ensure_surface_bo(ctx, decode_state, obj_surface, pic_param);
 775     gen7_mfd_init_avc_surface(ctx, pic_param, obj_surface);
 776
 777     dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo);
 778     gen7_mfd_context->post_deblocking_output.bo = obj_surface->bo;
 779     dri_bo_reference(gen7_mfd_context->post_deblocking_output.bo);
 780     gen7_mfd_context->post_deblocking_output.valid = enable_avc_ildb;
 781
 782     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
 783     gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
 784     dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
 785     gen7_mfd_context->pre_deblocking_output.valid = !enable_avc_ildb;
 786
 787     dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo);
 788     bo = dri_bo_alloc(i965->intel.bufmgr,
 789                       "intra row store",
 790                       width_in_mbs * 64,
 791                       0x1000);
 792     assert(bo);
 793     gen7_mfd_context->intra_row_store_scratch_buffer.bo = bo;
 794     gen7_mfd_context->intra_row_store_scratch_buffer.valid = 1;
 795
 796     dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
 797     bo = dri_bo_alloc(i965->intel.bufmgr,
 798                       "deblocking filter row store",
 799                       width_in_mbs * 64 * 4,
 800                       0x1000);
 801     assert(bo);
 802     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
 803     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1;
 804
 805     dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
 806     bo = dri_bo_alloc(i965->intel.bufmgr,
 807                       "bsd mpc row store",
 808                       width_in_mbs * 64 * 2,
 809                       0x1000);
 810     assert(bo);
 811     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
 812     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
 813
 814     dri_bo_unreference(gen7_mfd_context->mpr_row_store_scratch_buffer.bo);
 815     bo = dri_bo_alloc(i965->intel.bufmgr,
 816                       "mpr row store",
 817                       width_in_mbs * 64 * 2,
 818                       0x1000);
 819     assert(bo);
 820     gen7_mfd_context->mpr_row_store_scratch_buffer.bo = bo;
 821     gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 1;
 822
 823     gen7_mfd_context->bitplane_read_buffer.valid = 0;
 824 }
 825
 826 static void
 827 gen7_mfd_avc_decode_picture(VADriverContextP ctx,
 828                             struct decode_state *decode_state,
 829                             struct gen7_mfd_context *gen7_mfd_context)
 830 {
 831     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 832     VAPictureParameterBufferH264 *pic_param;
 833     VASliceParameterBufferH264 *slice_param, *next_slice_param, *next_slice_group_param;
 834     dri_bo *slice_data_bo;
 835     int i, j;
 836
 837     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 838     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 839     gen7_mfd_avc_decode_init(ctx, decode_state, gen7_mfd_context);
 840
 841     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
 842     intel_batchbuffer_emit_mi_flush(batch);
 843     gen7_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
 844     gen7_mfd_surface_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
 845     gen7_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
 846     gen7_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
 847     gen7_mfd_avc_qm_state(ctx, decode_state, gen7_mfd_context);
 848     gen7_mfd_avc_img_state(ctx, decode_state, gen7_mfd_context);
 849
 850     for (j = 0; j < decode_state->num_slice_params; j++) {
 851         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
 852         slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
 853         slice_data_bo = decode_state->slice_datas[j]->bo;
 854         gen7_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_AVC, gen7_mfd_context);
 855
 856         if (j == decode_state->num_slice_params - 1)
 857             next_slice_group_param = NULL;
 858         else
 859             next_slice_group_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j + 1]->buffer;
 860
 861         if (j == 0 && slice_param->first_mb_in_slice)
 862             gen7_mfd_avc_phantom_slice_first(ctx, pic_param, slice_param, gen7_mfd_context);
 863
 864         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
 865             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
 866             assert((slice_param->slice_type == SLICE_TYPE_I) ||
 867                    (slice_param->slice_type == SLICE_TYPE_SI) ||
 868                    (slice_param->slice_type == SLICE_TYPE_P) ||
 869                    (slice_param->slice_type == SLICE_TYPE_SP) ||
 870                    (slice_param->slice_type == SLICE_TYPE_B));
 871
 872             if (i < decode_state->slice_params[j]->num_elements - 1)
 873                 next_slice_param = slice_param + 1;
 874             else
 875                 next_slice_param = next_slice_group_param;
 876
 877             gen7_mfd_avc_directmode_state(ctx, decode_state, pic_param, slice_param, gen7_mfd_context);
 878             gen7_mfd_avc_ref_idx_state(ctx, pic_param, slice_param, gen7_mfd_context);
 879             gen7_mfd_avc_weightoffset_state(ctx, pic_param, slice_param, gen7_mfd_context);
 880             gen7_mfd_avc_slice_state(ctx, pic_param, slice_param, next_slice_param, gen7_mfd_context);
 881             gen7_mfd_avc_bsd_object(ctx, pic_param, slice_param, slice_data_bo, next_slice_param, gen7_mfd_context);
 882             slice_param++;
 883         }
 884     }
 885
 886     intel_batchbuffer_end_atomic(batch);
 887     intel_batchbuffer_flush(batch);
 888 }
 889
 890 static void
 891 gen7_mfd_mpeg2_decode_init(VADriverContextP ctx,
 892                            struct decode_state *decode_state,
 893                            struct gen7_mfd_context *gen7_mfd_context)
 894 {
 895     VAPictureParameterBufferMPEG2 *pic_param;
 896     struct i965_driver_data *i965 = i965_driver_data(ctx);
 897     struct object_surface *obj_surface;
 898     dri_bo *bo;
 899     unsigned int width_in_mbs;
 900
 901     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 902     pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
 903     width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16;
 904
 905     mpeg2_set_reference_surfaces(
 906         ctx,
 907         gen7_mfd_context->reference_surface,
 908         decode_state,
 909         pic_param
 910     );
 911
 912     /* Current decoded picture */
 913     obj_surface = decode_state->render_object;
 914     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
 915
 916     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
 917     gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
 918     dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
 919     gen7_mfd_context->pre_deblocking_output.valid = 1;
 920
 921     dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
 922     bo = dri_bo_alloc(i965->intel.bufmgr,
 923                       "bsd mpc row store",
 924                       width_in_mbs * 96,
 925                       0x1000);
 926     assert(bo);
 927     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
 928     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
 929
 930     gen7_mfd_context->post_deblocking_output.valid = 0;
 931     gen7_mfd_context->intra_row_store_scratch_buffer.valid = 0;
 932     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 0;
 933     gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
 934     gen7_mfd_context->bitplane_read_buffer.valid = 0;
 935 }
 936
 937 static void
 938 gen7_mfd_mpeg2_pic_state(VADriverContextP ctx,
 939                          struct decode_state *decode_state,
 940                          struct gen7_mfd_context *gen7_mfd_context)
 941 {
 942     struct i965_driver_data * const i965 = i965_driver_data(ctx);
 943     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 944     VAPictureParameterBufferMPEG2 *pic_param;
 945     unsigned int slice_concealment_disable_bit = 0;
 946
 947     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 948     pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
 949
 950     if (IS_HASWELL(i965->intel.device_info)) {
 951         /* XXX: disable concealment for now */
 952         slice_concealment_disable_bit = 1;
 953     }
 954
 955     BEGIN_BCS_BATCH(batch, 13);
 956     OUT_BCS_BATCH(batch, MFX_MPEG2_PIC_STATE | (13 - 2));
 957     OUT_BCS_BATCH(batch,
 958                   (pic_param->f_code & 0xf) << 28 | /* f_code[1][1] */
 959                   ((pic_param->f_code >> 4) & 0xf) << 24 | /* f_code[1][0] */
 960                   ((pic_param->f_code >> 8) & 0xf) << 20 | /* f_code[0][1] */
 961                   ((pic_param->f_code >> 12) & 0xf) << 16 | /* f_code[0][0] */
 962                   pic_param->picture_coding_extension.bits.intra_dc_precision << 14 |
 963                   pic_param->picture_coding_extension.bits.picture_structure << 12 |
 964                   pic_param->picture_coding_extension.bits.top_field_first << 11 |
 965                   pic_param->picture_coding_extension.bits.frame_pred_frame_dct << 10 |
 966                   pic_param->picture_coding_extension.bits.concealment_motion_vectors << 9 |
 967                   pic_param->picture_coding_extension.bits.q_scale_type << 8 |
 968                   pic_param->picture_coding_extension.bits.intra_vlc_format << 7 |
 969                   pic_param->picture_coding_extension.bits.alternate_scan << 6);
 970     OUT_BCS_BATCH(batch,
 971                   pic_param->picture_coding_type << 9);
 972     OUT_BCS_BATCH(batch,
 973                   (slice_concealment_disable_bit << 31) |
 974                   ((ALIGN(pic_param->vertical_size, 16) / 16) - 1) << 16 |
 975                   ((ALIGN(pic_param->horizontal_size, 16) / 16) - 1));
 976     OUT_BCS_BATCH(batch, 0);
 977     OUT_BCS_BATCH(batch, 0);
 978     OUT_BCS_BATCH(batch, 0);
 979     OUT_BCS_BATCH(batch, 0);
 980     OUT_BCS_BATCH(batch, 0);
 981     OUT_BCS_BATCH(batch, 0);
 982     OUT_BCS_BATCH(batch, 0);
 983     OUT_BCS_BATCH(batch, 0);
 984     OUT_BCS_BATCH(batch, 0);
 985     ADVANCE_BCS_BATCH(batch);
 986 }
 987
 988 static void
 989 gen7_mfd_mpeg2_qm_state(VADriverContextP ctx,
 990                         struct decode_state *decode_state,
 991                         struct gen7_mfd_context *gen7_mfd_context)
 992 {
 993     VAIQMatrixBufferMPEG2 * const gen_iq_matrix = &gen7_mfd_context->iq_matrix.mpeg2;
 994     int i, j;
 995
 996     /* Update internal QM state */
 997     if (decode_state->iq_matrix && decode_state->iq_matrix->buffer) {
 998         VAIQMatrixBufferMPEG2 * const iq_matrix =
 999             (VAIQMatrixBufferMPEG2 *)decode_state->iq_matrix->buffer;
1000
1001         if (gen_iq_matrix->load_intra_quantiser_matrix == -1 ||
1002             iq_matrix->load_intra_quantiser_matrix) {
1003             gen_iq_matrix->load_intra_quantiser_matrix =
1004                 iq_matrix->load_intra_quantiser_matrix;
1005             if (iq_matrix->load_intra_quantiser_matrix) {
1006                 for (j = 0; j < 64; j++)
1007                     gen_iq_matrix->intra_quantiser_matrix[zigzag_direct[j]] =
1008                         iq_matrix->intra_quantiser_matrix[j];
1009             }
1010         }
1011
1012         if (gen_iq_matrix->load_non_intra_quantiser_matrix == -1 ||
1013             iq_matrix->load_non_intra_quantiser_matrix) {
1014             gen_iq_matrix->load_non_intra_quantiser_matrix =
1015                 iq_matrix->load_non_intra_quantiser_matrix;
1016             if (iq_matrix->load_non_intra_quantiser_matrix) {
1017                 for (j = 0; j < 64; j++)
1018                     gen_iq_matrix->non_intra_quantiser_matrix[zigzag_direct[j]] =
1019                         iq_matrix->non_intra_quantiser_matrix[j];
1020             }
1021         }
1022     }
1023
1024     /* Commit QM state to HW */
1025     for (i = 0; i < 2; i++) {
1026         unsigned char *qm = NULL;
1027         int qm_type;
1028
1029         if (i == 0) {
1030             if (gen_iq_matrix->load_intra_quantiser_matrix) {
1031                 qm = gen_iq_matrix->intra_quantiser_matrix;
1032                 qm_type = MFX_QM_MPEG_INTRA_QUANTIZER_MATRIX;
1033             }
1034         } else {
1035             if (gen_iq_matrix->load_non_intra_quantiser_matrix) {
1036                 qm = gen_iq_matrix->non_intra_quantiser_matrix;
1037                 qm_type = MFX_QM_MPEG_NON_INTRA_QUANTIZER_MATRIX;
1038             }
1039         }
1040
1041         if (!qm)
1042             continue;
1043
1044         gen7_mfd_qm_state(ctx, qm_type, qm, 64, gen7_mfd_context);
1045     }
1046 }
1047
1048 uint32_t mpeg2_get_slice_data_length(dri_bo *slice_data_bo, VASliceParameterBufferMPEG2 *slice_param)
1049 {
1050     uint8_t *buf;
1051     uint32_t buf_offset = slice_param->slice_data_offset + (slice_param->macroblock_offset >> 3);
1052     uint32_t buf_size = slice_param->slice_data_size - (slice_param->macroblock_offset >> 3);
1053     uint32_t i = 0;
1054
1055     dri_bo_map(slice_data_bo, 0);
1056     buf = (uint8_t *)slice_data_bo->virtual + buf_offset;
1057
1058     if (buf_size < 4)
1059         return buf_size;
1060
1061     while (i <= (buf_size - 4)) {
1062         if (buf[i + 2] > 1) {
1063             i += 3;
1064         } else if (buf[i + 1]) {
1065             i += 2;
1066         } else if (buf[i] || buf[i + 2] != 1) {
1067             i++;
1068         } else {
1069             break;
1070         }
1071     }
1072
1073     if (i <= (buf_size - 4))
1074         buf_size = i;
1075
1076     dri_bo_unmap(slice_data_bo);
1077     return buf_size;
1078 }
1079
1080 static void
1081 gen7_mfd_mpeg2_bsd_object(VADriverContextP ctx,
1082                           VAPictureParameterBufferMPEG2 *pic_param,
1083                           VASliceParameterBufferMPEG2 *slice_param,
1084                           dri_bo *slice_data_bo,
1085                           VASliceParameterBufferMPEG2 *next_slice_param,
1086                           struct gen7_mfd_context *gen7_mfd_context)
1087 {
1088     struct i965_driver_data * const i965 = i965_driver_data(ctx);
1089     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1090     unsigned int width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16;
1091     int mb_count, vpos0, hpos0, vpos1, hpos1, is_field_pic_wa, is_field_pic = 0;
1092
1093     if (pic_param->picture_coding_extension.bits.picture_structure == MPEG_TOP_FIELD ||
1094         pic_param->picture_coding_extension.bits.picture_structure == MPEG_BOTTOM_FIELD)
1095         is_field_pic = 1;
1096     is_field_pic_wa = is_field_pic &&
1097                       gen7_mfd_context->wa_mpeg2_slice_vertical_position > 0;
1098
1099     vpos0 = slice_param->slice_vertical_position / (1 + is_field_pic_wa);
1100     hpos0 = slice_param->slice_horizontal_position;
1101
1102     if (next_slice_param == NULL) {
1103         vpos1 = ALIGN(pic_param->vertical_size, 16) / 16 / (1 + is_field_pic);
1104         hpos1 = 0;
1105     } else {
1106         vpos1 = next_slice_param->slice_vertical_position / (1 + is_field_pic_wa);
1107         hpos1 = next_slice_param->slice_horizontal_position;
1108     }
1109
1110     mb_count = (vpos1 * width_in_mbs + hpos1) - (vpos0 * width_in_mbs + hpos0);
1111
1112     BEGIN_BCS_BATCH(batch, 5);
1113     OUT_BCS_BATCH(batch, MFD_MPEG2_BSD_OBJECT | (5 - 2));
1114     OUT_BCS_BATCH(batch,
1115                   mpeg2_get_slice_data_length(slice_data_bo, slice_param));
1116     OUT_BCS_BATCH(batch,
1117                   slice_param->slice_data_offset + (slice_param->macroblock_offset >> 3));
1118     OUT_BCS_BATCH(batch,
1119                   hpos0 << 24 |
1120                   vpos0 << 16 |
1121                   mb_count << 8 |
1122                   (next_slice_param == NULL) << 5 |
1123                   (next_slice_param == NULL) << 3 |
1124                   (slice_param->macroblock_offset & 0x7));
1125     OUT_BCS_BATCH(batch,
1126                   (slice_param->quantiser_scale_code << 24) |
1127                   (IS_HASWELL(i965->intel.device_info) ? (vpos1 << 8 | hpos1) : 0));
1128     ADVANCE_BCS_BATCH(batch);
1129 }
1130
1131 static void
1132 gen7_mfd_mpeg2_decode_picture(VADriverContextP ctx,
1133                               struct decode_state *decode_state,
1134                               struct gen7_mfd_context *gen7_mfd_context)
1135 {
1136     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1137     VAPictureParameterBufferMPEG2 *pic_param;
1138     VASliceParameterBufferMPEG2 *slice_param, *next_slice_param, *next_slice_group_param;
1139     dri_bo *slice_data_bo;
1140     int i, j;
1141
1142     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1143     pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
1144
1145     gen7_mfd_mpeg2_decode_init(ctx, decode_state, gen7_mfd_context);
1146     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
1147     intel_batchbuffer_emit_mi_flush(batch);
1148     gen7_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1149     gen7_mfd_surface_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1150     gen7_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1151     gen7_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1152     gen7_mfd_mpeg2_pic_state(ctx, decode_state, gen7_mfd_context);
1153     gen7_mfd_mpeg2_qm_state(ctx, decode_state, gen7_mfd_context);
1154
1155     if (gen7_mfd_context->wa_mpeg2_slice_vertical_position < 0)
1156         gen7_mfd_context->wa_mpeg2_slice_vertical_position =
1157             mpeg2_wa_slice_vertical_position(decode_state, pic_param);
1158
1159     for (j = 0; j < decode_state->num_slice_params; j++) {
1160         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
1161         slice_param = (VASliceParameterBufferMPEG2 *)decode_state->slice_params[j]->buffer;
1162         slice_data_bo = decode_state->slice_datas[j]->bo;
1163         gen7_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_MPEG2, gen7_mfd_context);
1164
1165         if (j == decode_state->num_slice_params - 1)
1166             next_slice_group_param = NULL;
1167         else
1168             next_slice_group_param = (VASliceParameterBufferMPEG2 *)decode_state->slice_params[j + 1]->buffer;
1169
1170         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
1171             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
1172
1173             if (i < decode_state->slice_params[j]->num_elements - 1)
1174                 next_slice_param = slice_param + 1;
1175             else
1176                 next_slice_param = next_slice_group_param;
1177
1178             gen7_mfd_mpeg2_bsd_object(ctx, pic_param, slice_param, slice_data_bo, next_slice_param, gen7_mfd_context);
1179             slice_param++;
1180         }
1181     }
1182
1183     intel_batchbuffer_end_atomic(batch);
1184     intel_batchbuffer_flush(batch);
1185 }
1186
1187 static const int va_to_gen7_vc1_mv[4] = {
1188     1, /* 1-MV */
1189     2, /* 1-MV half-pel */
1190     3, /* 1-MV half-pef bilinear */
1191     0, /* Mixed MV */
1192 };
1193
1194 static const int b_picture_scale_factor[21] = {
1195     128, 85,  170, 64,  192,
1196     51,  102, 153, 204, 43,
1197     215, 37,  74,  111, 148,
1198     185, 222, 32,  96,  160,
1199     224,
1200 };
1201
1202 static const int va_to_gen7_vc1_condover[3] = {
1203     0,
1204     2,
1205     3
1206 };
1207
1208 static const int va_to_gen7_vc1_profile[4] = {
1209     GEN7_VC1_SIMPLE_PROFILE,
1210     GEN7_VC1_MAIN_PROFILE,
1211     GEN7_VC1_RESERVED_PROFILE,
1212     GEN7_VC1_ADVANCED_PROFILE
1213 };
1214
1215 static void
1216 gen7_mfd_free_vc1_surface(void **data)
1217 {
1218     struct gen7_vc1_surface *gen7_vc1_surface = *data;
1219
1220     if (!gen7_vc1_surface)
1221         return;
1222
1223     dri_bo_unreference(gen7_vc1_surface->dmv);
1224     free(gen7_vc1_surface);
1225     *data = NULL;
1226 }
1227
1228 static void
1229 gen7_mfd_init_vc1_surface(VADriverContextP ctx,
1230                           VAPictureParameterBufferVC1 *pic_param,
1231                           struct object_surface *obj_surface)
1232 {
1233     struct i965_driver_data *i965 = i965_driver_data(ctx);
1234     struct gen7_vc1_surface *gen7_vc1_surface = obj_surface->private_data;
1235     int height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16;
1236
1237     obj_surface->free_private_data = gen7_mfd_free_vc1_surface;
1238
1239     if (!gen7_vc1_surface) {
1240         gen7_vc1_surface = calloc(sizeof(struct gen7_vc1_surface), 1);
1241         assert(gen7_vc1_surface);
1242         assert((obj_surface->size & 0x3f) == 0);
1243         obj_surface->private_data = gen7_vc1_surface;
1244     }
1245
1246     gen7_vc1_surface->picture_type = pic_param->picture_fields.bits.picture_type;
1247     gen7_vc1_surface->intensity_compensation = 0;
1248     gen7_vc1_surface->luma_scale = 0;
1249     gen7_vc1_surface->luma_shift = 0;
1250
1251     if (gen7_vc1_surface->dmv == NULL) {
1252         gen7_vc1_surface->dmv = dri_bo_alloc(i965->intel.bufmgr,
1253                                              "direct mv w/r buffer",
1254                                              128 * height_in_mbs * 64,
1255                                              0x1000);
1256     }
1257 }
1258
1259 static void
1260 gen7_mfd_vc1_decode_init(VADriverContextP ctx,
1261                          struct decode_state *decode_state,
1262                          struct gen7_mfd_context *gen7_mfd_context)
1263 {
1264     VAPictureParameterBufferVC1 *pic_param;
1265     struct i965_driver_data *i965 = i965_driver_data(ctx);
1266     struct object_surface *obj_surface;
1267     dri_bo *bo;
1268     int width_in_mbs;
1269     int picture_type;
1270     int intensity_compensation;
1271
1272     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1273     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1274     width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1275     picture_type = pic_param->picture_fields.bits.picture_type;
1276     intensity_compensation = (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation);
1277
1278     intel_update_vc1_frame_store_index(ctx,
1279                                        decode_state,
1280                                        pic_param,
1281                                        gen7_mfd_context->reference_surface);
1282
1283     /* Forward reference picture */
1284     obj_surface = decode_state->reference_objects[0];
1285     if (pic_param->forward_reference_picture != VA_INVALID_ID &&
1286         obj_surface &&
1287         obj_surface->private_data) {
1288         if (picture_type == 1 && intensity_compensation) { /* P picture */
1289             struct gen7_vc1_surface *gen7_vc1_surface = obj_surface->private_data;
1290
1291             gen7_vc1_surface->intensity_compensation = intensity_compensation;
1292             gen7_vc1_surface->luma_scale = pic_param->luma_scale;
1293             gen7_vc1_surface->luma_shift = pic_param->luma_shift;
1294         }
1295     }
1296
1297     /* Current decoded picture */
1298     obj_surface = decode_state->render_object;
1299     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
1300     gen7_mfd_init_vc1_surface(ctx, pic_param, obj_surface);
1301
1302     dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo);
1303     gen7_mfd_context->post_deblocking_output.bo = obj_surface->bo;
1304     dri_bo_reference(gen7_mfd_context->post_deblocking_output.bo);
1305     gen7_mfd_context->post_deblocking_output.valid = pic_param->entrypoint_fields.bits.loopfilter;
1306
1307     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
1308     gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
1309     dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
1310     gen7_mfd_context->pre_deblocking_output.valid = !pic_param->entrypoint_fields.bits.loopfilter;
1311
1312     dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo);
1313     bo = dri_bo_alloc(i965->intel.bufmgr,
1314                       "intra row store",
1315                       width_in_mbs * 64,
1316                       0x1000);
1317     assert(bo);
1318     gen7_mfd_context->intra_row_store_scratch_buffer.bo = bo;
1319     gen7_mfd_context->intra_row_store_scratch_buffer.valid = 1;
1320
1321     dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
1322     bo = dri_bo_alloc(i965->intel.bufmgr,
1323                       "deblocking filter row store",
1324                       width_in_mbs * 7 * 64,
1325                       0x1000);
1326     assert(bo);
1327     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
1328     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1;
1329
1330     dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
1331     bo = dri_bo_alloc(i965->intel.bufmgr,
1332                       "bsd mpc row store",
1333                       width_in_mbs * 96,
1334                       0x1000);
1335     assert(bo);
1336     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
1337     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
1338
1339     gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
1340
1341     if (picture_type == GEN7_VC1_SKIPPED_PICTURE)
1342         gen7_mfd_context->bitplane_read_buffer.valid = 1;
1343     else
1344         gen7_mfd_context->bitplane_read_buffer.valid = !!(pic_param->bitplane_present.value & 0x7f);
1345     dri_bo_unreference(gen7_mfd_context->bitplane_read_buffer.bo);
1346
1347     if (gen7_mfd_context->bitplane_read_buffer.valid) {
1348         int width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1349         int height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16;
1350         int bitplane_width = ALIGN(width_in_mbs, 2) / 2;
1351         int src_w, src_h;
1352         uint8_t *src = NULL, *dst = NULL;
1353
1354         bo = dri_bo_alloc(i965->intel.bufmgr,
1355                           "VC-1 Bitplane",
1356                           bitplane_width * height_in_mbs,
1357                           0x1000);
1358         assert(bo);
1359         gen7_mfd_context->bitplane_read_buffer.bo = bo;
1360
1361         dri_bo_map(bo, True);
1362         assert(bo->virtual);
1363         dst = bo->virtual;
1364
1365         if (picture_type == GEN7_VC1_SKIPPED_PICTURE) {
1366             for (src_h = 0; src_h < height_in_mbs; src_h++) {
1367                 for (src_w = 0; src_w < width_in_mbs; src_w++) {
1368                     int dst_index;
1369                     uint8_t src_value = 0x2;
1370
1371                     dst_index = src_w / 2;
1372                     dst[dst_index] = ((dst[dst_index] >> 4) | (src_value << 4));
1373                 }
1374
1375                 if (src_w & 1)
1376                     dst[src_w / 2] >>= 4;
1377
1378                 dst += bitplane_width;
1379             }
1380         } else {
1381             assert(decode_state->bit_plane->buffer);
1382             src = decode_state->bit_plane->buffer;
1383
1384             for (src_h = 0; src_h < height_in_mbs; src_h++) {
1385                 for (src_w = 0; src_w < width_in_mbs; src_w++) {
1386                     int src_index, dst_index;
1387                     int src_shift;
1388                     uint8_t src_value;
1389
1390                     src_index = (src_h * width_in_mbs + src_w) / 2;
1391                     src_shift = !((src_h * width_in_mbs + src_w) & 1) * 4;
1392                     src_value = ((src[src_index] >> src_shift) & 0xf);
1393
1394                     dst_index = src_w / 2;
1395                     dst[dst_index] = ((dst[dst_index] >> 4) | (src_value << 4));
1396                 }
1397
1398                 if (src_w & 1)
1399                     dst[src_w / 2] >>= 4;
1400
1401                 dst += bitplane_width;
1402             }
1403         }
1404
1405         dri_bo_unmap(bo);
1406     } else
1407         gen7_mfd_context->bitplane_read_buffer.bo = NULL;
1408 }
1409
1410 static void
1411 gen7_mfd_vc1_pic_state(VADriverContextP ctx,
1412                        struct decode_state *decode_state,
1413                        struct gen7_mfd_context *gen7_mfd_context)
1414 {
1415     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1416     VAPictureParameterBufferVC1 *pic_param;
1417     struct object_surface *obj_surface;
1418     int alt_pquant_config = 0, alt_pquant_edge_mask = 0, alt_pq;
1419     int dquant, dquantfrm, dqprofile, dqdbedge, dqsbedge, dqbilevel;
1420     int unified_mv_mode;
1421     int ref_field_pic_polarity = 0;
1422     int scale_factor = 0;
1423     int trans_ac_y = 0;
1424     int dmv_surface_valid = 0;
1425     int brfd = 0;
1426     int fcm = 0;
1427     int picture_type;
1428     int ptype;
1429     int profile;
1430     int overlap = 0;
1431     int interpolation_mode = 0;
1432
1433     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1434     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1435
1436     picture_type = pic_param->picture_fields.bits.picture_type;
1437
1438     profile = va_to_gen7_vc1_profile[pic_param->sequence_fields.bits.profile];
1439     dquant = pic_param->pic_quantizer_fields.bits.dquant;
1440     dquantfrm = pic_param->pic_quantizer_fields.bits.dq_frame;
1441     dqprofile = pic_param->pic_quantizer_fields.bits.dq_profile;
1442     dqdbedge = pic_param->pic_quantizer_fields.bits.dq_db_edge;
1443     dqsbedge = pic_param->pic_quantizer_fields.bits.dq_sb_edge;
1444     dqbilevel = pic_param->pic_quantizer_fields.bits.dq_binary_level;
1445     alt_pq = pic_param->pic_quantizer_fields.bits.alt_pic_quantizer;
1446
1447     if (dquant == 0) {
1448         alt_pquant_config = 0;
1449         alt_pquant_edge_mask = 0;
1450     } else if (dquant == 2) {
1451         alt_pquant_config = 1;
1452         alt_pquant_edge_mask = 0xf;
1453     } else {
1454         assert(dquant == 1);
1455         if (dquantfrm == 0) {
1456             alt_pquant_config = 0;
1457             alt_pquant_edge_mask = 0;
1458             alt_pq = 0;
1459         } else {
1460             assert(dquantfrm == 1);
1461             alt_pquant_config = 1;
1462
1463             switch (dqprofile) {
1464             case 3:
1465                 if (dqbilevel == 0) {
1466                     alt_pquant_config = 2;
1467                     alt_pquant_edge_mask = 0;
1468                 } else {
1469                     assert(dqbilevel == 1);
1470                     alt_pquant_config = 3;
1471                     alt_pquant_edge_mask = 0;
1472                 }
1473                 break;
1474
1475             case 0:
1476                 alt_pquant_edge_mask = 0xf;
1477                 break;
1478
1479             case 1:
1480                 if (dqdbedge == 3)
1481                     alt_pquant_edge_mask = 0x9;
1482                 else
1483                     alt_pquant_edge_mask = (0x3 << dqdbedge);
1484
1485                 break;
1486
1487             case 2:
1488                 alt_pquant_edge_mask = (0x1 << dqsbedge);
1489                 break;
1490
1491             default:
1492                 assert(0);
1493             }
1494         }
1495     }
1496
1497     if (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation) {
1498         assert(pic_param->mv_fields.bits.mv_mode2 < 4);
1499         unified_mv_mode = va_to_gen7_vc1_mv[pic_param->mv_fields.bits.mv_mode2];
1500     } else {
1501         assert(pic_param->mv_fields.bits.mv_mode < 4);
1502         unified_mv_mode = va_to_gen7_vc1_mv[pic_param->mv_fields.bits.mv_mode];
1503     }
1504
1505     if (pic_param->sequence_fields.bits.interlace == 1 &&
1506         pic_param->picture_fields.bits.frame_coding_mode != 0) { /* frame-interlace or field-interlace */
1507         /* FIXME: calculate reference field picture polarity */
1508         assert(0);
1509         ref_field_pic_polarity = 0;
1510     }
1511
1512     if (pic_param->b_picture_fraction < 21)
1513         scale_factor = b_picture_scale_factor[pic_param->b_picture_fraction];
1514
1515     if (picture_type == GEN7_VC1_SKIPPED_PICTURE)
1516         ptype = GEN7_VC1_P_PICTURE;
1517     else
1518         ptype = pic_param->picture_fields.bits.picture_type;
1519
1520     if (profile == GEN7_VC1_ADVANCED_PROFILE &&
1521         picture_type == GEN7_VC1_I_PICTURE)
1522         picture_type = GEN7_VC1_BI_PICTURE;
1523
1524     if (picture_type == GEN7_VC1_I_PICTURE || picture_type == GEN7_VC1_BI_PICTURE) /* I picture */
1525         trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx2;
1526     else {
1527         trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx1;
1528         /*
1529          * 8.3.6.2.1 Transform Type Selection
1530          * If variable-sized transform coding is not enabled,
1531          * then the 8x8 transform shall be used for all blocks.
1532          * it is also MFX_VC1_PIC_STATE requirement.
1533          */
1534         if (pic_param->transform_fields.bits.variable_sized_transform_flag == 0) {
1535             pic_param->transform_fields.bits.mb_level_transform_type_flag   = 1;
1536             pic_param->transform_fields.bits.frame_level_transform_type     = 0;
1537         }
1538     }
1539
1540
1541     if (picture_type == GEN7_VC1_B_PICTURE) {
1542         struct gen7_vc1_surface *gen7_vc1_surface = NULL;
1543
1544         obj_surface = decode_state->reference_objects[1];
1545
1546         if (obj_surface)
1547             gen7_vc1_surface = obj_surface->private_data;
1548
1549         if (!gen7_vc1_surface ||
1550             (gen7_vc1_surface->picture_type == GEN7_VC1_I_PICTURE ||
1551              gen7_vc1_surface->picture_type == GEN7_VC1_BI_PICTURE))
1552             dmv_surface_valid = 0;
1553         else
1554             dmv_surface_valid = 1;
1555     }
1556
1557     assert(pic_param->picture_fields.bits.frame_coding_mode < 3);
1558
1559     if (pic_param->picture_fields.bits.frame_coding_mode < 2)
1560         fcm = pic_param->picture_fields.bits.frame_coding_mode;
1561     else {
1562         if (pic_param->picture_fields.bits.top_field_first)
1563             fcm = 2;
1564         else
1565             fcm = 3;
1566     }
1567
1568     if (picture_type == GEN7_VC1_B_PICTURE) { /* B picture */
1569         brfd = pic_param->reference_fields.bits.reference_distance;
1570         brfd = (scale_factor * brfd) >> 8;
1571         brfd = pic_param->reference_fields.bits.reference_distance - brfd - 1;
1572
1573         if (brfd < 0)
1574             brfd = 0;
1575     }
1576
1577     if (pic_param->sequence_fields.bits.overlap) {
1578         if (profile == GEN7_VC1_ADVANCED_PROFILE) {
1579             if (picture_type == GEN7_VC1_P_PICTURE &&
1580                 pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9) {
1581                 overlap = 1;
1582             }
1583             if (picture_type == GEN7_VC1_I_PICTURE ||
1584                 picture_type == GEN7_VC1_BI_PICTURE) {
1585                 if (pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9) {
1586                     overlap = 1;
1587                 } else if (pic_param->conditional_overlap_flag == 1 || /* all block boundaries */
1588                            pic_param->conditional_overlap_flag == 2) { /* coded by OVERFLAGSMB bitplane */
1589                     overlap = 1;
1590                 }
1591             }
1592         } else {
1593             if (pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9 &&
1594                 picture_type != GEN7_VC1_B_PICTURE) {
1595                 overlap = 1;
1596             }
1597         }
1598     }
1599
1600     assert(pic_param->conditional_overlap_flag < 3);
1601     assert(pic_param->mv_fields.bits.mv_table < 4); /* FIXME: interlace mode */
1602
1603     if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPelBilinear ||
1604         (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation &&
1605          pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPelBilinear))
1606         interpolation_mode = 9; /* Half-pel bilinear */
1607     else if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPel ||
1608              (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation &&
1609               pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPel))
1610         interpolation_mode = 1; /* Half-pel bicubic */
1611     else
1612         interpolation_mode = 0; /* Quarter-pel bicubic */
1613
1614     BEGIN_BCS_BATCH(batch, 6);
1615     OUT_BCS_BATCH(batch, MFD_VC1_LONG_PIC_STATE | (6 - 2));
1616     OUT_BCS_BATCH(batch,
1617                   (((ALIGN(pic_param->coded_height, 16) / 16) - 1) << 16) |
1618                   ((ALIGN(pic_param->coded_width, 16) / 16) - 1));
1619     OUT_BCS_BATCH(batch,
1620                   ((ALIGN(pic_param->coded_width, 16) / 16 + 1) / 2 - 1) << 24 |
1621                   dmv_surface_valid << 15 |
1622                   (pic_param->pic_quantizer_fields.bits.quantizer == 0) << 14 | /* implicit quantizer */
1623                   pic_param->rounding_control << 13 |
1624                   pic_param->sequence_fields.bits.syncmarker << 12 |
1625                   interpolation_mode << 8 |
1626                   0 << 7 | /* FIXME: scale up or down ??? */
1627                   pic_param->range_reduction_frame << 6 |
1628                   pic_param->entrypoint_fields.bits.loopfilter << 5 |
1629                   overlap << 4 |
1630                   !pic_param->picture_fields.bits.is_first_field << 3 |
1631                   (pic_param->sequence_fields.bits.profile == 3) << 0);
1632     OUT_BCS_BATCH(batch,
1633                   va_to_gen7_vc1_condover[pic_param->conditional_overlap_flag] << 29 |
1634                   ptype << 26 |
1635                   fcm << 24 |
1636                   alt_pq << 16 |
1637                   pic_param->pic_quantizer_fields.bits.pic_quantizer_scale << 8 |
1638                   scale_factor << 0);
1639     OUT_BCS_BATCH(batch,
1640                   unified_mv_mode << 28 |
1641                   pic_param->mv_fields.bits.four_mv_switch << 27 |
1642                   pic_param->fast_uvmc_flag << 26 |
1643                   ref_field_pic_polarity << 25 |
1644                   pic_param->reference_fields.bits.num_reference_pictures << 24 |
1645                   pic_param->reference_fields.bits.reference_distance << 20 |
1646                   pic_param->reference_fields.bits.reference_distance << 16 | /* FIXME: ??? */
1647                   pic_param->mv_fields.bits.extended_dmv_range << 10 |
1648                   pic_param->mv_fields.bits.extended_mv_range << 8 |
1649                   alt_pquant_edge_mask << 4 |
1650                   alt_pquant_config << 2 |
1651                   pic_param->pic_quantizer_fields.bits.half_qp << 1 |
1652                   pic_param->pic_quantizer_fields.bits.pic_quantizer_type << 0);
1653     OUT_BCS_BATCH(batch,
1654                   !!(pic_param->bitplane_present.value & 0x7f) << 31 |
1655                   pic_param->raw_coding.flags.forward_mb << 30 |
1656                   pic_param->raw_coding.flags.mv_type_mb << 29 |
1657                   pic_param->raw_coding.flags.skip_mb << 28 |
1658                   pic_param->raw_coding.flags.direct_mb << 27 |
1659                   pic_param->raw_coding.flags.overflags << 26 |
1660                   pic_param->raw_coding.flags.ac_pred << 25 |
1661                   pic_param->raw_coding.flags.field_tx << 24 |
1662                   pic_param->mv_fields.bits.mv_table << 20 |
1663                   pic_param->mv_fields.bits.four_mv_block_pattern_table << 18 |
1664                   pic_param->mv_fields.bits.two_mv_block_pattern_table << 16 |
1665                   pic_param->transform_fields.bits.frame_level_transform_type << 12 |
1666                   pic_param->transform_fields.bits.mb_level_transform_type_flag << 11 |
1667                   pic_param->mb_mode_table << 8 |
1668                   trans_ac_y << 6 |
1669                   pic_param->transform_fields.bits.transform_ac_codingset_idx1 << 4 |
1670                   pic_param->transform_fields.bits.intra_transform_dc_table << 3 |
1671                   pic_param->cbp_table << 0);
1672     ADVANCE_BCS_BATCH(batch);
1673 }
1674
1675 static void
1676 gen7_mfd_vc1_pred_pipe_state(VADriverContextP ctx,
1677                              struct decode_state *decode_state,
1678                              struct gen7_mfd_context *gen7_mfd_context)
1679 {
1680     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1681     VAPictureParameterBufferVC1 *pic_param;
1682     int picture_type;
1683     int intensitycomp_single_fwd = 0;
1684     int luma_scale1 = 0;
1685     int luma_shift1 = 0;
1686
1687     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1688     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1689     picture_type = pic_param->picture_fields.bits.picture_type;
1690
1691     if (gen7_mfd_context->reference_surface[0].surface_id != VA_INVALID_ID) {
1692         if (picture_type == 1 || picture_type == 2) { /* P/B picture */
1693             struct gen7_vc1_surface *gen7_vc1_surface = gen7_mfd_context->reference_surface[0].obj_surface->private_data;
1694             if (gen7_vc1_surface) {
1695                 intensitycomp_single_fwd = gen7_vc1_surface->intensity_compensation;
1696                 luma_scale1 = gen7_vc1_surface->luma_scale;
1697                 luma_shift1 = gen7_vc1_surface->luma_shift;
1698             }
1699         }
1700     }
1701
1702     BEGIN_BCS_BATCH(batch, 6);
1703     OUT_BCS_BATCH(batch, MFX_VC1_PRED_PIPE_STATE | (6 - 2));
1704     OUT_BCS_BATCH(batch,
1705                   0 << 14 | /* FIXME: double ??? */
1706                   0 << 12 |
1707                   intensitycomp_single_fwd << 10 |
1708                   0 << 8 |
1709                   0 << 4 | /* FIXME: interlace mode */
1710                   0);
1711     OUT_BCS_BATCH(batch,
1712                   luma_shift1 << 16 |
1713                   luma_scale1 << 0);
1714     OUT_BCS_BATCH(batch, 0);
1715     OUT_BCS_BATCH(batch, 0);
1716     OUT_BCS_BATCH(batch, 0);
1717     ADVANCE_BCS_BATCH(batch);
1718 }
1719
1720
1721 static void
1722 gen7_mfd_vc1_directmode_state(VADriverContextP ctx,
1723                               struct decode_state *decode_state,
1724                               struct gen7_mfd_context *gen7_mfd_context)
1725 {
1726     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1727     struct object_surface *obj_surface;
1728     dri_bo *dmv_read_buffer = NULL, *dmv_write_buffer = NULL;
1729
1730     obj_surface = decode_state->render_object;
1731
1732     if (obj_surface && obj_surface->private_data) {
1733         dmv_write_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv;
1734     }
1735
1736     obj_surface = decode_state->reference_objects[1];
1737
1738     if (obj_surface && obj_surface->private_data) {
1739         dmv_read_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv;
1740     }
1741
1742     BEGIN_BCS_BATCH(batch, 3);
1743     OUT_BCS_BATCH(batch, MFX_VC1_DIRECTMODE_STATE | (3 - 2));
1744
1745     if (dmv_write_buffer)
1746         OUT_BCS_RELOC(batch, dmv_write_buffer,
1747                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
1748                       0);
1749     else
1750         OUT_BCS_BATCH(batch, 0);
1751
1752     if (dmv_read_buffer)
1753         OUT_BCS_RELOC(batch, dmv_read_buffer,
1754                       I915_GEM_DOMAIN_INSTRUCTION, 0,
1755                       0);
1756     else
1757         OUT_BCS_BATCH(batch, 0);
1758
1759     ADVANCE_BCS_BATCH(batch);
1760 }
1761
1762 static int
1763 gen7_mfd_vc1_get_macroblock_bit_offset(uint8_t *buf, int in_slice_data_bit_offset, int profile)
1764 {
1765     int out_slice_data_bit_offset;
1766     int slice_header_size = in_slice_data_bit_offset / 8;
1767     int i, j;
1768
1769     if (profile != 3)
1770         out_slice_data_bit_offset = in_slice_data_bit_offset;
1771     else {
1772         for (i = 0, j = 0; i < slice_header_size; i++, j++) {
1773             if (!buf[j] && !buf[j + 1] && buf[j + 2] == 3 && buf[j + 3] < 4) {
1774                 if (i < slice_header_size - 1)
1775                     i++, j += 2;
1776                 else {
1777                     buf[j + 2] = buf[j + 1];
1778                     j++;
1779                 }
1780             }
1781         }
1782
1783         out_slice_data_bit_offset = 8 * j + in_slice_data_bit_offset % 8;
1784     }
1785
1786     return out_slice_data_bit_offset;
1787 }
1788
1789 static void
1790 gen7_mfd_vc1_bsd_object(VADriverContextP ctx,
1791                         VAPictureParameterBufferVC1 *pic_param,
1792                         VASliceParameterBufferVC1 *slice_param,
1793                         VASliceParameterBufferVC1 *next_slice_param,
1794                         dri_bo *slice_data_bo,
1795                         struct gen7_mfd_context *gen7_mfd_context)
1796 {
1797     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1798     int next_slice_start_vert_pos;
1799     int macroblock_offset;
1800     uint8_t *slice_data = NULL;
1801
1802     dri_bo_map(slice_data_bo, True);
1803     slice_data = (uint8_t *)(slice_data_bo->virtual + slice_param->slice_data_offset);
1804     macroblock_offset = gen7_mfd_vc1_get_macroblock_bit_offset(slice_data,
1805                                                                slice_param->macroblock_offset,
1806                                                                pic_param->sequence_fields.bits.profile);
1807     dri_bo_unmap(slice_data_bo);
1808
1809     if (next_slice_param)
1810         next_slice_start_vert_pos = next_slice_param->slice_vertical_position;
1811     else
1812         next_slice_start_vert_pos = ALIGN(pic_param->coded_height, 16) / 16;
1813
1814     BEGIN_BCS_BATCH(batch, 5);
1815     OUT_BCS_BATCH(batch, MFD_VC1_BSD_OBJECT | (5 - 2));
1816     OUT_BCS_BATCH(batch,
1817                   slice_param->slice_data_size - (macroblock_offset >> 3));
1818     OUT_BCS_BATCH(batch,
1819                   slice_param->slice_data_offset + (macroblock_offset >> 3));
1820     OUT_BCS_BATCH(batch,
1821                   slice_param->slice_vertical_position << 16 |
1822                   next_slice_start_vert_pos << 0);
1823     OUT_BCS_BATCH(batch,
1824                   (macroblock_offset & 0x7));
1825     ADVANCE_BCS_BATCH(batch);
1826 }
1827
1828 static void
1829 gen7_mfd_vc1_decode_picture(VADriverContextP ctx,
1830                             struct decode_state *decode_state,
1831                             struct gen7_mfd_context *gen7_mfd_context)
1832 {
1833     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1834     VAPictureParameterBufferVC1 *pic_param;
1835     VASliceParameterBufferVC1 *slice_param, *next_slice_param, *next_slice_group_param;
1836     dri_bo *slice_data_bo;
1837     int i, j;
1838
1839     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1840     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1841
1842     gen7_mfd_vc1_decode_init(ctx, decode_state, gen7_mfd_context);
1843     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
1844     intel_batchbuffer_emit_mi_flush(batch);
1845     gen7_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
1846     gen7_mfd_surface_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
1847     gen7_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
1848     gen7_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
1849     gen7_mfd_vc1_pic_state(ctx, decode_state, gen7_mfd_context);
1850     gen7_mfd_vc1_pred_pipe_state(ctx, decode_state, gen7_mfd_context);
1851     gen7_mfd_vc1_directmode_state(ctx, decode_state, gen7_mfd_context);
1852
1853     for (j = 0; j < decode_state->num_slice_params; j++) {
1854         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
1855         slice_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j]->buffer;
1856         slice_data_bo = decode_state->slice_datas[j]->bo;
1857         gen7_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_VC1, gen7_mfd_context);
1858
1859         if (j == decode_state->num_slice_params - 1)
1860             next_slice_group_param = NULL;
1861         else
1862             next_slice_group_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j + 1]->buffer;
1863
1864         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
1865             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
1866
1867             if (i < decode_state->slice_params[j]->num_elements - 1)
1868                 next_slice_param = slice_param + 1;
1869             else
1870                 next_slice_param = next_slice_group_param;
1871
1872             gen7_mfd_vc1_bsd_object(ctx, pic_param, slice_param, next_slice_param, slice_data_bo, gen7_mfd_context);
1873             slice_param++;
1874         }
1875     }
1876
1877     intel_batchbuffer_end_atomic(batch);
1878     intel_batchbuffer_flush(batch);
1879 }
1880
1881 static void
1882 gen7_mfd_jpeg_decode_init(VADriverContextP ctx,
1883                           struct decode_state *decode_state,
1884                           struct gen7_mfd_context *gen7_mfd_context)
1885 {
1886     struct object_surface *obj_surface;
1887     VAPictureParameterBufferJPEGBaseline *pic_param;
1888     int subsampling = SUBSAMPLE_YUV420;
1889     int fourcc = VA_FOURCC_IMC3;
1890
1891     pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
1892
1893     if (pic_param->num_components == 1) {
1894         subsampling = SUBSAMPLE_YUV400;
1895         fourcc = VA_FOURCC_Y800;
1896     } else if (pic_param->num_components == 3) {
1897         int h1 = pic_param->components[0].h_sampling_factor;
1898         int h2 = pic_param->components[1].h_sampling_factor;
1899         int h3 = pic_param->components[2].h_sampling_factor;
1900         int v1 = pic_param->components[0].v_sampling_factor;
1901         int v2 = pic_param->components[1].v_sampling_factor;
1902         int v3 = pic_param->components[2].v_sampling_factor;
1903
1904         if (h1 == 2 * h2 && h2 == h3 &&
1905             v1 == 2 * v2 && v2 == v3) {
1906             subsampling = SUBSAMPLE_YUV420;
1907             fourcc = VA_FOURCC_IMC3;
1908         } else if (h1 == 2 * h2  && h2 == h3 &&
1909                    v1 == v2 && v2 == v3) {
1910             subsampling = SUBSAMPLE_YUV422H;
1911             fourcc = VA_FOURCC_422H;
1912         } else if (h1 == h2 && h2 == h3 &&
1913                    v1 == v2  && v2 == v3) {
1914             subsampling = SUBSAMPLE_YUV444;
1915             fourcc = VA_FOURCC_444P;
1916         } else if (h1 == 4 * h2 && h2 ==  h3 &&
1917                    v1 == v2 && v2 == v3) {
1918             subsampling = SUBSAMPLE_YUV411;
1919             fourcc = VA_FOURCC_411P;
1920         } else if (h1 == h2 && h2 == h3 &&
1921                    v1 == 2 * v2 && v2 == v3) {
1922             subsampling = SUBSAMPLE_YUV422V;
1923             fourcc = VA_FOURCC_422V;
1924         } else
1925             assert(0);
1926     } else {
1927         assert(0);
1928     }
1929
1930     /* Current decoded picture */
1931     obj_surface = decode_state->render_object;
1932     i965_check_alloc_surface_bo(ctx, obj_surface, 1, fourcc, subsampling);
1933
1934     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
1935     gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
1936     dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
1937     gen7_mfd_context->pre_deblocking_output.valid = 1;
1938
1939     gen7_mfd_context->post_deblocking_output.bo = NULL;
1940     gen7_mfd_context->post_deblocking_output.valid = 0;
1941
1942     gen7_mfd_context->intra_row_store_scratch_buffer.bo = NULL;
1943     gen7_mfd_context->intra_row_store_scratch_buffer.valid = 0;
1944
1945     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
1946     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 0;
1947
1948     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
1949     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 0;
1950
1951     gen7_mfd_context->mpr_row_store_scratch_buffer.bo = NULL;
1952     gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
1953
1954     gen7_mfd_context->bitplane_read_buffer.bo = NULL;
1955     gen7_mfd_context->bitplane_read_buffer.valid = 0;
1956 }
1957
1958 static const int va_to_gen7_jpeg_rotation[4] = {
1959     GEN7_JPEG_ROTATION_0,
1960     GEN7_JPEG_ROTATION_90,
1961     GEN7_JPEG_ROTATION_180,
1962     GEN7_JPEG_ROTATION_270
1963 };
1964
1965 static void
1966 gen7_mfd_jpeg_pic_state(VADriverContextP ctx,
1967                         struct decode_state *decode_state,
1968                         struct gen7_mfd_context *gen7_mfd_context)
1969 {
1970     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1971     VAPictureParameterBufferJPEGBaseline *pic_param;
1972     int chroma_type = GEN7_YUV420;
1973     int frame_width_in_blks;
1974     int frame_height_in_blks;
1975
1976     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1977     pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
1978
1979     if (pic_param->num_components == 1)
1980         chroma_type = GEN7_YUV400;
1981     else if (pic_param->num_components == 3) {
1982         int h1 = pic_param->components[0].h_sampling_factor;
1983         int h2 = pic_param->components[1].h_sampling_factor;
1984         int h3 = pic_param->components[2].h_sampling_factor;
1985         int v1 = pic_param->components[0].v_sampling_factor;
1986         int v2 = pic_param->components[1].v_sampling_factor;
1987         int v3 = pic_param->components[2].v_sampling_factor;
1988
1989         if (h1 == 2 * h2 && h2 == h3 &&
1990             v1 == 2 * v2 && v2 == v3)
1991             chroma_type = GEN7_YUV420;
1992         else if (h1 == 2 && h2 == 1 && h3 == 1 &&
1993                  v1 == 1 && v2 == 1 && v3 == 1)
1994             chroma_type = GEN7_YUV422H_2Y;
1995         else if (h1 == h2 && h2 == h3 &&
1996                  v1 == v2 && v2 == v3)
1997             chroma_type = GEN7_YUV444;
1998         else if (h1 == 4 * h2 && h2 == h3 &&
1999                  v1 == v2 && v2 == v3)
2000             chroma_type = GEN7_YUV411;
2001         else if (h1 == 1 && h2 == 1 && h3 == 1 &&
2002                  v1 == 2 && v2 == 1 && v3 == 1)
2003             chroma_type = GEN7_YUV422V_2Y;
2004         else if (h1 == 2 && h2 == 1 && h3 == 1 &&
2005                  v1 == 2 && v2 == 2 && v3 == 2)
2006             chroma_type = GEN7_YUV422H_4Y;
2007         else if (h2 == 2 && h2 == 2 && h3 == 2 &&
2008                  v1 == 2 && v2 == 1 && v3 == 1)
2009             chroma_type = GEN7_YUV422V_4Y;
2010         else
2011             assert(0);
2012     }
2013
2014     if (chroma_type == GEN7_YUV400 ||
2015         chroma_type == GEN7_YUV444 ||
2016         chroma_type == GEN7_YUV422V_2Y) {
2017         frame_width_in_blks = ((pic_param->picture_width + 7) / 8);
2018         frame_height_in_blks = ((pic_param->picture_height + 7) / 8);
2019     } else if (chroma_type == GEN7_YUV411) {
2020         frame_width_in_blks = ((pic_param->picture_width + 31) / 32) * 4;
2021         frame_height_in_blks = ((pic_param->picture_height + 31) / 32) * 4;
2022     } else {
2023         frame_width_in_blks = ((pic_param->picture_width + 15) / 16) * 2;
2024         frame_height_in_blks = ((pic_param->picture_height + 15) / 16) * 2;
2025     }
2026
2027     BEGIN_BCS_BATCH(batch, 3);
2028     OUT_BCS_BATCH(batch, MFX_JPEG_PIC_STATE | (3 - 2));
2029     OUT_BCS_BATCH(batch,
2030                   (va_to_gen7_jpeg_rotation[0] << 4) |    /* without rotation */
2031                   (chroma_type << 0));
2032     OUT_BCS_BATCH(batch,
2033                   ((frame_height_in_blks - 1) << 16) |   /* FrameHeightInBlks */
2034                   ((frame_width_in_blks - 1) << 0));    /* FrameWidthInBlks */
2035     ADVANCE_BCS_BATCH(batch);
2036 }
2037
2038 static const int va_to_gen7_jpeg_hufftable[2] = {
2039     MFX_HUFFTABLE_ID_Y,
2040     MFX_HUFFTABLE_ID_UV
2041 };
2042
2043 static void
2044 gen7_mfd_jpeg_huff_table_state(VADriverContextP ctx,
2045                                struct decode_state *decode_state,
2046                                struct gen7_mfd_context *gen7_mfd_context,
2047                                int num_tables)
2048 {
2049     VAHuffmanTableBufferJPEGBaseline *huffman_table;
2050     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2051     int index;
2052
2053     if (!decode_state->huffman_table || !decode_state->huffman_table->buffer)
2054         return;
2055
2056     huffman_table = (VAHuffmanTableBufferJPEGBaseline *)decode_state->huffman_table->buffer;
2057
2058     for (index = 0; index < num_tables; index++) {
2059         int id = va_to_gen7_jpeg_hufftable[index];
2060         if (!huffman_table->load_huffman_table[index])
2061             continue;
2062         BEGIN_BCS_BATCH(batch, 53);
2063         OUT_BCS_BATCH(batch, MFX_JPEG_HUFF_TABLE_STATE | (53 - 2));
2064         OUT_BCS_BATCH(batch, id);
2065         intel_batchbuffer_data(batch, huffman_table->huffman_table[index].num_dc_codes, 12);
2066         intel_batchbuffer_data(batch, huffman_table->huffman_table[index].dc_values, 12);
2067         intel_batchbuffer_data(batch, huffman_table->huffman_table[index].num_ac_codes, 16);
2068         intel_batchbuffer_data(batch, huffman_table->huffman_table[index].ac_values, 164);
2069         ADVANCE_BCS_BATCH(batch);
2070     }
2071 }
2072
2073 static const int va_to_gen7_jpeg_qm[5] = {
2074     -1,
2075     MFX_QM_JPEG_LUMA_Y_QUANTIZER_MATRIX,
2076     MFX_QM_JPEG_CHROMA_CB_QUANTIZER_MATRIX,
2077     MFX_QM_JPEG_CHROMA_CR_QUANTIZER_MATRIX,
2078     MFX_QM_JPEG_ALPHA_QUANTIZER_MATRIX
2079 };
2080
2081 static void
2082 gen7_mfd_jpeg_qm_state(VADriverContextP ctx,
2083                        struct decode_state *decode_state,
2084                        struct gen7_mfd_context *gen7_mfd_context)
2085 {
2086     VAPictureParameterBufferJPEGBaseline *pic_param;
2087     VAIQMatrixBufferJPEGBaseline *iq_matrix;
2088     int index;
2089
2090     if (!decode_state->iq_matrix || !decode_state->iq_matrix->buffer)
2091         return;
2092
2093     iq_matrix = (VAIQMatrixBufferJPEGBaseline *)decode_state->iq_matrix->buffer;
2094     pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
2095
2096     assert(pic_param->num_components <= 3);
2097
2098     for (index = 0; index < pic_param->num_components; index++) {
2099         int id = pic_param->components[index].component_id - pic_param->components[0].component_id + 1;
2100         int qm_type;
2101         unsigned char *qm = iq_matrix->quantiser_table[pic_param->components[index].quantiser_table_selector];
2102         unsigned char raster_qm[64];
2103         int j;
2104
2105         if (id > 4 || id < 1)
2106             continue;
2107
2108         if (!iq_matrix->load_quantiser_table[pic_param->components[index].quantiser_table_selector])
2109             continue;
2110
2111         qm_type = va_to_gen7_jpeg_qm[id];
2112
2113         for (j = 0; j < 64; j++)
2114             raster_qm[zigzag_direct[j]] = qm[j];
2115
2116         gen7_mfd_qm_state(ctx, qm_type, raster_qm, 64, gen7_mfd_context);
2117     }
2118 }
2119
2120 static void
2121 gen7_mfd_jpeg_bsd_object(VADriverContextP ctx,
2122                          VAPictureParameterBufferJPEGBaseline *pic_param,
2123                          VASliceParameterBufferJPEGBaseline *slice_param,
2124                          VASliceParameterBufferJPEGBaseline *next_slice_param,
2125                          dri_bo *slice_data_bo,
2126                          struct gen7_mfd_context *gen7_mfd_context)
2127 {
2128     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2129     int scan_component_mask = 0;
2130     int i;
2131
2132     assert(slice_param->num_components > 0);
2133     assert(slice_param->num_components < 4);
2134     assert(slice_param->num_components <= pic_param->num_components);
2135
2136     for (i = 0; i < slice_param->num_components; i++) {
2137         switch (slice_param->components[i].component_selector - pic_param->components[0].component_id + 1) {
2138         case 1:
2139             scan_component_mask |= (1 << 0);
2140             break;
2141         case 2:
2142             scan_component_mask |= (1 << 1);
2143             break;
2144         case 3:
2145             scan_component_mask |= (1 << 2);
2146             break;
2147         default:
2148             assert(0);
2149             break;
2150         }
2151     }
2152
2153     BEGIN_BCS_BATCH(batch, 6);
2154     OUT_BCS_BATCH(batch, MFD_JPEG_BSD_OBJECT | (6 - 2));
2155     OUT_BCS_BATCH(batch,
2156                   slice_param->slice_data_size);
2157     OUT_BCS_BATCH(batch,
2158                   slice_param->slice_data_offset);
2159     OUT_BCS_BATCH(batch,
2160                   slice_param->slice_horizontal_position << 16 |
2161                   slice_param->slice_vertical_position << 0);
2162     OUT_BCS_BATCH(batch,
2163                   ((slice_param->num_components != 1) << 30) |  /* interleaved */
2164                   (scan_component_mask << 27) |                 /* scan components */
2165                   (0 << 26) |   /* disable interrupt allowed */
2166                   (slice_param->num_mcus << 0));                /* MCU count */
2167     OUT_BCS_BATCH(batch,
2168                   (slice_param->restart_interval << 0));    /* RestartInterval */
2169     ADVANCE_BCS_BATCH(batch);
2170 }
2171
2172 /* Workaround for JPEG decoding on Ivybridge */
2173
2174 static struct {
2175     int width;
2176     int height;
2177     unsigned char data[32];
2178     int data_size;
2179     int data_bit_offset;
2180     int qp;
2181 } gen7_jpeg_wa_clip = {
2182     16,
2183     16,
2184     {
2185         0x65, 0xb8, 0x40, 0x32, 0x13, 0xfd, 0x06, 0x6c,
2186         0xfc, 0x0a, 0x50, 0x71, 0x5c, 0x00
2187     },
2188     14,
2189     40,
2190     28,
2191 };
2192
2193 static void
2194 gen7_jpeg_wa_init(VADriverContextP ctx,
2195                   struct gen7_mfd_context *gen7_mfd_context)
2196 {
2197     struct i965_driver_data *i965 = i965_driver_data(ctx);
2198     VAStatus status;
2199     struct object_surface *obj_surface;
2200
2201     if (gen7_mfd_context->jpeg_wa_surface_id != VA_INVALID_SURFACE)
2202         i965_DestroySurfaces(ctx,
2203                              &gen7_mfd_context->jpeg_wa_surface_id,
2204                              1);
2205
2206     status = i965_CreateSurfaces(ctx,
2207                                  gen7_jpeg_wa_clip.width,
2208                                  gen7_jpeg_wa_clip.height,
2209                                  VA_RT_FORMAT_YUV420,
2210                                  1,
2211                                  &gen7_mfd_context->jpeg_wa_surface_id);
2212     assert(status == VA_STATUS_SUCCESS);
2213
2214     obj_surface = SURFACE(gen7_mfd_context->jpeg_wa_surface_id);
2215     assert(obj_surface);
2216     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
2217     gen7_mfd_context->jpeg_wa_surface_object = obj_surface;
2218
2219     if (!gen7_mfd_context->jpeg_wa_slice_data_bo) {
2220         gen7_mfd_context->jpeg_wa_slice_data_bo = dri_bo_alloc(i965->intel.bufmgr,
2221                                                                "JPEG WA data",
2222                                                                0x1000,
2223                                                                0x1000);
2224         dri_bo_subdata(gen7_mfd_context->jpeg_wa_slice_data_bo,
2225                        0,
2226                        gen7_jpeg_wa_clip.data_size,
2227                        gen7_jpeg_wa_clip.data);
2228     }
2229 }
2230
2231 static void
2232 gen7_jpeg_wa_pipe_mode_select(VADriverContextP ctx,
2233                               struct gen7_mfd_context *gen7_mfd_context)
2234 {
2235     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2236
2237     BEGIN_BCS_BATCH(batch, 5);
2238     OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2));
2239     OUT_BCS_BATCH(batch,
2240                   (MFX_LONG_MODE << 17) | /* Currently only support long format */
2241                   (MFD_MODE_VLD << 15) | /* VLD mode */
2242                   (0 << 10) | /* disable Stream-Out */
2243                   (0 << 9)  | /* Post Deblocking Output */
2244                   (1 << 8)  | /* Pre Deblocking Output */
2245                   (0 << 5)  | /* not in stitch mode */
2246                   (MFX_CODEC_DECODE << 4)  | /* decoding mode */
2247                   (MFX_FORMAT_AVC << 0));
2248     OUT_BCS_BATCH(batch,
2249                   (0 << 4)  | /* terminate if AVC motion and POC table error occurs */
2250                   (0 << 3)  | /* terminate if AVC mbdata error occurs */
2251                   (0 << 2)  | /* terminate if AVC CABAC/CAVLC decode error occurs */
2252                   (0 << 1)  |
2253                   (0 << 0));
2254     OUT_BCS_BATCH(batch, 0); /* pic status/error report id */
2255     OUT_BCS_BATCH(batch, 0); /* reserved */
2256     ADVANCE_BCS_BATCH(batch);
2257 }
2258
2259 static void
2260 gen7_jpeg_wa_surface_state(VADriverContextP ctx,
2261                            struct gen7_mfd_context *gen7_mfd_context)
2262 {
2263     struct object_surface *obj_surface = gen7_mfd_context->jpeg_wa_surface_object;
2264     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2265
2266     BEGIN_BCS_BATCH(batch, 6);
2267     OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
2268     OUT_BCS_BATCH(batch, 0);
2269     OUT_BCS_BATCH(batch,
2270                   ((obj_surface->orig_width - 1) << 18) |
2271                   ((obj_surface->orig_height - 1) << 4));
2272     OUT_BCS_BATCH(batch,
2273                   (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
2274                   (1 << 27) | /* interleave chroma, set to 0 for JPEG */
2275                   (0 << 22) | /* surface object control state, ignored */
2276                   ((obj_surface->width - 1) << 3) | /* pitch */
2277                   (0 << 2)  | /* must be 0 */
2278                   (1 << 1)  | /* must be tiled */
2279                   (I965_TILEWALK_YMAJOR << 0));  /* tile walk, must be 1 */
2280     OUT_BCS_BATCH(batch,
2281                   (0 << 16) | /* X offset for U(Cb), must be 0 */
2282                   (obj_surface->y_cb_offset << 0)); /* Y offset for U(Cb) */
2283     OUT_BCS_BATCH(batch,
2284                   (0 << 16) | /* X offset for V(Cr), must be 0 */
2285                   (0 << 0)); /* Y offset for V(Cr), must be 0 for video codec, non-zoro for JPEG */
2286     ADVANCE_BCS_BATCH(batch);
2287 }
2288
2289 static void
2290 gen7_jpeg_wa_pipe_buf_addr_state(VADriverContextP ctx,
2291                                  struct gen7_mfd_context *gen7_mfd_context)
2292 {
2293     struct i965_driver_data *i965 = i965_driver_data(ctx);
2294     struct object_surface *obj_surface = gen7_mfd_context->jpeg_wa_surface_object;
2295     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2296     dri_bo *intra_bo;
2297     int i;
2298
2299     intra_bo = dri_bo_alloc(i965->intel.bufmgr,
2300                             "intra row store",
2301                             128 * 64,
2302                             0x1000);
2303
2304     BEGIN_BCS_BATCH(batch, 24);
2305     OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
2306     OUT_BCS_RELOC(batch,
2307                   obj_surface->bo,
2308                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2309                   0);
2310
2311     OUT_BCS_BATCH(batch, 0); /* post deblocking */
2312
2313     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
2314     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
2315
2316     OUT_BCS_RELOC(batch,
2317                   intra_bo,
2318                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2319                   0);
2320
2321     OUT_BCS_BATCH(batch, 0);
2322
2323     /* DW 7..22 */
2324     for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
2325         OUT_BCS_BATCH(batch, 0);
2326     }
2327
2328     OUT_BCS_BATCH(batch, 0);   /* ignore DW23 for decoding */
2329     ADVANCE_BCS_BATCH(batch);
2330
2331     dri_bo_unreference(intra_bo);
2332 }
2333
2334 static void
2335 gen7_jpeg_wa_bsp_buf_base_addr_state(VADriverContextP ctx,
2336                                      struct gen7_mfd_context *gen7_mfd_context)
2337 {
2338     struct i965_driver_data *i965 = i965_driver_data(ctx);
2339     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2340     dri_bo *bsd_mpc_bo, *mpr_bo;
2341
2342     bsd_mpc_bo = dri_bo_alloc(i965->intel.bufmgr,
2343                               "bsd mpc row store",
2344                               11520, /* 1.5 * 120 * 64 */
2345                               0x1000);
2346
2347     mpr_bo = dri_bo_alloc(i965->intel.bufmgr,
2348                           "mpr row store",
2349                           7680, /* 1. 0 * 120 * 64 */
2350                           0x1000);
2351
2352     BEGIN_BCS_BATCH(batch, 4);
2353     OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
2354
2355     OUT_BCS_RELOC(batch,
2356                   bsd_mpc_bo,
2357                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2358                   0);
2359
2360     OUT_BCS_RELOC(batch,
2361                   mpr_bo,
2362                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2363                   0);
2364     OUT_BCS_BATCH(batch, 0);
2365
2366     ADVANCE_BCS_BATCH(batch);
2367
2368     dri_bo_unreference(bsd_mpc_bo);
2369     dri_bo_unreference(mpr_bo);
2370 }
2371
2372 static void
2373 gen7_jpeg_wa_avc_qm_state(VADriverContextP ctx,
2374                           struct gen7_mfd_context *gen7_mfd_context)
2375 {
2376
2377 }
2378
2379 static void
2380 gen7_jpeg_wa_avc_img_state(VADriverContextP ctx,
2381                            struct gen7_mfd_context *gen7_mfd_context)
2382 {
2383     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2384     int img_struct = 0;
2385     int mbaff_frame_flag = 0;
2386     unsigned int width_in_mbs = 1, height_in_mbs = 1;
2387
2388     BEGIN_BCS_BATCH(batch, 16);
2389     OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (16 - 2));
2390     OUT_BCS_BATCH(batch,
2391                   (width_in_mbs * height_in_mbs - 1));
2392     OUT_BCS_BATCH(batch,
2393                   ((height_in_mbs - 1) << 16) |
2394                   ((width_in_mbs - 1) << 0));
2395     OUT_BCS_BATCH(batch,
2396                   (0 << 24) |
2397                   (0 << 16) |
2398                   (0 << 14) |
2399                   (0 << 13) |
2400                   (0 << 12) | /* differ from GEN6 */
2401                   (0 << 10) |
2402                   (img_struct << 8));
2403     OUT_BCS_BATCH(batch,
2404                   (1 << 10) | /* 4:2:0 */
2405                   (1 << 7) |  /* CABAC */
2406                   (0 << 6) |
2407                   (0 << 5) |
2408                   (0 << 4) |
2409                   (0 << 3) |
2410                   (1 << 2) |
2411                   (mbaff_frame_flag << 1) |
2412                   (0 << 0));
2413     OUT_BCS_BATCH(batch, 0);
2414     OUT_BCS_BATCH(batch, 0);
2415     OUT_BCS_BATCH(batch, 0);
2416     OUT_BCS_BATCH(batch, 0);
2417     OUT_BCS_BATCH(batch, 0);
2418     OUT_BCS_BATCH(batch, 0);
2419     OUT_BCS_BATCH(batch, 0);
2420     OUT_BCS_BATCH(batch, 0);
2421     OUT_BCS_BATCH(batch, 0);
2422     OUT_BCS_BATCH(batch, 0);
2423     OUT_BCS_BATCH(batch, 0);
2424     ADVANCE_BCS_BATCH(batch);
2425 }
2426
2427 static void
2428 gen7_jpeg_wa_avc_directmode_state(VADriverContextP ctx,
2429                                   struct gen7_mfd_context *gen7_mfd_context)
2430 {
2431     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2432     int i;
2433
2434     BEGIN_BCS_BATCH(batch, 69);
2435     OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
2436
2437     /* reference surfaces 0..15 */
2438     for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
2439         OUT_BCS_BATCH(batch, 0); /* top */
2440         OUT_BCS_BATCH(batch, 0); /* bottom */
2441     }
2442
2443     /* the current decoding frame/field */
2444     OUT_BCS_BATCH(batch, 0); /* top */
2445     OUT_BCS_BATCH(batch, 0); /* bottom */
2446
2447     /* POC List */
2448     for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
2449         OUT_BCS_BATCH(batch, 0);
2450         OUT_BCS_BATCH(batch, 0);
2451     }
2452
2453     OUT_BCS_BATCH(batch, 0);
2454     OUT_BCS_BATCH(batch, 0);
2455
2456     ADVANCE_BCS_BATCH(batch);
2457 }
2458
2459 static void
2460 gen7_jpeg_wa_ind_obj_base_addr_state(VADriverContextP ctx,
2461                                      struct gen7_mfd_context *gen7_mfd_context)
2462 {
2463     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2464
2465     BEGIN_BCS_BATCH(batch, 11);
2466     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
2467     OUT_BCS_RELOC(batch,
2468                   gen7_mfd_context->jpeg_wa_slice_data_bo,
2469                   I915_GEM_DOMAIN_INSTRUCTION, 0,
2470                   0);
2471     OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
2472     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
2473     OUT_BCS_BATCH(batch, 0);
2474     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
2475     OUT_BCS_BATCH(batch, 0);
2476     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
2477     OUT_BCS_BATCH(batch, 0);
2478     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
2479     OUT_BCS_BATCH(batch, 0);
2480     ADVANCE_BCS_BATCH(batch);
2481 }
2482
2483 static void
2484 gen7_jpeg_wa_avc_bsd_object(VADriverContextP ctx,
2485                             struct gen7_mfd_context *gen7_mfd_context)
2486 {
2487     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2488
2489     /* the input bitsteam format on GEN7 differs from GEN6 */
2490     BEGIN_BCS_BATCH(batch, 6);
2491     OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2));
2492     OUT_BCS_BATCH(batch, gen7_jpeg_wa_clip.data_size);
2493     OUT_BCS_BATCH(batch, 0);
2494     OUT_BCS_BATCH(batch,
2495                   (0 << 31) |
2496                   (0 << 14) |
2497                   (0 << 12) |
2498                   (0 << 10) |
2499                   (0 << 8));
2500     OUT_BCS_BATCH(batch,
2501                   ((gen7_jpeg_wa_clip.data_bit_offset >> 3) << 16) |
2502                   (0 << 5)  |
2503                   (0 << 4)  |
2504                   (1 << 3) | /* LastSlice Flag */
2505                   (gen7_jpeg_wa_clip.data_bit_offset & 0x7));
2506     OUT_BCS_BATCH(batch, 0);
2507     ADVANCE_BCS_BATCH(batch);
2508 }
2509
2510 static void
2511 gen7_jpeg_wa_avc_slice_state(VADriverContextP ctx,
2512                              struct gen7_mfd_context *gen7_mfd_context)
2513 {
2514     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2515     int slice_hor_pos = 0, slice_ver_pos = 0, next_slice_hor_pos = 0, next_slice_ver_pos = 1;
2516     int num_ref_idx_l0 = 0, num_ref_idx_l1 = 0;
2517     int first_mb_in_slice = 0;
2518     int slice_type = SLICE_TYPE_I;
2519
2520     BEGIN_BCS_BATCH(batch, 11);
2521     OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2));
2522     OUT_BCS_BATCH(batch, slice_type);
2523     OUT_BCS_BATCH(batch,
2524                   (num_ref_idx_l1 << 24) |
2525                   (num_ref_idx_l0 << 16) |
2526                   (0 << 8) |
2527                   (0 << 0));
2528     OUT_BCS_BATCH(batch,
2529                   (0 << 29) |
2530                   (1 << 27) |   /* disable Deblocking */
2531                   (0 << 24) |
2532                   (gen7_jpeg_wa_clip.qp << 16) |
2533                   (0 << 8) |
2534                   (0 << 0));
2535     OUT_BCS_BATCH(batch,
2536                   (slice_ver_pos << 24) |
2537                   (slice_hor_pos << 16) |
2538                   (first_mb_in_slice << 0));
2539     OUT_BCS_BATCH(batch,
2540                   (next_slice_ver_pos << 16) |
2541                   (next_slice_hor_pos << 0));
2542     OUT_BCS_BATCH(batch, (1 << 19)); /* last slice flag */
2543     OUT_BCS_BATCH(batch, 0);
2544     OUT_BCS_BATCH(batch, 0);
2545     OUT_BCS_BATCH(batch, 0);
2546     OUT_BCS_BATCH(batch, 0);
2547     ADVANCE_BCS_BATCH(batch);
2548 }
2549
2550 static void
2551 gen7_mfd_jpeg_wa(VADriverContextP ctx,
2552                  struct gen7_mfd_context *gen7_mfd_context)
2553 {
2554     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2555     gen7_jpeg_wa_init(ctx, gen7_mfd_context);
2556     intel_batchbuffer_emit_mi_flush(batch);
2557     gen7_jpeg_wa_pipe_mode_select(ctx, gen7_mfd_context);
2558     gen7_jpeg_wa_surface_state(ctx, gen7_mfd_context);
2559     gen7_jpeg_wa_pipe_buf_addr_state(ctx, gen7_mfd_context);
2560     gen7_jpeg_wa_bsp_buf_base_addr_state(ctx, gen7_mfd_context);
2561     gen7_jpeg_wa_avc_qm_state(ctx, gen7_mfd_context);
2562     gen7_jpeg_wa_avc_img_state(ctx, gen7_mfd_context);
2563     gen7_jpeg_wa_ind_obj_base_addr_state(ctx, gen7_mfd_context);
2564
2565     gen7_jpeg_wa_avc_directmode_state(ctx, gen7_mfd_context);
2566     gen7_jpeg_wa_avc_slice_state(ctx, gen7_mfd_context);
2567     gen7_jpeg_wa_avc_bsd_object(ctx, gen7_mfd_context);
2568 }
2569
2570 void
2571 gen7_mfd_jpeg_decode_picture(VADriverContextP ctx,
2572                              struct decode_state *decode_state,
2573                              struct gen7_mfd_context *gen7_mfd_context)
2574 {
2575     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2576     VAPictureParameterBufferJPEGBaseline *pic_param;
2577     VASliceParameterBufferJPEGBaseline *slice_param, *next_slice_param, *next_slice_group_param;
2578     dri_bo *slice_data_bo;
2579     int i, j, max_selector = 0;
2580
2581     assert(decode_state->pic_param && decode_state->pic_param->buffer);
2582     pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
2583
2584     /* Currently only support Baseline DCT */
2585     gen7_mfd_jpeg_decode_init(ctx, decode_state, gen7_mfd_context);
2586     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
2587     gen7_mfd_jpeg_wa(ctx, gen7_mfd_context);
2588     intel_batchbuffer_emit_mi_flush(batch);
2589     gen7_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_JPEG, gen7_mfd_context);
2590     gen7_mfd_surface_state(ctx, decode_state, MFX_FORMAT_JPEG, gen7_mfd_context);
2591     gen7_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_JPEG, gen7_mfd_context);
2592     gen7_mfd_jpeg_pic_state(ctx, decode_state, gen7_mfd_context);
2593     gen7_mfd_jpeg_qm_state(ctx, decode_state, gen7_mfd_context);
2594
2595     for (j = 0; j < decode_state->num_slice_params; j++) {
2596         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
2597         slice_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j]->buffer;
2598         slice_data_bo = decode_state->slice_datas[j]->bo;
2599         gen7_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_JPEG, gen7_mfd_context);
2600
2601         if (j == decode_state->num_slice_params - 1)
2602             next_slice_group_param = NULL;
2603         else
2604             next_slice_group_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j + 1]->buffer;
2605
2606         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
2607             int component;
2608
2609             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
2610
2611             if (i < decode_state->slice_params[j]->num_elements - 1)
2612                 next_slice_param = slice_param + 1;
2613             else
2614                 next_slice_param = next_slice_group_param;
2615
2616             for (component = 0; component < slice_param->num_components; component++) {
2617                 if (max_selector < slice_param->components[component].dc_table_selector)
2618                     max_selector = slice_param->components[component].dc_table_selector;
2619
2620                 if (max_selector < slice_param->components[component].ac_table_selector)
2621                     max_selector = slice_param->components[component].ac_table_selector;
2622             }
2623
2624             slice_param++;
2625         }
2626     }
2627
2628     assert(max_selector < 2);
2629     gen7_mfd_jpeg_huff_table_state(ctx, decode_state, gen7_mfd_context, max_selector + 1);
2630
2631     for (j = 0; j < decode_state->num_slice_params; j++) {
2632         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
2633         slice_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j]->buffer;
2634         slice_data_bo = decode_state->slice_datas[j]->bo;
2635         gen7_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_JPEG, gen7_mfd_context);
2636
2637         if (j == decode_state->num_slice_params - 1)
2638             next_slice_group_param = NULL;
2639         else
2640             next_slice_group_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j + 1]->buffer;
2641
2642         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
2643             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
2644
2645             if (i < decode_state->slice_params[j]->num_elements - 1)
2646                 next_slice_param = slice_param + 1;
2647             else
2648                 next_slice_param = next_slice_group_param;
2649
2650             gen7_mfd_jpeg_bsd_object(ctx, pic_param, slice_param, next_slice_param, slice_data_bo, gen7_mfd_context);
2651             slice_param++;
2652         }
2653     }
2654
2655     intel_batchbuffer_end_atomic(batch);
2656     intel_batchbuffer_flush(batch);
2657 }
2658
2659 static VAStatus
2660 gen7_mfd_decode_picture(VADriverContextP ctx,
2661                         VAProfile profile,
2662                         union codec_state *codec_state,
2663                         struct hw_context *hw_context)
2664
2665 {
2666     struct gen7_mfd_context *gen7_mfd_context = (struct gen7_mfd_context *)hw_context;
2667     struct decode_state *decode_state = &codec_state->decode;
2668     VAStatus vaStatus;
2669
2670     assert(gen7_mfd_context);
2671
2672     vaStatus = intel_decoder_sanity_check_input(ctx, profile, decode_state);
2673
2674     if (vaStatus != VA_STATUS_SUCCESS)
2675         goto out;
2676
2677     gen7_mfd_context->wa_mpeg2_slice_vertical_position = -1;
2678
2679     switch (profile) {
2680     case VAProfileMPEG2Simple:
2681     case VAProfileMPEG2Main:
2682         gen7_mfd_mpeg2_decode_picture(ctx, decode_state, gen7_mfd_context);
2683         break;
2684
2685     case VAProfileH264ConstrainedBaseline:
2686     case VAProfileH264Main:
2687     case VAProfileH264High:
2688     case VAProfileH264StereoHigh:
2689         gen7_mfd_avc_decode_picture(ctx, decode_state, gen7_mfd_context);
2690         break;
2691
2692     case VAProfileVC1Simple:
2693     case VAProfileVC1Main:
2694     case VAProfileVC1Advanced:
2695         gen7_mfd_vc1_decode_picture(ctx, decode_state, gen7_mfd_context);
2696         break;
2697
2698     case VAProfileJPEGBaseline:
2699         gen7_mfd_jpeg_decode_picture(ctx, decode_state, gen7_mfd_context);
2700         break;
2701
2702     default:
2703         assert(0);
2704         break;
2705     }
2706
2707     vaStatus = VA_STATUS_SUCCESS;
2708
2709 out:
2710     return vaStatus;
2711 }
2712
2713 static void
2714 gen7_mfd_context_destroy(void *hw_context)
2715 {
2716     VADriverContextP ctx;
2717     struct gen7_mfd_context *gen7_mfd_context = (struct gen7_mfd_context *)hw_context;
2718
2719     ctx = (VADriverContextP)(gen7_mfd_context->driver_context);
2720
2721     dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo);
2722     gen7_mfd_context->post_deblocking_output.bo = NULL;
2723
2724     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
2725     gen7_mfd_context->pre_deblocking_output.bo = NULL;
2726
2727     dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo);
2728     gen7_mfd_context->intra_row_store_scratch_buffer.bo = NULL;
2729
2730     dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
2731     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
2732
2733     dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
2734     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
2735
2736     dri_bo_unreference(gen7_mfd_context->mpr_row_store_scratch_buffer.bo);
2737     gen7_mfd_context->mpr_row_store_scratch_buffer.bo = NULL;
2738
2739     dri_bo_unreference(gen7_mfd_context->bitplane_read_buffer.bo);
2740     gen7_mfd_context->bitplane_read_buffer.bo = NULL;
2741
2742     dri_bo_unreference(gen7_mfd_context->jpeg_wa_slice_data_bo);
2743
2744     if (gen7_mfd_context->jpeg_wa_surface_id != VA_INVALID_SURFACE) {
2745         i965_DestroySurfaces(ctx,
2746                              &gen7_mfd_context->jpeg_wa_surface_id,
2747                              1);
2748         gen7_mfd_context->jpeg_wa_surface_object = NULL;
2749     }
2750
2751     intel_batchbuffer_free(gen7_mfd_context->base.batch);
2752     free(gen7_mfd_context);
2753 }
2754
2755 static void gen7_mfd_mpeg2_context_init(VADriverContextP ctx,
2756                                         struct gen7_mfd_context *gen7_mfd_context)
2757 {
2758     gen7_mfd_context->iq_matrix.mpeg2.load_intra_quantiser_matrix = -1;
2759     gen7_mfd_context->iq_matrix.mpeg2.load_non_intra_quantiser_matrix = -1;
2760     gen7_mfd_context->iq_matrix.mpeg2.load_chroma_intra_quantiser_matrix = -1;
2761     gen7_mfd_context->iq_matrix.mpeg2.load_chroma_non_intra_quantiser_matrix = -1;
2762 }
2763
2764 struct hw_context *
2765 gen7_dec_hw_context_init(VADriverContextP ctx, struct object_config *obj_config)
2766 {
2767     struct intel_driver_data *intel = intel_driver_data(ctx);
2768     struct gen7_mfd_context *gen7_mfd_context = calloc(1, sizeof(struct gen7_mfd_context));
2769     int i;
2770
2771     assert(gen7_mfd_context);
2772     gen7_mfd_context->base.destroy = gen7_mfd_context_destroy;
2773     gen7_mfd_context->base.run = gen7_mfd_decode_picture;
2774     gen7_mfd_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER, 0);
2775
2776     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
2777         gen7_mfd_context->reference_surface[i].surface_id = VA_INVALID_ID;
2778         gen7_mfd_context->reference_surface[i].frame_store_id = -1;
2779         gen7_mfd_context->reference_surface[i].obj_surface = NULL;
2780     }
2781
2782     gen7_mfd_context->jpeg_wa_surface_id = VA_INVALID_SURFACE;
2783     gen7_mfd_context->jpeg_wa_surface_object = NULL;
2784
2785     switch (obj_config->profile) {
2786     case VAProfileMPEG2Simple:
2787     case VAProfileMPEG2Main:
2788         gen7_mfd_mpeg2_context_init(ctx, gen7_mfd_context);
2789         break;
2790
2791     case VAProfileH264ConstrainedBaseline:
2792     case VAProfileH264Main:
2793     case VAProfileH264High:
2794     case VAProfileH264StereoHigh:
2795         gen7_mfd_avc_context_init(ctx, gen7_mfd_context);
2796         break;
2797     default:
2798         break;
2799     }
2800
2801     gen7_mfd_context->driver_context = ctx;
2802     return (struct hw_context *)gen7_mfd_context;
2803 }