src/gen7_mfd.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Xiang Haihao <haihao.xiang@intel.com>
  26  *
  27  */
  28
  29 #include <stdio.h>
  30 #include <stdlib.h>
  31 #include <string.h>
  32 #include <assert.h>
  33
  34 #include "intel_batchbuffer.h"
  35 #include "intel_driver.h"
  36
  37 #include "i965_defines.h"
  38 #include "i965_drv_video.h"
  39 #include "i965_decoder_utils.h"
  40
  41 #include "gen7_mfd.h"
  42
  43 #define DMV_SIZE        0x88000 /* 557056 bytes for a frame */
  44
  45 static const uint32_t zigzag_direct[64] = {
  46     0,   1,  8, 16,  9,  2,  3, 10,
  47     17, 24, 32, 25, 18, 11,  4,  5,
  48     12, 19, 26, 33, 40, 48, 41, 34,
  49     27, 20, 13,  6,  7, 14, 21, 28,
  50     35, 42, 49, 56, 57, 50, 43, 36,
  51     29, 22, 15, 23, 30, 37, 44, 51,
  52     58, 59, 52, 45, 38, 31, 39, 46,
  53     53, 60, 61, 54, 47, 55, 62, 63
  54 };
  55
  56 static void
  57 gen7_mfd_avc_frame_store_index(VADriverContextP ctx,
  58                                VAPictureParameterBufferH264 *pic_param,
  59                                struct gen7_mfd_context *gen7_mfd_context)
  60 {
  61     struct i965_driver_data *i965 = i965_driver_data(ctx);
  62     int i, j;
  63
  64     assert(ARRAY_ELEMS(gen7_mfd_context->reference_surface) == ARRAY_ELEMS(pic_param->ReferenceFrames));
  65
  66     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
  67         int found = 0;
  68
  69         if (gen7_mfd_context->reference_surface[i].surface_id == VA_INVALID_ID)
  70             continue;
  71
  72         for (j = 0; j < ARRAY_ELEMS(pic_param->ReferenceFrames); j++) {
  73             VAPictureH264 *ref_pic = &pic_param->ReferenceFrames[j];
  74             if (ref_pic->flags & VA_PICTURE_H264_INVALID)
  75                 continue;
  76
  77             if (gen7_mfd_context->reference_surface[i].surface_id == ref_pic->picture_id) {
  78                 found = 1;
  79                 break;
  80             }
  81         }
  82
  83         if (!found) {
  84             struct object_surface *obj_surface = SURFACE(gen7_mfd_context->reference_surface[i].surface_id);
  85             obj_surface->flags &= ~SURFACE_REFERENCED;
  86
  87             if ((obj_surface->flags & SURFACE_ALL_MASK) == SURFACE_DISPLAYED) {
  88                 dri_bo_unreference(obj_surface->bo);
  89                 obj_surface->bo = NULL;
  90                 obj_surface->flags &= ~SURFACE_REF_DIS_MASK;
  91             }
  92
  93             if (obj_surface->free_private_data)
  94                 obj_surface->free_private_data(&obj_surface->private_data);
  95
  96             gen7_mfd_context->reference_surface[i].surface_id = VA_INVALID_ID;
  97             gen7_mfd_context->reference_surface[i].frame_store_id = -1;
  98         }
  99     }
 100
 101     for (i = 0; i < ARRAY_ELEMS(pic_param->ReferenceFrames); i++) {
 102         VAPictureH264 *ref_pic = &pic_param->ReferenceFrames[i];
 103         int found = 0;
 104
 105         if (ref_pic->flags & VA_PICTURE_H264_INVALID)
 106             continue;
 107
 108         for (j = 0; j < ARRAY_ELEMS(gen7_mfd_context->reference_surface); j++) {
 109             if (gen7_mfd_context->reference_surface[j].surface_id == VA_INVALID_ID)
 110                 continue;
 111
 112             if (gen7_mfd_context->reference_surface[j].surface_id == ref_pic->picture_id) {
 113                 found = 1;
 114                 break;
 115             }
 116         }
 117
 118         if (!found) {
 119             int frame_idx;
 120             struct object_surface *obj_surface = SURFACE(ref_pic->picture_id);
 121
 122             assert(obj_surface);
 123             i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'));
 124
 125             for (frame_idx = 0; frame_idx < ARRAY_ELEMS(gen7_mfd_context->reference_surface); frame_idx++) {
 126                 for (j = 0; j < ARRAY_ELEMS(gen7_mfd_context->reference_surface); j++) {
 127                     if (gen7_mfd_context->reference_surface[j].surface_id == VA_INVALID_ID)
 128                         continue;
 129
 130                     if (gen7_mfd_context->reference_surface[j].frame_store_id == frame_idx)
 131                         break;
 132                 }
 133
 134                 if (j == ARRAY_ELEMS(gen7_mfd_context->reference_surface))
 135                     break;
 136             }
 137
 138             assert(frame_idx < ARRAY_ELEMS(gen7_mfd_context->reference_surface));
 139
 140             for (j = 0; j < ARRAY_ELEMS(gen7_mfd_context->reference_surface); j++) {
 141                 if (gen7_mfd_context->reference_surface[j].surface_id == VA_INVALID_ID) {
 142                     gen7_mfd_context->reference_surface[j].surface_id = ref_pic->picture_id;
 143                     gen7_mfd_context->reference_surface[j].frame_store_id = frame_idx;
 144                     break;
 145                 }
 146             }
 147         }
 148     }
 149
 150     /* sort */
 151     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface) - 1; i++) {
 152         if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID &&
 153             gen7_mfd_context->reference_surface[i].frame_store_id == i)
 154             continue;
 155
 156         for (j = i + 1; j < ARRAY_ELEMS(gen7_mfd_context->reference_surface); j++) {
 157             if (gen7_mfd_context->reference_surface[j].surface_id != VA_INVALID_ID &&
 158                 gen7_mfd_context->reference_surface[j].frame_store_id == i) {
 159                 VASurfaceID id = gen7_mfd_context->reference_surface[i].surface_id;
 160                 int frame_idx = gen7_mfd_context->reference_surface[i].frame_store_id;
 161
 162                 gen7_mfd_context->reference_surface[i].surface_id = gen7_mfd_context->reference_surface[j].surface_id;
 163                 gen7_mfd_context->reference_surface[i].frame_store_id = gen7_mfd_context->reference_surface[j].frame_store_id;
 164                 gen7_mfd_context->reference_surface[j].surface_id = id;
 165                 gen7_mfd_context->reference_surface[j].frame_store_id = frame_idx;
 166                 break;
 167             }
 168         }
 169     }
 170 }
 171
 172 static void
 173 gen7_mfd_free_avc_surface(void **data)
 174 {
 175     struct gen7_avc_surface *gen7_avc_surface = *data;
 176
 177     if (!gen7_avc_surface)
 178         return;
 179
 180     dri_bo_unreference(gen7_avc_surface->dmv_top);
 181     gen7_avc_surface->dmv_top = NULL;
 182     dri_bo_unreference(gen7_avc_surface->dmv_bottom);
 183     gen7_avc_surface->dmv_bottom = NULL;
 184
 185     free(gen7_avc_surface);
 186     *data = NULL;
 187 }
 188
 189 static void
 190 gen7_mfd_init_avc_surface(VADriverContextP ctx,
 191                           VAPictureParameterBufferH264 *pic_param,
 192                           struct object_surface *obj_surface)
 193 {
 194     struct i965_driver_data *i965 = i965_driver_data(ctx);
 195     struct gen7_avc_surface *gen7_avc_surface = obj_surface->private_data;
 196
 197     obj_surface->free_private_data = gen7_mfd_free_avc_surface;
 198
 199     if (!gen7_avc_surface) {
 200         gen7_avc_surface = calloc(sizeof(struct gen7_avc_surface), 1);
 201         assert((obj_surface->size & 0x3f) == 0);
 202         obj_surface->private_data = gen7_avc_surface;
 203     }
 204
 205     gen7_avc_surface->dmv_bottom_flag = (pic_param->pic_fields.bits.field_pic_flag &&
 206                                          !pic_param->seq_fields.bits.direct_8x8_inference_flag);
 207
 208     if (gen7_avc_surface->dmv_top == NULL) {
 209         gen7_avc_surface->dmv_top = dri_bo_alloc(i965->intel.bufmgr,
 210                                                  "direct mv w/r buffer",
 211                                                  DMV_SIZE,
 212                                                  0x1000);
 213     }
 214
 215     if (gen7_avc_surface->dmv_bottom_flag &&
 216         gen7_avc_surface->dmv_bottom == NULL) {
 217         gen7_avc_surface->dmv_bottom = dri_bo_alloc(i965->intel.bufmgr,
 218                                                     "direct mv w/r buffer",
 219                                                     DMV_SIZE,
 220                                                     0x1000);
 221     }
 222 }
 223
 224 static void
 225 gen7_mfd_pipe_mode_select(VADriverContextP ctx,
 226                           struct decode_state *decode_state,
 227                           int standard_select,
 228                           struct gen7_mfd_context *gen7_mfd_context)
 229 {
 230     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 231
 232     assert(standard_select == MFX_FORMAT_MPEG2 ||
 233            standard_select == MFX_FORMAT_AVC ||
 234            standard_select == MFX_FORMAT_VC1 ||
 235            standard_select == MFX_FORMAT_JPEG);
 236
 237     BEGIN_BCS_BATCH(batch, 5); /* FIXME: 5 ??? */
 238     OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2));
 239     OUT_BCS_BATCH(batch,
 240                   (MFX_LONG_MODE << 17) | /* Currently only support long format */
 241                   (MFD_MODE_VLD << 15) | /* VLD mode */
 242                   (0 << 10) | /* disable Stream-Out */
 243                   (gen7_mfd_context->post_deblocking_output.valid << 9)  | /* Post Deblocking Output */
 244                   (gen7_mfd_context->pre_deblocking_output.valid << 8)  | /* Pre Deblocking Output */
 245                   (0 << 5)  | /* not in stitch mode */
 246                   (MFX_CODEC_DECODE << 4)  | /* decoding mode */
 247                   (standard_select << 0));
 248     OUT_BCS_BATCH(batch,
 249                   (0 << 4)  | /* terminate if AVC motion and POC table error occurs */
 250                   (0 << 3)  | /* terminate if AVC mbdata error occurs */
 251                   (0 << 2)  | /* terminate if AVC CABAC/CAVLC decode error occurs */
 252                   (0 << 1)  |
 253                   (0 << 0));
 254     OUT_BCS_BATCH(batch, 0); /* pic status/error report id */
 255     OUT_BCS_BATCH(batch, 0); /* reserved */
 256     ADVANCE_BCS_BATCH(batch);
 257 }
 258
 259 static void
 260 gen7_mfd_surface_state(VADriverContextP ctx,
 261                        struct decode_state *decode_state,
 262                        int standard_select,
 263                        struct gen7_mfd_context *gen7_mfd_context)
 264 {
 265     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 266     struct i965_driver_data *i965 = i965_driver_data(ctx);
 267     struct object_surface *obj_surface = SURFACE(decode_state->current_render_target);
 268     assert(obj_surface);
 269
 270     BEGIN_BCS_BATCH(batch, 6);
 271     OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
 272     OUT_BCS_BATCH(batch, 0);
 273     OUT_BCS_BATCH(batch,
 274                   ((obj_surface->orig_height - 1) << 18) |
 275                   ((obj_surface->orig_width - 1) << 4));
 276     OUT_BCS_BATCH(batch,
 277                   (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
 278                   (1 << 27) | /* FIXME: set to 0 for JPEG */
 279                   (0 << 22) | /* surface object control state, FIXME??? */
 280                   ((obj_surface->width - 1) << 3) | /* pitch */
 281                   (0 << 2)  | /* must be 0 for interleave U/V */
 282                   (1 << 1)  | /* must be tiled */
 283                   (I965_TILEWALK_YMAJOR << 0));  /* tile walk, must be 1 */
 284     OUT_BCS_BATCH(batch,
 285                   (0 << 16) | /* FIXME: fix it for JPEG */
 286                   (obj_surface->height)); /* FIXME: fix it for JPEG */
 287     OUT_BCS_BATCH(batch, 0); /* FIXME: fix it for JPEG */
 288     ADVANCE_BCS_BATCH(batch);
 289 }
 290
 291 static void
 292 gen7_mfd_pipe_buf_addr_state(VADriverContextP ctx,
 293                              struct decode_state *decode_state,
 294                              int standard_select,
 295                              struct gen7_mfd_context *gen7_mfd_context)
 296 {
 297     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 298     struct i965_driver_data *i965 = i965_driver_data(ctx);
 299     int i;
 300
 301     BEGIN_BCS_BATCH(batch, 24);
 302     OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
 303     if (gen7_mfd_context->pre_deblocking_output.valid)
 304         OUT_BCS_RELOC(batch, gen7_mfd_context->pre_deblocking_output.bo,
 305                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 306                       0);
 307     else
 308         OUT_BCS_BATCH(batch, 0);
 309
 310     if (gen7_mfd_context->post_deblocking_output.valid)
 311         OUT_BCS_RELOC(batch, gen7_mfd_context->post_deblocking_output.bo,
 312                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 313                       0);
 314     else
 315         OUT_BCS_BATCH(batch, 0);
 316
 317     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
 318     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
 319
 320     if (gen7_mfd_context->intra_row_store_scratch_buffer.valid)
 321         OUT_BCS_RELOC(batch, gen7_mfd_context->intra_row_store_scratch_buffer.bo,
 322                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 323                       0);
 324     else
 325         OUT_BCS_BATCH(batch, 0);
 326
 327     if (gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid)
 328         OUT_BCS_RELOC(batch, gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo,
 329                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 330                       0);
 331     else
 332         OUT_BCS_BATCH(batch, 0);
 333
 334     /* DW 7..22 */
 335     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
 336         struct object_surface *obj_surface;
 337
 338         if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) {
 339             obj_surface = SURFACE(gen7_mfd_context->reference_surface[i].surface_id);
 340             assert(obj_surface && obj_surface->bo);
 341
 342             OUT_BCS_RELOC(batch, obj_surface->bo,
 343                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 344                           0);
 345         } else {
 346             OUT_BCS_BATCH(batch, 0);
 347         }
 348     }
 349
 350     OUT_BCS_BATCH(batch, 0);   /* ignore DW23 for decoding */
 351     ADVANCE_BCS_BATCH(batch);
 352 }
 353
 354 static void
 355 gen7_mfd_ind_obj_base_addr_state(VADriverContextP ctx,
 356                                  dri_bo *slice_data_bo,
 357                                  int standard_select,
 358                                  struct gen7_mfd_context *gen7_mfd_context)
 359 {
 360     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 361
 362     BEGIN_BCS_BATCH(batch, 11);
 363     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
 364     OUT_BCS_RELOC(batch, slice_data_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); /* MFX Indirect Bitstream Object Base Address */
 365     OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
 366     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 367     OUT_BCS_BATCH(batch, 0);
 368     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 369     OUT_BCS_BATCH(batch, 0);
 370     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 371     OUT_BCS_BATCH(batch, 0);
 372     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 373     OUT_BCS_BATCH(batch, 0);
 374     ADVANCE_BCS_BATCH(batch);
 375 }
 376
 377 static void
 378 gen7_mfd_bsp_buf_base_addr_state(VADriverContextP ctx,
 379                                  struct decode_state *decode_state,
 380                                  int standard_select,
 381                                  struct gen7_mfd_context *gen7_mfd_context)
 382 {
 383     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 384
 385     BEGIN_BCS_BATCH(batch, 4);
 386     OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
 387
 388     if (gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid)
 389         OUT_BCS_RELOC(batch, gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo,
 390                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 391                       0);
 392     else
 393         OUT_BCS_BATCH(batch, 0);
 394
 395     if (gen7_mfd_context->mpr_row_store_scratch_buffer.valid)
 396         OUT_BCS_RELOC(batch, gen7_mfd_context->mpr_row_store_scratch_buffer.bo,
 397                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 398                       0);
 399     else
 400         OUT_BCS_BATCH(batch, 0);
 401
 402     if (gen7_mfd_context->bitplane_read_buffer.valid)
 403         OUT_BCS_RELOC(batch, gen7_mfd_context->bitplane_read_buffer.bo,
 404                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 405                       0);
 406     else
 407         OUT_BCS_BATCH(batch, 0);
 408
 409     ADVANCE_BCS_BATCH(batch);
 410 }
 411
 412 static void
 413 gen7_mfd_aes_state(VADriverContextP ctx,
 414                    struct decode_state *decode_state,
 415                    int standard_select)
 416 {
 417     /* FIXME */
 418 }
 419
 420 static void
 421 gen7_mfd_qm_state(VADriverContextP ctx,
 422                   int qm_type,
 423                   unsigned char *qm,
 424                   int qm_length,
 425                   struct gen7_mfd_context *gen7_mfd_context)
 426 {
 427     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 428     unsigned int qm_buffer[16];
 429
 430     assert(qm_length <= 16 * 4);
 431     memcpy(qm_buffer, qm, qm_length);
 432
 433     BEGIN_BCS_BATCH(batch, 18);
 434     OUT_BCS_BATCH(batch, MFX_QM_STATE | (18 - 2));
 435     OUT_BCS_BATCH(batch, qm_type << 0);
 436     intel_batchbuffer_data(batch, qm_buffer, 16 * 4);
 437     ADVANCE_BCS_BATCH(batch);
 438 }
 439 static void
 440 gen7_mfd_wait(VADriverContextP ctx,
 441               struct decode_state *decode_state,
 442               int standard_select,
 443               struct gen7_mfd_context *gen7_mfd_context)
 444 {
 445     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 446
 447     BEGIN_BCS_BATCH(batch, 1);
 448     OUT_BCS_BATCH(batch, MFX_WAIT | (1 << 8));
 449     ADVANCE_BCS_BATCH(batch);
 450 }
 451
 452 static void
 453 gen7_mfd_avc_img_state(VADriverContextP ctx,
 454                        struct decode_state *decode_state,
 455                        struct gen7_mfd_context *gen7_mfd_context)
 456 {
 457     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 458     int qm_present_flag;
 459     int img_struct;
 460     int mbaff_frame_flag;
 461     unsigned int width_in_mbs, height_in_mbs;
 462     VAPictureParameterBufferH264 *pic_param;
 463
 464     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 465     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 466     assert(!(pic_param->CurrPic.flags & VA_PICTURE_H264_INVALID));
 467
 468     if (decode_state->iq_matrix && decode_state->iq_matrix->buffer)
 469         qm_present_flag = 1;
 470     else
 471         qm_present_flag = 0; /* built-in QM matrices */
 472
 473     if (pic_param->CurrPic.flags & VA_PICTURE_H264_TOP_FIELD)
 474         img_struct = 1;
 475     else if (pic_param->CurrPic.flags & VA_PICTURE_H264_BOTTOM_FIELD)
 476         img_struct = 3;
 477     else
 478         img_struct = 0;
 479
 480     if ((img_struct & 0x1) == 0x1) {
 481         assert(pic_param->pic_fields.bits.field_pic_flag == 0x1);
 482     } else {
 483         assert(pic_param->pic_fields.bits.field_pic_flag == 0x0);
 484     }
 485
 486     if (pic_param->seq_fields.bits.frame_mbs_only_flag) { /* a frame containing only frame macroblocks */
 487         assert(pic_param->seq_fields.bits.mb_adaptive_frame_field_flag == 0);
 488         assert(pic_param->pic_fields.bits.field_pic_flag == 0);
 489     } else {
 490         assert(pic_param->seq_fields.bits.direct_8x8_inference_flag == 1); /* see H.264 spec */
 491     }
 492
 493     mbaff_frame_flag = (pic_param->seq_fields.bits.mb_adaptive_frame_field_flag &&
 494                         !pic_param->pic_fields.bits.field_pic_flag);
 495
 496     width_in_mbs = ((pic_param->picture_width_in_mbs_minus1 + 1) & 0xff);
 497     height_in_mbs = ((pic_param->picture_height_in_mbs_minus1 + 1) & 0xff); /* frame height */
 498
 499     /* MFX unit doesn't support 4:2:2 and 4:4:4 picture */
 500     assert(pic_param->seq_fields.bits.chroma_format_idc == 0 || /* monochrome picture */
 501            pic_param->seq_fields.bits.chroma_format_idc == 1);  /* 4:2:0 */
 502     assert(pic_param->seq_fields.bits.residual_colour_transform_flag == 0); /* only available for 4:4:4 */
 503
 504     BEGIN_BCS_BATCH(batch, 16);
 505     OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (16 - 2));
 506     OUT_BCS_BATCH(batch,
 507                   width_in_mbs * height_in_mbs);
 508     OUT_BCS_BATCH(batch,
 509                   ((height_in_mbs - 1) << 16) |
 510                   ((width_in_mbs - 1) << 0));
 511     OUT_BCS_BATCH(batch,
 512                   ((pic_param->second_chroma_qp_index_offset & 0x1f) << 24) |
 513                   ((pic_param->chroma_qp_index_offset & 0x1f) << 16) |
 514                   (0 << 14) | /* Max-bit conformance Intra flag ??? FIXME */
 515                   (0 << 13) | /* Max Macroblock size conformance Inter flag ??? FIXME */
 516                   (pic_param->pic_fields.bits.weighted_pred_flag << 12) | /* differ from GEN6 */
 517                   (pic_param->pic_fields.bits.weighted_bipred_idc << 10) |
 518                   (img_struct << 8));
 519     OUT_BCS_BATCH(batch,
 520                   (pic_param->seq_fields.bits.chroma_format_idc << 10) |
 521                   (pic_param->pic_fields.bits.entropy_coding_mode_flag << 7) |
 522                   ((!pic_param->pic_fields.bits.reference_pic_flag) << 6) |
 523                   (pic_param->pic_fields.bits.constrained_intra_pred_flag << 5) |
 524                   (pic_param->seq_fields.bits.direct_8x8_inference_flag << 4) |
 525                   (pic_param->pic_fields.bits.transform_8x8_mode_flag << 3) |
 526                   (pic_param->seq_fields.bits.frame_mbs_only_flag << 2) |
 527                   (mbaff_frame_flag << 1) |
 528                   (pic_param->pic_fields.bits.field_pic_flag << 0));
 529     OUT_BCS_BATCH(batch, 0);
 530     OUT_BCS_BATCH(batch, 0);
 531     OUT_BCS_BATCH(batch, 0);
 532     OUT_BCS_BATCH(batch, 0);
 533     OUT_BCS_BATCH(batch, 0);
 534     OUT_BCS_BATCH(batch, 0);
 535     OUT_BCS_BATCH(batch, 0);
 536     OUT_BCS_BATCH(batch, 0);
 537     OUT_BCS_BATCH(batch, 0);
 538     OUT_BCS_BATCH(batch, 0);
 539     OUT_BCS_BATCH(batch, 0);
 540     ADVANCE_BCS_BATCH(batch);
 541 }
 542
 543 static void
 544 gen7_mfd_avc_qm_state(VADriverContextP ctx,
 545                       struct decode_state *decode_state,
 546                       struct gen7_mfd_context *gen7_mfd_context)
 547 {
 548     VAIQMatrixBufferH264 *iq_matrix;
 549     VAPictureParameterBufferH264 *pic_param;
 550
 551     if (!decode_state->iq_matrix || !decode_state->iq_matrix->buffer)
 552         return;
 553
 554     iq_matrix = (VAIQMatrixBufferH264 *)decode_state->iq_matrix->buffer;
 555
 556     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 557     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 558
 559     gen7_mfd_qm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, &iq_matrix->ScalingList4x4[0][0], 3 * 16, gen7_mfd_context);
 560     gen7_mfd_qm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, &iq_matrix->ScalingList4x4[3][0], 3 * 16, gen7_mfd_context);
 561
 562     if (pic_param->pic_fields.bits.transform_8x8_mode_flag) {
 563         gen7_mfd_qm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, &iq_matrix->ScalingList8x8[0][0], 64, gen7_mfd_context);
 564         gen7_mfd_qm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, &iq_matrix->ScalingList8x8[1][0], 64, gen7_mfd_context);
 565     }
 566 }
 567
 568 static void
 569 gen7_mfd_avc_directmode_state(VADriverContextP ctx,
 570                               VAPictureParameterBufferH264 *pic_param,
 571                               VASliceParameterBufferH264 *slice_param,
 572                               struct gen7_mfd_context *gen7_mfd_context)
 573 {
 574     struct i965_driver_data *i965 = i965_driver_data(ctx);
 575     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 576     struct object_surface *obj_surface;
 577     struct gen7_avc_surface *gen7_avc_surface;
 578     VAPictureH264 *va_pic;
 579     int i, j;
 580
 581     BEGIN_BCS_BATCH(batch, 69);
 582     OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
 583
 584     /* reference surfaces 0..15 */
 585     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
 586         if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) {
 587             obj_surface = SURFACE(gen7_mfd_context->reference_surface[i].surface_id);
 588             assert(obj_surface);
 589             gen7_avc_surface = obj_surface->private_data;
 590
 591             if (gen7_avc_surface == NULL) {
 592                 OUT_BCS_BATCH(batch, 0);
 593                 OUT_BCS_BATCH(batch, 0);
 594             } else {
 595                 OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
 596                               I915_GEM_DOMAIN_INSTRUCTION, 0,
 597                               0);
 598
 599                 if (gen7_avc_surface->dmv_bottom_flag == 1)
 600                     OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_bottom,
 601                                   I915_GEM_DOMAIN_INSTRUCTION, 0,
 602                                   0);
 603                 else
 604                     OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
 605                                   I915_GEM_DOMAIN_INSTRUCTION, 0,
 606                                   0);
 607             }
 608         } else {
 609             OUT_BCS_BATCH(batch, 0);
 610             OUT_BCS_BATCH(batch, 0);
 611         }
 612     }
 613
 614     /* the current decoding frame/field */
 615     va_pic = &pic_param->CurrPic;
 616     assert(!(va_pic->flags & VA_PICTURE_H264_INVALID));
 617     obj_surface = SURFACE(va_pic->picture_id);
 618     assert(obj_surface && obj_surface->bo && obj_surface->private_data);
 619     gen7_avc_surface = obj_surface->private_data;
 620
 621     OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
 622                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 623                   0);
 624
 625     if (gen7_avc_surface->dmv_bottom_flag == 1)
 626         OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_bottom,
 627                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 628                       0);
 629     else
 630         OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
 631                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 632                       0);
 633
 634     /* POC List */
 635     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
 636         if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) {
 637             int found = 0;
 638             for (j = 0; j < ARRAY_ELEMS(pic_param->ReferenceFrames); j++) {
 639                 va_pic = &pic_param->ReferenceFrames[j];
 640
 641                 if (va_pic->flags & VA_PICTURE_H264_INVALID)
 642                     continue;
 643
 644                 if (va_pic->picture_id == gen7_mfd_context->reference_surface[i].surface_id) {
 645                     found = 1;
 646                     break;
 647                 }
 648             }
 649
 650             assert(found == 1);
 651             assert(!(va_pic->flags & VA_PICTURE_H264_INVALID));
 652
 653             OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
 654             OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
 655         } else {
 656             OUT_BCS_BATCH(batch, 0);
 657             OUT_BCS_BATCH(batch, 0);
 658         }
 659     }
 660
 661     va_pic = &pic_param->CurrPic;
 662     OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
 663     OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
 664
 665     ADVANCE_BCS_BATCH(batch);
 666 }
 667
 668 static void
 669 gen7_mfd_avc_slice_state(VADriverContextP ctx,
 670                          VAPictureParameterBufferH264 *pic_param,
 671                          VASliceParameterBufferH264 *slice_param,
 672                          VASliceParameterBufferH264 *next_slice_param,
 673                          struct gen7_mfd_context *gen7_mfd_context)
 674 {
 675     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 676     int width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
 677     int height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1;
 678     int slice_hor_pos, slice_ver_pos, next_slice_hor_pos, next_slice_ver_pos;
 679     int num_ref_idx_l0, num_ref_idx_l1;
 680     int mbaff_picture = (!pic_param->pic_fields.bits.field_pic_flag &&
 681                          pic_param->seq_fields.bits.mb_adaptive_frame_field_flag);
 682     int first_mb_in_slice = 0, first_mb_in_next_slice = 0;
 683     int slice_type;
 684
 685     if (slice_param->slice_type == SLICE_TYPE_I ||
 686         slice_param->slice_type == SLICE_TYPE_SI) {
 687         slice_type = SLICE_TYPE_I;
 688     } else if (slice_param->slice_type == SLICE_TYPE_P ||
 689                slice_param->slice_type == SLICE_TYPE_SP) {
 690         slice_type = SLICE_TYPE_P;
 691     } else {
 692         assert(slice_param->slice_type == SLICE_TYPE_B);
 693         slice_type = SLICE_TYPE_B;
 694     }
 695
 696     if (slice_type == SLICE_TYPE_I) {
 697         assert(slice_param->num_ref_idx_l0_active_minus1 == 0);
 698         assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
 699         num_ref_idx_l0 = 0;
 700         num_ref_idx_l1 = 0;
 701     } else if (slice_type == SLICE_TYPE_P) {
 702         assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
 703         num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
 704         num_ref_idx_l1 = 0;
 705     } else {
 706         num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
 707         num_ref_idx_l1 = slice_param->num_ref_idx_l1_active_minus1 + 1;
 708     }
 709
 710     first_mb_in_slice = slice_param->first_mb_in_slice << mbaff_picture;
 711     slice_hor_pos = first_mb_in_slice % width_in_mbs;
 712     slice_ver_pos = first_mb_in_slice / width_in_mbs;
 713
 714     if (next_slice_param) {
 715         first_mb_in_next_slice = next_slice_param->first_mb_in_slice << mbaff_picture;
 716         next_slice_hor_pos = first_mb_in_next_slice % width_in_mbs;
 717         next_slice_ver_pos = first_mb_in_next_slice / width_in_mbs;
 718     } else {
 719         next_slice_hor_pos = 0;
 720         next_slice_ver_pos = height_in_mbs / (1 + !!pic_param->pic_fields.bits.field_pic_flag);
 721     }
 722
 723     BEGIN_BCS_BATCH(batch, 11); /* FIXME: is it 10??? */
 724     OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2));
 725     OUT_BCS_BATCH(batch, slice_type);
 726     OUT_BCS_BATCH(batch,
 727                   (num_ref_idx_l1 << 24) |
 728                   (num_ref_idx_l0 << 16) |
 729                   (slice_param->chroma_log2_weight_denom << 8) |
 730                   (slice_param->luma_log2_weight_denom << 0));
 731     OUT_BCS_BATCH(batch,
 732                   (slice_param->direct_spatial_mv_pred_flag << 29) |
 733                   (slice_param->disable_deblocking_filter_idc << 27) |
 734                   (slice_param->cabac_init_idc << 24) |
 735                   ((pic_param->pic_init_qp_minus26 + 26 + slice_param->slice_qp_delta) << 16) |
 736                   ((slice_param->slice_beta_offset_div2 & 0xf) << 8) |
 737                   ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0));
 738     OUT_BCS_BATCH(batch,
 739                   (slice_ver_pos << 24) |
 740                   (slice_hor_pos << 16) |
 741                   (first_mb_in_slice << 0));
 742     OUT_BCS_BATCH(batch,
 743                   (next_slice_ver_pos << 16) |
 744                   (next_slice_hor_pos << 0));
 745     OUT_BCS_BATCH(batch,
 746                   (next_slice_param == NULL) << 19); /* last slice flag */
 747     OUT_BCS_BATCH(batch, 0);
 748     OUT_BCS_BATCH(batch, 0);
 749     OUT_BCS_BATCH(batch, 0);
 750     OUT_BCS_BATCH(batch, 0);
 751     ADVANCE_BCS_BATCH(batch);
 752 }
 753
 754 static inline void
 755 gen7_mfd_avc_ref_idx_state(VADriverContextP ctx,
 756                            VAPictureParameterBufferH264 *pic_param,
 757                            VASliceParameterBufferH264 *slice_param,
 758                            struct gen7_mfd_context *gen7_mfd_context)
 759 {
 760     gen6_send_avc_ref_idx_state(
 761         gen7_mfd_context->base.batch,
 762         slice_param,
 763         gen7_mfd_context->reference_surface
 764     );
 765 }
 766
 767 static void
 768 gen7_mfd_avc_weightoffset_state(VADriverContextP ctx,
 769                                 VAPictureParameterBufferH264 *pic_param,
 770                                 VASliceParameterBufferH264 *slice_param,
 771                                 struct gen7_mfd_context *gen7_mfd_context)
 772 {
 773     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 774     int i, j, num_weight_offset_table = 0;
 775     short weightoffsets[32 * 6];
 776
 777     if ((slice_param->slice_type == SLICE_TYPE_P ||
 778          slice_param->slice_type == SLICE_TYPE_SP) &&
 779         (pic_param->pic_fields.bits.weighted_pred_flag == 1)) {
 780         num_weight_offset_table = 1;
 781     }
 782
 783     if ((slice_param->slice_type == SLICE_TYPE_B) &&
 784         (pic_param->pic_fields.bits.weighted_bipred_idc == 1)) {
 785         num_weight_offset_table = 2;
 786     }
 787
 788     for (i = 0; i < num_weight_offset_table; i++) {
 789         BEGIN_BCS_BATCH(batch, 98);
 790         OUT_BCS_BATCH(batch, MFX_AVC_WEIGHTOFFSET_STATE | (98 - 2));
 791         OUT_BCS_BATCH(batch, i);
 792
 793         if (i == 0) {
 794             for (j = 0; j < 32; j++) {
 795                 weightoffsets[j * 6 + 0] = slice_param->luma_weight_l0[j];
 796                 weightoffsets[j * 6 + 1] = slice_param->luma_offset_l0[j];
 797                 weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l0[j][0];
 798                 weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l0[j][0];
 799                 weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l0[j][1];
 800                 weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l0[j][1];
 801             }
 802         } else {
 803             for (j = 0; j < 32; j++) {
 804                 weightoffsets[j * 6 + 0] = slice_param->luma_weight_l1[j];
 805                 weightoffsets[j * 6 + 1] = slice_param->luma_offset_l1[j];
 806                 weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l1[j][0];
 807                 weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l1[j][0];
 808                 weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l1[j][1];
 809                 weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l1[j][1];
 810             }
 811         }
 812
 813         intel_batchbuffer_data(batch, weightoffsets, sizeof(weightoffsets));
 814         ADVANCE_BCS_BATCH(batch);
 815     }
 816 }
 817
 818 static int
 819 gen7_mfd_avc_get_slice_bit_offset(uint8_t *buf, int mode_flag, int in_slice_data_bit_offset)
 820 {
 821     int out_slice_data_bit_offset;
 822     int slice_header_size = in_slice_data_bit_offset / 8;
 823     int i, j;
 824
 825     for (i = 0, j = 0; i < slice_header_size; i++, j++) {
 826         if (!buf[j] && !buf[j + 1] && buf[j + 2] == 3) {
 827             i++, j += 2;
 828         }
 829     }
 830
 831     out_slice_data_bit_offset = 8 * j + in_slice_data_bit_offset % 8;
 832
 833     if (mode_flag == ENTROPY_CABAC)
 834         out_slice_data_bit_offset = ALIGN(out_slice_data_bit_offset, 0x8);
 835
 836     return out_slice_data_bit_offset;
 837 }
 838
 839 static void
 840 gen7_mfd_avc_bsd_object(VADriverContextP ctx,
 841                         VAPictureParameterBufferH264 *pic_param,
 842                         VASliceParameterBufferH264 *slice_param,
 843                         dri_bo *slice_data_bo,
 844                         VASliceParameterBufferH264 *next_slice_param,
 845                         struct gen7_mfd_context *gen7_mfd_context)
 846 {
 847     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 848     int slice_data_bit_offset;
 849     uint8_t *slice_data = NULL;
 850
 851     dri_bo_map(slice_data_bo, 0);
 852     slice_data = (uint8_t *)(slice_data_bo->virtual + slice_param->slice_data_offset);
 853     slice_data_bit_offset = gen7_mfd_avc_get_slice_bit_offset(slice_data,
 854                                                               pic_param->pic_fields.bits.entropy_coding_mode_flag,
 855                                                               slice_param->slice_data_bit_offset);
 856     dri_bo_unmap(slice_data_bo);
 857
 858     /* the input bitsteam format on GEN7 differs from GEN6 */
 859     BEGIN_BCS_BATCH(batch, 6);
 860     OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2));
 861     OUT_BCS_BATCH(batch,
 862                   (slice_param->slice_data_size));
 863     OUT_BCS_BATCH(batch, slice_param->slice_data_offset);
 864     OUT_BCS_BATCH(batch,
 865                   (0 << 31) |
 866                   (0 << 14) |
 867                   (0 << 12) |
 868                   (0 << 10) |
 869                   (0 << 8));
 870     OUT_BCS_BATCH(batch,
 871                   ((slice_data_bit_offset >> 3) << 16) |
 872                   (0 << 5)  |
 873                   (0 << 4)  |
 874                   ((next_slice_param == NULL) << 3) | /* LastSlice Flag */
 875                   (slice_data_bit_offset & 0x7));
 876     OUT_BCS_BATCH(batch, 0);
 877     ADVANCE_BCS_BATCH(batch);
 878 }
 879
 880 static void
 881 gen7_mfd_avc_decode_init(VADriverContextP ctx,
 882                          struct decode_state *decode_state,
 883                          struct gen7_mfd_context *gen7_mfd_context)
 884 {
 885     VAPictureParameterBufferH264 *pic_param;
 886     VASliceParameterBufferH264 *slice_param;
 887     VAPictureH264 *va_pic;
 888     struct i965_driver_data *i965 = i965_driver_data(ctx);
 889     struct object_surface *obj_surface;
 890     dri_bo *bo;
 891     int i, j, enable_avc_ildb = 0;
 892
 893     for (j = 0; j < decode_state->num_slice_params && enable_avc_ildb == 0; j++) {
 894         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
 895         slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
 896
 897         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
 898             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
 899             assert((slice_param->slice_type == SLICE_TYPE_I) ||
 900                    (slice_param->slice_type == SLICE_TYPE_SI) ||
 901                    (slice_param->slice_type == SLICE_TYPE_P) ||
 902                    (slice_param->slice_type == SLICE_TYPE_SP) ||
 903                    (slice_param->slice_type == SLICE_TYPE_B));
 904
 905             if (slice_param->disable_deblocking_filter_idc != 1) {
 906                 enable_avc_ildb = 1;
 907                 break;
 908             }
 909
 910             slice_param++;
 911         }
 912     }
 913
 914     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 915     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 916     gen7_mfd_avc_frame_store_index(ctx, pic_param, gen7_mfd_context);
 917
 918     /* Current decoded picture */
 919     va_pic = &pic_param->CurrPic;
 920     assert(!(va_pic->flags & VA_PICTURE_H264_INVALID));
 921     obj_surface = SURFACE(va_pic->picture_id);
 922     assert(obj_surface);
 923     obj_surface->flags &= ~SURFACE_REF_DIS_MASK;
 924     obj_surface->flags |= (pic_param->pic_fields.bits.reference_pic_flag ? SURFACE_REFERENCED : 0);
 925     gen7_mfd_init_avc_surface(ctx, pic_param, obj_surface);
 926     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'));
 927
 928     dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo);
 929     gen7_mfd_context->post_deblocking_output.bo = obj_surface->bo;
 930     dri_bo_reference(gen7_mfd_context->post_deblocking_output.bo);
 931     gen7_mfd_context->post_deblocking_output.valid = enable_avc_ildb;
 932
 933     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
 934     gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
 935     dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
 936     gen7_mfd_context->pre_deblocking_output.valid = !enable_avc_ildb;
 937
 938     dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo);
 939     bo = dri_bo_alloc(i965->intel.bufmgr,
 940                       "intra row store",
 941                       128 * 64,
 942                       0x1000);
 943     assert(bo);
 944     gen7_mfd_context->intra_row_store_scratch_buffer.bo = bo;
 945     gen7_mfd_context->intra_row_store_scratch_buffer.valid = 1;
 946
 947     dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
 948     bo = dri_bo_alloc(i965->intel.bufmgr,
 949                       "deblocking filter row store",
 950                       30720, /* 4 * 120 * 64 */
 951                       0x1000);
 952     assert(bo);
 953     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
 954     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1;
 955
 956     dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
 957     bo = dri_bo_alloc(i965->intel.bufmgr,
 958                       "bsd mpc row store",
 959                       11520, /* 1.5 * 120 * 64 */
 960                       0x1000);
 961     assert(bo);
 962     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
 963     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
 964
 965     dri_bo_unreference(gen7_mfd_context->mpr_row_store_scratch_buffer.bo);
 966     bo = dri_bo_alloc(i965->intel.bufmgr,
 967                       "mpr row store",
 968                       7680, /* 1. 0 * 120 * 64 */
 969                       0x1000);
 970     assert(bo);
 971     gen7_mfd_context->mpr_row_store_scratch_buffer.bo = bo;
 972     gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 1;
 973
 974     gen7_mfd_context->bitplane_read_buffer.valid = 0;
 975 }
 976
 977 static void
 978 gen7_mfd_avc_decode_picture(VADriverContextP ctx,
 979                             struct decode_state *decode_state,
 980                             struct gen7_mfd_context *gen7_mfd_context)
 981 {
 982     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 983     VAPictureParameterBufferH264 *pic_param;
 984     VASliceParameterBufferH264 *slice_param, *next_slice_param, *next_slice_group_param;
 985     dri_bo *slice_data_bo;
 986     int i, j;
 987
 988     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 989     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 990     gen7_mfd_avc_decode_init(ctx, decode_state, gen7_mfd_context);
 991
 992     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
 993     intel_batchbuffer_emit_mi_flush(batch);
 994     gen7_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
 995     gen7_mfd_surface_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
 996     gen7_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
 997     gen7_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
 998     gen7_mfd_avc_qm_state(ctx, decode_state, gen7_mfd_context);
 999     gen7_mfd_avc_img_state(ctx, decode_state, gen7_mfd_context);
1000
1001     for (j = 0; j < decode_state->num_slice_params; j++) {
1002         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
1003         slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
1004         slice_data_bo = decode_state->slice_datas[j]->bo;
1005         gen7_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_AVC, gen7_mfd_context);
1006
1007         if (j == decode_state->num_slice_params - 1)
1008             next_slice_group_param = NULL;
1009         else
1010             next_slice_group_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j + 1]->buffer;
1011
1012         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
1013             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
1014             assert((slice_param->slice_type == SLICE_TYPE_I) ||
1015                    (slice_param->slice_type == SLICE_TYPE_SI) ||
1016                    (slice_param->slice_type == SLICE_TYPE_P) ||
1017                    (slice_param->slice_type == SLICE_TYPE_SP) ||
1018                    (slice_param->slice_type == SLICE_TYPE_B));
1019
1020             if (i < decode_state->slice_params[j]->num_elements - 1)
1021                 next_slice_param = slice_param + 1;
1022             else
1023                 next_slice_param = next_slice_group_param;
1024
1025             gen7_mfd_avc_directmode_state(ctx, pic_param, slice_param, gen7_mfd_context);
1026             gen7_mfd_avc_ref_idx_state(ctx, pic_param, slice_param, gen7_mfd_context);
1027             gen7_mfd_avc_weightoffset_state(ctx, pic_param, slice_param, gen7_mfd_context);
1028             gen7_mfd_avc_slice_state(ctx, pic_param, slice_param, next_slice_param, gen7_mfd_context);
1029             gen7_mfd_avc_bsd_object(ctx, pic_param, slice_param, slice_data_bo, next_slice_param, gen7_mfd_context);
1030             slice_param++;
1031         }
1032     }
1033
1034     intel_batchbuffer_end_atomic(batch);
1035     intel_batchbuffer_flush(batch);
1036 }
1037
1038 static void
1039 gen7_mfd_mpeg2_decode_init(VADriverContextP ctx,
1040                            struct decode_state *decode_state,
1041                            struct gen7_mfd_context *gen7_mfd_context)
1042 {
1043     VAPictureParameterBufferMPEG2 *pic_param;
1044     struct i965_driver_data *i965 = i965_driver_data(ctx);
1045     struct object_surface *obj_surface;
1046     int i;
1047     dri_bo *bo;
1048
1049     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1050     pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
1051
1052     /* reference picture */
1053     obj_surface = SURFACE(pic_param->forward_reference_picture);
1054
1055     if (obj_surface && obj_surface->bo)
1056         gen7_mfd_context->reference_surface[0].surface_id = pic_param->forward_reference_picture;
1057     else
1058         gen7_mfd_context->reference_surface[0].surface_id = VA_INVALID_ID;
1059
1060     obj_surface = SURFACE(pic_param->backward_reference_picture);
1061
1062     if (obj_surface && obj_surface->bo)
1063         gen7_mfd_context->reference_surface[1].surface_id = pic_param->backward_reference_picture;
1064     else
1065         gen7_mfd_context->reference_surface[1].surface_id = pic_param->forward_reference_picture;
1066
1067     /* must do so !!! */
1068     for (i = 2; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++)
1069         gen7_mfd_context->reference_surface[i].surface_id = gen7_mfd_context->reference_surface[i % 2].surface_id;
1070
1071     /* Current decoded picture */
1072     obj_surface = SURFACE(decode_state->current_render_target);
1073     assert(obj_surface);
1074     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'));
1075
1076     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
1077     gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
1078     dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
1079     gen7_mfd_context->pre_deblocking_output.valid = 1;
1080
1081     dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
1082     bo = dri_bo_alloc(i965->intel.bufmgr,
1083                       "bsd mpc row store",
1084                       11520, /* 1.5 * 120 * 64 */
1085                       0x1000);
1086     assert(bo);
1087     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
1088     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
1089
1090     gen7_mfd_context->post_deblocking_output.valid = 0;
1091     gen7_mfd_context->intra_row_store_scratch_buffer.valid = 0;
1092     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 0;
1093     gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
1094     gen7_mfd_context->bitplane_read_buffer.valid = 0;
1095 }
1096
1097 static void
1098 gen7_mfd_mpeg2_pic_state(VADriverContextP ctx,
1099                          struct decode_state *decode_state,
1100                          struct gen7_mfd_context *gen7_mfd_context)
1101 {
1102     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1103     VAPictureParameterBufferMPEG2 *pic_param;
1104
1105     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1106     pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
1107
1108     BEGIN_BCS_BATCH(batch, 13);
1109     OUT_BCS_BATCH(batch, MFX_MPEG2_PIC_STATE | (13 - 2));
1110     OUT_BCS_BATCH(batch,
1111                   (pic_param->f_code & 0xf) << 28 | /* f_code[1][1] */
1112                   ((pic_param->f_code >> 4) & 0xf) << 24 | /* f_code[1][0] */
1113                   ((pic_param->f_code >> 8) & 0xf) << 20 | /* f_code[0][1] */
1114                   ((pic_param->f_code >> 12) & 0xf) << 16 | /* f_code[0][0] */
1115                   pic_param->picture_coding_extension.bits.intra_dc_precision << 14 |
1116                   pic_param->picture_coding_extension.bits.picture_structure << 12 |
1117                   pic_param->picture_coding_extension.bits.top_field_first << 11 |
1118                   pic_param->picture_coding_extension.bits.frame_pred_frame_dct << 10 |
1119                   pic_param->picture_coding_extension.bits.concealment_motion_vectors << 9 |
1120                   pic_param->picture_coding_extension.bits.q_scale_type << 8 |
1121                   pic_param->picture_coding_extension.bits.intra_vlc_format << 7 |
1122                   pic_param->picture_coding_extension.bits.alternate_scan << 6);
1123     OUT_BCS_BATCH(batch,
1124                   pic_param->picture_coding_type << 9);
1125     OUT_BCS_BATCH(batch,
1126                   ((ALIGN(pic_param->vertical_size, 16) / 16) - 1) << 16 |
1127                   ((ALIGN(pic_param->horizontal_size, 16) / 16) - 1));
1128     OUT_BCS_BATCH(batch, 0);
1129     OUT_BCS_BATCH(batch, 0);
1130     OUT_BCS_BATCH(batch, 0);
1131     OUT_BCS_BATCH(batch, 0);
1132     OUT_BCS_BATCH(batch, 0);
1133     OUT_BCS_BATCH(batch, 0);
1134     OUT_BCS_BATCH(batch, 0);
1135     OUT_BCS_BATCH(batch, 0);
1136     OUT_BCS_BATCH(batch, 0);
1137     ADVANCE_BCS_BATCH(batch);
1138 }
1139
1140 static void
1141 gen7_mfd_mpeg2_qm_state(VADriverContextP ctx,
1142                         struct decode_state *decode_state,
1143                         struct gen7_mfd_context *gen7_mfd_context)
1144 {
1145     VAIQMatrixBufferMPEG2 * const gen_iq_matrix = &gen7_mfd_context->iq_matrix.mpeg2;
1146     int i, j;
1147
1148     /* Update internal QM state */
1149     if (decode_state->iq_matrix && decode_state->iq_matrix->buffer) {
1150         VAIQMatrixBufferMPEG2 * const iq_matrix =
1151             (VAIQMatrixBufferMPEG2 *)decode_state->iq_matrix->buffer;
1152
1153         gen_iq_matrix->load_intra_quantiser_matrix =
1154             iq_matrix->load_intra_quantiser_matrix;
1155         if (iq_matrix->load_intra_quantiser_matrix) {
1156             for (j = 0; j < 64; j++)
1157                 gen_iq_matrix->intra_quantiser_matrix[zigzag_direct[j]] =
1158                     iq_matrix->intra_quantiser_matrix[j];
1159         }
1160
1161         gen_iq_matrix->load_non_intra_quantiser_matrix =
1162             iq_matrix->load_non_intra_quantiser_matrix;
1163         if (iq_matrix->load_non_intra_quantiser_matrix) {
1164             for (j = 0; j < 64; j++)
1165                 gen_iq_matrix->non_intra_quantiser_matrix[zigzag_direct[j]] =
1166                     iq_matrix->non_intra_quantiser_matrix[j];
1167         }
1168     }
1169
1170     /* Commit QM state to HW */
1171     for (i = 0; i < 2; i++) {
1172         unsigned char *qm = NULL;
1173         int qm_type;
1174
1175         if (i == 0) {
1176             if (gen_iq_matrix->load_intra_quantiser_matrix) {
1177                 qm = gen_iq_matrix->intra_quantiser_matrix;
1178                 qm_type = MFX_QM_MPEG_INTRA_QUANTIZER_MATRIX;
1179             }
1180         } else {
1181             if (gen_iq_matrix->load_non_intra_quantiser_matrix) {
1182                 qm = gen_iq_matrix->non_intra_quantiser_matrix;
1183                 qm_type = MFX_QM_MPEG_NON_INTRA_QUANTIZER_MATRIX;
1184             }
1185         }
1186
1187         if (!qm)
1188             continue;
1189
1190         gen7_mfd_qm_state(ctx, qm_type, qm, 64, gen7_mfd_context);
1191     }
1192 }
1193
1194 static void
1195 gen7_mfd_mpeg2_bsd_object(VADriverContextP ctx,
1196                           VAPictureParameterBufferMPEG2 *pic_param,
1197                           VASliceParameterBufferMPEG2 *slice_param,
1198                           VASliceParameterBufferMPEG2 *next_slice_param,
1199                           struct gen7_mfd_context *gen7_mfd_context)
1200 {
1201     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1202     unsigned int width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16;
1203     int mb_count, vpos0, hpos0, vpos1, hpos1, is_field_pic = 0;
1204
1205     if (pic_param->picture_coding_extension.bits.picture_structure == MPEG_TOP_FIELD ||
1206         pic_param->picture_coding_extension.bits.picture_structure == MPEG_BOTTOM_FIELD)
1207         is_field_pic = 1;
1208
1209     vpos0 = slice_param->slice_vertical_position / (1 + is_field_pic);
1210     hpos0 = slice_param->slice_horizontal_position;
1211
1212     if (next_slice_param == NULL) {
1213         vpos1 = ALIGN(pic_param->vertical_size, 16) / 16 / (1 + is_field_pic);
1214         hpos1 = 0;
1215     } else {
1216         vpos1 = next_slice_param->slice_vertical_position / (1 + is_field_pic);
1217         hpos1 = next_slice_param->slice_horizontal_position;
1218     }
1219
1220     mb_count = (vpos1 * width_in_mbs + hpos1) - (vpos0 * width_in_mbs + hpos0);
1221
1222     BEGIN_BCS_BATCH(batch, 5);
1223     OUT_BCS_BATCH(batch, MFD_MPEG2_BSD_OBJECT | (5 - 2));
1224     OUT_BCS_BATCH(batch,
1225                   slice_param->slice_data_size - (slice_param->macroblock_offset >> 3));
1226     OUT_BCS_BATCH(batch,
1227                   slice_param->slice_data_offset + (slice_param->macroblock_offset >> 3));
1228     OUT_BCS_BATCH(batch,
1229                   hpos0 << 24 |
1230                   vpos0 << 16 |
1231                   mb_count << 8 |
1232                   (next_slice_param == NULL) << 5 |
1233                   (next_slice_param == NULL) << 3 |
1234                   (slice_param->macroblock_offset & 0x7));
1235     OUT_BCS_BATCH(batch,
1236                   slice_param->quantiser_scale_code << 24);
1237     ADVANCE_BCS_BATCH(batch);
1238 }
1239
1240 static void
1241 gen7_mfd_mpeg2_decode_picture(VADriverContextP ctx,
1242                               struct decode_state *decode_state,
1243                               struct gen7_mfd_context *gen7_mfd_context)
1244 {
1245     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1246     VAPictureParameterBufferMPEG2 *pic_param;
1247     VASliceParameterBufferMPEG2 *slice_param, *next_slice_param, *next_slice_group_param;
1248     dri_bo *slice_data_bo;
1249     int i, j;
1250
1251     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1252     pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
1253
1254     gen7_mfd_mpeg2_decode_init(ctx, decode_state, gen7_mfd_context);
1255     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
1256     intel_batchbuffer_emit_mi_flush(batch);
1257     gen7_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1258     gen7_mfd_surface_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1259     gen7_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1260     gen7_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1261     gen7_mfd_mpeg2_pic_state(ctx, decode_state, gen7_mfd_context);
1262     gen7_mfd_mpeg2_qm_state(ctx, decode_state, gen7_mfd_context);
1263
1264     for (j = 0; j < decode_state->num_slice_params; j++) {
1265         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
1266         slice_param = (VASliceParameterBufferMPEG2 *)decode_state->slice_params[j]->buffer;
1267         slice_data_bo = decode_state->slice_datas[j]->bo;
1268         gen7_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_MPEG2, gen7_mfd_context);
1269
1270         if (j == decode_state->num_slice_params - 1)
1271             next_slice_group_param = NULL;
1272         else
1273             next_slice_group_param = (VASliceParameterBufferMPEG2 *)decode_state->slice_params[j + 1]->buffer;
1274
1275         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
1276             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
1277
1278             if (i < decode_state->slice_params[j]->num_elements - 1)
1279                 next_slice_param = slice_param + 1;
1280             else
1281                 next_slice_param = next_slice_group_param;
1282
1283             gen7_mfd_mpeg2_bsd_object(ctx, pic_param, slice_param, next_slice_param, gen7_mfd_context);
1284             slice_param++;
1285         }
1286     }
1287
1288     intel_batchbuffer_end_atomic(batch);
1289     intel_batchbuffer_flush(batch);
1290 }
1291
1292 static const int va_to_gen7_vc1_pic_type[5] = {
1293     GEN7_VC1_I_PICTURE,
1294     GEN7_VC1_P_PICTURE,
1295     GEN7_VC1_B_PICTURE,
1296     GEN7_VC1_BI_PICTURE,
1297     GEN7_VC1_P_PICTURE,
1298 };
1299
1300 static const int va_to_gen7_vc1_mv[4] = {
1301     1, /* 1-MV */
1302     2, /* 1-MV half-pel */
1303     3, /* 1-MV half-pef bilinear */
1304     0, /* Mixed MV */
1305 };
1306
1307 static const int b_picture_scale_factor[21] = {
1308     128, 85,  170, 64,  192,
1309     51,  102, 153, 204, 43,
1310     215, 37,  74,  111, 148,
1311     185, 222, 32,  96,  160,
1312     224,
1313 };
1314
1315 static const int va_to_gen7_vc1_condover[3] = {
1316     0,
1317     2,
1318     3
1319 };
1320
1321 static const int va_to_gen7_vc1_profile[4] = {
1322     GEN7_VC1_SIMPLE_PROFILE,
1323     GEN7_VC1_MAIN_PROFILE,
1324     GEN7_VC1_RESERVED_PROFILE,
1325     GEN7_VC1_ADVANCED_PROFILE
1326 };
1327
1328 static void
1329 gen7_mfd_free_vc1_surface(void **data)
1330 {
1331     struct gen7_vc1_surface *gen7_vc1_surface = *data;
1332
1333     if (!gen7_vc1_surface)
1334         return;
1335
1336     dri_bo_unreference(gen7_vc1_surface->dmv);
1337     free(gen7_vc1_surface);
1338     *data = NULL;
1339 }
1340
1341 static void
1342 gen7_mfd_init_vc1_surface(VADriverContextP ctx,
1343                           VAPictureParameterBufferVC1 *pic_param,
1344                           struct object_surface *obj_surface)
1345 {
1346     struct i965_driver_data *i965 = i965_driver_data(ctx);
1347     struct gen7_vc1_surface *gen7_vc1_surface = obj_surface->private_data;
1348
1349     obj_surface->free_private_data = gen7_mfd_free_vc1_surface;
1350
1351     if (!gen7_vc1_surface) {
1352         gen7_vc1_surface = calloc(sizeof(struct gen7_vc1_surface), 1);
1353         assert((obj_surface->size & 0x3f) == 0);
1354         obj_surface->private_data = gen7_vc1_surface;
1355     }
1356
1357     gen7_vc1_surface->picture_type = pic_param->picture_fields.bits.picture_type;
1358
1359     if (gen7_vc1_surface->dmv == NULL) {
1360         gen7_vc1_surface->dmv = dri_bo_alloc(i965->intel.bufmgr,
1361                                              "direct mv w/r buffer",
1362                                              557056,    /* 64 * 128 * 64 */
1363                                              0x1000);
1364     }
1365 }
1366
1367 static void
1368 gen7_mfd_vc1_decode_init(VADriverContextP ctx,
1369                          struct decode_state *decode_state,
1370                          struct gen7_mfd_context *gen7_mfd_context)
1371 {
1372     VAPictureParameterBufferVC1 *pic_param;
1373     struct i965_driver_data *i965 = i965_driver_data(ctx);
1374     struct object_surface *obj_surface;
1375     int i;
1376     dri_bo *bo;
1377
1378     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1379     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1380
1381     /* reference picture */
1382     obj_surface = SURFACE(pic_param->forward_reference_picture);
1383
1384     if (obj_surface && obj_surface->bo)
1385         gen7_mfd_context->reference_surface[0].surface_id = pic_param->forward_reference_picture;
1386     else
1387         gen7_mfd_context->reference_surface[0].surface_id = VA_INVALID_ID;
1388
1389     obj_surface = SURFACE(pic_param->backward_reference_picture);
1390
1391     if (obj_surface && obj_surface->bo)
1392         gen7_mfd_context->reference_surface[1].surface_id = pic_param->backward_reference_picture;
1393     else
1394         gen7_mfd_context->reference_surface[1].surface_id = pic_param->forward_reference_picture;
1395
1396     /* must do so !!! */
1397     for (i = 2; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++)
1398         gen7_mfd_context->reference_surface[i].surface_id = gen7_mfd_context->reference_surface[i % 2].surface_id;
1399
1400     /* Current decoded picture */
1401     obj_surface = SURFACE(decode_state->current_render_target);
1402     assert(obj_surface);
1403     gen7_mfd_init_vc1_surface(ctx, pic_param, obj_surface);
1404     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'));
1405
1406     dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo);
1407     gen7_mfd_context->post_deblocking_output.bo = obj_surface->bo;
1408     dri_bo_reference(gen7_mfd_context->post_deblocking_output.bo);
1409     gen7_mfd_context->post_deblocking_output.valid = pic_param->entrypoint_fields.bits.loopfilter;
1410
1411     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
1412     gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
1413     dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
1414     gen7_mfd_context->pre_deblocking_output.valid = !pic_param->entrypoint_fields.bits.loopfilter;
1415
1416     dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo);
1417     bo = dri_bo_alloc(i965->intel.bufmgr,
1418                       "intra row store",
1419                       128 * 64,
1420                       0x1000);
1421     assert(bo);
1422     gen7_mfd_context->intra_row_store_scratch_buffer.bo = bo;
1423     gen7_mfd_context->intra_row_store_scratch_buffer.valid = 1;
1424
1425     dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
1426     bo = dri_bo_alloc(i965->intel.bufmgr,
1427                       "deblocking filter row store",
1428                       46080, /* 6 * 120 * 64 */
1429                       0x1000);
1430     assert(bo);
1431     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
1432     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1;
1433
1434     dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
1435     bo = dri_bo_alloc(i965->intel.bufmgr,
1436                       "bsd mpc row store",
1437                       11520, /* 1.5 * 120 * 64 */
1438                       0x1000);
1439     assert(bo);
1440     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
1441     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
1442
1443     gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
1444
1445     gen7_mfd_context->bitplane_read_buffer.valid = !!pic_param->bitplane_present.value;
1446     dri_bo_unreference(gen7_mfd_context->bitplane_read_buffer.bo);
1447
1448     if (gen7_mfd_context->bitplane_read_buffer.valid) {
1449         int width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1450         int height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16;
1451         int bitplane_width = ALIGN(width_in_mbs, 2) / 2;
1452         int src_w, src_h;
1453         uint8_t *src = NULL, *dst = NULL;
1454
1455         assert(decode_state->bit_plane->buffer);
1456         src = decode_state->bit_plane->buffer;
1457
1458         bo = dri_bo_alloc(i965->intel.bufmgr,
1459                           "VC-1 Bitplane",
1460                           bitplane_width * bitplane_width,
1461                           0x1000);
1462         assert(bo);
1463         gen7_mfd_context->bitplane_read_buffer.bo = bo;
1464
1465         dri_bo_map(bo, True);
1466         assert(bo->virtual);
1467         dst = bo->virtual;
1468
1469         for (src_h = 0; src_h < height_in_mbs; src_h++) {
1470             for(src_w = 0; src_w < width_in_mbs; src_w++) {
1471                 int src_index, dst_index;
1472                 int src_shift;
1473                 uint8_t src_value;
1474
1475                 src_index = (src_h * width_in_mbs + src_w) / 2;
1476                 src_shift = !((src_h * width_in_mbs + src_w) & 1) * 4;
1477                 src_value = ((src[src_index] >> src_shift) & 0xf);
1478
1479                 dst_index = src_w / 2;
1480                 dst[dst_index] = ((dst[dst_index] >> 4) | (src_value << 4));
1481             }
1482
1483             if (src_w & 1)
1484                 dst[src_w / 2] >>= 4;
1485
1486             dst += bitplane_width;
1487         }
1488
1489         dri_bo_unmap(bo);
1490     } else
1491         gen7_mfd_context->bitplane_read_buffer.bo = NULL;
1492 }
1493
1494 static void
1495 gen7_mfd_vc1_pic_state(VADriverContextP ctx,
1496                        struct decode_state *decode_state,
1497                        struct gen7_mfd_context *gen7_mfd_context)
1498 {
1499     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1500     VAPictureParameterBufferVC1 *pic_param;
1501     struct i965_driver_data *i965 = i965_driver_data(ctx);
1502     struct object_surface *obj_surface;
1503     int alt_pquant_config = 0, alt_pquant_edge_mask = 0, alt_pq;
1504     int dquant, dquantfrm, dqprofile, dqdbedge, dqsbedge, dqbilevel;
1505     int unified_mv_mode;
1506     int ref_field_pic_polarity = 0;
1507     int scale_factor = 0;
1508     int trans_ac_y = 0;
1509     int dmv_surface_valid = 0;
1510     int brfd = 0;
1511     int fcm = 0;
1512     int picture_type;
1513     int profile;
1514     int overlap;
1515     int interpolation_mode = 0;
1516
1517     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1518     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1519
1520     profile = va_to_gen7_vc1_profile[pic_param->sequence_fields.bits.profile];
1521     dquant = pic_param->pic_quantizer_fields.bits.dquant;
1522     dquantfrm = pic_param->pic_quantizer_fields.bits.dq_frame;
1523     dqprofile = pic_param->pic_quantizer_fields.bits.dq_profile;
1524     dqdbedge = pic_param->pic_quantizer_fields.bits.dq_db_edge;
1525     dqsbedge = pic_param->pic_quantizer_fields.bits.dq_sb_edge;
1526     dqbilevel = pic_param->pic_quantizer_fields.bits.dq_binary_level;
1527     alt_pq = pic_param->pic_quantizer_fields.bits.alt_pic_quantizer;
1528
1529     if (dquant == 0) {
1530         alt_pquant_config = 0;
1531         alt_pquant_edge_mask = 0;
1532     } else if (dquant == 2) {
1533         alt_pquant_config = 1;
1534         alt_pquant_edge_mask = 0xf;
1535     } else {
1536         assert(dquant == 1);
1537         if (dquantfrm == 0) {
1538             alt_pquant_config = 0;
1539             alt_pquant_edge_mask = 0;
1540             alt_pq = 0;
1541         } else {
1542             assert(dquantfrm == 1);
1543             alt_pquant_config = 1;
1544
1545             switch (dqprofile) {
1546             case 3:
1547                 if (dqbilevel == 0) {
1548                     alt_pquant_config = 2;
1549                     alt_pquant_edge_mask = 0;
1550                 } else {
1551                     assert(dqbilevel == 1);
1552                     alt_pquant_config = 3;
1553                     alt_pquant_edge_mask = 0;
1554                 }
1555                 break;
1556
1557             case 0:
1558                 alt_pquant_edge_mask = 0xf;
1559                 break;
1560
1561             case 1:
1562                 if (dqdbedge == 3)
1563                     alt_pquant_edge_mask = 0x9;
1564                 else
1565                     alt_pquant_edge_mask = (0x3 << dqdbedge);
1566
1567                 break;
1568
1569             case 2:
1570                 alt_pquant_edge_mask = (0x1 << dqsbedge);
1571                 break;
1572
1573             default:
1574                 assert(0);
1575             }
1576         }
1577     }
1578
1579     if (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation) {
1580         assert(pic_param->mv_fields.bits.mv_mode2 < 4);
1581         unified_mv_mode = va_to_gen7_vc1_mv[pic_param->mv_fields.bits.mv_mode2];
1582     } else {
1583         assert(pic_param->mv_fields.bits.mv_mode < 4);
1584         unified_mv_mode = va_to_gen7_vc1_mv[pic_param->mv_fields.bits.mv_mode];
1585     }
1586
1587     if (pic_param->sequence_fields.bits.interlace == 1 &&
1588         pic_param->picture_fields.bits.frame_coding_mode != 0) { /* frame-interlace or field-interlace */
1589         /* FIXME: calculate reference field picture polarity */
1590         assert(0);
1591         ref_field_pic_polarity = 0;
1592     }
1593
1594     if (pic_param->b_picture_fraction < 21)
1595         scale_factor = b_picture_scale_factor[pic_param->b_picture_fraction];
1596
1597     picture_type = va_to_gen7_vc1_pic_type[pic_param->picture_fields.bits.picture_type];
1598
1599     if (profile == GEN7_VC1_ADVANCED_PROFILE &&
1600         picture_type == GEN7_VC1_I_PICTURE)
1601         picture_type = GEN7_VC1_BI_PICTURE;
1602
1603     if (picture_type == GEN7_VC1_I_PICTURE || picture_type == GEN7_VC1_BI_PICTURE) /* I picture */
1604         trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx2;
1605     else
1606         trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx1;
1607
1608
1609     if (picture_type == GEN7_VC1_B_PICTURE) {
1610         struct gen7_vc1_surface *gen7_vc1_surface = NULL;
1611
1612         obj_surface = SURFACE(pic_param->backward_reference_picture);
1613         assert(obj_surface);
1614         gen7_vc1_surface = obj_surface->private_data;
1615
1616         if (!gen7_vc1_surface ||
1617             (va_to_gen7_vc1_pic_type[gen7_vc1_surface->picture_type] == GEN7_VC1_I_PICTURE ||
1618              va_to_gen7_vc1_pic_type[gen7_vc1_surface->picture_type] == GEN7_VC1_BI_PICTURE))
1619             dmv_surface_valid = 0;
1620         else
1621             dmv_surface_valid = 1;
1622     }
1623
1624     assert(pic_param->picture_fields.bits.frame_coding_mode < 3);
1625
1626     if (pic_param->picture_fields.bits.frame_coding_mode < 2)
1627         fcm = pic_param->picture_fields.bits.frame_coding_mode;
1628     else {
1629         if (pic_param->picture_fields.bits.top_field_first)
1630             fcm = 2;
1631         else
1632             fcm = 3;
1633     }
1634
1635     if (pic_param->picture_fields.bits.picture_type == GEN7_VC1_B_PICTURE) { /* B picture */
1636         brfd = pic_param->reference_fields.bits.reference_distance;
1637         brfd = (scale_factor * brfd) >> 8;
1638         brfd = pic_param->reference_fields.bits.reference_distance - brfd - 1;
1639
1640         if (brfd < 0)
1641             brfd = 0;
1642     }
1643
1644     overlap = pic_param->sequence_fields.bits.overlap;
1645     if (profile != GEN7_VC1_ADVANCED_PROFILE && pic_param->pic_quantizer_fields.bits.pic_quantizer_scale < 9)
1646         overlap = 0;
1647
1648     assert(pic_param->conditional_overlap_flag < 3);
1649     assert(pic_param->mv_fields.bits.mv_table < 4); /* FIXME: interlace mode */
1650
1651     if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPelBilinear ||
1652         (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation &&
1653          pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPelBilinear))
1654         interpolation_mode = 9; /* Half-pel bilinear */
1655     else if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPel ||
1656              (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation &&
1657               pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPel))
1658         interpolation_mode = 1; /* Half-pel bicubic */
1659     else
1660         interpolation_mode = 0; /* Quarter-pel bicubic */
1661
1662     BEGIN_BCS_BATCH(batch, 6);
1663     OUT_BCS_BATCH(batch, MFD_VC1_LONG_PIC_STATE | (6 - 2));
1664     OUT_BCS_BATCH(batch,
1665                   (((ALIGN(pic_param->coded_height, 16) / 16) - 1) << 16) |
1666                   ((ALIGN(pic_param->coded_width, 16) / 16) - 1));
1667     OUT_BCS_BATCH(batch,
1668                   ((ALIGN(pic_param->coded_width, 16) / 16 + 1) / 2 - 1) << 24 |
1669                   dmv_surface_valid << 15 |
1670                   (pic_param->pic_quantizer_fields.bits.quantizer == 0) << 14 | /* implicit quantizer */
1671                   pic_param->rounding_control << 13 |
1672                   pic_param->sequence_fields.bits.syncmarker << 12 |
1673                   interpolation_mode << 8 |
1674                   0 << 7 | /* FIXME: scale up or down ??? */
1675                   pic_param->range_reduction_frame << 6 |
1676                   pic_param->entrypoint_fields.bits.loopfilter << 5 |
1677                   overlap << 4 |
1678                   !pic_param->picture_fields.bits.is_first_field << 3 |
1679                   (pic_param->sequence_fields.bits.profile == 3) << 0);
1680     OUT_BCS_BATCH(batch,
1681                   va_to_gen7_vc1_condover[pic_param->conditional_overlap_flag] << 29 |
1682                   picture_type << 26 |
1683                   fcm << 24 |
1684                   alt_pq << 16 |
1685                   pic_param->pic_quantizer_fields.bits.pic_quantizer_scale << 8 |
1686                   scale_factor << 0);
1687     OUT_BCS_BATCH(batch,
1688                   unified_mv_mode << 28 |
1689                   pic_param->mv_fields.bits.four_mv_switch << 27 |
1690                   pic_param->fast_uvmc_flag << 26 |
1691                   ref_field_pic_polarity << 25 |
1692                   pic_param->reference_fields.bits.num_reference_pictures << 24 |
1693                   pic_param->reference_fields.bits.reference_distance << 20 |
1694                   pic_param->reference_fields.bits.reference_distance << 16 | /* FIXME: ??? */
1695                   pic_param->mv_fields.bits.extended_dmv_range << 10 |
1696                   pic_param->mv_fields.bits.extended_mv_range << 8 |
1697                   alt_pquant_edge_mask << 4 |
1698                   alt_pquant_config << 2 |
1699                   pic_param->pic_quantizer_fields.bits.half_qp << 1 |
1700                   pic_param->pic_quantizer_fields.bits.pic_quantizer_type << 0);
1701     OUT_BCS_BATCH(batch,
1702                   !!pic_param->bitplane_present.value << 31 |
1703                   !pic_param->bitplane_present.flags.bp_forward_mb << 30 |
1704                   !pic_param->bitplane_present.flags.bp_mv_type_mb << 29 |
1705                   !pic_param->bitplane_present.flags.bp_skip_mb << 28 |
1706                   !pic_param->bitplane_present.flags.bp_direct_mb << 27 |
1707                   !pic_param->bitplane_present.flags.bp_overflags << 26 |
1708                   !pic_param->bitplane_present.flags.bp_ac_pred << 25 |
1709                   !pic_param->bitplane_present.flags.bp_field_tx << 24 |
1710                   pic_param->mv_fields.bits.mv_table << 20 |
1711                   pic_param->mv_fields.bits.four_mv_block_pattern_table << 18 |
1712                   pic_param->mv_fields.bits.two_mv_block_pattern_table << 16 |
1713                   pic_param->transform_fields.bits.frame_level_transform_type << 12 |
1714                   pic_param->transform_fields.bits.mb_level_transform_type_flag << 11 |
1715                   pic_param->mb_mode_table << 8 |
1716                   trans_ac_y << 6 |
1717                   pic_param->transform_fields.bits.transform_ac_codingset_idx1 << 4 |
1718                   pic_param->transform_fields.bits.intra_transform_dc_table << 3 |
1719                   pic_param->cbp_table << 0);
1720     ADVANCE_BCS_BATCH(batch);
1721 }
1722
1723 static void
1724 gen7_mfd_vc1_pred_pipe_state(VADriverContextP ctx,
1725                              struct decode_state *decode_state,
1726                              struct gen7_mfd_context *gen7_mfd_context)
1727 {
1728     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1729     VAPictureParameterBufferVC1 *pic_param;
1730     int intensitycomp_single;
1731
1732     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1733     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1734
1735     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1736     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1737     intensitycomp_single = (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation);
1738
1739     BEGIN_BCS_BATCH(batch, 6);
1740     OUT_BCS_BATCH(batch, MFX_VC1_PRED_PIPE_STATE | (6 - 2));
1741     OUT_BCS_BATCH(batch,
1742                   0 << 14 | /* FIXME: double ??? */
1743                   0 << 12 |
1744                   intensitycomp_single << 10 |
1745                   intensitycomp_single << 8 |
1746                   0 << 4 | /* FIXME: interlace mode */
1747                   0);
1748     OUT_BCS_BATCH(batch,
1749                   pic_param->luma_shift << 16 |
1750                   pic_param->luma_scale << 0); /* FIXME: Luma Scaling */
1751     OUT_BCS_BATCH(batch, 0);
1752     OUT_BCS_BATCH(batch, 0);
1753     OUT_BCS_BATCH(batch, 0);
1754     ADVANCE_BCS_BATCH(batch);
1755 }
1756
1757
1758 static void
1759 gen7_mfd_vc1_directmode_state(VADriverContextP ctx,
1760                               struct decode_state *decode_state,
1761                               struct gen7_mfd_context *gen7_mfd_context)
1762 {
1763     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1764     VAPictureParameterBufferVC1 *pic_param;
1765     struct i965_driver_data *i965 = i965_driver_data(ctx);
1766     struct object_surface *obj_surface;
1767     dri_bo *dmv_read_buffer = NULL, *dmv_write_buffer = NULL;
1768
1769     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1770     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1771
1772     obj_surface = SURFACE(decode_state->current_render_target);
1773
1774     if (obj_surface && obj_surface->private_data) {
1775         dmv_write_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv;
1776     }
1777
1778     obj_surface = SURFACE(pic_param->backward_reference_picture);
1779
1780     if (obj_surface && obj_surface->private_data) {
1781         dmv_read_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv;
1782     }
1783
1784     BEGIN_BCS_BATCH(batch, 3);
1785     OUT_BCS_BATCH(batch, MFX_VC1_DIRECTMODE_STATE | (3 - 2));
1786
1787     if (dmv_write_buffer)
1788         OUT_BCS_RELOC(batch, dmv_write_buffer,
1789                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
1790                       0);
1791     else
1792         OUT_BCS_BATCH(batch, 0);
1793
1794     if (dmv_read_buffer)
1795         OUT_BCS_RELOC(batch, dmv_read_buffer,
1796                       I915_GEM_DOMAIN_INSTRUCTION, 0,
1797                       0);
1798     else
1799         OUT_BCS_BATCH(batch, 0);
1800
1801     ADVANCE_BCS_BATCH(batch);
1802 }
1803
1804 static int
1805 gen7_mfd_vc1_get_macroblock_bit_offset(uint8_t *buf, int in_slice_data_bit_offset, int profile)
1806 {
1807     int out_slice_data_bit_offset;
1808     int slice_header_size = in_slice_data_bit_offset / 8;
1809     int i, j;
1810
1811     if (profile != 3)
1812         out_slice_data_bit_offset = in_slice_data_bit_offset;
1813     else {
1814         for (i = 0, j = 0; i < slice_header_size; i++, j++) {
1815             if (!buf[j] && !buf[j + 1] && buf[j + 2] == 3 && buf[j + 3] < 4) {
1816                 i++, j += 2;
1817             }
1818         }
1819
1820         out_slice_data_bit_offset = 8 * j + in_slice_data_bit_offset % 8;
1821     }
1822
1823     return out_slice_data_bit_offset;
1824 }
1825
1826 static void
1827 gen7_mfd_vc1_bsd_object(VADriverContextP ctx,
1828                         VAPictureParameterBufferVC1 *pic_param,
1829                         VASliceParameterBufferVC1 *slice_param,
1830                         VASliceParameterBufferVC1 *next_slice_param,
1831                         dri_bo *slice_data_bo,
1832                         struct gen7_mfd_context *gen7_mfd_context)
1833 {
1834     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1835     int next_slice_start_vert_pos;
1836     int macroblock_offset;
1837     uint8_t *slice_data = NULL;
1838
1839     dri_bo_map(slice_data_bo, 0);
1840     slice_data = (uint8_t *)(slice_data_bo->virtual + slice_param->slice_data_offset);
1841     macroblock_offset = gen7_mfd_vc1_get_macroblock_bit_offset(slice_data,
1842                                                                slice_param->macroblock_offset,
1843                                                                pic_param->sequence_fields.bits.profile);
1844     dri_bo_unmap(slice_data_bo);
1845
1846     if (next_slice_param)
1847         next_slice_start_vert_pos = next_slice_param->slice_vertical_position;
1848     else
1849         next_slice_start_vert_pos = ALIGN(pic_param->coded_height, 16) / 16;
1850
1851     BEGIN_BCS_BATCH(batch, 5);
1852     OUT_BCS_BATCH(batch, MFD_VC1_BSD_OBJECT | (5 - 2));
1853     OUT_BCS_BATCH(batch,
1854                   slice_param->slice_data_size - (macroblock_offset >> 3));
1855     OUT_BCS_BATCH(batch,
1856                   slice_param->slice_data_offset + (macroblock_offset >> 3));
1857     OUT_BCS_BATCH(batch,
1858                   slice_param->slice_vertical_position << 16 |
1859                   next_slice_start_vert_pos << 0);
1860     OUT_BCS_BATCH(batch,
1861                   (macroblock_offset & 0x7));
1862     ADVANCE_BCS_BATCH(batch);
1863 }
1864
1865 static void
1866 gen7_mfd_vc1_decode_picture(VADriverContextP ctx,
1867                             struct decode_state *decode_state,
1868                             struct gen7_mfd_context *gen7_mfd_context)
1869 {
1870     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1871     VAPictureParameterBufferVC1 *pic_param;
1872     VASliceParameterBufferVC1 *slice_param, *next_slice_param, *next_slice_group_param;
1873     dri_bo *slice_data_bo;
1874     int i, j;
1875
1876     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1877     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1878
1879     gen7_mfd_vc1_decode_init(ctx, decode_state, gen7_mfd_context);
1880     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
1881     intel_batchbuffer_emit_mi_flush(batch);
1882     gen7_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
1883     gen7_mfd_surface_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
1884     gen7_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
1885     gen7_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
1886     gen7_mfd_vc1_pic_state(ctx, decode_state, gen7_mfd_context);
1887     gen7_mfd_vc1_pred_pipe_state(ctx, decode_state, gen7_mfd_context);
1888     gen7_mfd_vc1_directmode_state(ctx, decode_state, gen7_mfd_context);
1889
1890     for (j = 0; j < decode_state->num_slice_params; j++) {
1891         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
1892         slice_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j]->buffer;
1893         slice_data_bo = decode_state->slice_datas[j]->bo;
1894         gen7_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_VC1, gen7_mfd_context);
1895
1896         if (j == decode_state->num_slice_params - 1)
1897             next_slice_group_param = NULL;
1898         else
1899             next_slice_group_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j + 1]->buffer;
1900
1901         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
1902             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
1903
1904             if (i < decode_state->slice_params[j]->num_elements - 1)
1905                 next_slice_param = slice_param + 1;
1906             else
1907                 next_slice_param = next_slice_group_param;
1908
1909             gen7_mfd_vc1_bsd_object(ctx, pic_param, slice_param, next_slice_param, slice_data_bo, gen7_mfd_context);
1910             slice_param++;
1911         }
1912     }
1913
1914     intel_batchbuffer_end_atomic(batch);
1915     intel_batchbuffer_flush(batch);
1916 }
1917
1918 static void
1919 gen7_mfd_decode_picture(VADriverContextP ctx,
1920                         VAProfile profile,
1921                         union codec_state *codec_state,
1922                         struct hw_context *hw_context)
1923
1924 {
1925     struct gen7_mfd_context *gen7_mfd_context = (struct gen7_mfd_context *)hw_context;
1926     struct decode_state *decode_state = &codec_state->dec;
1927
1928     assert(gen7_mfd_context);
1929
1930     switch (profile) {
1931     case VAProfileMPEG2Simple:
1932     case VAProfileMPEG2Main:
1933         gen7_mfd_mpeg2_decode_picture(ctx, decode_state, gen7_mfd_context);
1934         break;
1935
1936     case VAProfileH264Baseline:
1937     case VAProfileH264Main:
1938     case VAProfileH264High:
1939         gen7_mfd_avc_decode_picture(ctx, decode_state, gen7_mfd_context);
1940         break;
1941
1942     case VAProfileVC1Simple:
1943     case VAProfileVC1Main:
1944     case VAProfileVC1Advanced:
1945         gen7_mfd_vc1_decode_picture(ctx, decode_state, gen7_mfd_context);
1946         break;
1947
1948     default:
1949         assert(0);
1950         break;
1951     }
1952 }
1953
1954 static void
1955 gen7_mfd_context_destroy(void *hw_context)
1956 {
1957     struct gen7_mfd_context *gen7_mfd_context = (struct gen7_mfd_context *)hw_context;
1958
1959     dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo);
1960     gen7_mfd_context->post_deblocking_output.bo = NULL;
1961
1962     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
1963     gen7_mfd_context->pre_deblocking_output.bo = NULL;
1964
1965     dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo);
1966     gen7_mfd_context->intra_row_store_scratch_buffer.bo = NULL;
1967
1968     dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
1969     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
1970
1971     dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
1972     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
1973
1974     dri_bo_unreference(gen7_mfd_context->mpr_row_store_scratch_buffer.bo);
1975     gen7_mfd_context->mpr_row_store_scratch_buffer.bo = NULL;
1976
1977     dri_bo_unreference(gen7_mfd_context->bitplane_read_buffer.bo);
1978     gen7_mfd_context->bitplane_read_buffer.bo = NULL;
1979
1980     intel_batchbuffer_free(gen7_mfd_context->base.batch);
1981     free(gen7_mfd_context);
1982 }
1983
1984 struct hw_context *
1985 gen7_dec_hw_context_init(VADriverContextP ctx, VAProfile profile)
1986 {
1987     struct intel_driver_data *intel = intel_driver_data(ctx);
1988     struct gen7_mfd_context *gen7_mfd_context = calloc(1, sizeof(struct gen7_mfd_context));
1989     int i;
1990
1991     gen7_mfd_context->base.destroy = gen7_mfd_context_destroy;
1992     gen7_mfd_context->base.run = gen7_mfd_decode_picture;
1993     gen7_mfd_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER);
1994
1995     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
1996         gen7_mfd_context->reference_surface[i].surface_id = VA_INVALID_ID;
1997         gen7_mfd_context->reference_surface[i].frame_store_id = -1;
1998     }
1999
2000     return (struct hw_context *)gen7_mfd_context;
2001 }