2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Xiang Haihao <haihao.xiang@intel.com>
31 #include <va/va_dec_jpeg.h>
33 #include "intel_batchbuffer.h"
34 #include "intel_driver.h"
35 #include "i965_defines.h"
36 #include "i965_drv_video.h"
37 #include "i965_decoder_utils.h"
40 #include "intel_media.h"
42 static const uint32_t zigzag_direct[64] = {
43 0, 1, 8, 16, 9, 2, 3, 10,
44 17, 24, 32, 25, 18, 11, 4, 5,
45 12, 19, 26, 33, 40, 48, 41, 34,
46 27, 20, 13, 6, 7, 14, 21, 28,
47 35, 42, 49, 56, 57, 50, 43, 36,
48 29, 22, 15, 23, 30, 37, 44, 51,
49 58, 59, 52, 45, 38, 31, 39, 46,
50 53, 60, 61, 54, 47, 55, 62, 63
54 gen7_mfd_init_avc_surface(VADriverContextP ctx,
55 VAPictureParameterBufferH264 *pic_param,
56 struct object_surface *obj_surface)
58 struct i965_driver_data *i965 = i965_driver_data(ctx);
59 GenAvcSurface *gen7_avc_surface = obj_surface->private_data;
60 int width_in_mbs, height_in_mbs;
62 obj_surface->free_private_data = gen_free_avc_surface;
63 width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
64 height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; /* frame height */
66 if (!gen7_avc_surface) {
67 gen7_avc_surface = calloc(sizeof(GenAvcSurface), 1);
68 assert(gen7_avc_surface);
69 gen7_avc_surface->base.frame_store_id = -1;
70 assert((obj_surface->size & 0x3f) == 0);
71 obj_surface->private_data = gen7_avc_surface;
74 gen7_avc_surface->dmv_bottom_flag = (pic_param->pic_fields.bits.field_pic_flag &&
75 !pic_param->seq_fields.bits.direct_8x8_inference_flag);
77 if (gen7_avc_surface->dmv_top == NULL) {
78 gen7_avc_surface->dmv_top = dri_bo_alloc(i965->intel.bufmgr,
79 "direct mv w/r buffer",
80 width_in_mbs * (height_in_mbs + 1) * 64,
82 assert(gen7_avc_surface->dmv_top);
85 if (gen7_avc_surface->dmv_bottom_flag &&
86 gen7_avc_surface->dmv_bottom == NULL) {
87 gen7_avc_surface->dmv_bottom = dri_bo_alloc(i965->intel.bufmgr,
88 "direct mv w/r buffer",
89 width_in_mbs * (height_in_mbs + 1) * 64,
91 assert(gen7_avc_surface->dmv_bottom);
96 gen7_mfd_pipe_mode_select(VADriverContextP ctx,
97 struct decode_state *decode_state,
99 struct gen7_mfd_context *gen7_mfd_context)
101 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
103 assert(standard_select == MFX_FORMAT_MPEG2 ||
104 standard_select == MFX_FORMAT_AVC ||
105 standard_select == MFX_FORMAT_VC1 ||
106 standard_select == MFX_FORMAT_JPEG);
108 BEGIN_BCS_BATCH(batch, 5);
109 OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2));
111 (MFX_LONG_MODE << 17) | /* Currently only support long format */
112 (MFD_MODE_VLD << 15) | /* VLD mode */
113 (0 << 10) | /* disable Stream-Out */
114 (gen7_mfd_context->post_deblocking_output.valid << 9) | /* Post Deblocking Output */
115 (gen7_mfd_context->pre_deblocking_output.valid << 8) | /* Pre Deblocking Output */
116 (0 << 5) | /* not in stitch mode */
117 (MFX_CODEC_DECODE << 4) | /* decoding mode */
118 (standard_select << 0));
120 (0 << 4) | /* terminate if AVC motion and POC table error occurs */
121 (0 << 3) | /* terminate if AVC mbdata error occurs */
122 (0 << 2) | /* terminate if AVC CABAC/CAVLC decode error occurs */
125 OUT_BCS_BATCH(batch, 0); /* pic status/error report id */
126 OUT_BCS_BATCH(batch, 0); /* reserved */
127 ADVANCE_BCS_BATCH(batch);
131 gen7_mfd_surface_state(VADriverContextP ctx,
132 struct decode_state *decode_state,
134 struct gen7_mfd_context *gen7_mfd_context)
136 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
137 struct object_surface *obj_surface = decode_state->render_object;
138 unsigned int y_cb_offset;
139 unsigned int y_cr_offset;
140 unsigned int surface_format;
144 y_cb_offset = obj_surface->y_cb_offset;
145 y_cr_offset = obj_surface->y_cr_offset;
147 surface_format = obj_surface->fourcc == VA_FOURCC_Y800 ?
148 MFX_SURFACE_MONOCHROME : MFX_SURFACE_PLANAR_420_8;
150 BEGIN_BCS_BATCH(batch, 6);
151 OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
152 OUT_BCS_BATCH(batch, 0);
154 ((obj_surface->orig_height - 1) << 18) |
155 ((obj_surface->orig_width - 1) << 4));
157 (surface_format << 28) | /* 420 planar YUV surface */
158 ((standard_select != MFX_FORMAT_JPEG) << 27) | /* interleave chroma, set to 0 for JPEG */
159 (0 << 22) | /* surface object control state, ignored */
160 ((obj_surface->width - 1) << 3) | /* pitch */
161 (0 << 2) | /* must be 0 */
162 (1 << 1) | /* must be tiled */
163 (I965_TILEWALK_YMAJOR << 0)); /* tile walk, must be 1 */
165 (0 << 16) | /* X offset for U(Cb), must be 0 */
166 (y_cb_offset << 0)); /* Y offset for U(Cb) */
168 (0 << 16) | /* X offset for V(Cr), must be 0 */
169 (y_cr_offset << 0)); /* Y offset for V(Cr), must be 0 for video codec, non-zoro for JPEG */
170 ADVANCE_BCS_BATCH(batch);
174 gen7_mfd_pipe_buf_addr_state(VADriverContextP ctx,
175 struct decode_state *decode_state,
177 struct gen7_mfd_context *gen7_mfd_context)
179 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
182 BEGIN_BCS_BATCH(batch, 24);
183 OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
184 if (gen7_mfd_context->pre_deblocking_output.valid)
185 OUT_BCS_RELOC(batch, gen7_mfd_context->pre_deblocking_output.bo,
186 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
189 OUT_BCS_BATCH(batch, 0);
191 if (gen7_mfd_context->post_deblocking_output.valid)
192 OUT_BCS_RELOC(batch, gen7_mfd_context->post_deblocking_output.bo,
193 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
196 OUT_BCS_BATCH(batch, 0);
198 OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
199 OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
201 if (gen7_mfd_context->intra_row_store_scratch_buffer.valid)
202 OUT_BCS_RELOC(batch, gen7_mfd_context->intra_row_store_scratch_buffer.bo,
203 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
206 OUT_BCS_BATCH(batch, 0);
208 if (gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid)
209 OUT_BCS_RELOC(batch, gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo,
210 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
213 OUT_BCS_BATCH(batch, 0);
216 for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
217 struct object_surface *obj_surface;
219 if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID &&
220 gen7_mfd_context->reference_surface[i].obj_surface &&
221 gen7_mfd_context->reference_surface[i].obj_surface->bo) {
222 obj_surface = gen7_mfd_context->reference_surface[i].obj_surface;
224 OUT_BCS_RELOC(batch, obj_surface->bo,
225 I915_GEM_DOMAIN_INSTRUCTION, 0,
228 OUT_BCS_BATCH(batch, 0);
232 OUT_BCS_BATCH(batch, 0); /* ignore DW23 for decoding */
233 ADVANCE_BCS_BATCH(batch);
237 gen7_mfd_ind_obj_base_addr_state(VADriverContextP ctx,
238 dri_bo *slice_data_bo,
240 struct gen7_mfd_context *gen7_mfd_context)
242 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
244 BEGIN_BCS_BATCH(batch, 11);
245 OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
246 OUT_BCS_RELOC(batch, slice_data_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); /* MFX Indirect Bitstream Object Base Address */
247 OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
248 OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
249 OUT_BCS_BATCH(batch, 0);
250 OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
251 OUT_BCS_BATCH(batch, 0);
252 OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
253 OUT_BCS_BATCH(batch, 0);
254 OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
255 OUT_BCS_BATCH(batch, 0);
256 ADVANCE_BCS_BATCH(batch);
260 gen7_mfd_bsp_buf_base_addr_state(VADriverContextP ctx,
261 struct decode_state *decode_state,
263 struct gen7_mfd_context *gen7_mfd_context)
265 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
267 BEGIN_BCS_BATCH(batch, 4);
268 OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
270 if (gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid)
271 OUT_BCS_RELOC(batch, gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo,
272 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
275 OUT_BCS_BATCH(batch, 0);
277 if (gen7_mfd_context->mpr_row_store_scratch_buffer.valid)
278 OUT_BCS_RELOC(batch, gen7_mfd_context->mpr_row_store_scratch_buffer.bo,
279 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
282 OUT_BCS_BATCH(batch, 0);
284 if (gen7_mfd_context->bitplane_read_buffer.valid)
285 OUT_BCS_RELOC(batch, gen7_mfd_context->bitplane_read_buffer.bo,
286 I915_GEM_DOMAIN_INSTRUCTION, 0,
289 OUT_BCS_BATCH(batch, 0);
291 ADVANCE_BCS_BATCH(batch);
295 gen7_mfd_qm_state(VADriverContextP ctx,
299 struct gen7_mfd_context *gen7_mfd_context)
301 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
302 unsigned int qm_buffer[16];
304 assert(qm_length <= 16 * 4);
305 memcpy(qm_buffer, qm, qm_length);
307 BEGIN_BCS_BATCH(batch, 18);
308 OUT_BCS_BATCH(batch, MFX_QM_STATE | (18 - 2));
309 OUT_BCS_BATCH(batch, qm_type << 0);
310 intel_batchbuffer_data(batch, qm_buffer, 16 * 4);
311 ADVANCE_BCS_BATCH(batch);
315 gen7_mfd_avc_img_state(VADriverContextP ctx,
316 struct decode_state *decode_state,
317 struct gen7_mfd_context *gen7_mfd_context)
319 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
321 int mbaff_frame_flag;
322 unsigned int width_in_mbs, height_in_mbs;
323 VAPictureParameterBufferH264 *pic_param;
325 assert(decode_state->pic_param && decode_state->pic_param->buffer);
326 pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
328 if (pic_param->CurrPic.flags & VA_PICTURE_H264_TOP_FIELD)
330 else if (pic_param->CurrPic.flags & VA_PICTURE_H264_BOTTOM_FIELD)
335 if ((img_struct & 0x1) == 0x1) {
336 assert(pic_param->pic_fields.bits.field_pic_flag == 0x1);
338 assert(pic_param->pic_fields.bits.field_pic_flag == 0x0);
341 if (pic_param->seq_fields.bits.frame_mbs_only_flag) { /* a frame containing only frame macroblocks */
342 assert(pic_param->seq_fields.bits.mb_adaptive_frame_field_flag == 0);
343 assert(pic_param->pic_fields.bits.field_pic_flag == 0);
345 assert(pic_param->seq_fields.bits.direct_8x8_inference_flag == 1); /* see H.264 spec */
348 mbaff_frame_flag = (pic_param->seq_fields.bits.mb_adaptive_frame_field_flag &&
349 !pic_param->pic_fields.bits.field_pic_flag);
351 width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
352 height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; /* frame height */
354 /* MFX unit doesn't support 4:2:2 and 4:4:4 picture */
355 assert(pic_param->seq_fields.bits.chroma_format_idc == 0 || /* monochrome picture */
356 pic_param->seq_fields.bits.chroma_format_idc == 1); /* 4:2:0 */
357 assert(pic_param->seq_fields.bits.residual_colour_transform_flag == 0); /* only available for 4:4:4 */
359 BEGIN_BCS_BATCH(batch, 16);
360 OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (16 - 2));
362 (width_in_mbs * height_in_mbs - 1));
364 ((height_in_mbs - 1) << 16) |
365 ((width_in_mbs - 1) << 0));
367 ((pic_param->second_chroma_qp_index_offset & 0x1f) << 24) |
368 ((pic_param->chroma_qp_index_offset & 0x1f) << 16) |
369 (0 << 14) | /* Max-bit conformance Intra flag ??? FIXME */
370 (0 << 13) | /* Max Macroblock size conformance Inter flag ??? FIXME */
371 (pic_param->pic_fields.bits.weighted_pred_flag << 12) | /* differ from GEN6 */
372 (pic_param->pic_fields.bits.weighted_bipred_idc << 10) |
375 (pic_param->seq_fields.bits.chroma_format_idc << 10) |
376 (pic_param->pic_fields.bits.entropy_coding_mode_flag << 7) |
377 ((!pic_param->pic_fields.bits.reference_pic_flag) << 6) |
378 (pic_param->pic_fields.bits.constrained_intra_pred_flag << 5) |
379 (pic_param->seq_fields.bits.direct_8x8_inference_flag << 4) |
380 (pic_param->pic_fields.bits.transform_8x8_mode_flag << 3) |
381 (pic_param->seq_fields.bits.frame_mbs_only_flag << 2) |
382 (mbaff_frame_flag << 1) |
383 (pic_param->pic_fields.bits.field_pic_flag << 0));
384 OUT_BCS_BATCH(batch, 0);
385 OUT_BCS_BATCH(batch, 0);
386 OUT_BCS_BATCH(batch, 0);
387 OUT_BCS_BATCH(batch, 0);
388 OUT_BCS_BATCH(batch, 0);
389 OUT_BCS_BATCH(batch, 0);
390 OUT_BCS_BATCH(batch, 0);
391 OUT_BCS_BATCH(batch, 0);
392 OUT_BCS_BATCH(batch, 0);
393 OUT_BCS_BATCH(batch, 0);
394 OUT_BCS_BATCH(batch, 0);
395 ADVANCE_BCS_BATCH(batch);
399 gen7_mfd_avc_qm_state(VADriverContextP ctx,
400 struct decode_state *decode_state,
401 struct gen7_mfd_context *gen7_mfd_context)
403 VAIQMatrixBufferH264 *iq_matrix;
404 VAPictureParameterBufferH264 *pic_param;
406 if (decode_state->iq_matrix && decode_state->iq_matrix->buffer)
407 iq_matrix = (VAIQMatrixBufferH264 *)decode_state->iq_matrix->buffer;
409 iq_matrix = &gen7_mfd_context->iq_matrix.h264;
411 assert(decode_state->pic_param && decode_state->pic_param->buffer);
412 pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
414 gen7_mfd_qm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, &iq_matrix->ScalingList4x4[0][0], 3 * 16, gen7_mfd_context);
415 gen7_mfd_qm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, &iq_matrix->ScalingList4x4[3][0], 3 * 16, gen7_mfd_context);
417 if (pic_param->pic_fields.bits.transform_8x8_mode_flag) {
418 gen7_mfd_qm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, &iq_matrix->ScalingList8x8[0][0], 64, gen7_mfd_context);
419 gen7_mfd_qm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, &iq_matrix->ScalingList8x8[1][0], 64, gen7_mfd_context);
424 gen7_mfd_avc_directmode_state(VADriverContextP ctx,
425 struct decode_state *decode_state,
426 VAPictureParameterBufferH264 *pic_param,
427 VASliceParameterBufferH264 *slice_param,
428 struct gen7_mfd_context *gen7_mfd_context)
430 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
431 struct object_surface *obj_surface;
432 GenAvcSurface *gen7_avc_surface;
433 VAPictureH264 *va_pic;
436 BEGIN_BCS_BATCH(batch, 69);
437 OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
439 /* reference surfaces 0..15 */
440 for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
441 if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID &&
442 gen7_mfd_context->reference_surface[i].obj_surface &&
443 gen7_mfd_context->reference_surface[i].obj_surface->private_data) {
445 obj_surface = gen7_mfd_context->reference_surface[i].obj_surface;
446 gen7_avc_surface = obj_surface->private_data;
447 OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
448 I915_GEM_DOMAIN_INSTRUCTION, 0,
451 if (gen7_avc_surface->dmv_bottom_flag == 1)
452 OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_bottom,
453 I915_GEM_DOMAIN_INSTRUCTION, 0,
456 OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
457 I915_GEM_DOMAIN_INSTRUCTION, 0,
460 OUT_BCS_BATCH(batch, 0);
461 OUT_BCS_BATCH(batch, 0);
465 /* the current decoding frame/field */
466 va_pic = &pic_param->CurrPic;
467 obj_surface = decode_state->render_object;
468 assert(obj_surface->bo && obj_surface->private_data);
469 gen7_avc_surface = obj_surface->private_data;
471 OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
472 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
475 if (gen7_avc_surface->dmv_bottom_flag == 1)
476 OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_bottom,
477 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
480 OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
481 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
485 for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
486 obj_surface = gen7_mfd_context->reference_surface[i].obj_surface;
489 const VAPictureH264 * const va_pic = avc_find_picture(
490 obj_surface->base.id, pic_param->ReferenceFrames,
491 ARRAY_ELEMS(pic_param->ReferenceFrames));
493 assert(va_pic != NULL);
494 OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
495 OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
497 OUT_BCS_BATCH(batch, 0);
498 OUT_BCS_BATCH(batch, 0);
502 va_pic = &pic_param->CurrPic;
503 OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
504 OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
506 ADVANCE_BCS_BATCH(batch);
510 gen7_mfd_avc_phantom_slice_first(VADriverContextP ctx,
511 VAPictureParameterBufferH264 *pic_param,
512 VASliceParameterBufferH264 *next_slice_param,
513 struct gen7_mfd_context *gen7_mfd_context)
515 gen6_mfd_avc_phantom_slice(ctx, pic_param, next_slice_param, gen7_mfd_context->base.batch);
519 gen7_mfd_avc_slice_state(VADriverContextP ctx,
520 VAPictureParameterBufferH264 *pic_param,
521 VASliceParameterBufferH264 *slice_param,
522 VASliceParameterBufferH264 *next_slice_param,
523 struct gen7_mfd_context *gen7_mfd_context)
525 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
526 int width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
527 int height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1;
528 int slice_hor_pos, slice_ver_pos, next_slice_hor_pos, next_slice_ver_pos;
529 int num_ref_idx_l0, num_ref_idx_l1;
530 int mbaff_picture = (!pic_param->pic_fields.bits.field_pic_flag &&
531 pic_param->seq_fields.bits.mb_adaptive_frame_field_flag);
532 int first_mb_in_slice = 0, first_mb_in_next_slice = 0;
535 if (slice_param->slice_type == SLICE_TYPE_I ||
536 slice_param->slice_type == SLICE_TYPE_SI) {
537 slice_type = SLICE_TYPE_I;
538 } else if (slice_param->slice_type == SLICE_TYPE_P ||
539 slice_param->slice_type == SLICE_TYPE_SP) {
540 slice_type = SLICE_TYPE_P;
542 assert(slice_param->slice_type == SLICE_TYPE_B);
543 slice_type = SLICE_TYPE_B;
546 if (slice_type == SLICE_TYPE_I) {
547 assert(slice_param->num_ref_idx_l0_active_minus1 == 0);
548 assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
551 } else if (slice_type == SLICE_TYPE_P) {
552 assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
553 num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
556 num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
557 num_ref_idx_l1 = slice_param->num_ref_idx_l1_active_minus1 + 1;
560 first_mb_in_slice = slice_param->first_mb_in_slice;
561 slice_hor_pos = first_mb_in_slice % width_in_mbs;
562 slice_ver_pos = first_mb_in_slice / width_in_mbs;
565 slice_ver_pos = slice_ver_pos << 1;
567 if (next_slice_param) {
568 first_mb_in_next_slice = next_slice_param->first_mb_in_slice;
569 next_slice_hor_pos = first_mb_in_next_slice % width_in_mbs;
570 next_slice_ver_pos = first_mb_in_next_slice / width_in_mbs;
573 next_slice_ver_pos = next_slice_ver_pos << 1;
575 next_slice_hor_pos = 0;
576 next_slice_ver_pos = height_in_mbs / (1 + !!pic_param->pic_fields.bits.field_pic_flag);
579 BEGIN_BCS_BATCH(batch, 11); /* FIXME: is it 10??? */
580 OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2));
581 OUT_BCS_BATCH(batch, slice_type);
583 (num_ref_idx_l1 << 24) |
584 (num_ref_idx_l0 << 16) |
585 (slice_param->chroma_log2_weight_denom << 8) |
586 (slice_param->luma_log2_weight_denom << 0));
588 (slice_param->direct_spatial_mv_pred_flag << 29) |
589 (slice_param->disable_deblocking_filter_idc << 27) |
590 (slice_param->cabac_init_idc << 24) |
591 ((pic_param->pic_init_qp_minus26 + 26 + slice_param->slice_qp_delta) << 16) |
592 ((slice_param->slice_beta_offset_div2 & 0xf) << 8) |
593 ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0));
595 (slice_ver_pos << 24) |
596 (slice_hor_pos << 16) |
597 (first_mb_in_slice << 0));
599 (next_slice_ver_pos << 16) |
600 (next_slice_hor_pos << 0));
602 (next_slice_param == NULL) << 19); /* last slice flag */
603 OUT_BCS_BATCH(batch, 0);
604 OUT_BCS_BATCH(batch, 0);
605 OUT_BCS_BATCH(batch, 0);
606 OUT_BCS_BATCH(batch, 0);
607 ADVANCE_BCS_BATCH(batch);
611 gen7_mfd_avc_ref_idx_state(VADriverContextP ctx,
612 VAPictureParameterBufferH264 *pic_param,
613 VASliceParameterBufferH264 *slice_param,
614 struct gen7_mfd_context *gen7_mfd_context)
616 gen6_send_avc_ref_idx_state(
617 gen7_mfd_context->base.batch,
619 gen7_mfd_context->reference_surface
624 gen7_mfd_avc_weightoffset_state(VADriverContextP ctx,
625 VAPictureParameterBufferH264 *pic_param,
626 VASliceParameterBufferH264 *slice_param,
627 struct gen7_mfd_context *gen7_mfd_context)
629 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
630 int i, j, num_weight_offset_table = 0;
631 short weightoffsets[32 * 6];
633 if ((slice_param->slice_type == SLICE_TYPE_P ||
634 slice_param->slice_type == SLICE_TYPE_SP) &&
635 (pic_param->pic_fields.bits.weighted_pred_flag == 1)) {
636 num_weight_offset_table = 1;
639 if ((slice_param->slice_type == SLICE_TYPE_B) &&
640 (pic_param->pic_fields.bits.weighted_bipred_idc == 1)) {
641 num_weight_offset_table = 2;
644 for (i = 0; i < num_weight_offset_table; i++) {
645 BEGIN_BCS_BATCH(batch, 98);
646 OUT_BCS_BATCH(batch, MFX_AVC_WEIGHTOFFSET_STATE | (98 - 2));
647 OUT_BCS_BATCH(batch, i);
650 for (j = 0; j < 32; j++) {
651 weightoffsets[j * 6 + 0] = slice_param->luma_weight_l0[j];
652 weightoffsets[j * 6 + 1] = slice_param->luma_offset_l0[j];
653 weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l0[j][0];
654 weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l0[j][0];
655 weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l0[j][1];
656 weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l0[j][1];
659 for (j = 0; j < 32; j++) {
660 weightoffsets[j * 6 + 0] = slice_param->luma_weight_l1[j];
661 weightoffsets[j * 6 + 1] = slice_param->luma_offset_l1[j];
662 weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l1[j][0];
663 weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l1[j][0];
664 weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l1[j][1];
665 weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l1[j][1];
669 intel_batchbuffer_data(batch, weightoffsets, sizeof(weightoffsets));
670 ADVANCE_BCS_BATCH(batch);
675 gen7_mfd_avc_bsd_object(VADriverContextP ctx,
676 VAPictureParameterBufferH264 *pic_param,
677 VASliceParameterBufferH264 *slice_param,
678 dri_bo *slice_data_bo,
679 VASliceParameterBufferH264 *next_slice_param,
680 struct gen7_mfd_context *gen7_mfd_context)
682 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
683 unsigned int slice_data_bit_offset;
685 slice_data_bit_offset = avc_get_first_mb_bit_offset(
688 pic_param->pic_fields.bits.entropy_coding_mode_flag
691 /* the input bitsteam format on GEN7 differs from GEN6 */
692 BEGIN_BCS_BATCH(batch, 6);
693 OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2));
695 (slice_param->slice_data_size - slice_param->slice_data_offset));
696 OUT_BCS_BATCH(batch, slice_param->slice_data_offset);
704 ((slice_data_bit_offset >> 3) << 16) |
708 ((next_slice_param == NULL) << 3) | /* LastSlice Flag */
709 (slice_data_bit_offset & 0x7));
710 OUT_BCS_BATCH(batch, 0);
711 ADVANCE_BCS_BATCH(batch);
715 gen7_mfd_avc_context_init(
716 VADriverContextP ctx,
717 struct gen7_mfd_context *gen7_mfd_context
720 /* Initialize flat scaling lists */
721 avc_gen_default_iq_matrix(&gen7_mfd_context->iq_matrix.h264);
725 gen7_mfd_avc_decode_init(VADriverContextP ctx,
726 struct decode_state *decode_state,
727 struct gen7_mfd_context *gen7_mfd_context)
729 VAPictureParameterBufferH264 *pic_param;
730 VASliceParameterBufferH264 *slice_param;
731 struct i965_driver_data *i965 = i965_driver_data(ctx);
732 struct object_surface *obj_surface;
734 int i, j, enable_avc_ildb = 0;
735 unsigned int width_in_mbs, height_in_mbs;
737 for (j = 0; j < decode_state->num_slice_params && enable_avc_ildb == 0; j++) {
738 assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
739 slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
741 for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
742 assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
743 assert((slice_param->slice_type == SLICE_TYPE_I) ||
744 (slice_param->slice_type == SLICE_TYPE_SI) ||
745 (slice_param->slice_type == SLICE_TYPE_P) ||
746 (slice_param->slice_type == SLICE_TYPE_SP) ||
747 (slice_param->slice_type == SLICE_TYPE_B));
749 if (slice_param->disable_deblocking_filter_idc != 1) {
758 assert(decode_state->pic_param && decode_state->pic_param->buffer);
759 pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
760 intel_update_avc_frame_store_index(ctx, decode_state, pic_param,
761 gen7_mfd_context->reference_surface, &gen7_mfd_context->fs_ctx);
762 width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
763 height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1;
764 assert(width_in_mbs > 0 && width_in_mbs <= 256); /* 4K */
765 assert(height_in_mbs > 0 && height_in_mbs <= 256);
767 /* Current decoded picture */
768 obj_surface = decode_state->render_object;
769 if (pic_param->pic_fields.bits.reference_pic_flag)
770 obj_surface->flags |= SURFACE_REFERENCED;
772 obj_surface->flags &= ~SURFACE_REFERENCED;
774 avc_ensure_surface_bo(ctx, decode_state, obj_surface, pic_param);
775 gen7_mfd_init_avc_surface(ctx, pic_param, obj_surface);
777 dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo);
778 gen7_mfd_context->post_deblocking_output.bo = obj_surface->bo;
779 dri_bo_reference(gen7_mfd_context->post_deblocking_output.bo);
780 gen7_mfd_context->post_deblocking_output.valid = enable_avc_ildb;
782 dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
783 gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
784 dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
785 gen7_mfd_context->pre_deblocking_output.valid = !enable_avc_ildb;
787 dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo);
788 bo = dri_bo_alloc(i965->intel.bufmgr,
793 gen7_mfd_context->intra_row_store_scratch_buffer.bo = bo;
794 gen7_mfd_context->intra_row_store_scratch_buffer.valid = 1;
796 dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
797 bo = dri_bo_alloc(i965->intel.bufmgr,
798 "deblocking filter row store",
799 width_in_mbs * 64 * 4,
802 gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
803 gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1;
805 dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
806 bo = dri_bo_alloc(i965->intel.bufmgr,
808 width_in_mbs * 64 * 2,
811 gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
812 gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
814 dri_bo_unreference(gen7_mfd_context->mpr_row_store_scratch_buffer.bo);
815 bo = dri_bo_alloc(i965->intel.bufmgr,
817 width_in_mbs * 64 * 2,
820 gen7_mfd_context->mpr_row_store_scratch_buffer.bo = bo;
821 gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 1;
823 gen7_mfd_context->bitplane_read_buffer.valid = 0;
827 gen7_mfd_avc_decode_picture(VADriverContextP ctx,
828 struct decode_state *decode_state,
829 struct gen7_mfd_context *gen7_mfd_context)
831 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
832 VAPictureParameterBufferH264 *pic_param;
833 VASliceParameterBufferH264 *slice_param, *next_slice_param, *next_slice_group_param;
834 dri_bo *slice_data_bo;
837 assert(decode_state->pic_param && decode_state->pic_param->buffer);
838 pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
839 gen7_mfd_avc_decode_init(ctx, decode_state, gen7_mfd_context);
841 intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
842 intel_batchbuffer_emit_mi_flush(batch);
843 gen7_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
844 gen7_mfd_surface_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
845 gen7_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
846 gen7_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
847 gen7_mfd_avc_qm_state(ctx, decode_state, gen7_mfd_context);
848 gen7_mfd_avc_img_state(ctx, decode_state, gen7_mfd_context);
850 for (j = 0; j < decode_state->num_slice_params; j++) {
851 assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
852 slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
853 slice_data_bo = decode_state->slice_datas[j]->bo;
854 gen7_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_AVC, gen7_mfd_context);
856 if (j == decode_state->num_slice_params - 1)
857 next_slice_group_param = NULL;
859 next_slice_group_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j + 1]->buffer;
861 if (j == 0 && slice_param->first_mb_in_slice)
862 gen7_mfd_avc_phantom_slice_first(ctx, pic_param, slice_param, gen7_mfd_context);
864 for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
865 assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
866 assert((slice_param->slice_type == SLICE_TYPE_I) ||
867 (slice_param->slice_type == SLICE_TYPE_SI) ||
868 (slice_param->slice_type == SLICE_TYPE_P) ||
869 (slice_param->slice_type == SLICE_TYPE_SP) ||
870 (slice_param->slice_type == SLICE_TYPE_B));
872 if (i < decode_state->slice_params[j]->num_elements - 1)
873 next_slice_param = slice_param + 1;
875 next_slice_param = next_slice_group_param;
877 gen7_mfd_avc_directmode_state(ctx, decode_state, pic_param, slice_param, gen7_mfd_context);
878 gen7_mfd_avc_ref_idx_state(ctx, pic_param, slice_param, gen7_mfd_context);
879 gen7_mfd_avc_weightoffset_state(ctx, pic_param, slice_param, gen7_mfd_context);
880 gen7_mfd_avc_slice_state(ctx, pic_param, slice_param, next_slice_param, gen7_mfd_context);
881 gen7_mfd_avc_bsd_object(ctx, pic_param, slice_param, slice_data_bo, next_slice_param, gen7_mfd_context);
886 intel_batchbuffer_end_atomic(batch);
887 intel_batchbuffer_flush(batch);
891 gen7_mfd_mpeg2_decode_init(VADriverContextP ctx,
892 struct decode_state *decode_state,
893 struct gen7_mfd_context *gen7_mfd_context)
895 VAPictureParameterBufferMPEG2 *pic_param;
896 struct i965_driver_data *i965 = i965_driver_data(ctx);
897 struct object_surface *obj_surface;
899 unsigned int width_in_mbs;
901 assert(decode_state->pic_param && decode_state->pic_param->buffer);
902 pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
903 width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16;
905 mpeg2_set_reference_surfaces(
907 gen7_mfd_context->reference_surface,
912 /* Current decoded picture */
913 obj_surface = decode_state->render_object;
914 i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
916 dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
917 gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
918 dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
919 gen7_mfd_context->pre_deblocking_output.valid = 1;
921 dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
922 bo = dri_bo_alloc(i965->intel.bufmgr,
927 gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
928 gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
930 gen7_mfd_context->post_deblocking_output.valid = 0;
931 gen7_mfd_context->intra_row_store_scratch_buffer.valid = 0;
932 gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 0;
933 gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
934 gen7_mfd_context->bitplane_read_buffer.valid = 0;
938 gen7_mfd_mpeg2_pic_state(VADriverContextP ctx,
939 struct decode_state *decode_state,
940 struct gen7_mfd_context *gen7_mfd_context)
942 struct i965_driver_data * const i965 = i965_driver_data(ctx);
943 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
944 VAPictureParameterBufferMPEG2 *pic_param;
945 unsigned int slice_concealment_disable_bit = 0;
947 assert(decode_state->pic_param && decode_state->pic_param->buffer);
948 pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
950 if (IS_HASWELL(i965->intel.device_info)) {
951 /* XXX: disable concealment for now */
952 slice_concealment_disable_bit = 1;
955 BEGIN_BCS_BATCH(batch, 13);
956 OUT_BCS_BATCH(batch, MFX_MPEG2_PIC_STATE | (13 - 2));
958 (pic_param->f_code & 0xf) << 28 | /* f_code[1][1] */
959 ((pic_param->f_code >> 4) & 0xf) << 24 | /* f_code[1][0] */
960 ((pic_param->f_code >> 8) & 0xf) << 20 | /* f_code[0][1] */
961 ((pic_param->f_code >> 12) & 0xf) << 16 | /* f_code[0][0] */
962 pic_param->picture_coding_extension.bits.intra_dc_precision << 14 |
963 pic_param->picture_coding_extension.bits.picture_structure << 12 |
964 pic_param->picture_coding_extension.bits.top_field_first << 11 |
965 pic_param->picture_coding_extension.bits.frame_pred_frame_dct << 10 |
966 pic_param->picture_coding_extension.bits.concealment_motion_vectors << 9 |
967 pic_param->picture_coding_extension.bits.q_scale_type << 8 |
968 pic_param->picture_coding_extension.bits.intra_vlc_format << 7 |
969 pic_param->picture_coding_extension.bits.alternate_scan << 6);
971 pic_param->picture_coding_type << 9);
973 (slice_concealment_disable_bit << 31) |
974 ((ALIGN(pic_param->vertical_size, 16) / 16) - 1) << 16 |
975 ((ALIGN(pic_param->horizontal_size, 16) / 16) - 1));
976 OUT_BCS_BATCH(batch, 0);
977 OUT_BCS_BATCH(batch, 0);
978 OUT_BCS_BATCH(batch, 0);
979 OUT_BCS_BATCH(batch, 0);
980 OUT_BCS_BATCH(batch, 0);
981 OUT_BCS_BATCH(batch, 0);
982 OUT_BCS_BATCH(batch, 0);
983 OUT_BCS_BATCH(batch, 0);
984 OUT_BCS_BATCH(batch, 0);
985 ADVANCE_BCS_BATCH(batch);
989 gen7_mfd_mpeg2_qm_state(VADriverContextP ctx,
990 struct decode_state *decode_state,
991 struct gen7_mfd_context *gen7_mfd_context)
993 VAIQMatrixBufferMPEG2 * const gen_iq_matrix = &gen7_mfd_context->iq_matrix.mpeg2;
996 /* Update internal QM state */
997 if (decode_state->iq_matrix && decode_state->iq_matrix->buffer) {
998 VAIQMatrixBufferMPEG2 * const iq_matrix =
999 (VAIQMatrixBufferMPEG2 *)decode_state->iq_matrix->buffer;
1001 if (gen_iq_matrix->load_intra_quantiser_matrix == -1 ||
1002 iq_matrix->load_intra_quantiser_matrix) {
1003 gen_iq_matrix->load_intra_quantiser_matrix =
1004 iq_matrix->load_intra_quantiser_matrix;
1005 if (iq_matrix->load_intra_quantiser_matrix) {
1006 for (j = 0; j < 64; j++)
1007 gen_iq_matrix->intra_quantiser_matrix[zigzag_direct[j]] =
1008 iq_matrix->intra_quantiser_matrix[j];
1012 if (gen_iq_matrix->load_non_intra_quantiser_matrix == -1 ||
1013 iq_matrix->load_non_intra_quantiser_matrix) {
1014 gen_iq_matrix->load_non_intra_quantiser_matrix =
1015 iq_matrix->load_non_intra_quantiser_matrix;
1016 if (iq_matrix->load_non_intra_quantiser_matrix) {
1017 for (j = 0; j < 64; j++)
1018 gen_iq_matrix->non_intra_quantiser_matrix[zigzag_direct[j]] =
1019 iq_matrix->non_intra_quantiser_matrix[j];
1024 /* Commit QM state to HW */
1025 for (i = 0; i < 2; i++) {
1026 unsigned char *qm = NULL;
1030 if (gen_iq_matrix->load_intra_quantiser_matrix) {
1031 qm = gen_iq_matrix->intra_quantiser_matrix;
1032 qm_type = MFX_QM_MPEG_INTRA_QUANTIZER_MATRIX;
1035 if (gen_iq_matrix->load_non_intra_quantiser_matrix) {
1036 qm = gen_iq_matrix->non_intra_quantiser_matrix;
1037 qm_type = MFX_QM_MPEG_NON_INTRA_QUANTIZER_MATRIX;
1044 gen7_mfd_qm_state(ctx, qm_type, qm, 64, gen7_mfd_context);
1048 uint32_t mpeg2_get_slice_data_length(dri_bo *slice_data_bo, VASliceParameterBufferMPEG2 *slice_param)
1051 uint32_t buf_offset = slice_param->slice_data_offset + (slice_param->macroblock_offset >> 3);
1052 uint32_t buf_size = slice_param->slice_data_size - (slice_param->macroblock_offset >> 3);
1055 dri_bo_map(slice_data_bo, 0);
1056 buf = (uint8_t *)slice_data_bo->virtual + buf_offset;
1061 while (i <= (buf_size - 4)) {
1062 if (buf[i + 2] > 1) {
1064 } else if (buf[i + 1]) {
1066 } else if (buf[i] || buf[i + 2] != 1) {
1073 if (i <= (buf_size - 4))
1076 dri_bo_unmap(slice_data_bo);
1081 gen7_mfd_mpeg2_bsd_object(VADriverContextP ctx,
1082 VAPictureParameterBufferMPEG2 *pic_param,
1083 VASliceParameterBufferMPEG2 *slice_param,
1084 dri_bo *slice_data_bo,
1085 VASliceParameterBufferMPEG2 *next_slice_param,
1086 struct gen7_mfd_context *gen7_mfd_context)
1088 struct i965_driver_data * const i965 = i965_driver_data(ctx);
1089 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1090 unsigned int width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16;
1091 int mb_count, vpos0, hpos0, vpos1, hpos1, is_field_pic_wa, is_field_pic = 0;
1093 if (pic_param->picture_coding_extension.bits.picture_structure == MPEG_TOP_FIELD ||
1094 pic_param->picture_coding_extension.bits.picture_structure == MPEG_BOTTOM_FIELD)
1096 is_field_pic_wa = is_field_pic &&
1097 gen7_mfd_context->wa_mpeg2_slice_vertical_position > 0;
1099 vpos0 = slice_param->slice_vertical_position / (1 + is_field_pic_wa);
1100 hpos0 = slice_param->slice_horizontal_position;
1102 if (next_slice_param == NULL) {
1103 vpos1 = ALIGN(pic_param->vertical_size, 16) / 16 / (1 + is_field_pic);
1106 vpos1 = next_slice_param->slice_vertical_position / (1 + is_field_pic_wa);
1107 hpos1 = next_slice_param->slice_horizontal_position;
1110 mb_count = (vpos1 * width_in_mbs + hpos1) - (vpos0 * width_in_mbs + hpos0);
1112 BEGIN_BCS_BATCH(batch, 5);
1113 OUT_BCS_BATCH(batch, MFD_MPEG2_BSD_OBJECT | (5 - 2));
1114 OUT_BCS_BATCH(batch,
1115 mpeg2_get_slice_data_length(slice_data_bo, slice_param));
1116 OUT_BCS_BATCH(batch,
1117 slice_param->slice_data_offset + (slice_param->macroblock_offset >> 3));
1118 OUT_BCS_BATCH(batch,
1122 (next_slice_param == NULL) << 5 |
1123 (next_slice_param == NULL) << 3 |
1124 (slice_param->macroblock_offset & 0x7));
1125 OUT_BCS_BATCH(batch,
1126 (slice_param->quantiser_scale_code << 24) |
1127 (IS_HASWELL(i965->intel.device_info) ? (vpos1 << 8 | hpos1) : 0));
1128 ADVANCE_BCS_BATCH(batch);
1132 gen7_mfd_mpeg2_decode_picture(VADriverContextP ctx,
1133 struct decode_state *decode_state,
1134 struct gen7_mfd_context *gen7_mfd_context)
1136 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1137 VAPictureParameterBufferMPEG2 *pic_param;
1138 VASliceParameterBufferMPEG2 *slice_param, *next_slice_param, *next_slice_group_param;
1139 dri_bo *slice_data_bo;
1142 assert(decode_state->pic_param && decode_state->pic_param->buffer);
1143 pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
1145 gen7_mfd_mpeg2_decode_init(ctx, decode_state, gen7_mfd_context);
1146 intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
1147 intel_batchbuffer_emit_mi_flush(batch);
1148 gen7_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1149 gen7_mfd_surface_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1150 gen7_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1151 gen7_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1152 gen7_mfd_mpeg2_pic_state(ctx, decode_state, gen7_mfd_context);
1153 gen7_mfd_mpeg2_qm_state(ctx, decode_state, gen7_mfd_context);
1155 if (gen7_mfd_context->wa_mpeg2_slice_vertical_position < 0)
1156 gen7_mfd_context->wa_mpeg2_slice_vertical_position =
1157 mpeg2_wa_slice_vertical_position(decode_state, pic_param);
1159 for (j = 0; j < decode_state->num_slice_params; j++) {
1160 assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
1161 slice_param = (VASliceParameterBufferMPEG2 *)decode_state->slice_params[j]->buffer;
1162 slice_data_bo = decode_state->slice_datas[j]->bo;
1163 gen7_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_MPEG2, gen7_mfd_context);
1165 if (j == decode_state->num_slice_params - 1)
1166 next_slice_group_param = NULL;
1168 next_slice_group_param = (VASliceParameterBufferMPEG2 *)decode_state->slice_params[j + 1]->buffer;
1170 for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
1171 assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
1173 if (i < decode_state->slice_params[j]->num_elements - 1)
1174 next_slice_param = slice_param + 1;
1176 next_slice_param = next_slice_group_param;
1178 gen7_mfd_mpeg2_bsd_object(ctx, pic_param, slice_param, slice_data_bo, next_slice_param, gen7_mfd_context);
1183 intel_batchbuffer_end_atomic(batch);
1184 intel_batchbuffer_flush(batch);
1187 static const int va_to_gen7_vc1_pic_type[5] = {
1191 GEN7_VC1_BI_PICTURE,
1195 static const int va_to_gen7_vc1_mv[4] = {
1197 2, /* 1-MV half-pel */
1198 3, /* 1-MV half-pef bilinear */
1202 static const int b_picture_scale_factor[21] = {
1203 128, 85, 170, 64, 192,
1204 51, 102, 153, 204, 43,
1205 215, 37, 74, 111, 148,
1206 185, 222, 32, 96, 160,
1210 static const int va_to_gen7_vc1_condover[3] = {
1216 static const int va_to_gen7_vc1_profile[4] = {
1217 GEN7_VC1_SIMPLE_PROFILE,
1218 GEN7_VC1_MAIN_PROFILE,
1219 GEN7_VC1_RESERVED_PROFILE,
1220 GEN7_VC1_ADVANCED_PROFILE
1224 gen7_mfd_free_vc1_surface(void **data)
1226 struct gen7_vc1_surface *gen7_vc1_surface = *data;
1228 if (!gen7_vc1_surface)
1231 dri_bo_unreference(gen7_vc1_surface->dmv);
1232 free(gen7_vc1_surface);
1237 gen7_mfd_init_vc1_surface(VADriverContextP ctx,
1238 VAPictureParameterBufferVC1 *pic_param,
1239 struct object_surface *obj_surface)
1241 struct i965_driver_data *i965 = i965_driver_data(ctx);
1242 struct gen7_vc1_surface *gen7_vc1_surface = obj_surface->private_data;
1243 int width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1244 int height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16;
1246 obj_surface->free_private_data = gen7_mfd_free_vc1_surface;
1248 if (!gen7_vc1_surface) {
1249 gen7_vc1_surface = calloc(sizeof(struct gen7_vc1_surface), 1);
1250 assert(gen7_vc1_surface);
1251 assert((obj_surface->size & 0x3f) == 0);
1252 obj_surface->private_data = gen7_vc1_surface;
1255 gen7_vc1_surface->picture_type = pic_param->picture_fields.bits.picture_type;
1257 if (gen7_vc1_surface->dmv == NULL) {
1258 gen7_vc1_surface->dmv = dri_bo_alloc(i965->intel.bufmgr,
1259 "direct mv w/r buffer",
1260 width_in_mbs * height_in_mbs * 64,
1266 gen7_mfd_vc1_decode_init(VADriverContextP ctx,
1267 struct decode_state *decode_state,
1268 struct gen7_mfd_context *gen7_mfd_context)
1270 VAPictureParameterBufferVC1 *pic_param;
1271 struct i965_driver_data *i965 = i965_driver_data(ctx);
1272 struct object_surface *obj_surface;
1277 assert(decode_state->pic_param && decode_state->pic_param->buffer);
1278 pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1279 width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1280 picture_type = pic_param->picture_fields.bits.picture_type;
1282 intel_update_vc1_frame_store_index(ctx,
1285 gen7_mfd_context->reference_surface);
1287 /* Current decoded picture */
1288 obj_surface = decode_state->render_object;
1289 i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
1290 gen7_mfd_init_vc1_surface(ctx, pic_param, obj_surface);
1292 dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo);
1293 gen7_mfd_context->post_deblocking_output.bo = obj_surface->bo;
1294 dri_bo_reference(gen7_mfd_context->post_deblocking_output.bo);
1295 gen7_mfd_context->post_deblocking_output.valid = pic_param->entrypoint_fields.bits.loopfilter;
1297 dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
1298 gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
1299 dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
1300 gen7_mfd_context->pre_deblocking_output.valid = !pic_param->entrypoint_fields.bits.loopfilter;
1302 dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo);
1303 bo = dri_bo_alloc(i965->intel.bufmgr,
1308 gen7_mfd_context->intra_row_store_scratch_buffer.bo = bo;
1309 gen7_mfd_context->intra_row_store_scratch_buffer.valid = 1;
1311 dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
1312 bo = dri_bo_alloc(i965->intel.bufmgr,
1313 "deblocking filter row store",
1314 width_in_mbs * 7 * 64,
1317 gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
1318 gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1;
1320 dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
1321 bo = dri_bo_alloc(i965->intel.bufmgr,
1322 "bsd mpc row store",
1326 gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
1327 gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
1329 gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
1331 gen7_mfd_context->bitplane_read_buffer.valid = !!pic_param->bitplane_present.value;
1332 dri_bo_unreference(gen7_mfd_context->bitplane_read_buffer.bo);
1334 if (gen7_mfd_context->bitplane_read_buffer.valid) {
1335 int width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1336 int height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16;
1337 int bitplane_width = ALIGN(width_in_mbs, 2) / 2;
1339 uint8_t *src = NULL, *dst = NULL;
1341 assert(decode_state->bit_plane->buffer);
1342 src = decode_state->bit_plane->buffer;
1344 bo = dri_bo_alloc(i965->intel.bufmgr,
1346 bitplane_width * height_in_mbs,
1349 gen7_mfd_context->bitplane_read_buffer.bo = bo;
1351 dri_bo_map(bo, True);
1352 assert(bo->virtual);
1355 for (src_h = 0; src_h < height_in_mbs; src_h++) {
1356 for(src_w = 0; src_w < width_in_mbs; src_w++) {
1357 int src_index, dst_index;
1361 src_index = (src_h * width_in_mbs + src_w) / 2;
1362 src_shift = !((src_h * width_in_mbs + src_w) & 1) * 4;
1363 src_value = ((src[src_index] >> src_shift) & 0xf);
1365 if (picture_type == GEN7_VC1_SKIPPED_PICTURE){
1369 dst_index = src_w / 2;
1370 dst[dst_index] = ((dst[dst_index] >> 4) | (src_value << 4));
1374 dst[src_w / 2] >>= 4;
1376 dst += bitplane_width;
1381 gen7_mfd_context->bitplane_read_buffer.bo = NULL;
1385 gen7_mfd_vc1_pic_state(VADriverContextP ctx,
1386 struct decode_state *decode_state,
1387 struct gen7_mfd_context *gen7_mfd_context)
1389 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1390 VAPictureParameterBufferVC1 *pic_param;
1391 struct object_surface *obj_surface;
1392 int alt_pquant_config = 0, alt_pquant_edge_mask = 0, alt_pq;
1393 int dquant, dquantfrm, dqprofile, dqdbedge, dqsbedge, dqbilevel;
1394 int unified_mv_mode;
1395 int ref_field_pic_polarity = 0;
1396 int scale_factor = 0;
1398 int dmv_surface_valid = 0;
1404 int interpolation_mode = 0;
1406 assert(decode_state->pic_param && decode_state->pic_param->buffer);
1407 pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1409 profile = va_to_gen7_vc1_profile[pic_param->sequence_fields.bits.profile];
1410 dquant = pic_param->pic_quantizer_fields.bits.dquant;
1411 dquantfrm = pic_param->pic_quantizer_fields.bits.dq_frame;
1412 dqprofile = pic_param->pic_quantizer_fields.bits.dq_profile;
1413 dqdbedge = pic_param->pic_quantizer_fields.bits.dq_db_edge;
1414 dqsbedge = pic_param->pic_quantizer_fields.bits.dq_sb_edge;
1415 dqbilevel = pic_param->pic_quantizer_fields.bits.dq_binary_level;
1416 alt_pq = pic_param->pic_quantizer_fields.bits.alt_pic_quantizer;
1419 alt_pquant_config = 0;
1420 alt_pquant_edge_mask = 0;
1421 } else if (dquant == 2) {
1422 alt_pquant_config = 1;
1423 alt_pquant_edge_mask = 0xf;
1425 assert(dquant == 1);
1426 if (dquantfrm == 0) {
1427 alt_pquant_config = 0;
1428 alt_pquant_edge_mask = 0;
1431 assert(dquantfrm == 1);
1432 alt_pquant_config = 1;
1434 switch (dqprofile) {
1436 if (dqbilevel == 0) {
1437 alt_pquant_config = 2;
1438 alt_pquant_edge_mask = 0;
1440 assert(dqbilevel == 1);
1441 alt_pquant_config = 3;
1442 alt_pquant_edge_mask = 0;
1447 alt_pquant_edge_mask = 0xf;
1452 alt_pquant_edge_mask = 0x9;
1454 alt_pquant_edge_mask = (0x3 << dqdbedge);
1459 alt_pquant_edge_mask = (0x1 << dqsbedge);
1468 if (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation) {
1469 assert(pic_param->mv_fields.bits.mv_mode2 < 4);
1470 unified_mv_mode = va_to_gen7_vc1_mv[pic_param->mv_fields.bits.mv_mode2];
1472 assert(pic_param->mv_fields.bits.mv_mode < 4);
1473 unified_mv_mode = va_to_gen7_vc1_mv[pic_param->mv_fields.bits.mv_mode];
1476 if (pic_param->sequence_fields.bits.interlace == 1 &&
1477 pic_param->picture_fields.bits.frame_coding_mode != 0) { /* frame-interlace or field-interlace */
1478 /* FIXME: calculate reference field picture polarity */
1480 ref_field_pic_polarity = 0;
1483 if (pic_param->b_picture_fraction < 21)
1484 scale_factor = b_picture_scale_factor[pic_param->b_picture_fraction];
1486 picture_type = va_to_gen7_vc1_pic_type[pic_param->picture_fields.bits.picture_type];
1488 if (profile == GEN7_VC1_ADVANCED_PROFILE &&
1489 picture_type == GEN7_VC1_I_PICTURE)
1490 picture_type = GEN7_VC1_BI_PICTURE;
1492 if (picture_type == GEN7_VC1_I_PICTURE || picture_type == GEN7_VC1_BI_PICTURE) /* I picture */
1493 trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx2;
1495 trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx1;
1497 * 8.3.6.2.1 Transform Type Selection
1498 * If variable-sized transform coding is not enabled,
1499 * then the 8x8 transform shall be used for all blocks.
1500 * it is also MFX_VC1_PIC_STATE requirement.
1502 if (pic_param->transform_fields.bits.variable_sized_transform_flag == 0) {
1503 pic_param->transform_fields.bits.mb_level_transform_type_flag = 1;
1504 pic_param->transform_fields.bits.frame_level_transform_type = 0;
1509 if (picture_type == GEN7_VC1_B_PICTURE) {
1510 struct gen7_vc1_surface *gen7_vc1_surface = NULL;
1512 obj_surface = decode_state->reference_objects[1];
1515 gen7_vc1_surface = obj_surface->private_data;
1517 if (!gen7_vc1_surface ||
1518 (va_to_gen7_vc1_pic_type[gen7_vc1_surface->picture_type] == GEN7_VC1_I_PICTURE ||
1519 va_to_gen7_vc1_pic_type[gen7_vc1_surface->picture_type] == GEN7_VC1_BI_PICTURE))
1520 dmv_surface_valid = 0;
1522 dmv_surface_valid = 1;
1525 assert(pic_param->picture_fields.bits.frame_coding_mode < 3);
1527 if (pic_param->picture_fields.bits.frame_coding_mode < 2)
1528 fcm = pic_param->picture_fields.bits.frame_coding_mode;
1530 if (pic_param->picture_fields.bits.top_field_first)
1536 if (pic_param->picture_fields.bits.picture_type == GEN7_VC1_B_PICTURE) { /* B picture */
1537 brfd = pic_param->reference_fields.bits.reference_distance;
1538 brfd = (scale_factor * brfd) >> 8;
1539 brfd = pic_param->reference_fields.bits.reference_distance - brfd - 1;
1545 overlap = pic_param->sequence_fields.bits.overlap;
1549 if (profile != GEN7_VC1_ADVANCED_PROFILE) {
1550 if (pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9 &&
1551 pic_param->picture_fields.bits.picture_type != GEN7_VC1_B_PICTURE) {
1555 if (pic_param->picture_fields.bits.picture_type == GEN7_VC1_P_PICTURE &&
1556 pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9){
1559 if (pic_param->picture_fields.bits.picture_type == GEN7_VC1_I_PICTURE ||
1560 pic_param->picture_fields.bits.picture_type == GEN7_VC1_BI_PICTURE){
1561 if (pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9){
1563 } else if (va_to_gen7_vc1_condover[pic_param->conditional_overlap_flag] == 2 ||
1564 va_to_gen7_vc1_condover[pic_param->conditional_overlap_flag] == 3) {
1571 assert(pic_param->conditional_overlap_flag < 3);
1572 assert(pic_param->mv_fields.bits.mv_table < 4); /* FIXME: interlace mode */
1574 if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPelBilinear ||
1575 (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation &&
1576 pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPelBilinear))
1577 interpolation_mode = 9; /* Half-pel bilinear */
1578 else if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPel ||
1579 (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation &&
1580 pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPel))
1581 interpolation_mode = 1; /* Half-pel bicubic */
1583 interpolation_mode = 0; /* Quarter-pel bicubic */
1585 BEGIN_BCS_BATCH(batch, 6);
1586 OUT_BCS_BATCH(batch, MFD_VC1_LONG_PIC_STATE | (6 - 2));
1587 OUT_BCS_BATCH(batch,
1588 (((ALIGN(pic_param->coded_height, 16) / 16) - 1) << 16) |
1589 ((ALIGN(pic_param->coded_width, 16) / 16) - 1));
1590 OUT_BCS_BATCH(batch,
1591 ((ALIGN(pic_param->coded_width, 16) / 16 + 1) / 2 - 1) << 24 |
1592 dmv_surface_valid << 15 |
1593 (pic_param->pic_quantizer_fields.bits.quantizer == 0) << 14 | /* implicit quantizer */
1594 pic_param->rounding_control << 13 |
1595 pic_param->sequence_fields.bits.syncmarker << 12 |
1596 interpolation_mode << 8 |
1597 0 << 7 | /* FIXME: scale up or down ??? */
1598 pic_param->range_reduction_frame << 6 |
1599 pic_param->entrypoint_fields.bits.loopfilter << 5 |
1601 !pic_param->picture_fields.bits.is_first_field << 3 |
1602 (pic_param->sequence_fields.bits.profile == 3) << 0);
1603 OUT_BCS_BATCH(batch,
1604 va_to_gen7_vc1_condover[pic_param->conditional_overlap_flag] << 29 |
1605 picture_type << 26 |
1608 pic_param->pic_quantizer_fields.bits.pic_quantizer_scale << 8 |
1610 OUT_BCS_BATCH(batch,
1611 unified_mv_mode << 28 |
1612 pic_param->mv_fields.bits.four_mv_switch << 27 |
1613 pic_param->fast_uvmc_flag << 26 |
1614 ref_field_pic_polarity << 25 |
1615 pic_param->reference_fields.bits.num_reference_pictures << 24 |
1616 pic_param->reference_fields.bits.reference_distance << 20 |
1617 pic_param->reference_fields.bits.reference_distance << 16 | /* FIXME: ??? */
1618 pic_param->mv_fields.bits.extended_dmv_range << 10 |
1619 pic_param->mv_fields.bits.extended_mv_range << 8 |
1620 alt_pquant_edge_mask << 4 |
1621 alt_pquant_config << 2 |
1622 pic_param->pic_quantizer_fields.bits.half_qp << 1 |
1623 pic_param->pic_quantizer_fields.bits.pic_quantizer_type << 0);
1624 OUT_BCS_BATCH(batch,
1625 !!pic_param->bitplane_present.value << 31 |
1626 !pic_param->bitplane_present.flags.bp_forward_mb << 30 |
1627 !pic_param->bitplane_present.flags.bp_mv_type_mb << 29 |
1628 !pic_param->bitplane_present.flags.bp_skip_mb << 28 |
1629 !pic_param->bitplane_present.flags.bp_direct_mb << 27 |
1630 !pic_param->bitplane_present.flags.bp_overflags << 26 |
1631 !pic_param->bitplane_present.flags.bp_ac_pred << 25 |
1632 !pic_param->bitplane_present.flags.bp_field_tx << 24 |
1633 pic_param->mv_fields.bits.mv_table << 20 |
1634 pic_param->mv_fields.bits.four_mv_block_pattern_table << 18 |
1635 pic_param->mv_fields.bits.two_mv_block_pattern_table << 16 |
1636 pic_param->transform_fields.bits.frame_level_transform_type << 12 |
1637 pic_param->transform_fields.bits.mb_level_transform_type_flag << 11 |
1638 pic_param->mb_mode_table << 8 |
1640 pic_param->transform_fields.bits.transform_ac_codingset_idx1 << 4 |
1641 pic_param->transform_fields.bits.intra_transform_dc_table << 3 |
1642 pic_param->cbp_table << 0);
1643 ADVANCE_BCS_BATCH(batch);
1647 gen7_mfd_vc1_pred_pipe_state(VADriverContextP ctx,
1648 struct decode_state *decode_state,
1649 struct gen7_mfd_context *gen7_mfd_context)
1651 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1652 VAPictureParameterBufferVC1 *pic_param;
1653 int intensitycomp_single;
1655 assert(decode_state->pic_param && decode_state->pic_param->buffer);
1656 pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1657 intensitycomp_single = (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation);
1659 BEGIN_BCS_BATCH(batch, 6);
1660 OUT_BCS_BATCH(batch, MFX_VC1_PRED_PIPE_STATE | (6 - 2));
1661 OUT_BCS_BATCH(batch,
1662 0 << 14 | /* FIXME: double ??? */
1664 intensitycomp_single << 10 |
1665 intensitycomp_single << 8 |
1666 0 << 4 | /* FIXME: interlace mode */
1668 OUT_BCS_BATCH(batch,
1669 pic_param->luma_shift << 16 |
1670 pic_param->luma_scale << 0); /* FIXME: Luma Scaling */
1671 OUT_BCS_BATCH(batch, 0);
1672 OUT_BCS_BATCH(batch, 0);
1673 OUT_BCS_BATCH(batch, 0);
1674 ADVANCE_BCS_BATCH(batch);
1679 gen7_mfd_vc1_directmode_state(VADriverContextP ctx,
1680 struct decode_state *decode_state,
1681 struct gen7_mfd_context *gen7_mfd_context)
1683 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1684 struct object_surface *obj_surface;
1685 dri_bo *dmv_read_buffer = NULL, *dmv_write_buffer = NULL;
1687 obj_surface = decode_state->render_object;
1689 if (obj_surface && obj_surface->private_data) {
1690 dmv_write_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv;
1693 obj_surface = decode_state->reference_objects[1];
1695 if (obj_surface && obj_surface->private_data) {
1696 dmv_read_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv;
1699 BEGIN_BCS_BATCH(batch, 3);
1700 OUT_BCS_BATCH(batch, MFX_VC1_DIRECTMODE_STATE | (3 - 2));
1702 if (dmv_write_buffer)
1703 OUT_BCS_RELOC(batch, dmv_write_buffer,
1704 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
1707 OUT_BCS_BATCH(batch, 0);
1709 if (dmv_read_buffer)
1710 OUT_BCS_RELOC(batch, dmv_read_buffer,
1711 I915_GEM_DOMAIN_INSTRUCTION, 0,
1714 OUT_BCS_BATCH(batch, 0);
1716 ADVANCE_BCS_BATCH(batch);
1720 gen7_mfd_vc1_get_macroblock_bit_offset(uint8_t *buf, int in_slice_data_bit_offset, int profile)
1722 int out_slice_data_bit_offset;
1723 int slice_header_size = in_slice_data_bit_offset / 8;
1727 out_slice_data_bit_offset = in_slice_data_bit_offset;
1729 for (i = 0, j = 0; i < slice_header_size; i++, j++) {
1730 if (!buf[j] && !buf[j + 1] && buf[j + 2] == 3 && buf[j + 3] < 4) {
1735 out_slice_data_bit_offset = 8 * j + in_slice_data_bit_offset % 8;
1738 return out_slice_data_bit_offset;
1742 gen7_mfd_vc1_bsd_object(VADriverContextP ctx,
1743 VAPictureParameterBufferVC1 *pic_param,
1744 VASliceParameterBufferVC1 *slice_param,
1745 VASliceParameterBufferVC1 *next_slice_param,
1746 dri_bo *slice_data_bo,
1747 struct gen7_mfd_context *gen7_mfd_context)
1749 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1750 int next_slice_start_vert_pos;
1751 int macroblock_offset;
1752 uint8_t *slice_data = NULL;
1754 dri_bo_map(slice_data_bo, 0);
1755 slice_data = (uint8_t *)(slice_data_bo->virtual + slice_param->slice_data_offset);
1756 macroblock_offset = gen7_mfd_vc1_get_macroblock_bit_offset(slice_data,
1757 slice_param->macroblock_offset,
1758 pic_param->sequence_fields.bits.profile);
1759 dri_bo_unmap(slice_data_bo);
1761 if (next_slice_param)
1762 next_slice_start_vert_pos = next_slice_param->slice_vertical_position;
1764 next_slice_start_vert_pos = ALIGN(pic_param->coded_height, 16) / 16;
1766 BEGIN_BCS_BATCH(batch, 5);
1767 OUT_BCS_BATCH(batch, MFD_VC1_BSD_OBJECT | (5 - 2));
1768 OUT_BCS_BATCH(batch,
1769 slice_param->slice_data_size - (macroblock_offset >> 3));
1770 OUT_BCS_BATCH(batch,
1771 slice_param->slice_data_offset + (macroblock_offset >> 3));
1772 OUT_BCS_BATCH(batch,
1773 slice_param->slice_vertical_position << 16 |
1774 next_slice_start_vert_pos << 0);
1775 OUT_BCS_BATCH(batch,
1776 (macroblock_offset & 0x7));
1777 ADVANCE_BCS_BATCH(batch);
1781 gen7_mfd_vc1_decode_picture(VADriverContextP ctx,
1782 struct decode_state *decode_state,
1783 struct gen7_mfd_context *gen7_mfd_context)
1785 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1786 VAPictureParameterBufferVC1 *pic_param;
1787 VASliceParameterBufferVC1 *slice_param, *next_slice_param, *next_slice_group_param;
1788 dri_bo *slice_data_bo;
1791 assert(decode_state->pic_param && decode_state->pic_param->buffer);
1792 pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1794 gen7_mfd_vc1_decode_init(ctx, decode_state, gen7_mfd_context);
1795 intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
1796 intel_batchbuffer_emit_mi_flush(batch);
1797 gen7_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
1798 gen7_mfd_surface_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
1799 gen7_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
1800 gen7_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
1801 gen7_mfd_vc1_pic_state(ctx, decode_state, gen7_mfd_context);
1802 gen7_mfd_vc1_pred_pipe_state(ctx, decode_state, gen7_mfd_context);
1803 gen7_mfd_vc1_directmode_state(ctx, decode_state, gen7_mfd_context);
1805 for (j = 0; j < decode_state->num_slice_params; j++) {
1806 assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
1807 slice_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j]->buffer;
1808 slice_data_bo = decode_state->slice_datas[j]->bo;
1809 gen7_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_VC1, gen7_mfd_context);
1811 if (j == decode_state->num_slice_params - 1)
1812 next_slice_group_param = NULL;
1814 next_slice_group_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j + 1]->buffer;
1816 for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
1817 assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
1819 if (i < decode_state->slice_params[j]->num_elements - 1)
1820 next_slice_param = slice_param + 1;
1822 next_slice_param = next_slice_group_param;
1824 gen7_mfd_vc1_bsd_object(ctx, pic_param, slice_param, next_slice_param, slice_data_bo, gen7_mfd_context);
1829 intel_batchbuffer_end_atomic(batch);
1830 intel_batchbuffer_flush(batch);
1834 gen7_mfd_jpeg_decode_init(VADriverContextP ctx,
1835 struct decode_state *decode_state,
1836 struct gen7_mfd_context *gen7_mfd_context)
1838 struct object_surface *obj_surface;
1839 VAPictureParameterBufferJPEGBaseline *pic_param;
1840 int subsampling = SUBSAMPLE_YUV420;
1841 int fourcc = VA_FOURCC_IMC3;
1843 pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
1845 if (pic_param->num_components == 1) {
1846 subsampling = SUBSAMPLE_YUV400;
1847 fourcc = VA_FOURCC_Y800;
1848 } else if (pic_param->num_components == 3) {
1849 int h1 = pic_param->components[0].h_sampling_factor;
1850 int h2 = pic_param->components[1].h_sampling_factor;
1851 int h3 = pic_param->components[2].h_sampling_factor;
1852 int v1 = pic_param->components[0].v_sampling_factor;
1853 int v2 = pic_param->components[1].v_sampling_factor;
1854 int v3 = pic_param->components[2].v_sampling_factor;
1856 if (h1 == 2 && h2 == 1 && h3 == 1 &&
1857 v1 == 2 && v2 == 1 && v3 == 1) {
1858 subsampling = SUBSAMPLE_YUV420;
1859 fourcc = VA_FOURCC_IMC3;
1860 } else if (h1 == 2 && h2 == 1 && h3 == 1 &&
1861 v1 == 1 && v2 == 1 && v3 == 1) {
1862 subsampling = SUBSAMPLE_YUV422H;
1863 fourcc = VA_FOURCC_422H;
1864 } else if (h1 == 1 && h2 == 1 && h3 == 1 &&
1865 v1 == 1 && v2 == 1 && v3 == 1) {
1866 subsampling = SUBSAMPLE_YUV444;
1867 fourcc = VA_FOURCC_444P;
1868 } else if (h1 == 4 && h2 == 1 && h3 == 1 &&
1869 v1 == 1 && v2 == 1 && v3 == 1) {
1870 subsampling = SUBSAMPLE_YUV411;
1871 fourcc = VA_FOURCC_411P;
1872 } else if (h1 == 1 && h2 == 1 && h3 == 1 &&
1873 v1 == 2 && v2 == 1 && v3 == 1) {
1874 subsampling = SUBSAMPLE_YUV422V;
1875 fourcc = VA_FOURCC_422V;
1876 } else if (h1 == 2 && h2 == 1 && h3 == 1 &&
1877 v1 == 2 && v2 == 2 && v3 == 2) {
1878 subsampling = SUBSAMPLE_YUV422H;
1879 fourcc = VA_FOURCC_422H;
1880 } else if (h1 == 2 && h2 == 2 && h3 == 2 &&
1881 v1 == 2 && v2 == 1 && v3 == 1) {
1882 subsampling = SUBSAMPLE_YUV422V;
1883 fourcc = VA_FOURCC_422V;
1890 /* Current decoded picture */
1891 obj_surface = decode_state->render_object;
1892 i965_check_alloc_surface_bo(ctx, obj_surface, 1, fourcc, subsampling);
1894 dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
1895 gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
1896 dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
1897 gen7_mfd_context->pre_deblocking_output.valid = 1;
1899 gen7_mfd_context->post_deblocking_output.bo = NULL;
1900 gen7_mfd_context->post_deblocking_output.valid = 0;
1902 gen7_mfd_context->intra_row_store_scratch_buffer.bo = NULL;
1903 gen7_mfd_context->intra_row_store_scratch_buffer.valid = 0;
1905 gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
1906 gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 0;
1908 gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
1909 gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 0;
1911 gen7_mfd_context->mpr_row_store_scratch_buffer.bo = NULL;
1912 gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
1914 gen7_mfd_context->bitplane_read_buffer.bo = NULL;
1915 gen7_mfd_context->bitplane_read_buffer.valid = 0;
1918 static const int va_to_gen7_jpeg_rotation[4] = {
1919 GEN7_JPEG_ROTATION_0,
1920 GEN7_JPEG_ROTATION_90,
1921 GEN7_JPEG_ROTATION_180,
1922 GEN7_JPEG_ROTATION_270
1926 gen7_mfd_jpeg_pic_state(VADriverContextP ctx,
1927 struct decode_state *decode_state,
1928 struct gen7_mfd_context *gen7_mfd_context)
1930 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1931 VAPictureParameterBufferJPEGBaseline *pic_param;
1932 int chroma_type = GEN7_YUV420;
1933 int frame_width_in_blks;
1934 int frame_height_in_blks;
1936 assert(decode_state->pic_param && decode_state->pic_param->buffer);
1937 pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
1939 if (pic_param->num_components == 1)
1940 chroma_type = GEN7_YUV400;
1941 else if (pic_param->num_components == 3) {
1942 int h1 = pic_param->components[0].h_sampling_factor;
1943 int h2 = pic_param->components[1].h_sampling_factor;
1944 int h3 = pic_param->components[2].h_sampling_factor;
1945 int v1 = pic_param->components[0].v_sampling_factor;
1946 int v2 = pic_param->components[1].v_sampling_factor;
1947 int v3 = pic_param->components[2].v_sampling_factor;
1949 if (h1 == 2 && h2 == 1 && h3 == 1 &&
1950 v1 == 2 && v2 == 1 && v3 == 1)
1951 chroma_type = GEN7_YUV420;
1952 else if (h1 == 2 && h2 == 1 && h3 == 1 &&
1953 v1 == 1 && v2 == 1 && v3 == 1)
1954 chroma_type = GEN7_YUV422H_2Y;
1955 else if (h1 == 1 && h2 == 1 && h3 == 1 &&
1956 v1 == 1 && v2 == 1 && v3 == 1)
1957 chroma_type = GEN7_YUV444;
1958 else if (h1 == 4 && h2 == 1 && h3 == 1 &&
1959 v1 == 1 && v2 == 1 && v3 == 1)
1960 chroma_type = GEN7_YUV411;
1961 else if (h1 == 1 && h2 == 1 && h3 == 1 &&
1962 v1 == 2 && v2 == 1 && v3 == 1)
1963 chroma_type = GEN7_YUV422V_2Y;
1964 else if (h1 == 2 && h2 == 1 && h3 == 1 &&
1965 v1 == 2 && v2 == 2 && v3 == 2)
1966 chroma_type = GEN7_YUV422H_4Y;
1967 else if (h2 == 2 && h2 == 2 && h3 == 2 &&
1968 v1 == 2 && v2 == 1 && v3 == 1)
1969 chroma_type = GEN7_YUV422V_4Y;
1974 if (chroma_type == GEN7_YUV400 ||
1975 chroma_type == GEN7_YUV444 ||
1976 chroma_type == GEN7_YUV422V_2Y) {
1977 frame_width_in_blks = ((pic_param->picture_width + 7) / 8);
1978 frame_height_in_blks = ((pic_param->picture_height + 7) / 8);
1979 } else if (chroma_type == GEN7_YUV411) {
1980 frame_width_in_blks = ((pic_param->picture_width + 31) / 32) * 4;
1981 frame_height_in_blks = ((pic_param->picture_height + 31) / 32) * 4;
1983 frame_width_in_blks = ((pic_param->picture_width + 15) / 16) * 2;
1984 frame_height_in_blks = ((pic_param->picture_height + 15) / 16) * 2;
1987 BEGIN_BCS_BATCH(batch, 3);
1988 OUT_BCS_BATCH(batch, MFX_JPEG_PIC_STATE | (3 - 2));
1989 OUT_BCS_BATCH(batch,
1990 (va_to_gen7_jpeg_rotation[0] << 4) | /* without rotation */
1991 (chroma_type << 0));
1992 OUT_BCS_BATCH(batch,
1993 ((frame_height_in_blks - 1) << 16) | /* FrameHeightInBlks */
1994 ((frame_width_in_blks - 1) << 0)); /* FrameWidthInBlks */
1995 ADVANCE_BCS_BATCH(batch);
1998 static const int va_to_gen7_jpeg_hufftable[2] = {
2004 gen7_mfd_jpeg_huff_table_state(VADriverContextP ctx,
2005 struct decode_state *decode_state,
2006 struct gen7_mfd_context *gen7_mfd_context,
2009 VAHuffmanTableBufferJPEGBaseline *huffman_table;
2010 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2013 if (!decode_state->huffman_table || !decode_state->huffman_table->buffer)
2016 huffman_table = (VAHuffmanTableBufferJPEGBaseline *)decode_state->huffman_table->buffer;
2018 for (index = 0; index < num_tables; index++) {
2019 int id = va_to_gen7_jpeg_hufftable[index];
2020 if (!huffman_table->load_huffman_table[index])
2022 BEGIN_BCS_BATCH(batch, 53);
2023 OUT_BCS_BATCH(batch, MFX_JPEG_HUFF_TABLE_STATE | (53 - 2));
2024 OUT_BCS_BATCH(batch, id);
2025 intel_batchbuffer_data(batch, huffman_table->huffman_table[index].num_dc_codes, 12);
2026 intel_batchbuffer_data(batch, huffman_table->huffman_table[index].dc_values, 12);
2027 intel_batchbuffer_data(batch, huffman_table->huffman_table[index].num_ac_codes, 16);
2028 intel_batchbuffer_data(batch, huffman_table->huffman_table[index].ac_values, 164);
2029 ADVANCE_BCS_BATCH(batch);
2033 static const int va_to_gen7_jpeg_qm[5] = {
2035 MFX_QM_JPEG_LUMA_Y_QUANTIZER_MATRIX,
2036 MFX_QM_JPEG_CHROMA_CB_QUANTIZER_MATRIX,
2037 MFX_QM_JPEG_CHROMA_CR_QUANTIZER_MATRIX,
2038 MFX_QM_JPEG_ALPHA_QUANTIZER_MATRIX
2042 gen7_mfd_jpeg_qm_state(VADriverContextP ctx,
2043 struct decode_state *decode_state,
2044 struct gen7_mfd_context *gen7_mfd_context)
2046 VAPictureParameterBufferJPEGBaseline *pic_param;
2047 VAIQMatrixBufferJPEGBaseline *iq_matrix;
2050 if (!decode_state->iq_matrix || !decode_state->iq_matrix->buffer)
2053 iq_matrix = (VAIQMatrixBufferJPEGBaseline *)decode_state->iq_matrix->buffer;
2054 pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
2056 assert(pic_param->num_components <= 3);
2058 for (index = 0; index < pic_param->num_components; index++) {
2059 int id = pic_param->components[index].component_id - pic_param->components[0].component_id + 1;
2061 unsigned char *qm = iq_matrix->quantiser_table[pic_param->components[index].quantiser_table_selector];
2062 unsigned char raster_qm[64];
2065 if (id > 4 || id < 1)
2068 if (!iq_matrix->load_quantiser_table[pic_param->components[index].quantiser_table_selector])
2071 qm_type = va_to_gen7_jpeg_qm[id];
2073 for (j = 0; j < 64; j++)
2074 raster_qm[zigzag_direct[j]] = qm[j];
2076 gen7_mfd_qm_state(ctx, qm_type, raster_qm, 64, gen7_mfd_context);
2081 gen7_mfd_jpeg_bsd_object(VADriverContextP ctx,
2082 VAPictureParameterBufferJPEGBaseline *pic_param,
2083 VASliceParameterBufferJPEGBaseline *slice_param,
2084 VASliceParameterBufferJPEGBaseline *next_slice_param,
2085 dri_bo *slice_data_bo,
2086 struct gen7_mfd_context *gen7_mfd_context)
2088 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2089 int scan_component_mask = 0;
2092 assert(slice_param->num_components > 0);
2093 assert(slice_param->num_components < 4);
2094 assert(slice_param->num_components <= pic_param->num_components);
2096 for (i = 0; i < slice_param->num_components; i++) {
2097 switch (slice_param->components[i].component_selector - pic_param->components[0].component_id + 1) {
2099 scan_component_mask |= (1 << 0);
2102 scan_component_mask |= (1 << 1);
2105 scan_component_mask |= (1 << 2);
2113 BEGIN_BCS_BATCH(batch, 6);
2114 OUT_BCS_BATCH(batch, MFD_JPEG_BSD_OBJECT | (6 - 2));
2115 OUT_BCS_BATCH(batch,
2116 slice_param->slice_data_size);
2117 OUT_BCS_BATCH(batch,
2118 slice_param->slice_data_offset);
2119 OUT_BCS_BATCH(batch,
2120 slice_param->slice_horizontal_position << 16 |
2121 slice_param->slice_vertical_position << 0);
2122 OUT_BCS_BATCH(batch,
2123 ((slice_param->num_components != 1) << 30) | /* interleaved */
2124 (scan_component_mask << 27) | /* scan components */
2125 (0 << 26) | /* disable interrupt allowed */
2126 (slice_param->num_mcus << 0)); /* MCU count */
2127 OUT_BCS_BATCH(batch,
2128 (slice_param->restart_interval << 0)); /* RestartInterval */
2129 ADVANCE_BCS_BATCH(batch);
2132 /* Workaround for JPEG decoding on Ivybridge */
2137 unsigned char data[32];
2139 int data_bit_offset;
2141 } gen7_jpeg_wa_clip = {
2145 0x65, 0xb8, 0x40, 0x32, 0x13, 0xfd, 0x06, 0x6c,
2146 0xfc, 0x0a, 0x50, 0x71, 0x5c, 0x00
2154 gen7_jpeg_wa_init(VADriverContextP ctx,
2155 struct gen7_mfd_context *gen7_mfd_context)
2157 struct i965_driver_data *i965 = i965_driver_data(ctx);
2159 struct object_surface *obj_surface;
2161 if (gen7_mfd_context->jpeg_wa_surface_id != VA_INVALID_SURFACE)
2162 i965_DestroySurfaces(ctx,
2163 &gen7_mfd_context->jpeg_wa_surface_id,
2166 status = i965_CreateSurfaces(ctx,
2167 gen7_jpeg_wa_clip.width,
2168 gen7_jpeg_wa_clip.height,
2169 VA_RT_FORMAT_YUV420,
2171 &gen7_mfd_context->jpeg_wa_surface_id);
2172 assert(status == VA_STATUS_SUCCESS);
2174 obj_surface = SURFACE(gen7_mfd_context->jpeg_wa_surface_id);
2175 assert(obj_surface);
2176 i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
2177 gen7_mfd_context->jpeg_wa_surface_object = obj_surface;
2179 if (!gen7_mfd_context->jpeg_wa_slice_data_bo) {
2180 gen7_mfd_context->jpeg_wa_slice_data_bo = dri_bo_alloc(i965->intel.bufmgr,
2184 dri_bo_subdata(gen7_mfd_context->jpeg_wa_slice_data_bo,
2186 gen7_jpeg_wa_clip.data_size,
2187 gen7_jpeg_wa_clip.data);
2192 gen7_jpeg_wa_pipe_mode_select(VADriverContextP ctx,
2193 struct gen7_mfd_context *gen7_mfd_context)
2195 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2197 BEGIN_BCS_BATCH(batch, 5);
2198 OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2));
2199 OUT_BCS_BATCH(batch,
2200 (MFX_LONG_MODE << 17) | /* Currently only support long format */
2201 (MFD_MODE_VLD << 15) | /* VLD mode */
2202 (0 << 10) | /* disable Stream-Out */
2203 (0 << 9) | /* Post Deblocking Output */
2204 (1 << 8) | /* Pre Deblocking Output */
2205 (0 << 5) | /* not in stitch mode */
2206 (MFX_CODEC_DECODE << 4) | /* decoding mode */
2207 (MFX_FORMAT_AVC << 0));
2208 OUT_BCS_BATCH(batch,
2209 (0 << 4) | /* terminate if AVC motion and POC table error occurs */
2210 (0 << 3) | /* terminate if AVC mbdata error occurs */
2211 (0 << 2) | /* terminate if AVC CABAC/CAVLC decode error occurs */
2214 OUT_BCS_BATCH(batch, 0); /* pic status/error report id */
2215 OUT_BCS_BATCH(batch, 0); /* reserved */
2216 ADVANCE_BCS_BATCH(batch);
2220 gen7_jpeg_wa_surface_state(VADriverContextP ctx,
2221 struct gen7_mfd_context *gen7_mfd_context)
2223 struct object_surface *obj_surface = gen7_mfd_context->jpeg_wa_surface_object;
2224 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2226 BEGIN_BCS_BATCH(batch, 6);
2227 OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
2228 OUT_BCS_BATCH(batch, 0);
2229 OUT_BCS_BATCH(batch,
2230 ((obj_surface->orig_width - 1) << 18) |
2231 ((obj_surface->orig_height - 1) << 4));
2232 OUT_BCS_BATCH(batch,
2233 (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
2234 (1 << 27) | /* interleave chroma, set to 0 for JPEG */
2235 (0 << 22) | /* surface object control state, ignored */
2236 ((obj_surface->width - 1) << 3) | /* pitch */
2237 (0 << 2) | /* must be 0 */
2238 (1 << 1) | /* must be tiled */
2239 (I965_TILEWALK_YMAJOR << 0)); /* tile walk, must be 1 */
2240 OUT_BCS_BATCH(batch,
2241 (0 << 16) | /* X offset for U(Cb), must be 0 */
2242 (obj_surface->y_cb_offset << 0)); /* Y offset for U(Cb) */
2243 OUT_BCS_BATCH(batch,
2244 (0 << 16) | /* X offset for V(Cr), must be 0 */
2245 (0 << 0)); /* Y offset for V(Cr), must be 0 for video codec, non-zoro for JPEG */
2246 ADVANCE_BCS_BATCH(batch);
2250 gen7_jpeg_wa_pipe_buf_addr_state(VADriverContextP ctx,
2251 struct gen7_mfd_context *gen7_mfd_context)
2253 struct i965_driver_data *i965 = i965_driver_data(ctx);
2254 struct object_surface *obj_surface = gen7_mfd_context->jpeg_wa_surface_object;
2255 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2259 intra_bo = dri_bo_alloc(i965->intel.bufmgr,
2264 BEGIN_BCS_BATCH(batch, 24);
2265 OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
2266 OUT_BCS_RELOC(batch,
2268 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2271 OUT_BCS_BATCH(batch, 0); /* post deblocking */
2273 OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
2274 OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
2276 OUT_BCS_RELOC(batch,
2278 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2281 OUT_BCS_BATCH(batch, 0);
2284 for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
2285 OUT_BCS_BATCH(batch, 0);
2288 OUT_BCS_BATCH(batch, 0); /* ignore DW23 for decoding */
2289 ADVANCE_BCS_BATCH(batch);
2291 dri_bo_unreference(intra_bo);
2295 gen7_jpeg_wa_bsp_buf_base_addr_state(VADriverContextP ctx,
2296 struct gen7_mfd_context *gen7_mfd_context)
2298 struct i965_driver_data *i965 = i965_driver_data(ctx);
2299 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2300 dri_bo *bsd_mpc_bo, *mpr_bo;
2302 bsd_mpc_bo = dri_bo_alloc(i965->intel.bufmgr,
2303 "bsd mpc row store",
2304 11520, /* 1.5 * 120 * 64 */
2307 mpr_bo = dri_bo_alloc(i965->intel.bufmgr,
2309 7680, /* 1. 0 * 120 * 64 */
2312 BEGIN_BCS_BATCH(batch, 4);
2313 OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
2315 OUT_BCS_RELOC(batch,
2317 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2320 OUT_BCS_RELOC(batch,
2322 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2324 OUT_BCS_BATCH(batch, 0);
2326 ADVANCE_BCS_BATCH(batch);
2328 dri_bo_unreference(bsd_mpc_bo);
2329 dri_bo_unreference(mpr_bo);
2333 gen7_jpeg_wa_avc_qm_state(VADriverContextP ctx,
2334 struct gen7_mfd_context *gen7_mfd_context)
2340 gen7_jpeg_wa_avc_img_state(VADriverContextP ctx,
2341 struct gen7_mfd_context *gen7_mfd_context)
2343 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2345 int mbaff_frame_flag = 0;
2346 unsigned int width_in_mbs = 1, height_in_mbs = 1;
2348 BEGIN_BCS_BATCH(batch, 16);
2349 OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (16 - 2));
2350 OUT_BCS_BATCH(batch,
2351 (width_in_mbs * height_in_mbs - 1));
2352 OUT_BCS_BATCH(batch,
2353 ((height_in_mbs - 1) << 16) |
2354 ((width_in_mbs - 1) << 0));
2355 OUT_BCS_BATCH(batch,
2360 (0 << 12) | /* differ from GEN6 */
2363 OUT_BCS_BATCH(batch,
2364 (1 << 10) | /* 4:2:0 */
2365 (1 << 7) | /* CABAC */
2371 (mbaff_frame_flag << 1) |
2373 OUT_BCS_BATCH(batch, 0);
2374 OUT_BCS_BATCH(batch, 0);
2375 OUT_BCS_BATCH(batch, 0);
2376 OUT_BCS_BATCH(batch, 0);
2377 OUT_BCS_BATCH(batch, 0);
2378 OUT_BCS_BATCH(batch, 0);
2379 OUT_BCS_BATCH(batch, 0);
2380 OUT_BCS_BATCH(batch, 0);
2381 OUT_BCS_BATCH(batch, 0);
2382 OUT_BCS_BATCH(batch, 0);
2383 OUT_BCS_BATCH(batch, 0);
2384 ADVANCE_BCS_BATCH(batch);
2388 gen7_jpeg_wa_avc_directmode_state(VADriverContextP ctx,
2389 struct gen7_mfd_context *gen7_mfd_context)
2391 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2394 BEGIN_BCS_BATCH(batch, 69);
2395 OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
2397 /* reference surfaces 0..15 */
2398 for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
2399 OUT_BCS_BATCH(batch, 0); /* top */
2400 OUT_BCS_BATCH(batch, 0); /* bottom */
2403 /* the current decoding frame/field */
2404 OUT_BCS_BATCH(batch, 0); /* top */
2405 OUT_BCS_BATCH(batch, 0); /* bottom */
2408 for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
2409 OUT_BCS_BATCH(batch, 0);
2410 OUT_BCS_BATCH(batch, 0);
2413 OUT_BCS_BATCH(batch, 0);
2414 OUT_BCS_BATCH(batch, 0);
2416 ADVANCE_BCS_BATCH(batch);
2420 gen7_jpeg_wa_ind_obj_base_addr_state(VADriverContextP ctx,
2421 struct gen7_mfd_context *gen7_mfd_context)
2423 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2425 BEGIN_BCS_BATCH(batch, 11);
2426 OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
2427 OUT_BCS_RELOC(batch,
2428 gen7_mfd_context->jpeg_wa_slice_data_bo,
2429 I915_GEM_DOMAIN_INSTRUCTION, 0,
2431 OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
2432 OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
2433 OUT_BCS_BATCH(batch, 0);
2434 OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
2435 OUT_BCS_BATCH(batch, 0);
2436 OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
2437 OUT_BCS_BATCH(batch, 0);
2438 OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
2439 OUT_BCS_BATCH(batch, 0);
2440 ADVANCE_BCS_BATCH(batch);
2444 gen7_jpeg_wa_avc_bsd_object(VADriverContextP ctx,
2445 struct gen7_mfd_context *gen7_mfd_context)
2447 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2449 /* the input bitsteam format on GEN7 differs from GEN6 */
2450 BEGIN_BCS_BATCH(batch, 6);
2451 OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2));
2452 OUT_BCS_BATCH(batch, gen7_jpeg_wa_clip.data_size);
2453 OUT_BCS_BATCH(batch, 0);
2454 OUT_BCS_BATCH(batch,
2460 OUT_BCS_BATCH(batch,
2461 ((gen7_jpeg_wa_clip.data_bit_offset >> 3) << 16) |
2464 (1 << 3) | /* LastSlice Flag */
2465 (gen7_jpeg_wa_clip.data_bit_offset & 0x7));
2466 OUT_BCS_BATCH(batch, 0);
2467 ADVANCE_BCS_BATCH(batch);
2471 gen7_jpeg_wa_avc_slice_state(VADriverContextP ctx,
2472 struct gen7_mfd_context *gen7_mfd_context)
2474 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2475 int slice_hor_pos = 0, slice_ver_pos = 0, next_slice_hor_pos = 0, next_slice_ver_pos = 1;
2476 int num_ref_idx_l0 = 0, num_ref_idx_l1 = 0;
2477 int first_mb_in_slice = 0;
2478 int slice_type = SLICE_TYPE_I;
2480 BEGIN_BCS_BATCH(batch, 11);
2481 OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2));
2482 OUT_BCS_BATCH(batch, slice_type);
2483 OUT_BCS_BATCH(batch,
2484 (num_ref_idx_l1 << 24) |
2485 (num_ref_idx_l0 << 16) |
2488 OUT_BCS_BATCH(batch,
2490 (1 << 27) | /* disable Deblocking */
2492 (gen7_jpeg_wa_clip.qp << 16) |
2495 OUT_BCS_BATCH(batch,
2496 (slice_ver_pos << 24) |
2497 (slice_hor_pos << 16) |
2498 (first_mb_in_slice << 0));
2499 OUT_BCS_BATCH(batch,
2500 (next_slice_ver_pos << 16) |
2501 (next_slice_hor_pos << 0));
2502 OUT_BCS_BATCH(batch, (1 << 19)); /* last slice flag */
2503 OUT_BCS_BATCH(batch, 0);
2504 OUT_BCS_BATCH(batch, 0);
2505 OUT_BCS_BATCH(batch, 0);
2506 OUT_BCS_BATCH(batch, 0);
2507 ADVANCE_BCS_BATCH(batch);
2511 gen7_mfd_jpeg_wa(VADriverContextP ctx,
2512 struct gen7_mfd_context *gen7_mfd_context)
2514 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2515 gen7_jpeg_wa_init(ctx, gen7_mfd_context);
2516 intel_batchbuffer_emit_mi_flush(batch);
2517 gen7_jpeg_wa_pipe_mode_select(ctx, gen7_mfd_context);
2518 gen7_jpeg_wa_surface_state(ctx, gen7_mfd_context);
2519 gen7_jpeg_wa_pipe_buf_addr_state(ctx, gen7_mfd_context);
2520 gen7_jpeg_wa_bsp_buf_base_addr_state(ctx, gen7_mfd_context);
2521 gen7_jpeg_wa_avc_qm_state(ctx, gen7_mfd_context);
2522 gen7_jpeg_wa_avc_img_state(ctx, gen7_mfd_context);
2523 gen7_jpeg_wa_ind_obj_base_addr_state(ctx, gen7_mfd_context);
2525 gen7_jpeg_wa_avc_directmode_state(ctx, gen7_mfd_context);
2526 gen7_jpeg_wa_avc_slice_state(ctx, gen7_mfd_context);
2527 gen7_jpeg_wa_avc_bsd_object(ctx, gen7_mfd_context);
2531 gen7_mfd_jpeg_decode_picture(VADriverContextP ctx,
2532 struct decode_state *decode_state,
2533 struct gen7_mfd_context *gen7_mfd_context)
2535 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2536 VAPictureParameterBufferJPEGBaseline *pic_param;
2537 VASliceParameterBufferJPEGBaseline *slice_param, *next_slice_param, *next_slice_group_param;
2538 dri_bo *slice_data_bo;
2539 int i, j, max_selector = 0;
2541 assert(decode_state->pic_param && decode_state->pic_param->buffer);
2542 pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
2544 /* Currently only support Baseline DCT */
2545 gen7_mfd_jpeg_decode_init(ctx, decode_state, gen7_mfd_context);
2546 intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
2547 gen7_mfd_jpeg_wa(ctx, gen7_mfd_context);
2548 intel_batchbuffer_emit_mi_flush(batch);
2549 gen7_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_JPEG, gen7_mfd_context);
2550 gen7_mfd_surface_state(ctx, decode_state, MFX_FORMAT_JPEG, gen7_mfd_context);
2551 gen7_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_JPEG, gen7_mfd_context);
2552 gen7_mfd_jpeg_pic_state(ctx, decode_state, gen7_mfd_context);
2553 gen7_mfd_jpeg_qm_state(ctx, decode_state, gen7_mfd_context);
2555 for (j = 0; j < decode_state->num_slice_params; j++) {
2556 assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
2557 slice_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j]->buffer;
2558 slice_data_bo = decode_state->slice_datas[j]->bo;
2559 gen7_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_JPEG, gen7_mfd_context);
2561 if (j == decode_state->num_slice_params - 1)
2562 next_slice_group_param = NULL;
2564 next_slice_group_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j + 1]->buffer;
2566 for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
2569 assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
2571 if (i < decode_state->slice_params[j]->num_elements - 1)
2572 next_slice_param = slice_param + 1;
2574 next_slice_param = next_slice_group_param;
2576 for (component = 0; component < slice_param->num_components; component++) {
2577 if (max_selector < slice_param->components[component].dc_table_selector)
2578 max_selector = slice_param->components[component].dc_table_selector;
2580 if (max_selector < slice_param->components[component].ac_table_selector)
2581 max_selector = slice_param->components[component].ac_table_selector;
2588 assert(max_selector < 2);
2589 gen7_mfd_jpeg_huff_table_state(ctx, decode_state, gen7_mfd_context, max_selector + 1);
2591 for (j = 0; j < decode_state->num_slice_params; j++) {
2592 assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
2593 slice_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j]->buffer;
2594 slice_data_bo = decode_state->slice_datas[j]->bo;
2595 gen7_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_JPEG, gen7_mfd_context);
2597 if (j == decode_state->num_slice_params - 1)
2598 next_slice_group_param = NULL;
2600 next_slice_group_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j + 1]->buffer;
2602 for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
2603 assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
2605 if (i < decode_state->slice_params[j]->num_elements - 1)
2606 next_slice_param = slice_param + 1;
2608 next_slice_param = next_slice_group_param;
2610 gen7_mfd_jpeg_bsd_object(ctx, pic_param, slice_param, next_slice_param, slice_data_bo, gen7_mfd_context);
2615 intel_batchbuffer_end_atomic(batch);
2616 intel_batchbuffer_flush(batch);
2620 gen7_mfd_decode_picture(VADriverContextP ctx,
2622 union codec_state *codec_state,
2623 struct hw_context *hw_context)
2626 struct gen7_mfd_context *gen7_mfd_context = (struct gen7_mfd_context *)hw_context;
2627 struct decode_state *decode_state = &codec_state->decode;
2630 assert(gen7_mfd_context);
2632 vaStatus = intel_decoder_sanity_check_input(ctx, profile, decode_state);
2634 if (vaStatus != VA_STATUS_SUCCESS)
2637 gen7_mfd_context->wa_mpeg2_slice_vertical_position = -1;
2640 case VAProfileMPEG2Simple:
2641 case VAProfileMPEG2Main:
2642 gen7_mfd_mpeg2_decode_picture(ctx, decode_state, gen7_mfd_context);
2645 case VAProfileH264ConstrainedBaseline:
2646 case VAProfileH264Main:
2647 case VAProfileH264High:
2648 case VAProfileH264StereoHigh:
2649 gen7_mfd_avc_decode_picture(ctx, decode_state, gen7_mfd_context);
2652 case VAProfileVC1Simple:
2653 case VAProfileVC1Main:
2654 case VAProfileVC1Advanced:
2655 gen7_mfd_vc1_decode_picture(ctx, decode_state, gen7_mfd_context);
2658 case VAProfileJPEGBaseline:
2659 gen7_mfd_jpeg_decode_picture(ctx, decode_state, gen7_mfd_context);
2667 vaStatus = VA_STATUS_SUCCESS;
2674 gen7_mfd_context_destroy(void *hw_context)
2676 VADriverContextP ctx;
2677 struct gen7_mfd_context *gen7_mfd_context = (struct gen7_mfd_context *)hw_context;
2679 ctx = (VADriverContextP)(gen7_mfd_context->driver_context);
2681 dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo);
2682 gen7_mfd_context->post_deblocking_output.bo = NULL;
2684 dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
2685 gen7_mfd_context->pre_deblocking_output.bo = NULL;
2687 dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo);
2688 gen7_mfd_context->intra_row_store_scratch_buffer.bo = NULL;
2690 dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
2691 gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
2693 dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
2694 gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
2696 dri_bo_unreference(gen7_mfd_context->mpr_row_store_scratch_buffer.bo);
2697 gen7_mfd_context->mpr_row_store_scratch_buffer.bo = NULL;
2699 dri_bo_unreference(gen7_mfd_context->bitplane_read_buffer.bo);
2700 gen7_mfd_context->bitplane_read_buffer.bo = NULL;
2702 dri_bo_unreference(gen7_mfd_context->jpeg_wa_slice_data_bo);
2704 if (gen7_mfd_context->jpeg_wa_surface_id != VA_INVALID_SURFACE) {
2705 i965_DestroySurfaces(ctx,
2706 &gen7_mfd_context->jpeg_wa_surface_id,
2708 gen7_mfd_context->jpeg_wa_surface_object = NULL;
2711 intel_batchbuffer_free(gen7_mfd_context->base.batch);
2712 free(gen7_mfd_context);
2715 static void gen7_mfd_mpeg2_context_init(VADriverContextP ctx,
2716 struct gen7_mfd_context *gen7_mfd_context)
2718 gen7_mfd_context->iq_matrix.mpeg2.load_intra_quantiser_matrix = -1;
2719 gen7_mfd_context->iq_matrix.mpeg2.load_non_intra_quantiser_matrix = -1;
2720 gen7_mfd_context->iq_matrix.mpeg2.load_chroma_intra_quantiser_matrix = -1;
2721 gen7_mfd_context->iq_matrix.mpeg2.load_chroma_non_intra_quantiser_matrix = -1;
2725 gen7_dec_hw_context_init(VADriverContextP ctx, struct object_config *obj_config)
2727 struct intel_driver_data *intel = intel_driver_data(ctx);
2728 struct gen7_mfd_context *gen7_mfd_context = calloc(1, sizeof(struct gen7_mfd_context));
2731 assert(gen7_mfd_context);
2732 gen7_mfd_context->base.destroy = gen7_mfd_context_destroy;
2733 gen7_mfd_context->base.run = gen7_mfd_decode_picture;
2734 gen7_mfd_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER, 0);
2736 for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
2737 gen7_mfd_context->reference_surface[i].surface_id = VA_INVALID_ID;
2738 gen7_mfd_context->reference_surface[i].frame_store_id = -1;
2739 gen7_mfd_context->reference_surface[i].obj_surface = NULL;
2742 gen7_mfd_context->jpeg_wa_surface_id = VA_INVALID_SURFACE;
2743 gen7_mfd_context->jpeg_wa_surface_object = NULL;
2745 switch (obj_config->profile) {
2746 case VAProfileMPEG2Simple:
2747 case VAProfileMPEG2Main:
2748 gen7_mfd_mpeg2_context_init(ctx, gen7_mfd_context);
2751 case VAProfileH264ConstrainedBaseline:
2752 case VAProfileH264Main:
2753 case VAProfileH264High:
2754 case VAProfileH264StereoHigh:
2755 gen7_mfd_avc_context_init(ctx, gen7_mfd_context);
2761 gen7_mfd_context->driver_context = ctx;
2762 return (struct hw_context *)gen7_mfd_context;