src/gen7_mfd.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Xiang Haihao <haihao.xiang@intel.com>
  26  *
  27  */
  28
  29 #include "sysdeps.h"
  30
  31 #include <va/va_dec_jpeg.h>
  32
  33 #include "intel_batchbuffer.h"
  34 #include "intel_driver.h"
  35 #include "i965_defines.h"
  36 #include "i965_drv_video.h"
  37 #include "i965_decoder_utils.h"
  38
  39 #include "gen7_mfd.h"
  40 #include "intel_media.h"
  41
  42 static const uint32_t zigzag_direct[64] = {
  43     0,   1,  8, 16,  9,  2,  3, 10,
  44     17, 24, 32, 25, 18, 11,  4,  5,
  45     12, 19, 26, 33, 40, 48, 41, 34,
  46     27, 20, 13,  6,  7, 14, 21, 28,
  47     35, 42, 49, 56, 57, 50, 43, 36,
  48     29, 22, 15, 23, 30, 37, 44, 51,
  49     58, 59, 52, 45, 38, 31, 39, 46,
  50     53, 60, 61, 54, 47, 55, 62, 63
  51 };
  52
  53 static void
  54 gen7_mfd_init_avc_surface(VADriverContextP ctx,
  55                           VAPictureParameterBufferH264 *pic_param,
  56                           struct object_surface *obj_surface)
  57 {
  58     struct i965_driver_data *i965 = i965_driver_data(ctx);
  59     GenAvcSurface *gen7_avc_surface = obj_surface->private_data;
  60     int width_in_mbs, height_in_mbs;
  61
  62     obj_surface->free_private_data = gen_free_avc_surface;
  63     width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
  64     height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; /* frame height */
  65
  66     if (!gen7_avc_surface) {
  67         gen7_avc_surface = calloc(sizeof(GenAvcSurface), 1);
  68         assert(gen7_avc_surface);
  69         gen7_avc_surface->base.frame_store_id = -1;
  70         assert((obj_surface->size & 0x3f) == 0);
  71         obj_surface->private_data = gen7_avc_surface;
  72     }
  73
  74     gen7_avc_surface->dmv_bottom_flag = (pic_param->pic_fields.bits.field_pic_flag &&
  75                                          !pic_param->seq_fields.bits.direct_8x8_inference_flag);
  76
  77     if (gen7_avc_surface->dmv_top == NULL) {
  78         gen7_avc_surface->dmv_top = dri_bo_alloc(i965->intel.bufmgr,
  79                                                  "direct mv w/r buffer",
  80                                                  width_in_mbs * (height_in_mbs + 1) * 64,
  81                                                  0x1000);
  82         assert(gen7_avc_surface->dmv_top);
  83     }
  84
  85     if (gen7_avc_surface->dmv_bottom_flag &&
  86         gen7_avc_surface->dmv_bottom == NULL) {
  87         gen7_avc_surface->dmv_bottom = dri_bo_alloc(i965->intel.bufmgr,
  88                                                     "direct mv w/r buffer",
  89                                                     width_in_mbs * (height_in_mbs + 1) * 64,
  90                                                     0x1000);
  91         assert(gen7_avc_surface->dmv_bottom);
  92     }
  93 }
  94
  95 static void
  96 gen7_mfd_pipe_mode_select(VADriverContextP ctx,
  97                           struct decode_state *decode_state,
  98                           int standard_select,
  99                           struct gen7_mfd_context *gen7_mfd_context)
 100 {
 101     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 102
 103     assert(standard_select == MFX_FORMAT_MPEG2 ||
 104            standard_select == MFX_FORMAT_AVC ||
 105            standard_select == MFX_FORMAT_VC1 ||
 106            standard_select == MFX_FORMAT_JPEG);
 107
 108     BEGIN_BCS_BATCH(batch, 5);
 109     OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2));
 110     OUT_BCS_BATCH(batch,
 111                   (MFX_LONG_MODE << 17) | /* Currently only support long format */
 112                   (MFD_MODE_VLD << 15) | /* VLD mode */
 113                   (0 << 10) | /* disable Stream-Out */
 114                   (gen7_mfd_context->post_deblocking_output.valid << 9)  | /* Post Deblocking Output */
 115                   (gen7_mfd_context->pre_deblocking_output.valid << 8)  | /* Pre Deblocking Output */
 116                   (0 << 5)  | /* not in stitch mode */
 117                   (MFX_CODEC_DECODE << 4)  | /* decoding mode */
 118                   (standard_select << 0));
 119     OUT_BCS_BATCH(batch,
 120                   (0 << 4)  | /* terminate if AVC motion and POC table error occurs */
 121                   (0 << 3)  | /* terminate if AVC mbdata error occurs */
 122                   (0 << 2)  | /* terminate if AVC CABAC/CAVLC decode error occurs */
 123                   (0 << 1)  |
 124                   (0 << 0));
 125     OUT_BCS_BATCH(batch, 0); /* pic status/error report id */
 126     OUT_BCS_BATCH(batch, 0); /* reserved */
 127     ADVANCE_BCS_BATCH(batch);
 128 }
 129
 130 static void
 131 gen7_mfd_surface_state(VADriverContextP ctx,
 132                        struct decode_state *decode_state,
 133                        int standard_select,
 134                        struct gen7_mfd_context *gen7_mfd_context)
 135 {
 136     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 137     struct object_surface *obj_surface = decode_state->render_object;
 138     unsigned int y_cb_offset;
 139     unsigned int y_cr_offset;
 140     unsigned int surface_format;
 141
 142     assert(obj_surface);
 143
 144     y_cb_offset = obj_surface->y_cb_offset;
 145     y_cr_offset = obj_surface->y_cr_offset;
 146
 147     surface_format = obj_surface->fourcc == VA_FOURCC_Y800 ?
 148         MFX_SURFACE_MONOCHROME : MFX_SURFACE_PLANAR_420_8;
 149
 150     BEGIN_BCS_BATCH(batch, 6);
 151     OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
 152     OUT_BCS_BATCH(batch, 0);
 153     OUT_BCS_BATCH(batch,
 154                   ((obj_surface->orig_height - 1) << 18) |
 155                   ((obj_surface->orig_width - 1) << 4));
 156     OUT_BCS_BATCH(batch,
 157                   (surface_format << 28) | /* 420 planar YUV surface */
 158                   ((standard_select != MFX_FORMAT_JPEG) << 27) | /* interleave chroma, set to 0 for JPEG */
 159                   (0 << 22) | /* surface object control state, ignored */
 160                   ((obj_surface->width - 1) << 3) | /* pitch */
 161                   (0 << 2)  | /* must be 0 */
 162                   (1 << 1)  | /* must be tiled */
 163                   (I965_TILEWALK_YMAJOR << 0));  /* tile walk, must be 1 */
 164     OUT_BCS_BATCH(batch,
 165                   (0 << 16) | /* X offset for U(Cb), must be 0 */
 166                   (y_cb_offset << 0)); /* Y offset for U(Cb) */
 167     OUT_BCS_BATCH(batch,
 168                   (0 << 16) | /* X offset for V(Cr), must be 0 */
 169                   (y_cr_offset << 0)); /* Y offset for V(Cr), must be 0 for video codec, non-zoro for JPEG */
 170     ADVANCE_BCS_BATCH(batch);
 171 }
 172
 173 static void
 174 gen7_mfd_pipe_buf_addr_state(VADriverContextP ctx,
 175                              struct decode_state *decode_state,
 176                              int standard_select,
 177                              struct gen7_mfd_context *gen7_mfd_context)
 178 {
 179     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 180     int i;
 181
 182     BEGIN_BCS_BATCH(batch, 24);
 183     OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
 184     if (gen7_mfd_context->pre_deblocking_output.valid)
 185         OUT_BCS_RELOC(batch, gen7_mfd_context->pre_deblocking_output.bo,
 186                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 187                       0);
 188     else
 189         OUT_BCS_BATCH(batch, 0);
 190
 191     if (gen7_mfd_context->post_deblocking_output.valid)
 192         OUT_BCS_RELOC(batch, gen7_mfd_context->post_deblocking_output.bo,
 193                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 194                       0);
 195     else
 196         OUT_BCS_BATCH(batch, 0);
 197
 198     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
 199     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
 200
 201     if (gen7_mfd_context->intra_row_store_scratch_buffer.valid)
 202         OUT_BCS_RELOC(batch, gen7_mfd_context->intra_row_store_scratch_buffer.bo,
 203                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 204                       0);
 205     else
 206         OUT_BCS_BATCH(batch, 0);
 207
 208     if (gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid)
 209         OUT_BCS_RELOC(batch, gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo,
 210                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 211                       0);
 212     else
 213         OUT_BCS_BATCH(batch, 0);
 214
 215     /* DW 7..22 */
 216     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
 217         struct object_surface *obj_surface;
 218
 219         if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID &&
 220             gen7_mfd_context->reference_surface[i].obj_surface &&
 221             gen7_mfd_context->reference_surface[i].obj_surface->bo) {
 222             obj_surface = gen7_mfd_context->reference_surface[i].obj_surface;
 223
 224             OUT_BCS_RELOC(batch, obj_surface->bo,
 225                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 226                           0);
 227         } else {
 228             OUT_BCS_BATCH(batch, 0);
 229         }
 230     }
 231
 232     OUT_BCS_BATCH(batch, 0);   /* ignore DW23 for decoding */
 233     ADVANCE_BCS_BATCH(batch);
 234 }
 235
 236 static void
 237 gen7_mfd_ind_obj_base_addr_state(VADriverContextP ctx,
 238                                  dri_bo *slice_data_bo,
 239                                  int standard_select,
 240                                  struct gen7_mfd_context *gen7_mfd_context)
 241 {
 242     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 243
 244     BEGIN_BCS_BATCH(batch, 11);
 245     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
 246     OUT_BCS_RELOC(batch, slice_data_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); /* MFX Indirect Bitstream Object Base Address */
 247     OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
 248     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 249     OUT_BCS_BATCH(batch, 0);
 250     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 251     OUT_BCS_BATCH(batch, 0);
 252     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 253     OUT_BCS_BATCH(batch, 0);
 254     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 255     OUT_BCS_BATCH(batch, 0);
 256     ADVANCE_BCS_BATCH(batch);
 257 }
 258
 259 static void
 260 gen7_mfd_bsp_buf_base_addr_state(VADriverContextP ctx,
 261                                  struct decode_state *decode_state,
 262                                  int standard_select,
 263                                  struct gen7_mfd_context *gen7_mfd_context)
 264 {
 265     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 266
 267     BEGIN_BCS_BATCH(batch, 4);
 268     OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
 269
 270     if (gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid)
 271         OUT_BCS_RELOC(batch, gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo,
 272                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 273                       0);
 274     else
 275         OUT_BCS_BATCH(batch, 0);
 276
 277     if (gen7_mfd_context->mpr_row_store_scratch_buffer.valid)
 278         OUT_BCS_RELOC(batch, gen7_mfd_context->mpr_row_store_scratch_buffer.bo,
 279                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 280                       0);
 281     else
 282         OUT_BCS_BATCH(batch, 0);
 283
 284     if (gen7_mfd_context->bitplane_read_buffer.valid)
 285         OUT_BCS_RELOC(batch, gen7_mfd_context->bitplane_read_buffer.bo,
 286                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 287                       0);
 288     else
 289         OUT_BCS_BATCH(batch, 0);
 290
 291     ADVANCE_BCS_BATCH(batch);
 292 }
 293
 294 static void
 295 gen7_mfd_qm_state(VADriverContextP ctx,
 296                   int qm_type,
 297                   unsigned char *qm,
 298                   int qm_length,
 299                   struct gen7_mfd_context *gen7_mfd_context)
 300 {
 301     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 302     unsigned int qm_buffer[16];
 303
 304     assert(qm_length <= 16 * 4);
 305     memcpy(qm_buffer, qm, qm_length);
 306
 307     BEGIN_BCS_BATCH(batch, 18);
 308     OUT_BCS_BATCH(batch, MFX_QM_STATE | (18 - 2));
 309     OUT_BCS_BATCH(batch, qm_type << 0);
 310     intel_batchbuffer_data(batch, qm_buffer, 16 * 4);
 311     ADVANCE_BCS_BATCH(batch);
 312 }
 313
 314 static void
 315 gen7_mfd_avc_img_state(VADriverContextP ctx,
 316                        struct decode_state *decode_state,
 317                        struct gen7_mfd_context *gen7_mfd_context)
 318 {
 319     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 320     int img_struct;
 321     int mbaff_frame_flag;
 322     unsigned int width_in_mbs, height_in_mbs;
 323     VAPictureParameterBufferH264 *pic_param;
 324
 325     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 326     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 327
 328     if (pic_param->CurrPic.flags & VA_PICTURE_H264_TOP_FIELD)
 329         img_struct = 1;
 330     else if (pic_param->CurrPic.flags & VA_PICTURE_H264_BOTTOM_FIELD)
 331         img_struct = 3;
 332     else
 333         img_struct = 0;
 334
 335     if ((img_struct & 0x1) == 0x1) {
 336         assert(pic_param->pic_fields.bits.field_pic_flag == 0x1);
 337     } else {
 338         assert(pic_param->pic_fields.bits.field_pic_flag == 0x0);
 339     }
 340
 341     if (pic_param->seq_fields.bits.frame_mbs_only_flag) { /* a frame containing only frame macroblocks */
 342         assert(pic_param->seq_fields.bits.mb_adaptive_frame_field_flag == 0);
 343         assert(pic_param->pic_fields.bits.field_pic_flag == 0);
 344     } else {
 345         assert(pic_param->seq_fields.bits.direct_8x8_inference_flag == 1); /* see H.264 spec */
 346     }
 347
 348     mbaff_frame_flag = (pic_param->seq_fields.bits.mb_adaptive_frame_field_flag &&
 349                         !pic_param->pic_fields.bits.field_pic_flag);
 350
 351     width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
 352     height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; /* frame height */
 353
 354     /* MFX unit doesn't support 4:2:2 and 4:4:4 picture */
 355     assert(pic_param->seq_fields.bits.chroma_format_idc == 0 || /* monochrome picture */
 356            pic_param->seq_fields.bits.chroma_format_idc == 1);  /* 4:2:0 */
 357     assert(pic_param->seq_fields.bits.residual_colour_transform_flag == 0); /* only available for 4:4:4 */
 358
 359     BEGIN_BCS_BATCH(batch, 16);
 360     OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (16 - 2));
 361     OUT_BCS_BATCH(batch,
 362                   (width_in_mbs * height_in_mbs - 1));
 363     OUT_BCS_BATCH(batch,
 364                   ((height_in_mbs - 1) << 16) |
 365                   ((width_in_mbs - 1) << 0));
 366     OUT_BCS_BATCH(batch,
 367                   ((pic_param->second_chroma_qp_index_offset & 0x1f) << 24) |
 368                   ((pic_param->chroma_qp_index_offset & 0x1f) << 16) |
 369                   (0 << 14) | /* Max-bit conformance Intra flag ??? FIXME */
 370                   (0 << 13) | /* Max Macroblock size conformance Inter flag ??? FIXME */
 371                   (pic_param->pic_fields.bits.weighted_pred_flag << 12) | /* differ from GEN6 */
 372                   (pic_param->pic_fields.bits.weighted_bipred_idc << 10) |
 373                   (img_struct << 8));
 374     OUT_BCS_BATCH(batch,
 375                   (pic_param->seq_fields.bits.chroma_format_idc << 10) |
 376                   (pic_param->pic_fields.bits.entropy_coding_mode_flag << 7) |
 377                   ((!pic_param->pic_fields.bits.reference_pic_flag) << 6) |
 378                   (pic_param->pic_fields.bits.constrained_intra_pred_flag << 5) |
 379                   (pic_param->seq_fields.bits.direct_8x8_inference_flag << 4) |
 380                   (pic_param->pic_fields.bits.transform_8x8_mode_flag << 3) |
 381                   (pic_param->seq_fields.bits.frame_mbs_only_flag << 2) |
 382                   (mbaff_frame_flag << 1) |
 383                   (pic_param->pic_fields.bits.field_pic_flag << 0));
 384     OUT_BCS_BATCH(batch, 0);
 385     OUT_BCS_BATCH(batch, 0);
 386     OUT_BCS_BATCH(batch, 0);
 387     OUT_BCS_BATCH(batch, 0);
 388     OUT_BCS_BATCH(batch, 0);
 389     OUT_BCS_BATCH(batch, 0);
 390     OUT_BCS_BATCH(batch, 0);
 391     OUT_BCS_BATCH(batch, 0);
 392     OUT_BCS_BATCH(batch, 0);
 393     OUT_BCS_BATCH(batch, 0);
 394     OUT_BCS_BATCH(batch, 0);
 395     ADVANCE_BCS_BATCH(batch);
 396 }
 397
 398 static void
 399 gen7_mfd_avc_qm_state(VADriverContextP ctx,
 400                       struct decode_state *decode_state,
 401                       struct gen7_mfd_context *gen7_mfd_context)
 402 {
 403     VAIQMatrixBufferH264 *iq_matrix;
 404     VAPictureParameterBufferH264 *pic_param;
 405
 406     if (decode_state->iq_matrix && decode_state->iq_matrix->buffer)
 407         iq_matrix = (VAIQMatrixBufferH264 *)decode_state->iq_matrix->buffer;
 408     else
 409         iq_matrix = &gen7_mfd_context->iq_matrix.h264;
 410
 411     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 412     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 413
 414     gen7_mfd_qm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, &iq_matrix->ScalingList4x4[0][0], 3 * 16, gen7_mfd_context);
 415     gen7_mfd_qm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, &iq_matrix->ScalingList4x4[3][0], 3 * 16, gen7_mfd_context);
 416
 417     if (pic_param->pic_fields.bits.transform_8x8_mode_flag) {
 418         gen7_mfd_qm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, &iq_matrix->ScalingList8x8[0][0], 64, gen7_mfd_context);
 419         gen7_mfd_qm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, &iq_matrix->ScalingList8x8[1][0], 64, gen7_mfd_context);
 420     }
 421 }
 422
 423 static void
 424 gen7_mfd_avc_directmode_state(VADriverContextP ctx,
 425                               struct decode_state *decode_state,
 426                               VAPictureParameterBufferH264 *pic_param,
 427                               VASliceParameterBufferH264 *slice_param,
 428                               struct gen7_mfd_context *gen7_mfd_context)
 429 {
 430     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 431     struct object_surface *obj_surface;
 432     GenAvcSurface *gen7_avc_surface;
 433     VAPictureH264 *va_pic;
 434     int i;
 435
 436     BEGIN_BCS_BATCH(batch, 69);
 437     OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
 438
 439     /* reference surfaces 0..15 */
 440     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
 441         if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID &&
 442             gen7_mfd_context->reference_surface[i].obj_surface &&
 443             gen7_mfd_context->reference_surface[i].obj_surface->private_data) {
 444
 445             obj_surface = gen7_mfd_context->reference_surface[i].obj_surface;
 446             gen7_avc_surface = obj_surface->private_data;
 447             OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
 448                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 449                           0);
 450
 451             if (gen7_avc_surface->dmv_bottom_flag == 1)
 452                 OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_bottom,
 453                               I915_GEM_DOMAIN_INSTRUCTION, 0,
 454                               0);
 455             else
 456                 OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
 457                               I915_GEM_DOMAIN_INSTRUCTION, 0,
 458                               0);
 459         } else {
 460             OUT_BCS_BATCH(batch, 0);
 461             OUT_BCS_BATCH(batch, 0);
 462         }
 463     }
 464
 465     /* the current decoding frame/field */
 466     va_pic = &pic_param->CurrPic;
 467     obj_surface = decode_state->render_object;
 468     assert(obj_surface->bo && obj_surface->private_data);
 469     gen7_avc_surface = obj_surface->private_data;
 470
 471     OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
 472                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 473                   0);
 474
 475     if (gen7_avc_surface->dmv_bottom_flag == 1)
 476         OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_bottom,
 477                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 478                       0);
 479     else
 480         OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
 481                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 482                       0);
 483
 484     /* POC List */
 485     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
 486         obj_surface = gen7_mfd_context->reference_surface[i].obj_surface;
 487
 488         if (obj_surface) {
 489             const VAPictureH264 * const va_pic = avc_find_picture(
 490                 obj_surface->base.id, pic_param->ReferenceFrames,
 491                 ARRAY_ELEMS(pic_param->ReferenceFrames));
 492
 493             assert(va_pic != NULL);
 494             OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
 495             OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
 496         } else {
 497             OUT_BCS_BATCH(batch, 0);
 498             OUT_BCS_BATCH(batch, 0);
 499         }
 500     }
 501
 502     va_pic = &pic_param->CurrPic;
 503     OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
 504     OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
 505
 506     ADVANCE_BCS_BATCH(batch);
 507 }
 508
 509 static void
 510 gen7_mfd_avc_phantom_slice_first(VADriverContextP ctx,
 511                                  VAPictureParameterBufferH264 *pic_param,
 512                                  VASliceParameterBufferH264 *next_slice_param,
 513                                  struct gen7_mfd_context *gen7_mfd_context)
 514 {
 515     gen6_mfd_avc_phantom_slice(ctx, pic_param, next_slice_param, gen7_mfd_context->base.batch);
 516 }
 517
 518 static void
 519 gen7_mfd_avc_slice_state(VADriverContextP ctx,
 520                          VAPictureParameterBufferH264 *pic_param,
 521                          VASliceParameterBufferH264 *slice_param,
 522                          VASliceParameterBufferH264 *next_slice_param,
 523                          struct gen7_mfd_context *gen7_mfd_context)
 524 {
 525     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 526     int width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
 527     int height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1;
 528     int slice_hor_pos, slice_ver_pos, next_slice_hor_pos, next_slice_ver_pos;
 529     int num_ref_idx_l0, num_ref_idx_l1;
 530     int mbaff_picture = (!pic_param->pic_fields.bits.field_pic_flag &&
 531                          pic_param->seq_fields.bits.mb_adaptive_frame_field_flag);
 532     int first_mb_in_slice = 0, first_mb_in_next_slice = 0;
 533     int slice_type;
 534
 535     if (slice_param->slice_type == SLICE_TYPE_I ||
 536         slice_param->slice_type == SLICE_TYPE_SI) {
 537         slice_type = SLICE_TYPE_I;
 538     } else if (slice_param->slice_type == SLICE_TYPE_P ||
 539                slice_param->slice_type == SLICE_TYPE_SP) {
 540         slice_type = SLICE_TYPE_P;
 541     } else {
 542         assert(slice_param->slice_type == SLICE_TYPE_B);
 543         slice_type = SLICE_TYPE_B;
 544     }
 545
 546     if (slice_type == SLICE_TYPE_I) {
 547         assert(slice_param->num_ref_idx_l0_active_minus1 == 0);
 548         assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
 549         num_ref_idx_l0 = 0;
 550         num_ref_idx_l1 = 0;
 551     } else if (slice_type == SLICE_TYPE_P) {
 552         assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
 553         num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
 554         num_ref_idx_l1 = 0;
 555     } else {
 556         num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
 557         num_ref_idx_l1 = slice_param->num_ref_idx_l1_active_minus1 + 1;
 558     }
 559
 560     first_mb_in_slice = slice_param->first_mb_in_slice;
 561     slice_hor_pos = first_mb_in_slice % width_in_mbs;
 562     slice_ver_pos = first_mb_in_slice / width_in_mbs;
 563
 564     if (mbaff_picture)
 565         slice_ver_pos = slice_ver_pos << 1;
 566
 567     if (next_slice_param) {
 568         first_mb_in_next_slice = next_slice_param->first_mb_in_slice;
 569         next_slice_hor_pos = first_mb_in_next_slice % width_in_mbs;
 570         next_slice_ver_pos = first_mb_in_next_slice / width_in_mbs;
 571
 572         if (mbaff_picture)
 573             next_slice_ver_pos = next_slice_ver_pos << 1;
 574     } else {
 575         next_slice_hor_pos = 0;
 576         next_slice_ver_pos = height_in_mbs / (1 + !!pic_param->pic_fields.bits.field_pic_flag);
 577     }
 578
 579     BEGIN_BCS_BATCH(batch, 11); /* FIXME: is it 10??? */
 580     OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2));
 581     OUT_BCS_BATCH(batch, slice_type);
 582     OUT_BCS_BATCH(batch,
 583                   (num_ref_idx_l1 << 24) |
 584                   (num_ref_idx_l0 << 16) |
 585                   (slice_param->chroma_log2_weight_denom << 8) |
 586                   (slice_param->luma_log2_weight_denom << 0));
 587     OUT_BCS_BATCH(batch,
 588                   (slice_param->direct_spatial_mv_pred_flag << 29) |
 589                   (slice_param->disable_deblocking_filter_idc << 27) |
 590                   (slice_param->cabac_init_idc << 24) |
 591                   ((pic_param->pic_init_qp_minus26 + 26 + slice_param->slice_qp_delta) << 16) |
 592                   ((slice_param->slice_beta_offset_div2 & 0xf) << 8) |
 593                   ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0));
 594     OUT_BCS_BATCH(batch,
 595                   (slice_ver_pos << 24) |
 596                   (slice_hor_pos << 16) |
 597                   (first_mb_in_slice << 0));
 598     OUT_BCS_BATCH(batch,
 599                   (next_slice_ver_pos << 16) |
 600                   (next_slice_hor_pos << 0));
 601     OUT_BCS_BATCH(batch,
 602                   (next_slice_param == NULL) << 19); /* last slice flag */
 603     OUT_BCS_BATCH(batch, 0);
 604     OUT_BCS_BATCH(batch, 0);
 605     OUT_BCS_BATCH(batch, 0);
 606     OUT_BCS_BATCH(batch, 0);
 607     ADVANCE_BCS_BATCH(batch);
 608 }
 609
 610 static inline void
 611 gen7_mfd_avc_ref_idx_state(VADriverContextP ctx,
 612                            VAPictureParameterBufferH264 *pic_param,
 613                            VASliceParameterBufferH264 *slice_param,
 614                            struct gen7_mfd_context *gen7_mfd_context)
 615 {
 616     gen6_send_avc_ref_idx_state(
 617         gen7_mfd_context->base.batch,
 618         slice_param,
 619         gen7_mfd_context->reference_surface
 620     );
 621 }
 622
 623 static void
 624 gen7_mfd_avc_weightoffset_state(VADriverContextP ctx,
 625                                 VAPictureParameterBufferH264 *pic_param,
 626                                 VASliceParameterBufferH264 *slice_param,
 627                                 struct gen7_mfd_context *gen7_mfd_context)
 628 {
 629     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 630     int i, j, num_weight_offset_table = 0;
 631     short weightoffsets[32 * 6];
 632
 633     if ((slice_param->slice_type == SLICE_TYPE_P ||
 634          slice_param->slice_type == SLICE_TYPE_SP) &&
 635         (pic_param->pic_fields.bits.weighted_pred_flag == 1)) {
 636         num_weight_offset_table = 1;
 637     }
 638
 639     if ((slice_param->slice_type == SLICE_TYPE_B) &&
 640         (pic_param->pic_fields.bits.weighted_bipred_idc == 1)) {
 641         num_weight_offset_table = 2;
 642     }
 643
 644     for (i = 0; i < num_weight_offset_table; i++) {
 645         BEGIN_BCS_BATCH(batch, 98);
 646         OUT_BCS_BATCH(batch, MFX_AVC_WEIGHTOFFSET_STATE | (98 - 2));
 647         OUT_BCS_BATCH(batch, i);
 648
 649         if (i == 0) {
 650             for (j = 0; j < 32; j++) {
 651                 weightoffsets[j * 6 + 0] = slice_param->luma_weight_l0[j];
 652                 weightoffsets[j * 6 + 1] = slice_param->luma_offset_l0[j];
 653                 weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l0[j][0];
 654                 weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l0[j][0];
 655                 weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l0[j][1];
 656                 weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l0[j][1];
 657             }
 658         } else {
 659             for (j = 0; j < 32; j++) {
 660                 weightoffsets[j * 6 + 0] = slice_param->luma_weight_l1[j];
 661                 weightoffsets[j * 6 + 1] = slice_param->luma_offset_l1[j];
 662                 weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l1[j][0];
 663                 weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l1[j][0];
 664                 weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l1[j][1];
 665                 weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l1[j][1];
 666             }
 667         }
 668
 669         intel_batchbuffer_data(batch, weightoffsets, sizeof(weightoffsets));
 670         ADVANCE_BCS_BATCH(batch);
 671     }
 672 }
 673
 674 static void
 675 gen7_mfd_avc_bsd_object(VADriverContextP ctx,
 676                         VAPictureParameterBufferH264 *pic_param,
 677                         VASliceParameterBufferH264 *slice_param,
 678                         dri_bo *slice_data_bo,
 679                         VASliceParameterBufferH264 *next_slice_param,
 680                         struct gen7_mfd_context *gen7_mfd_context)
 681 {
 682     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 683     unsigned int slice_data_bit_offset;
 684
 685     slice_data_bit_offset = avc_get_first_mb_bit_offset(
 686         slice_data_bo,
 687         slice_param,
 688         pic_param->pic_fields.bits.entropy_coding_mode_flag
 689     );
 690
 691     /* the input bitsteam format on GEN7 differs from GEN6 */
 692     BEGIN_BCS_BATCH(batch, 6);
 693     OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2));
 694     OUT_BCS_BATCH(batch,
 695                   (slice_param->slice_data_size - slice_param->slice_data_offset));
 696     OUT_BCS_BATCH(batch, slice_param->slice_data_offset);
 697     OUT_BCS_BATCH(batch,
 698                   (0 << 31) |
 699                   (0 << 14) |
 700                   (0 << 12) |
 701                   (0 << 10) |
 702                   (0 << 8));
 703     OUT_BCS_BATCH(batch,
 704                   ((slice_data_bit_offset >> 3) << 16) |
 705                   (1 << 7)  |
 706                   (0 << 5)  |
 707                   (0 << 4)  |
 708                   ((next_slice_param == NULL) << 3) | /* LastSlice Flag */
 709                   (slice_data_bit_offset & 0x7));
 710     OUT_BCS_BATCH(batch, 0);
 711     ADVANCE_BCS_BATCH(batch);
 712 }
 713
 714 static inline void
 715 gen7_mfd_avc_context_init(
 716     VADriverContextP         ctx,
 717     struct gen7_mfd_context *gen7_mfd_context
 718 )
 719 {
 720     /* Initialize flat scaling lists */
 721     avc_gen_default_iq_matrix(&gen7_mfd_context->iq_matrix.h264);
 722 }
 723
 724 static void
 725 gen7_mfd_avc_decode_init(VADriverContextP ctx,
 726                          struct decode_state *decode_state,
 727                          struct gen7_mfd_context *gen7_mfd_context)
 728 {
 729     VAPictureParameterBufferH264 *pic_param;
 730     VASliceParameterBufferH264 *slice_param;
 731     struct i965_driver_data *i965 = i965_driver_data(ctx);
 732     struct object_surface *obj_surface;
 733     dri_bo *bo;
 734     int i, j, enable_avc_ildb = 0;
 735     unsigned int width_in_mbs, height_in_mbs;
 736
 737     for (j = 0; j < decode_state->num_slice_params && enable_avc_ildb == 0; j++) {
 738         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
 739         slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
 740
 741         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
 742             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
 743             assert((slice_param->slice_type == SLICE_TYPE_I) ||
 744                    (slice_param->slice_type == SLICE_TYPE_SI) ||
 745                    (slice_param->slice_type == SLICE_TYPE_P) ||
 746                    (slice_param->slice_type == SLICE_TYPE_SP) ||
 747                    (slice_param->slice_type == SLICE_TYPE_B));
 748
 749             if (slice_param->disable_deblocking_filter_idc != 1) {
 750                 enable_avc_ildb = 1;
 751                 break;
 752             }
 753
 754             slice_param++;
 755         }
 756     }
 757
 758     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 759     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 760     intel_update_avc_frame_store_index(ctx, decode_state, pic_param,
 761         gen7_mfd_context->reference_surface, &gen7_mfd_context->fs_ctx);
 762     width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
 763     height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1;
 764     assert(width_in_mbs > 0 && width_in_mbs <= 256); /* 4K */
 765     assert(height_in_mbs > 0 && height_in_mbs <= 256);
 766
 767     /* Current decoded picture */
 768     obj_surface = decode_state->render_object;
 769     if (pic_param->pic_fields.bits.reference_pic_flag)
 770         obj_surface->flags |= SURFACE_REFERENCED;
 771     else
 772         obj_surface->flags &= ~SURFACE_REFERENCED;
 773
 774     avc_ensure_surface_bo(ctx, decode_state, obj_surface, pic_param);
 775     gen7_mfd_init_avc_surface(ctx, pic_param, obj_surface);
 776
 777     dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo);
 778     gen7_mfd_context->post_deblocking_output.bo = obj_surface->bo;
 779     dri_bo_reference(gen7_mfd_context->post_deblocking_output.bo);
 780     gen7_mfd_context->post_deblocking_output.valid = enable_avc_ildb;
 781
 782     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
 783     gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
 784     dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
 785     gen7_mfd_context->pre_deblocking_output.valid = !enable_avc_ildb;
 786
 787     dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo);
 788     bo = dri_bo_alloc(i965->intel.bufmgr,
 789                       "intra row store",
 790                       width_in_mbs * 64,
 791                       0x1000);
 792     assert(bo);
 793     gen7_mfd_context->intra_row_store_scratch_buffer.bo = bo;
 794     gen7_mfd_context->intra_row_store_scratch_buffer.valid = 1;
 795
 796     dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
 797     bo = dri_bo_alloc(i965->intel.bufmgr,
 798                       "deblocking filter row store",
 799                       width_in_mbs * 64 * 4,
 800                       0x1000);
 801     assert(bo);
 802     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
 803     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1;
 804
 805     dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
 806     bo = dri_bo_alloc(i965->intel.bufmgr,
 807                       "bsd mpc row store",
 808                       width_in_mbs * 64 * 2,
 809                       0x1000);
 810     assert(bo);
 811     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
 812     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
 813
 814     dri_bo_unreference(gen7_mfd_context->mpr_row_store_scratch_buffer.bo);
 815     bo = dri_bo_alloc(i965->intel.bufmgr,
 816                       "mpr row store",
 817                       width_in_mbs * 64 * 2,
 818                       0x1000);
 819     assert(bo);
 820     gen7_mfd_context->mpr_row_store_scratch_buffer.bo = bo;
 821     gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 1;
 822
 823     gen7_mfd_context->bitplane_read_buffer.valid = 0;
 824 }
 825
 826 static void
 827 gen7_mfd_avc_decode_picture(VADriverContextP ctx,
 828                             struct decode_state *decode_state,
 829                             struct gen7_mfd_context *gen7_mfd_context)
 830 {
 831     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 832     VAPictureParameterBufferH264 *pic_param;
 833     VASliceParameterBufferH264 *slice_param, *next_slice_param, *next_slice_group_param;
 834     dri_bo *slice_data_bo;
 835     int i, j;
 836
 837     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 838     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 839     gen7_mfd_avc_decode_init(ctx, decode_state, gen7_mfd_context);
 840
 841     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
 842     intel_batchbuffer_emit_mi_flush(batch);
 843     gen7_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
 844     gen7_mfd_surface_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
 845     gen7_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
 846     gen7_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
 847     gen7_mfd_avc_qm_state(ctx, decode_state, gen7_mfd_context);
 848     gen7_mfd_avc_img_state(ctx, decode_state, gen7_mfd_context);
 849
 850     for (j = 0; j < decode_state->num_slice_params; j++) {
 851         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
 852         slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
 853         slice_data_bo = decode_state->slice_datas[j]->bo;
 854         gen7_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_AVC, gen7_mfd_context);
 855
 856         if (j == decode_state->num_slice_params - 1)
 857             next_slice_group_param = NULL;
 858         else
 859             next_slice_group_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j + 1]->buffer;
 860
 861         if (j == 0 && slice_param->first_mb_in_slice)
 862             gen7_mfd_avc_phantom_slice_first(ctx, pic_param, slice_param, gen7_mfd_context);
 863
 864         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
 865             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
 866             assert((slice_param->slice_type == SLICE_TYPE_I) ||
 867                    (slice_param->slice_type == SLICE_TYPE_SI) ||
 868                    (slice_param->slice_type == SLICE_TYPE_P) ||
 869                    (slice_param->slice_type == SLICE_TYPE_SP) ||
 870                    (slice_param->slice_type == SLICE_TYPE_B));
 871
 872             if (i < decode_state->slice_params[j]->num_elements - 1)
 873                 next_slice_param = slice_param + 1;
 874             else
 875                 next_slice_param = next_slice_group_param;
 876
 877             gen7_mfd_avc_directmode_state(ctx, decode_state, pic_param, slice_param, gen7_mfd_context);
 878             gen7_mfd_avc_ref_idx_state(ctx, pic_param, slice_param, gen7_mfd_context);
 879             gen7_mfd_avc_weightoffset_state(ctx, pic_param, slice_param, gen7_mfd_context);
 880             gen7_mfd_avc_slice_state(ctx, pic_param, slice_param, next_slice_param, gen7_mfd_context);
 881             gen7_mfd_avc_bsd_object(ctx, pic_param, slice_param, slice_data_bo, next_slice_param, gen7_mfd_context);
 882             slice_param++;
 883         }
 884     }
 885
 886     intel_batchbuffer_end_atomic(batch);
 887     intel_batchbuffer_flush(batch);
 888 }
 889
 890 static void
 891 gen7_mfd_mpeg2_decode_init(VADriverContextP ctx,
 892                            struct decode_state *decode_state,
 893                            struct gen7_mfd_context *gen7_mfd_context)
 894 {
 895     VAPictureParameterBufferMPEG2 *pic_param;
 896     struct i965_driver_data *i965 = i965_driver_data(ctx);
 897     struct object_surface *obj_surface;
 898     dri_bo *bo;
 899     unsigned int width_in_mbs;
 900
 901     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 902     pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
 903     width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16;
 904
 905     mpeg2_set_reference_surfaces(
 906         ctx,
 907         gen7_mfd_context->reference_surface,
 908         decode_state,
 909         pic_param
 910     );
 911
 912     /* Current decoded picture */
 913     obj_surface = decode_state->render_object;
 914     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
 915
 916     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
 917     gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
 918     dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
 919     gen7_mfd_context->pre_deblocking_output.valid = 1;
 920
 921     dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
 922     bo = dri_bo_alloc(i965->intel.bufmgr,
 923                       "bsd mpc row store",
 924                       width_in_mbs * 96,
 925                       0x1000);
 926     assert(bo);
 927     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
 928     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
 929
 930     gen7_mfd_context->post_deblocking_output.valid = 0;
 931     gen7_mfd_context->intra_row_store_scratch_buffer.valid = 0;
 932     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 0;
 933     gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
 934     gen7_mfd_context->bitplane_read_buffer.valid = 0;
 935 }
 936
 937 static void
 938 gen7_mfd_mpeg2_pic_state(VADriverContextP ctx,
 939                          struct decode_state *decode_state,
 940                          struct gen7_mfd_context *gen7_mfd_context)
 941 {
 942     struct i965_driver_data * const i965 = i965_driver_data(ctx);
 943     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 944     VAPictureParameterBufferMPEG2 *pic_param;
 945     unsigned int slice_concealment_disable_bit = 0;
 946
 947     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 948     pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
 949
 950     if (IS_HASWELL(i965->intel.device_info)) {
 951         /* XXX: disable concealment for now */
 952         slice_concealment_disable_bit = 1;
 953     }
 954
 955     BEGIN_BCS_BATCH(batch, 13);
 956     OUT_BCS_BATCH(batch, MFX_MPEG2_PIC_STATE | (13 - 2));
 957     OUT_BCS_BATCH(batch,
 958                   (pic_param->f_code & 0xf) << 28 | /* f_code[1][1] */
 959                   ((pic_param->f_code >> 4) & 0xf) << 24 | /* f_code[1][0] */
 960                   ((pic_param->f_code >> 8) & 0xf) << 20 | /* f_code[0][1] */
 961                   ((pic_param->f_code >> 12) & 0xf) << 16 | /* f_code[0][0] */
 962                   pic_param->picture_coding_extension.bits.intra_dc_precision << 14 |
 963                   pic_param->picture_coding_extension.bits.picture_structure << 12 |
 964                   pic_param->picture_coding_extension.bits.top_field_first << 11 |
 965                   pic_param->picture_coding_extension.bits.frame_pred_frame_dct << 10 |
 966                   pic_param->picture_coding_extension.bits.concealment_motion_vectors << 9 |
 967                   pic_param->picture_coding_extension.bits.q_scale_type << 8 |
 968                   pic_param->picture_coding_extension.bits.intra_vlc_format << 7 |
 969                   pic_param->picture_coding_extension.bits.alternate_scan << 6);
 970     OUT_BCS_BATCH(batch,
 971                   pic_param->picture_coding_type << 9);
 972     OUT_BCS_BATCH(batch,
 973                   (slice_concealment_disable_bit << 31) |
 974                   ((ALIGN(pic_param->vertical_size, 16) / 16) - 1) << 16 |
 975                   ((ALIGN(pic_param->horizontal_size, 16) / 16) - 1));
 976     OUT_BCS_BATCH(batch, 0);
 977     OUT_BCS_BATCH(batch, 0);
 978     OUT_BCS_BATCH(batch, 0);
 979     OUT_BCS_BATCH(batch, 0);
 980     OUT_BCS_BATCH(batch, 0);
 981     OUT_BCS_BATCH(batch, 0);
 982     OUT_BCS_BATCH(batch, 0);
 983     OUT_BCS_BATCH(batch, 0);
 984     OUT_BCS_BATCH(batch, 0);
 985     ADVANCE_BCS_BATCH(batch);
 986 }
 987
 988 static void
 989 gen7_mfd_mpeg2_qm_state(VADriverContextP ctx,
 990                         struct decode_state *decode_state,
 991                         struct gen7_mfd_context *gen7_mfd_context)
 992 {
 993     VAIQMatrixBufferMPEG2 * const gen_iq_matrix = &gen7_mfd_context->iq_matrix.mpeg2;
 994     int i, j;
 995
 996     /* Update internal QM state */
 997     if (decode_state->iq_matrix && decode_state->iq_matrix->buffer) {
 998         VAIQMatrixBufferMPEG2 * const iq_matrix =
 999             (VAIQMatrixBufferMPEG2 *)decode_state->iq_matrix->buffer;
1000
1001         if (gen_iq_matrix->load_intra_quantiser_matrix == -1 ||
1002             iq_matrix->load_intra_quantiser_matrix) {
1003             gen_iq_matrix->load_intra_quantiser_matrix =
1004                 iq_matrix->load_intra_quantiser_matrix;
1005             if (iq_matrix->load_intra_quantiser_matrix) {
1006                 for (j = 0; j < 64; j++)
1007                     gen_iq_matrix->intra_quantiser_matrix[zigzag_direct[j]] =
1008                         iq_matrix->intra_quantiser_matrix[j];
1009             }
1010         }
1011
1012         if (gen_iq_matrix->load_non_intra_quantiser_matrix == -1 ||
1013             iq_matrix->load_non_intra_quantiser_matrix) {
1014             gen_iq_matrix->load_non_intra_quantiser_matrix =
1015                 iq_matrix->load_non_intra_quantiser_matrix;
1016             if (iq_matrix->load_non_intra_quantiser_matrix) {
1017                 for (j = 0; j < 64; j++)
1018                     gen_iq_matrix->non_intra_quantiser_matrix[zigzag_direct[j]] =
1019                         iq_matrix->non_intra_quantiser_matrix[j];
1020             }
1021         }
1022     }
1023
1024     /* Commit QM state to HW */
1025     for (i = 0; i < 2; i++) {
1026         unsigned char *qm = NULL;
1027         int qm_type;
1028
1029         if (i == 0) {
1030             if (gen_iq_matrix->load_intra_quantiser_matrix) {
1031                 qm = gen_iq_matrix->intra_quantiser_matrix;
1032                 qm_type = MFX_QM_MPEG_INTRA_QUANTIZER_MATRIX;
1033             }
1034         } else {
1035             if (gen_iq_matrix->load_non_intra_quantiser_matrix) {
1036                 qm = gen_iq_matrix->non_intra_quantiser_matrix;
1037                 qm_type = MFX_QM_MPEG_NON_INTRA_QUANTIZER_MATRIX;
1038             }
1039         }
1040
1041         if (!qm)
1042             continue;
1043
1044         gen7_mfd_qm_state(ctx, qm_type, qm, 64, gen7_mfd_context);
1045     }
1046 }
1047
1048 uint32_t mpeg2_get_slice_data_length(dri_bo *slice_data_bo, VASliceParameterBufferMPEG2 *slice_param)
1049 {
1050     uint8_t *buf;
1051     uint32_t buf_offset = slice_param->slice_data_offset + (slice_param->macroblock_offset >> 3);
1052     uint32_t buf_size = slice_param->slice_data_size - (slice_param->macroblock_offset >> 3);
1053     uint32_t i = 0;
1054
1055     dri_bo_map(slice_data_bo, 0);
1056     buf = (uint8_t *)slice_data_bo->virtual + buf_offset;
1057
1058     if (buf_size < 4)
1059       return buf_size;
1060
1061     while (i <= (buf_size - 4)) {
1062       if (buf[i + 2] > 1) {
1063         i += 3;
1064       } else if (buf[i + 1]) {
1065         i += 2;
1066       } else if (buf[i] || buf[i + 2] != 1) {
1067         i++;
1068       } else {
1069         break;
1070       }
1071     }
1072
1073     if (i <= (buf_size - 4))
1074       buf_size = i;
1075
1076     dri_bo_unmap(slice_data_bo);
1077     return buf_size;
1078 }
1079
1080 static void
1081 gen7_mfd_mpeg2_bsd_object(VADriverContextP ctx,
1082                           VAPictureParameterBufferMPEG2 *pic_param,
1083                           VASliceParameterBufferMPEG2 *slice_param,
1084                           dri_bo *slice_data_bo,
1085                           VASliceParameterBufferMPEG2 *next_slice_param,
1086                           struct gen7_mfd_context *gen7_mfd_context)
1087 {
1088     struct i965_driver_data * const i965 = i965_driver_data(ctx);
1089     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1090     unsigned int width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16;
1091     int mb_count, vpos0, hpos0, vpos1, hpos1, is_field_pic_wa, is_field_pic = 0;
1092
1093     if (pic_param->picture_coding_extension.bits.picture_structure == MPEG_TOP_FIELD ||
1094         pic_param->picture_coding_extension.bits.picture_structure == MPEG_BOTTOM_FIELD)
1095         is_field_pic = 1;
1096     is_field_pic_wa = is_field_pic &&
1097         gen7_mfd_context->wa_mpeg2_slice_vertical_position > 0;
1098
1099     vpos0 = slice_param->slice_vertical_position / (1 + is_field_pic_wa);
1100     hpos0 = slice_param->slice_horizontal_position;
1101
1102     if (next_slice_param == NULL) {
1103         vpos1 = ALIGN(pic_param->vertical_size, 16) / 16 / (1 + is_field_pic);
1104         hpos1 = 0;
1105     } else {
1106         vpos1 = next_slice_param->slice_vertical_position / (1 + is_field_pic_wa);
1107         hpos1 = next_slice_param->slice_horizontal_position;
1108     }
1109
1110     mb_count = (vpos1 * width_in_mbs + hpos1) - (vpos0 * width_in_mbs + hpos0);
1111
1112     BEGIN_BCS_BATCH(batch, 5);
1113     OUT_BCS_BATCH(batch, MFD_MPEG2_BSD_OBJECT | (5 - 2));
1114     OUT_BCS_BATCH(batch,
1115                   mpeg2_get_slice_data_length(slice_data_bo, slice_param));
1116     OUT_BCS_BATCH(batch,
1117                   slice_param->slice_data_offset + (slice_param->macroblock_offset >> 3));
1118     OUT_BCS_BATCH(batch,
1119                   hpos0 << 24 |
1120                   vpos0 << 16 |
1121                   mb_count << 8 |
1122                   (next_slice_param == NULL) << 5 |
1123                   (next_slice_param == NULL) << 3 |
1124                   (slice_param->macroblock_offset & 0x7));
1125     OUT_BCS_BATCH(batch,
1126                   (slice_param->quantiser_scale_code << 24) |
1127                   (IS_HASWELL(i965->intel.device_info) ? (vpos1 << 8 | hpos1) : 0));
1128     ADVANCE_BCS_BATCH(batch);
1129 }
1130
1131 static void
1132 gen7_mfd_mpeg2_decode_picture(VADriverContextP ctx,
1133                               struct decode_state *decode_state,
1134                               struct gen7_mfd_context *gen7_mfd_context)
1135 {
1136     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1137     VAPictureParameterBufferMPEG2 *pic_param;
1138     VASliceParameterBufferMPEG2 *slice_param, *next_slice_param, *next_slice_group_param;
1139     dri_bo *slice_data_bo;
1140     int i, j;
1141
1142     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1143     pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
1144
1145     gen7_mfd_mpeg2_decode_init(ctx, decode_state, gen7_mfd_context);
1146     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
1147     intel_batchbuffer_emit_mi_flush(batch);
1148     gen7_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1149     gen7_mfd_surface_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1150     gen7_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1151     gen7_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1152     gen7_mfd_mpeg2_pic_state(ctx, decode_state, gen7_mfd_context);
1153     gen7_mfd_mpeg2_qm_state(ctx, decode_state, gen7_mfd_context);
1154
1155     if (gen7_mfd_context->wa_mpeg2_slice_vertical_position < 0)
1156         gen7_mfd_context->wa_mpeg2_slice_vertical_position =
1157             mpeg2_wa_slice_vertical_position(decode_state, pic_param);
1158
1159     for (j = 0; j < decode_state->num_slice_params; j++) {
1160         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
1161         slice_param = (VASliceParameterBufferMPEG2 *)decode_state->slice_params[j]->buffer;
1162         slice_data_bo = decode_state->slice_datas[j]->bo;
1163         gen7_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_MPEG2, gen7_mfd_context);
1164
1165         if (j == decode_state->num_slice_params - 1)
1166             next_slice_group_param = NULL;
1167         else
1168             next_slice_group_param = (VASliceParameterBufferMPEG2 *)decode_state->slice_params[j + 1]->buffer;
1169
1170         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
1171             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
1172
1173             if (i < decode_state->slice_params[j]->num_elements - 1)
1174                 next_slice_param = slice_param + 1;
1175             else
1176                 next_slice_param = next_slice_group_param;
1177
1178             gen7_mfd_mpeg2_bsd_object(ctx, pic_param, slice_param, slice_data_bo, next_slice_param, gen7_mfd_context);
1179             slice_param++;
1180         }
1181     }
1182
1183     intel_batchbuffer_end_atomic(batch);
1184     intel_batchbuffer_flush(batch);
1185 }
1186
1187 static const int va_to_gen7_vc1_pic_type[5] = {
1188     GEN7_VC1_I_PICTURE,
1189     GEN7_VC1_P_PICTURE,
1190     GEN7_VC1_B_PICTURE,
1191     GEN7_VC1_BI_PICTURE,
1192     GEN7_VC1_P_PICTURE,
1193 };
1194
1195 static const int va_to_gen7_vc1_mv[4] = {
1196     1, /* 1-MV */
1197     2, /* 1-MV half-pel */
1198     3, /* 1-MV half-pef bilinear */
1199     0, /* Mixed MV */
1200 };
1201
1202 static const int b_picture_scale_factor[21] = {
1203     128, 85,  170, 64,  192,
1204     51,  102, 153, 204, 43,
1205     215, 37,  74,  111, 148,
1206     185, 222, 32,  96,  160,
1207     224,
1208 };
1209
1210 static const int va_to_gen7_vc1_condover[3] = {
1211     0,
1212     2,
1213     3
1214 };
1215
1216 static const int va_to_gen7_vc1_profile[4] = {
1217     GEN7_VC1_SIMPLE_PROFILE,
1218     GEN7_VC1_MAIN_PROFILE,
1219     GEN7_VC1_RESERVED_PROFILE,
1220     GEN7_VC1_ADVANCED_PROFILE
1221 };
1222
1223 static void
1224 gen7_mfd_free_vc1_surface(void **data)
1225 {
1226     struct gen7_vc1_surface *gen7_vc1_surface = *data;
1227
1228     if (!gen7_vc1_surface)
1229         return;
1230
1231     dri_bo_unreference(gen7_vc1_surface->dmv);
1232     free(gen7_vc1_surface);
1233     *data = NULL;
1234 }
1235
1236 static void
1237 gen7_mfd_init_vc1_surface(VADriverContextP ctx,
1238                           VAPictureParameterBufferVC1 *pic_param,
1239                           struct object_surface *obj_surface)
1240 {
1241     struct i965_driver_data *i965 = i965_driver_data(ctx);
1242     struct gen7_vc1_surface *gen7_vc1_surface = obj_surface->private_data;
1243     int width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1244     int height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16;
1245
1246     obj_surface->free_private_data = gen7_mfd_free_vc1_surface;
1247
1248     if (!gen7_vc1_surface) {
1249         gen7_vc1_surface = calloc(sizeof(struct gen7_vc1_surface), 1);
1250         assert(gen7_vc1_surface);
1251         assert((obj_surface->size & 0x3f) == 0);
1252         obj_surface->private_data = gen7_vc1_surface;
1253     }
1254
1255     gen7_vc1_surface->picture_type = pic_param->picture_fields.bits.picture_type;
1256
1257     if (gen7_vc1_surface->dmv == NULL) {
1258         gen7_vc1_surface->dmv = dri_bo_alloc(i965->intel.bufmgr,
1259                                              "direct mv w/r buffer",
1260                                              width_in_mbs * height_in_mbs * 64,
1261                                              0x1000);
1262     }
1263 }
1264
1265 static void
1266 gen7_mfd_vc1_decode_init(VADriverContextP ctx,
1267                          struct decode_state *decode_state,
1268                          struct gen7_mfd_context *gen7_mfd_context)
1269 {
1270     VAPictureParameterBufferVC1 *pic_param;
1271     struct i965_driver_data *i965 = i965_driver_data(ctx);
1272     struct object_surface *obj_surface;
1273     dri_bo *bo;
1274     int width_in_mbs;
1275     int picture_type;
1276
1277     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1278     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1279     width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1280     picture_type = pic_param->picture_fields.bits.picture_type;
1281
1282     intel_update_vc1_frame_store_index(ctx,
1283                                        decode_state,
1284                                        pic_param,
1285                                        gen7_mfd_context->reference_surface);
1286
1287     /* Current decoded picture */
1288     obj_surface = decode_state->render_object;
1289     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
1290     gen7_mfd_init_vc1_surface(ctx, pic_param, obj_surface);
1291
1292     dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo);
1293     gen7_mfd_context->post_deblocking_output.bo = obj_surface->bo;
1294     dri_bo_reference(gen7_mfd_context->post_deblocking_output.bo);
1295     gen7_mfd_context->post_deblocking_output.valid = pic_param->entrypoint_fields.bits.loopfilter;
1296
1297     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
1298     gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
1299     dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
1300     gen7_mfd_context->pre_deblocking_output.valid = !pic_param->entrypoint_fields.bits.loopfilter;
1301
1302     dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo);
1303     bo = dri_bo_alloc(i965->intel.bufmgr,
1304                       "intra row store",
1305                       width_in_mbs * 64,
1306                       0x1000);
1307     assert(bo);
1308     gen7_mfd_context->intra_row_store_scratch_buffer.bo = bo;
1309     gen7_mfd_context->intra_row_store_scratch_buffer.valid = 1;
1310
1311     dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
1312     bo = dri_bo_alloc(i965->intel.bufmgr,
1313                       "deblocking filter row store",
1314                       width_in_mbs * 7 * 64,
1315                       0x1000);
1316     assert(bo);
1317     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
1318     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1;
1319
1320     dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
1321     bo = dri_bo_alloc(i965->intel.bufmgr,
1322                       "bsd mpc row store",
1323                       width_in_mbs * 96,
1324                       0x1000);
1325     assert(bo);
1326     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
1327     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
1328
1329     gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
1330
1331     gen7_mfd_context->bitplane_read_buffer.valid = !!pic_param->bitplane_present.value;
1332     dri_bo_unreference(gen7_mfd_context->bitplane_read_buffer.bo);
1333
1334     if (gen7_mfd_context->bitplane_read_buffer.valid) {
1335         int width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1336         int height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16;
1337         int bitplane_width = ALIGN(width_in_mbs, 2) / 2;
1338         int src_w, src_h;
1339         uint8_t *src = NULL, *dst = NULL;
1340
1341         assert(decode_state->bit_plane->buffer);
1342         src = decode_state->bit_plane->buffer;
1343
1344         bo = dri_bo_alloc(i965->intel.bufmgr,
1345                           "VC-1 Bitplane",
1346                           bitplane_width * height_in_mbs,
1347                           0x1000);
1348         assert(bo);
1349         gen7_mfd_context->bitplane_read_buffer.bo = bo;
1350
1351         dri_bo_map(bo, True);
1352         assert(bo->virtual);
1353         dst = bo->virtual;
1354
1355         for (src_h = 0; src_h < height_in_mbs; src_h++) {
1356             for(src_w = 0; src_w < width_in_mbs; src_w++) {
1357                 int src_index, dst_index;
1358                 int src_shift;
1359                 uint8_t src_value;
1360
1361                 src_index = (src_h * width_in_mbs + src_w) / 2;
1362                 src_shift = !((src_h * width_in_mbs + src_w) & 1) * 4;
1363                 src_value = ((src[src_index] >> src_shift) & 0xf);
1364
1365                 if (picture_type == GEN7_VC1_SKIPPED_PICTURE){
1366                     src_value |= 0x2;
1367                 }
1368
1369                 dst_index = src_w / 2;
1370                 dst[dst_index] = ((dst[dst_index] >> 4) | (src_value << 4));
1371             }
1372
1373             if (src_w & 1)
1374                 dst[src_w / 2] >>= 4;
1375
1376             dst += bitplane_width;
1377         }
1378
1379         dri_bo_unmap(bo);
1380     } else
1381         gen7_mfd_context->bitplane_read_buffer.bo = NULL;
1382 }
1383
1384 static void
1385 gen7_mfd_vc1_pic_state(VADriverContextP ctx,
1386                        struct decode_state *decode_state,
1387                        struct gen7_mfd_context *gen7_mfd_context)
1388 {
1389     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1390     VAPictureParameterBufferVC1 *pic_param;
1391     struct object_surface *obj_surface;
1392     int alt_pquant_config = 0, alt_pquant_edge_mask = 0, alt_pq;
1393     int dquant, dquantfrm, dqprofile, dqdbedge, dqsbedge, dqbilevel;
1394     int unified_mv_mode;
1395     int ref_field_pic_polarity = 0;
1396     int scale_factor = 0;
1397     int trans_ac_y = 0;
1398     int dmv_surface_valid = 0;
1399     int brfd = 0;
1400     int fcm = 0;
1401     int picture_type;
1402     int profile;
1403     int overlap;
1404     int interpolation_mode = 0;
1405
1406     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1407     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1408
1409     profile = va_to_gen7_vc1_profile[pic_param->sequence_fields.bits.profile];
1410     dquant = pic_param->pic_quantizer_fields.bits.dquant;
1411     dquantfrm = pic_param->pic_quantizer_fields.bits.dq_frame;
1412     dqprofile = pic_param->pic_quantizer_fields.bits.dq_profile;
1413     dqdbedge = pic_param->pic_quantizer_fields.bits.dq_db_edge;
1414     dqsbedge = pic_param->pic_quantizer_fields.bits.dq_sb_edge;
1415     dqbilevel = pic_param->pic_quantizer_fields.bits.dq_binary_level;
1416     alt_pq = pic_param->pic_quantizer_fields.bits.alt_pic_quantizer;
1417
1418     if (dquant == 0) {
1419         alt_pquant_config = 0;
1420         alt_pquant_edge_mask = 0;
1421     } else if (dquant == 2) {
1422         alt_pquant_config = 1;
1423         alt_pquant_edge_mask = 0xf;
1424     } else {
1425         assert(dquant == 1);
1426         if (dquantfrm == 0) {
1427             alt_pquant_config = 0;
1428             alt_pquant_edge_mask = 0;
1429             alt_pq = 0;
1430         } else {
1431             assert(dquantfrm == 1);
1432             alt_pquant_config = 1;
1433
1434             switch (dqprofile) {
1435             case 3:
1436                 if (dqbilevel == 0) {
1437                     alt_pquant_config = 2;
1438                     alt_pquant_edge_mask = 0;
1439                 } else {
1440                     assert(dqbilevel == 1);
1441                     alt_pquant_config = 3;
1442                     alt_pquant_edge_mask = 0;
1443                 }
1444                 break;
1445
1446             case 0:
1447                 alt_pquant_edge_mask = 0xf;
1448                 break;
1449
1450             case 1:
1451                 if (dqdbedge == 3)
1452                     alt_pquant_edge_mask = 0x9;
1453                 else
1454                     alt_pquant_edge_mask = (0x3 << dqdbedge);
1455
1456                 break;
1457
1458             case 2:
1459                 alt_pquant_edge_mask = (0x1 << dqsbedge);
1460                 break;
1461
1462             default:
1463                 assert(0);
1464             }
1465         }
1466     }
1467
1468     if (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation) {
1469         assert(pic_param->mv_fields.bits.mv_mode2 < 4);
1470         unified_mv_mode = va_to_gen7_vc1_mv[pic_param->mv_fields.bits.mv_mode2];
1471     } else {
1472         assert(pic_param->mv_fields.bits.mv_mode < 4);
1473         unified_mv_mode = va_to_gen7_vc1_mv[pic_param->mv_fields.bits.mv_mode];
1474     }
1475
1476     if (pic_param->sequence_fields.bits.interlace == 1 &&
1477         pic_param->picture_fields.bits.frame_coding_mode != 0) { /* frame-interlace or field-interlace */
1478         /* FIXME: calculate reference field picture polarity */
1479         assert(0);
1480         ref_field_pic_polarity = 0;
1481     }
1482
1483     if (pic_param->b_picture_fraction < 21)
1484         scale_factor = b_picture_scale_factor[pic_param->b_picture_fraction];
1485
1486     picture_type = va_to_gen7_vc1_pic_type[pic_param->picture_fields.bits.picture_type];
1487
1488     if (profile == GEN7_VC1_ADVANCED_PROFILE &&
1489         picture_type == GEN7_VC1_I_PICTURE)
1490         picture_type = GEN7_VC1_BI_PICTURE;
1491
1492     if (picture_type == GEN7_VC1_I_PICTURE || picture_type == GEN7_VC1_BI_PICTURE) /* I picture */
1493         trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx2;
1494     else {
1495         trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx1;
1496         /*
1497          * 8.3.6.2.1 Transform Type Selection
1498          * If variable-sized transform coding is not enabled,
1499          * then the 8x8 transform shall be used for all blocks.
1500          * it is also MFX_VC1_PIC_STATE requirement.
1501          */
1502         if (pic_param->transform_fields.bits.variable_sized_transform_flag == 0) {
1503             pic_param->transform_fields.bits.mb_level_transform_type_flag   = 1;
1504             pic_param->transform_fields.bits.frame_level_transform_type     = 0;
1505         }
1506     }
1507
1508
1509     if (picture_type == GEN7_VC1_B_PICTURE) {
1510         struct gen7_vc1_surface *gen7_vc1_surface = NULL;
1511
1512         obj_surface = decode_state->reference_objects[1];
1513
1514         if (obj_surface)
1515             gen7_vc1_surface = obj_surface->private_data;
1516
1517         if (!gen7_vc1_surface ||
1518             (va_to_gen7_vc1_pic_type[gen7_vc1_surface->picture_type] == GEN7_VC1_I_PICTURE ||
1519              va_to_gen7_vc1_pic_type[gen7_vc1_surface->picture_type] == GEN7_VC1_BI_PICTURE))
1520             dmv_surface_valid = 0;
1521         else
1522             dmv_surface_valid = 1;
1523     }
1524
1525     assert(pic_param->picture_fields.bits.frame_coding_mode < 3);
1526
1527     if (pic_param->picture_fields.bits.frame_coding_mode < 2)
1528         fcm = pic_param->picture_fields.bits.frame_coding_mode;
1529     else {
1530         if (pic_param->picture_fields.bits.top_field_first)
1531             fcm = 2;
1532         else
1533             fcm = 3;
1534     }
1535
1536     if (pic_param->picture_fields.bits.picture_type == GEN7_VC1_B_PICTURE) { /* B picture */
1537         brfd = pic_param->reference_fields.bits.reference_distance;
1538         brfd = (scale_factor * brfd) >> 8;
1539         brfd = pic_param->reference_fields.bits.reference_distance - brfd - 1;
1540
1541         if (brfd < 0)
1542             brfd = 0;
1543     }
1544
1545     overlap = pic_param->sequence_fields.bits.overlap;
1546
1547     if (overlap) {
1548         overlap = 0;
1549         if (profile != GEN7_VC1_ADVANCED_PROFILE) {
1550             if (pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9 &&
1551                 pic_param->picture_fields.bits.picture_type != GEN7_VC1_B_PICTURE) {
1552                 overlap = 1;
1553             }
1554         }else {
1555             if (pic_param->picture_fields.bits.picture_type == GEN7_VC1_P_PICTURE &&
1556                 pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9){
1557                 overlap = 1;
1558             }
1559             if (pic_param->picture_fields.bits.picture_type == GEN7_VC1_I_PICTURE ||
1560                 pic_param->picture_fields.bits.picture_type == GEN7_VC1_BI_PICTURE){
1561                 if (pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9){
1562                     overlap = 1;
1563                 } else if (va_to_gen7_vc1_condover[pic_param->conditional_overlap_flag] == 2 ||
1564                            va_to_gen7_vc1_condover[pic_param->conditional_overlap_flag] == 3) {
1565                     overlap = 1;
1566                 }
1567             }
1568         }
1569     }
1570
1571     assert(pic_param->conditional_overlap_flag < 3);
1572     assert(pic_param->mv_fields.bits.mv_table < 4); /* FIXME: interlace mode */
1573
1574     if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPelBilinear ||
1575         (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation &&
1576          pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPelBilinear))
1577         interpolation_mode = 9; /* Half-pel bilinear */
1578     else if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPel ||
1579              (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation &&
1580               pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPel))
1581         interpolation_mode = 1; /* Half-pel bicubic */
1582     else
1583         interpolation_mode = 0; /* Quarter-pel bicubic */
1584
1585     BEGIN_BCS_BATCH(batch, 6);
1586     OUT_BCS_BATCH(batch, MFD_VC1_LONG_PIC_STATE | (6 - 2));
1587     OUT_BCS_BATCH(batch,
1588                   (((ALIGN(pic_param->coded_height, 16) / 16) - 1) << 16) |
1589                   ((ALIGN(pic_param->coded_width, 16) / 16) - 1));
1590     OUT_BCS_BATCH(batch,
1591                   ((ALIGN(pic_param->coded_width, 16) / 16 + 1) / 2 - 1) << 24 |
1592                   dmv_surface_valid << 15 |
1593                   (pic_param->pic_quantizer_fields.bits.quantizer == 0) << 14 | /* implicit quantizer */
1594                   pic_param->rounding_control << 13 |
1595                   pic_param->sequence_fields.bits.syncmarker << 12 |
1596                   interpolation_mode << 8 |
1597                   0 << 7 | /* FIXME: scale up or down ??? */
1598                   pic_param->range_reduction_frame << 6 |
1599                   pic_param->entrypoint_fields.bits.loopfilter << 5 |
1600                   overlap << 4 |
1601                   !pic_param->picture_fields.bits.is_first_field << 3 |
1602                   (pic_param->sequence_fields.bits.profile == 3) << 0);
1603     OUT_BCS_BATCH(batch,
1604                   va_to_gen7_vc1_condover[pic_param->conditional_overlap_flag] << 29 |
1605                   picture_type << 26 |
1606                   fcm << 24 |
1607                   alt_pq << 16 |
1608                   pic_param->pic_quantizer_fields.bits.pic_quantizer_scale << 8 |
1609                   scale_factor << 0);
1610     OUT_BCS_BATCH(batch,
1611                   unified_mv_mode << 28 |
1612                   pic_param->mv_fields.bits.four_mv_switch << 27 |
1613                   pic_param->fast_uvmc_flag << 26 |
1614                   ref_field_pic_polarity << 25 |
1615                   pic_param->reference_fields.bits.num_reference_pictures << 24 |
1616                   pic_param->reference_fields.bits.reference_distance << 20 |
1617                   pic_param->reference_fields.bits.reference_distance << 16 | /* FIXME: ??? */
1618                   pic_param->mv_fields.bits.extended_dmv_range << 10 |
1619                   pic_param->mv_fields.bits.extended_mv_range << 8 |
1620                   alt_pquant_edge_mask << 4 |
1621                   alt_pquant_config << 2 |
1622                   pic_param->pic_quantizer_fields.bits.half_qp << 1 |
1623                   pic_param->pic_quantizer_fields.bits.pic_quantizer_type << 0);
1624     OUT_BCS_BATCH(batch,
1625                   !!pic_param->bitplane_present.value << 31 |
1626                   !pic_param->bitplane_present.flags.bp_forward_mb << 30 |
1627                   !pic_param->bitplane_present.flags.bp_mv_type_mb << 29 |
1628                   !pic_param->bitplane_present.flags.bp_skip_mb << 28 |
1629                   !pic_param->bitplane_present.flags.bp_direct_mb << 27 |
1630                   !pic_param->bitplane_present.flags.bp_overflags << 26 |
1631                   !pic_param->bitplane_present.flags.bp_ac_pred << 25 |
1632                   !pic_param->bitplane_present.flags.bp_field_tx << 24 |
1633                   pic_param->mv_fields.bits.mv_table << 20 |
1634                   pic_param->mv_fields.bits.four_mv_block_pattern_table << 18 |
1635                   pic_param->mv_fields.bits.two_mv_block_pattern_table << 16 |
1636                   pic_param->transform_fields.bits.frame_level_transform_type << 12 |
1637                   pic_param->transform_fields.bits.mb_level_transform_type_flag << 11 |
1638                   pic_param->mb_mode_table << 8 |
1639                   trans_ac_y << 6 |
1640                   pic_param->transform_fields.bits.transform_ac_codingset_idx1 << 4 |
1641                   pic_param->transform_fields.bits.intra_transform_dc_table << 3 |
1642                   pic_param->cbp_table << 0);
1643     ADVANCE_BCS_BATCH(batch);
1644 }
1645
1646 static void
1647 gen7_mfd_vc1_pred_pipe_state(VADriverContextP ctx,
1648                              struct decode_state *decode_state,
1649                              struct gen7_mfd_context *gen7_mfd_context)
1650 {
1651     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1652     VAPictureParameterBufferVC1 *pic_param;
1653     int intensitycomp_single;
1654
1655     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1656     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1657     intensitycomp_single = (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation);
1658
1659     BEGIN_BCS_BATCH(batch, 6);
1660     OUT_BCS_BATCH(batch, MFX_VC1_PRED_PIPE_STATE | (6 - 2));
1661     OUT_BCS_BATCH(batch,
1662                   0 << 14 | /* FIXME: double ??? */
1663                   0 << 12 |
1664                   intensitycomp_single << 10 |
1665                   intensitycomp_single << 8 |
1666                   0 << 4 | /* FIXME: interlace mode */
1667                   0);
1668     OUT_BCS_BATCH(batch,
1669                   pic_param->luma_shift << 16 |
1670                   pic_param->luma_scale << 0); /* FIXME: Luma Scaling */
1671     OUT_BCS_BATCH(batch, 0);
1672     OUT_BCS_BATCH(batch, 0);
1673     OUT_BCS_BATCH(batch, 0);
1674     ADVANCE_BCS_BATCH(batch);
1675 }
1676
1677
1678 static void
1679 gen7_mfd_vc1_directmode_state(VADriverContextP ctx,
1680                               struct decode_state *decode_state,
1681                               struct gen7_mfd_context *gen7_mfd_context)
1682 {
1683     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1684     struct object_surface *obj_surface;
1685     dri_bo *dmv_read_buffer = NULL, *dmv_write_buffer = NULL;
1686
1687     obj_surface = decode_state->render_object;
1688
1689     if (obj_surface && obj_surface->private_data) {
1690         dmv_write_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv;
1691     }
1692
1693     obj_surface = decode_state->reference_objects[1];
1694
1695     if (obj_surface && obj_surface->private_data) {
1696         dmv_read_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv;
1697     }
1698
1699     BEGIN_BCS_BATCH(batch, 3);
1700     OUT_BCS_BATCH(batch, MFX_VC1_DIRECTMODE_STATE | (3 - 2));
1701
1702     if (dmv_write_buffer)
1703         OUT_BCS_RELOC(batch, dmv_write_buffer,
1704                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
1705                       0);
1706     else
1707         OUT_BCS_BATCH(batch, 0);
1708
1709     if (dmv_read_buffer)
1710         OUT_BCS_RELOC(batch, dmv_read_buffer,
1711                       I915_GEM_DOMAIN_INSTRUCTION, 0,
1712                       0);
1713     else
1714         OUT_BCS_BATCH(batch, 0);
1715
1716     ADVANCE_BCS_BATCH(batch);
1717 }
1718
1719 static int
1720 gen7_mfd_vc1_get_macroblock_bit_offset(uint8_t *buf, int in_slice_data_bit_offset, int profile)
1721 {
1722     int out_slice_data_bit_offset;
1723     int slice_header_size = in_slice_data_bit_offset / 8;
1724     int i, j;
1725
1726     if (profile != 3)
1727         out_slice_data_bit_offset = in_slice_data_bit_offset;
1728     else {
1729         for (i = 0, j = 0; i < slice_header_size; i++, j++) {
1730             if (!buf[j] && !buf[j + 1] && buf[j + 2] == 3 && buf[j + 3] < 4) {
1731                 i++, j += 2;
1732             }
1733         }
1734
1735         out_slice_data_bit_offset = 8 * j + in_slice_data_bit_offset % 8;
1736     }
1737
1738     return out_slice_data_bit_offset;
1739 }
1740
1741 static void
1742 gen7_mfd_vc1_bsd_object(VADriverContextP ctx,
1743                         VAPictureParameterBufferVC1 *pic_param,
1744                         VASliceParameterBufferVC1 *slice_param,
1745                         VASliceParameterBufferVC1 *next_slice_param,
1746                         dri_bo *slice_data_bo,
1747                         struct gen7_mfd_context *gen7_mfd_context)
1748 {
1749     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1750     int next_slice_start_vert_pos;
1751     int macroblock_offset;
1752     uint8_t *slice_data = NULL;
1753
1754     dri_bo_map(slice_data_bo, 0);
1755     slice_data = (uint8_t *)(slice_data_bo->virtual + slice_param->slice_data_offset);
1756     macroblock_offset = gen7_mfd_vc1_get_macroblock_bit_offset(slice_data,
1757                                                                slice_param->macroblock_offset,
1758                                                                pic_param->sequence_fields.bits.profile);
1759     dri_bo_unmap(slice_data_bo);
1760
1761     if (next_slice_param)
1762         next_slice_start_vert_pos = next_slice_param->slice_vertical_position;
1763     else
1764         next_slice_start_vert_pos = ALIGN(pic_param->coded_height, 16) / 16;
1765
1766     BEGIN_BCS_BATCH(batch, 5);
1767     OUT_BCS_BATCH(batch, MFD_VC1_BSD_OBJECT | (5 - 2));
1768     OUT_BCS_BATCH(batch,
1769                   slice_param->slice_data_size - (macroblock_offset >> 3));
1770     OUT_BCS_BATCH(batch,
1771                   slice_param->slice_data_offset + (macroblock_offset >> 3));
1772     OUT_BCS_BATCH(batch,
1773                   slice_param->slice_vertical_position << 16 |
1774                   next_slice_start_vert_pos << 0);
1775     OUT_BCS_BATCH(batch,
1776                   (macroblock_offset & 0x7));
1777     ADVANCE_BCS_BATCH(batch);
1778 }
1779
1780 static void
1781 gen7_mfd_vc1_decode_picture(VADriverContextP ctx,
1782                             struct decode_state *decode_state,
1783                             struct gen7_mfd_context *gen7_mfd_context)
1784 {
1785     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1786     VAPictureParameterBufferVC1 *pic_param;
1787     VASliceParameterBufferVC1 *slice_param, *next_slice_param, *next_slice_group_param;
1788     dri_bo *slice_data_bo;
1789     int i, j;
1790
1791     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1792     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1793
1794     gen7_mfd_vc1_decode_init(ctx, decode_state, gen7_mfd_context);
1795     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
1796     intel_batchbuffer_emit_mi_flush(batch);
1797     gen7_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
1798     gen7_mfd_surface_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
1799     gen7_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
1800     gen7_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
1801     gen7_mfd_vc1_pic_state(ctx, decode_state, gen7_mfd_context);
1802     gen7_mfd_vc1_pred_pipe_state(ctx, decode_state, gen7_mfd_context);
1803     gen7_mfd_vc1_directmode_state(ctx, decode_state, gen7_mfd_context);
1804
1805     for (j = 0; j < decode_state->num_slice_params; j++) {
1806         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
1807         slice_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j]->buffer;
1808         slice_data_bo = decode_state->slice_datas[j]->bo;
1809         gen7_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_VC1, gen7_mfd_context);
1810
1811         if (j == decode_state->num_slice_params - 1)
1812             next_slice_group_param = NULL;
1813         else
1814             next_slice_group_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j + 1]->buffer;
1815
1816         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
1817             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
1818
1819             if (i < decode_state->slice_params[j]->num_elements - 1)
1820                 next_slice_param = slice_param + 1;
1821             else
1822                 next_slice_param = next_slice_group_param;
1823
1824             gen7_mfd_vc1_bsd_object(ctx, pic_param, slice_param, next_slice_param, slice_data_bo, gen7_mfd_context);
1825             slice_param++;
1826         }
1827     }
1828
1829     intel_batchbuffer_end_atomic(batch);
1830     intel_batchbuffer_flush(batch);
1831 }
1832
1833 static void
1834 gen7_mfd_jpeg_decode_init(VADriverContextP ctx,
1835                           struct decode_state *decode_state,
1836                           struct gen7_mfd_context *gen7_mfd_context)
1837 {
1838     struct object_surface *obj_surface;
1839     VAPictureParameterBufferJPEGBaseline *pic_param;
1840     int subsampling = SUBSAMPLE_YUV420;
1841     int fourcc = VA_FOURCC_IMC3;
1842
1843     pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
1844
1845     if (pic_param->num_components == 1) {
1846         subsampling = SUBSAMPLE_YUV400;
1847         fourcc = VA_FOURCC_Y800;
1848     } else if (pic_param->num_components == 3) {
1849         int h1 = pic_param->components[0].h_sampling_factor;
1850         int h2 = pic_param->components[1].h_sampling_factor;
1851         int h3 = pic_param->components[2].h_sampling_factor;
1852         int v1 = pic_param->components[0].v_sampling_factor;
1853         int v2 = pic_param->components[1].v_sampling_factor;
1854         int v3 = pic_param->components[2].v_sampling_factor;
1855
1856         if (h1 == 2 && h2 == 1 && h3 == 1 &&
1857             v1 == 2 && v2 == 1 && v3 == 1) {
1858             subsampling = SUBSAMPLE_YUV420;
1859             fourcc = VA_FOURCC_IMC3;
1860         } else if (h1 == 2 && h2 == 1 && h3 == 1 &&
1861                    v1 == 1 && v2 == 1 && v3 == 1) {
1862             subsampling = SUBSAMPLE_YUV422H;
1863             fourcc = VA_FOURCC_422H;
1864         } else if (h1 == 1 && h2 == 1 && h3 == 1 &&
1865                    v1 == 1 && v2 == 1 && v3 == 1) {
1866             subsampling = SUBSAMPLE_YUV444;
1867             fourcc = VA_FOURCC_444P;
1868         } else if (h1 == 4 && h2 == 1 && h3 == 1 &&
1869                    v1 == 1 && v2 == 1 && v3 == 1) {
1870             subsampling = SUBSAMPLE_YUV411;
1871             fourcc = VA_FOURCC_411P;
1872         } else if (h1 == 1 && h2 == 1 && h3 == 1 &&
1873                    v1 == 2 && v2 == 1 && v3 == 1) {
1874             subsampling = SUBSAMPLE_YUV422V;
1875             fourcc = VA_FOURCC_422V;
1876         } else if (h1 == 2 && h2 == 1 && h3 == 1 &&
1877                    v1 == 2 && v2 == 2 && v3 == 2) {
1878             subsampling = SUBSAMPLE_YUV422H;
1879             fourcc = VA_FOURCC_422H;
1880         } else if (h1 == 2 && h2 == 2 && h3 == 2 &&
1881                    v1 == 2 && v2 == 1 && v3 == 1) {
1882             subsampling = SUBSAMPLE_YUV422V;
1883             fourcc = VA_FOURCC_422V;
1884         } else
1885             assert(0);
1886     } else {
1887         assert(0);
1888     }
1889
1890     /* Current decoded picture */
1891     obj_surface = decode_state->render_object;
1892     i965_check_alloc_surface_bo(ctx, obj_surface, 1, fourcc, subsampling);
1893
1894     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
1895     gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
1896     dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
1897     gen7_mfd_context->pre_deblocking_output.valid = 1;
1898
1899     gen7_mfd_context->post_deblocking_output.bo = NULL;
1900     gen7_mfd_context->post_deblocking_output.valid = 0;
1901
1902     gen7_mfd_context->intra_row_store_scratch_buffer.bo = NULL;
1903     gen7_mfd_context->intra_row_store_scratch_buffer.valid = 0;
1904
1905     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
1906     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 0;
1907
1908     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
1909     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 0;
1910
1911     gen7_mfd_context->mpr_row_store_scratch_buffer.bo = NULL;
1912     gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
1913
1914     gen7_mfd_context->bitplane_read_buffer.bo = NULL;
1915     gen7_mfd_context->bitplane_read_buffer.valid = 0;
1916 }
1917
1918 static const int va_to_gen7_jpeg_rotation[4] = {
1919     GEN7_JPEG_ROTATION_0,
1920     GEN7_JPEG_ROTATION_90,
1921     GEN7_JPEG_ROTATION_180,
1922     GEN7_JPEG_ROTATION_270
1923 };
1924
1925 static void
1926 gen7_mfd_jpeg_pic_state(VADriverContextP ctx,
1927                         struct decode_state *decode_state,
1928                         struct gen7_mfd_context *gen7_mfd_context)
1929 {
1930     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1931     VAPictureParameterBufferJPEGBaseline *pic_param;
1932     int chroma_type = GEN7_YUV420;
1933     int frame_width_in_blks;
1934     int frame_height_in_blks;
1935
1936     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1937     pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
1938
1939     if (pic_param->num_components == 1)
1940         chroma_type = GEN7_YUV400;
1941     else if (pic_param->num_components == 3) {
1942         int h1 = pic_param->components[0].h_sampling_factor;
1943         int h2 = pic_param->components[1].h_sampling_factor;
1944         int h3 = pic_param->components[2].h_sampling_factor;
1945         int v1 = pic_param->components[0].v_sampling_factor;
1946         int v2 = pic_param->components[1].v_sampling_factor;
1947         int v3 = pic_param->components[2].v_sampling_factor;
1948
1949         if (h1 == 2 && h2 == 1 && h3 == 1 &&
1950             v1 == 2 && v2 == 1 && v3 == 1)
1951             chroma_type = GEN7_YUV420;
1952         else if (h1 == 2 && h2 == 1 && h3 == 1 &&
1953                  v1 == 1 && v2 == 1 && v3 == 1)
1954             chroma_type = GEN7_YUV422H_2Y;
1955         else if (h1 == 1 && h2 == 1 && h3 == 1 &&
1956                  v1 == 1 && v2 == 1 && v3 == 1)
1957             chroma_type = GEN7_YUV444;
1958         else if (h1 == 4 && h2 == 1 && h3 == 1 &&
1959                  v1 == 1 && v2 == 1 && v3 == 1)
1960             chroma_type = GEN7_YUV411;
1961         else if (h1 == 1 && h2 == 1 && h3 == 1 &&
1962                  v1 == 2 && v2 == 1 && v3 == 1)
1963             chroma_type = GEN7_YUV422V_2Y;
1964         else if (h1 == 2 && h2 == 1 && h3 == 1 &&
1965                  v1 == 2 && v2 == 2 && v3 == 2)
1966             chroma_type = GEN7_YUV422H_4Y;
1967         else if (h2 == 2 && h2 == 2 && h3 == 2 &&
1968                  v1 == 2 && v2 == 1 && v3 == 1)
1969             chroma_type = GEN7_YUV422V_4Y;
1970         else
1971             assert(0);
1972     }
1973
1974     if (chroma_type == GEN7_YUV400 ||
1975         chroma_type == GEN7_YUV444 ||
1976         chroma_type == GEN7_YUV422V_2Y) {
1977         frame_width_in_blks = ((pic_param->picture_width + 7) / 8);
1978         frame_height_in_blks = ((pic_param->picture_height + 7) / 8);
1979     } else if (chroma_type == GEN7_YUV411) {
1980         frame_width_in_blks = ((pic_param->picture_width + 31) / 32) * 4;
1981         frame_height_in_blks = ((pic_param->picture_height + 31) / 32) * 4;
1982     } else {
1983         frame_width_in_blks = ((pic_param->picture_width + 15) / 16) * 2;
1984         frame_height_in_blks = ((pic_param->picture_height + 15) / 16) * 2;
1985     }
1986
1987     BEGIN_BCS_BATCH(batch, 3);
1988     OUT_BCS_BATCH(batch, MFX_JPEG_PIC_STATE | (3 - 2));
1989     OUT_BCS_BATCH(batch,
1990                   (va_to_gen7_jpeg_rotation[0] << 4) |    /* without rotation */
1991                   (chroma_type << 0));
1992     OUT_BCS_BATCH(batch,
1993                   ((frame_height_in_blks - 1) << 16) |   /* FrameHeightInBlks */
1994                   ((frame_width_in_blks - 1) << 0));    /* FrameWidthInBlks */
1995     ADVANCE_BCS_BATCH(batch);
1996 }
1997
1998 static const int va_to_gen7_jpeg_hufftable[2] = {
1999     MFX_HUFFTABLE_ID_Y,
2000     MFX_HUFFTABLE_ID_UV
2001 };
2002
2003 static void
2004 gen7_mfd_jpeg_huff_table_state(VADriverContextP ctx,
2005                                struct decode_state *decode_state,
2006                                struct gen7_mfd_context *gen7_mfd_context,
2007                                int num_tables)
2008 {
2009     VAHuffmanTableBufferJPEGBaseline *huffman_table;
2010     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2011     int index;
2012
2013     if (!decode_state->huffman_table || !decode_state->huffman_table->buffer)
2014         return;
2015
2016     huffman_table = (VAHuffmanTableBufferJPEGBaseline *)decode_state->huffman_table->buffer;
2017
2018     for (index = 0; index < num_tables; index++) {
2019         int id = va_to_gen7_jpeg_hufftable[index];
2020         if (!huffman_table->load_huffman_table[index])
2021             continue;
2022         BEGIN_BCS_BATCH(batch, 53);
2023         OUT_BCS_BATCH(batch, MFX_JPEG_HUFF_TABLE_STATE | (53 - 2));
2024         OUT_BCS_BATCH(batch, id);
2025         intel_batchbuffer_data(batch, huffman_table->huffman_table[index].num_dc_codes, 12);
2026         intel_batchbuffer_data(batch, huffman_table->huffman_table[index].dc_values, 12);
2027         intel_batchbuffer_data(batch, huffman_table->huffman_table[index].num_ac_codes, 16);
2028         intel_batchbuffer_data(batch, huffman_table->huffman_table[index].ac_values, 164);
2029         ADVANCE_BCS_BATCH(batch);
2030     }
2031 }
2032
2033 static const int va_to_gen7_jpeg_qm[5] = {
2034     -1,
2035     MFX_QM_JPEG_LUMA_Y_QUANTIZER_MATRIX,
2036     MFX_QM_JPEG_CHROMA_CB_QUANTIZER_MATRIX,
2037     MFX_QM_JPEG_CHROMA_CR_QUANTIZER_MATRIX,
2038     MFX_QM_JPEG_ALPHA_QUANTIZER_MATRIX
2039 };
2040
2041 static void
2042 gen7_mfd_jpeg_qm_state(VADriverContextP ctx,
2043                        struct decode_state *decode_state,
2044                        struct gen7_mfd_context *gen7_mfd_context)
2045 {
2046     VAPictureParameterBufferJPEGBaseline *pic_param;
2047     VAIQMatrixBufferJPEGBaseline *iq_matrix;
2048     int index;
2049
2050     if (!decode_state->iq_matrix || !decode_state->iq_matrix->buffer)
2051         return;
2052
2053     iq_matrix = (VAIQMatrixBufferJPEGBaseline *)decode_state->iq_matrix->buffer;
2054     pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
2055
2056     assert(pic_param->num_components <= 3);
2057
2058     for (index = 0; index < pic_param->num_components; index++) {
2059         int id = pic_param->components[index].component_id - pic_param->components[0].component_id + 1;
2060         int qm_type;
2061         unsigned char *qm = iq_matrix->quantiser_table[pic_param->components[index].quantiser_table_selector];
2062         unsigned char raster_qm[64];
2063         int j;
2064
2065         if (id > 4 || id < 1)
2066             continue;
2067
2068         if (!iq_matrix->load_quantiser_table[pic_param->components[index].quantiser_table_selector])
2069             continue;
2070
2071         qm_type = va_to_gen7_jpeg_qm[id];
2072
2073         for (j = 0; j < 64; j++)
2074             raster_qm[zigzag_direct[j]] = qm[j];
2075
2076         gen7_mfd_qm_state(ctx, qm_type, raster_qm, 64, gen7_mfd_context);
2077     }
2078 }
2079
2080 static void
2081 gen7_mfd_jpeg_bsd_object(VADriverContextP ctx,
2082                          VAPictureParameterBufferJPEGBaseline *pic_param,
2083                          VASliceParameterBufferJPEGBaseline *slice_param,
2084                          VASliceParameterBufferJPEGBaseline *next_slice_param,
2085                          dri_bo *slice_data_bo,
2086                          struct gen7_mfd_context *gen7_mfd_context)
2087 {
2088     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2089     int scan_component_mask = 0;
2090     int i;
2091
2092     assert(slice_param->num_components > 0);
2093     assert(slice_param->num_components < 4);
2094     assert(slice_param->num_components <= pic_param->num_components);
2095
2096     for (i = 0; i < slice_param->num_components; i++) {
2097         switch (slice_param->components[i].component_selector - pic_param->components[0].component_id + 1) {
2098         case 1:
2099             scan_component_mask |= (1 << 0);
2100             break;
2101         case 2:
2102             scan_component_mask |= (1 << 1);
2103             break;
2104         case 3:
2105             scan_component_mask |= (1 << 2);
2106             break;
2107         default:
2108             assert(0);
2109             break;
2110         }
2111     }
2112
2113     BEGIN_BCS_BATCH(batch, 6);
2114     OUT_BCS_BATCH(batch, MFD_JPEG_BSD_OBJECT | (6 - 2));
2115     OUT_BCS_BATCH(batch,
2116                   slice_param->slice_data_size);
2117     OUT_BCS_BATCH(batch,
2118                   slice_param->slice_data_offset);
2119     OUT_BCS_BATCH(batch,
2120                   slice_param->slice_horizontal_position << 16 |
2121                   slice_param->slice_vertical_position << 0);
2122     OUT_BCS_BATCH(batch,
2123                   ((slice_param->num_components != 1) << 30) |  /* interleaved */
2124                   (scan_component_mask << 27) |                 /* scan components */
2125                   (0 << 26) |   /* disable interrupt allowed */
2126                   (slice_param->num_mcus << 0));                /* MCU count */
2127     OUT_BCS_BATCH(batch,
2128                   (slice_param->restart_interval << 0));    /* RestartInterval */
2129     ADVANCE_BCS_BATCH(batch);
2130 }
2131
2132 /* Workaround for JPEG decoding on Ivybridge */
2133
2134 static struct {
2135     int width;
2136     int height;
2137     unsigned char data[32];
2138     int data_size;
2139     int data_bit_offset;
2140     int qp;
2141 } gen7_jpeg_wa_clip = {
2142     16,
2143     16,
2144     {
2145         0x65, 0xb8, 0x40, 0x32, 0x13, 0xfd, 0x06, 0x6c,
2146         0xfc, 0x0a, 0x50, 0x71, 0x5c, 0x00
2147     },
2148     14,
2149     40,
2150     28,
2151 };
2152
2153 static void
2154 gen7_jpeg_wa_init(VADriverContextP ctx,
2155                   struct gen7_mfd_context *gen7_mfd_context)
2156 {
2157     struct i965_driver_data *i965 = i965_driver_data(ctx);
2158     VAStatus status;
2159     struct object_surface *obj_surface;
2160
2161     if (gen7_mfd_context->jpeg_wa_surface_id != VA_INVALID_SURFACE)
2162         i965_DestroySurfaces(ctx,
2163                              &gen7_mfd_context->jpeg_wa_surface_id,
2164                              1);
2165
2166     status = i965_CreateSurfaces(ctx,
2167                                  gen7_jpeg_wa_clip.width,
2168                                  gen7_jpeg_wa_clip.height,
2169                                  VA_RT_FORMAT_YUV420,
2170                                  1,
2171                                  &gen7_mfd_context->jpeg_wa_surface_id);
2172     assert(status == VA_STATUS_SUCCESS);
2173
2174     obj_surface = SURFACE(gen7_mfd_context->jpeg_wa_surface_id);
2175     assert(obj_surface);
2176     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
2177     gen7_mfd_context->jpeg_wa_surface_object = obj_surface;
2178
2179     if (!gen7_mfd_context->jpeg_wa_slice_data_bo) {
2180         gen7_mfd_context->jpeg_wa_slice_data_bo = dri_bo_alloc(i965->intel.bufmgr,
2181                                                                "JPEG WA data",
2182                                                                0x1000,
2183                                                                0x1000);
2184         dri_bo_subdata(gen7_mfd_context->jpeg_wa_slice_data_bo,
2185                        0,
2186                        gen7_jpeg_wa_clip.data_size,
2187                        gen7_jpeg_wa_clip.data);
2188     }
2189 }
2190
2191 static void
2192 gen7_jpeg_wa_pipe_mode_select(VADriverContextP ctx,
2193                               struct gen7_mfd_context *gen7_mfd_context)
2194 {
2195     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2196
2197     BEGIN_BCS_BATCH(batch, 5);
2198     OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2));
2199     OUT_BCS_BATCH(batch,
2200                   (MFX_LONG_MODE << 17) | /* Currently only support long format */
2201                   (MFD_MODE_VLD << 15) | /* VLD mode */
2202                   (0 << 10) | /* disable Stream-Out */
2203                   (0 << 9)  | /* Post Deblocking Output */
2204                   (1 << 8)  | /* Pre Deblocking Output */
2205                   (0 << 5)  | /* not in stitch mode */
2206                   (MFX_CODEC_DECODE << 4)  | /* decoding mode */
2207                   (MFX_FORMAT_AVC << 0));
2208     OUT_BCS_BATCH(batch,
2209                   (0 << 4)  | /* terminate if AVC motion and POC table error occurs */
2210                   (0 << 3)  | /* terminate if AVC mbdata error occurs */
2211                   (0 << 2)  | /* terminate if AVC CABAC/CAVLC decode error occurs */
2212                   (0 << 1)  |
2213                   (0 << 0));
2214     OUT_BCS_BATCH(batch, 0); /* pic status/error report id */
2215     OUT_BCS_BATCH(batch, 0); /* reserved */
2216     ADVANCE_BCS_BATCH(batch);
2217 }
2218
2219 static void
2220 gen7_jpeg_wa_surface_state(VADriverContextP ctx,
2221                            struct gen7_mfd_context *gen7_mfd_context)
2222 {
2223     struct object_surface *obj_surface = gen7_mfd_context->jpeg_wa_surface_object;
2224     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2225
2226     BEGIN_BCS_BATCH(batch, 6);
2227     OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
2228     OUT_BCS_BATCH(batch, 0);
2229     OUT_BCS_BATCH(batch,
2230                   ((obj_surface->orig_width - 1) << 18) |
2231                   ((obj_surface->orig_height - 1) << 4));
2232     OUT_BCS_BATCH(batch,
2233                   (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
2234                   (1 << 27) | /* interleave chroma, set to 0 for JPEG */
2235                   (0 << 22) | /* surface object control state, ignored */
2236                   ((obj_surface->width - 1) << 3) | /* pitch */
2237                   (0 << 2)  | /* must be 0 */
2238                   (1 << 1)  | /* must be tiled */
2239                   (I965_TILEWALK_YMAJOR << 0));  /* tile walk, must be 1 */
2240     OUT_BCS_BATCH(batch,
2241                   (0 << 16) | /* X offset for U(Cb), must be 0 */
2242                   (obj_surface->y_cb_offset << 0)); /* Y offset for U(Cb) */
2243     OUT_BCS_BATCH(batch,
2244                   (0 << 16) | /* X offset for V(Cr), must be 0 */
2245                   (0 << 0)); /* Y offset for V(Cr), must be 0 for video codec, non-zoro for JPEG */
2246     ADVANCE_BCS_BATCH(batch);
2247 }
2248
2249 static void
2250 gen7_jpeg_wa_pipe_buf_addr_state(VADriverContextP ctx,
2251                                  struct gen7_mfd_context *gen7_mfd_context)
2252 {
2253     struct i965_driver_data *i965 = i965_driver_data(ctx);
2254     struct object_surface *obj_surface = gen7_mfd_context->jpeg_wa_surface_object;
2255     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2256     dri_bo *intra_bo;
2257     int i;
2258
2259     intra_bo = dri_bo_alloc(i965->intel.bufmgr,
2260                             "intra row store",
2261                             128 * 64,
2262                             0x1000);
2263
2264     BEGIN_BCS_BATCH(batch, 24);
2265     OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
2266     OUT_BCS_RELOC(batch,
2267                   obj_surface->bo,
2268                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2269                   0);
2270
2271     OUT_BCS_BATCH(batch, 0); /* post deblocking */
2272
2273     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
2274     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
2275
2276     OUT_BCS_RELOC(batch,
2277                   intra_bo,
2278                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2279                   0);
2280
2281     OUT_BCS_BATCH(batch, 0);
2282
2283     /* DW 7..22 */
2284     for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
2285         OUT_BCS_BATCH(batch, 0);
2286     }
2287
2288     OUT_BCS_BATCH(batch, 0);   /* ignore DW23 for decoding */
2289     ADVANCE_BCS_BATCH(batch);
2290
2291     dri_bo_unreference(intra_bo);
2292 }
2293
2294 static void
2295 gen7_jpeg_wa_bsp_buf_base_addr_state(VADriverContextP ctx,
2296                                      struct gen7_mfd_context *gen7_mfd_context)
2297 {
2298     struct i965_driver_data *i965 = i965_driver_data(ctx);
2299     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2300     dri_bo *bsd_mpc_bo, *mpr_bo;
2301
2302     bsd_mpc_bo = dri_bo_alloc(i965->intel.bufmgr,
2303                               "bsd mpc row store",
2304                               11520, /* 1.5 * 120 * 64 */
2305                               0x1000);
2306
2307     mpr_bo = dri_bo_alloc(i965->intel.bufmgr,
2308                           "mpr row store",
2309                           7680, /* 1. 0 * 120 * 64 */
2310                           0x1000);
2311
2312     BEGIN_BCS_BATCH(batch, 4);
2313     OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
2314
2315     OUT_BCS_RELOC(batch,
2316                   bsd_mpc_bo,
2317                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2318                   0);
2319
2320     OUT_BCS_RELOC(batch,
2321                   mpr_bo,
2322                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2323                   0);
2324     OUT_BCS_BATCH(batch, 0);
2325
2326     ADVANCE_BCS_BATCH(batch);
2327
2328     dri_bo_unreference(bsd_mpc_bo);
2329     dri_bo_unreference(mpr_bo);
2330 }
2331
2332 static void
2333 gen7_jpeg_wa_avc_qm_state(VADriverContextP ctx,
2334                           struct gen7_mfd_context *gen7_mfd_context)
2335 {
2336
2337 }
2338
2339 static void
2340 gen7_jpeg_wa_avc_img_state(VADriverContextP ctx,
2341                            struct gen7_mfd_context *gen7_mfd_context)
2342 {
2343     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2344     int img_struct = 0;
2345     int mbaff_frame_flag = 0;
2346     unsigned int width_in_mbs = 1, height_in_mbs = 1;
2347
2348     BEGIN_BCS_BATCH(batch, 16);
2349     OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (16 - 2));
2350     OUT_BCS_BATCH(batch,
2351                   (width_in_mbs * height_in_mbs - 1));
2352     OUT_BCS_BATCH(batch,
2353                   ((height_in_mbs - 1) << 16) |
2354                   ((width_in_mbs - 1) << 0));
2355     OUT_BCS_BATCH(batch,
2356                   (0 << 24) |
2357                   (0 << 16) |
2358                   (0 << 14) |
2359                   (0 << 13) |
2360                   (0 << 12) | /* differ from GEN6 */
2361                   (0 << 10) |
2362                   (img_struct << 8));
2363     OUT_BCS_BATCH(batch,
2364                   (1 << 10) | /* 4:2:0 */
2365                   (1 << 7) |  /* CABAC */
2366                   (0 << 6) |
2367                   (0 << 5) |
2368                   (0 << 4) |
2369                   (0 << 3) |
2370                   (1 << 2) |
2371                   (mbaff_frame_flag << 1) |
2372                   (0 << 0));
2373     OUT_BCS_BATCH(batch, 0);
2374     OUT_BCS_BATCH(batch, 0);
2375     OUT_BCS_BATCH(batch, 0);
2376     OUT_BCS_BATCH(batch, 0);
2377     OUT_BCS_BATCH(batch, 0);
2378     OUT_BCS_BATCH(batch, 0);
2379     OUT_BCS_BATCH(batch, 0);
2380     OUT_BCS_BATCH(batch, 0);
2381     OUT_BCS_BATCH(batch, 0);
2382     OUT_BCS_BATCH(batch, 0);
2383     OUT_BCS_BATCH(batch, 0);
2384     ADVANCE_BCS_BATCH(batch);
2385 }
2386
2387 static void
2388 gen7_jpeg_wa_avc_directmode_state(VADriverContextP ctx,
2389                                   struct gen7_mfd_context *gen7_mfd_context)
2390 {
2391     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2392     int i;
2393
2394     BEGIN_BCS_BATCH(batch, 69);
2395     OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
2396
2397     /* reference surfaces 0..15 */
2398     for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
2399         OUT_BCS_BATCH(batch, 0); /* top */
2400         OUT_BCS_BATCH(batch, 0); /* bottom */
2401     }
2402
2403     /* the current decoding frame/field */
2404     OUT_BCS_BATCH(batch, 0); /* top */
2405     OUT_BCS_BATCH(batch, 0); /* bottom */
2406
2407     /* POC List */
2408     for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
2409         OUT_BCS_BATCH(batch, 0);
2410         OUT_BCS_BATCH(batch, 0);
2411     }
2412
2413     OUT_BCS_BATCH(batch, 0);
2414     OUT_BCS_BATCH(batch, 0);
2415
2416     ADVANCE_BCS_BATCH(batch);
2417 }
2418
2419 static void
2420 gen7_jpeg_wa_ind_obj_base_addr_state(VADriverContextP ctx,
2421                                      struct gen7_mfd_context *gen7_mfd_context)
2422 {
2423     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2424
2425     BEGIN_BCS_BATCH(batch, 11);
2426     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
2427     OUT_BCS_RELOC(batch,
2428                   gen7_mfd_context->jpeg_wa_slice_data_bo,
2429                   I915_GEM_DOMAIN_INSTRUCTION, 0,
2430                   0);
2431     OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
2432     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
2433     OUT_BCS_BATCH(batch, 0);
2434     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
2435     OUT_BCS_BATCH(batch, 0);
2436     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
2437     OUT_BCS_BATCH(batch, 0);
2438     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
2439     OUT_BCS_BATCH(batch, 0);
2440     ADVANCE_BCS_BATCH(batch);
2441 }
2442
2443 static void
2444 gen7_jpeg_wa_avc_bsd_object(VADriverContextP ctx,
2445                             struct gen7_mfd_context *gen7_mfd_context)
2446 {
2447     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2448
2449     /* the input bitsteam format on GEN7 differs from GEN6 */
2450     BEGIN_BCS_BATCH(batch, 6);
2451     OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2));
2452     OUT_BCS_BATCH(batch, gen7_jpeg_wa_clip.data_size);
2453     OUT_BCS_BATCH(batch, 0);
2454     OUT_BCS_BATCH(batch,
2455                   (0 << 31) |
2456                   (0 << 14) |
2457                   (0 << 12) |
2458                   (0 << 10) |
2459                   (0 << 8));
2460     OUT_BCS_BATCH(batch,
2461                   ((gen7_jpeg_wa_clip.data_bit_offset >> 3) << 16) |
2462                   (0 << 5)  |
2463                   (0 << 4)  |
2464                   (1 << 3) | /* LastSlice Flag */
2465                   (gen7_jpeg_wa_clip.data_bit_offset & 0x7));
2466     OUT_BCS_BATCH(batch, 0);
2467     ADVANCE_BCS_BATCH(batch);
2468 }
2469
2470 static void
2471 gen7_jpeg_wa_avc_slice_state(VADriverContextP ctx,
2472                              struct gen7_mfd_context *gen7_mfd_context)
2473 {
2474     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2475     int slice_hor_pos = 0, slice_ver_pos = 0, next_slice_hor_pos = 0, next_slice_ver_pos = 1;
2476     int num_ref_idx_l0 = 0, num_ref_idx_l1 = 0;
2477     int first_mb_in_slice = 0;
2478     int slice_type = SLICE_TYPE_I;
2479
2480     BEGIN_BCS_BATCH(batch, 11);
2481     OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2));
2482     OUT_BCS_BATCH(batch, slice_type);
2483     OUT_BCS_BATCH(batch,
2484                   (num_ref_idx_l1 << 24) |
2485                   (num_ref_idx_l0 << 16) |
2486                   (0 << 8) |
2487                   (0 << 0));
2488     OUT_BCS_BATCH(batch,
2489                   (0 << 29) |
2490                   (1 << 27) |   /* disable Deblocking */
2491                   (0 << 24) |
2492                   (gen7_jpeg_wa_clip.qp << 16) |
2493                   (0 << 8) |
2494                   (0 << 0));
2495     OUT_BCS_BATCH(batch,
2496                   (slice_ver_pos << 24) |
2497                   (slice_hor_pos << 16) |
2498                   (first_mb_in_slice << 0));
2499     OUT_BCS_BATCH(batch,
2500                   (next_slice_ver_pos << 16) |
2501                   (next_slice_hor_pos << 0));
2502     OUT_BCS_BATCH(batch, (1 << 19)); /* last slice flag */
2503     OUT_BCS_BATCH(batch, 0);
2504     OUT_BCS_BATCH(batch, 0);
2505     OUT_BCS_BATCH(batch, 0);
2506     OUT_BCS_BATCH(batch, 0);
2507     ADVANCE_BCS_BATCH(batch);
2508 }
2509
2510 static void
2511 gen7_mfd_jpeg_wa(VADriverContextP ctx,
2512                  struct gen7_mfd_context *gen7_mfd_context)
2513 {
2514     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2515     gen7_jpeg_wa_init(ctx, gen7_mfd_context);
2516     intel_batchbuffer_emit_mi_flush(batch);
2517     gen7_jpeg_wa_pipe_mode_select(ctx, gen7_mfd_context);
2518     gen7_jpeg_wa_surface_state(ctx, gen7_mfd_context);
2519     gen7_jpeg_wa_pipe_buf_addr_state(ctx, gen7_mfd_context);
2520     gen7_jpeg_wa_bsp_buf_base_addr_state(ctx, gen7_mfd_context);
2521     gen7_jpeg_wa_avc_qm_state(ctx, gen7_mfd_context);
2522     gen7_jpeg_wa_avc_img_state(ctx, gen7_mfd_context);
2523     gen7_jpeg_wa_ind_obj_base_addr_state(ctx, gen7_mfd_context);
2524
2525     gen7_jpeg_wa_avc_directmode_state(ctx, gen7_mfd_context);
2526     gen7_jpeg_wa_avc_slice_state(ctx, gen7_mfd_context);
2527     gen7_jpeg_wa_avc_bsd_object(ctx, gen7_mfd_context);
2528 }
2529
2530 void
2531 gen7_mfd_jpeg_decode_picture(VADriverContextP ctx,
2532                              struct decode_state *decode_state,
2533                              struct gen7_mfd_context *gen7_mfd_context)
2534 {
2535     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2536     VAPictureParameterBufferJPEGBaseline *pic_param;
2537     VASliceParameterBufferJPEGBaseline *slice_param, *next_slice_param, *next_slice_group_param;
2538     dri_bo *slice_data_bo;
2539     int i, j, max_selector = 0;
2540
2541     assert(decode_state->pic_param && decode_state->pic_param->buffer);
2542     pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
2543
2544     /* Currently only support Baseline DCT */
2545     gen7_mfd_jpeg_decode_init(ctx, decode_state, gen7_mfd_context);
2546     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
2547     gen7_mfd_jpeg_wa(ctx, gen7_mfd_context);
2548     intel_batchbuffer_emit_mi_flush(batch);
2549     gen7_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_JPEG, gen7_mfd_context);
2550     gen7_mfd_surface_state(ctx, decode_state, MFX_FORMAT_JPEG, gen7_mfd_context);
2551     gen7_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_JPEG, gen7_mfd_context);
2552     gen7_mfd_jpeg_pic_state(ctx, decode_state, gen7_mfd_context);
2553     gen7_mfd_jpeg_qm_state(ctx, decode_state, gen7_mfd_context);
2554
2555     for (j = 0; j < decode_state->num_slice_params; j++) {
2556         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
2557         slice_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j]->buffer;
2558         slice_data_bo = decode_state->slice_datas[j]->bo;
2559         gen7_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_JPEG, gen7_mfd_context);
2560
2561         if (j == decode_state->num_slice_params - 1)
2562             next_slice_group_param = NULL;
2563         else
2564             next_slice_group_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j + 1]->buffer;
2565
2566         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
2567             int component;
2568
2569             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
2570
2571             if (i < decode_state->slice_params[j]->num_elements - 1)
2572                 next_slice_param = slice_param + 1;
2573             else
2574                 next_slice_param = next_slice_group_param;
2575
2576             for (component = 0; component < slice_param->num_components; component++) {
2577                 if (max_selector < slice_param->components[component].dc_table_selector)
2578                     max_selector = slice_param->components[component].dc_table_selector;
2579
2580                 if (max_selector < slice_param->components[component].ac_table_selector)
2581                     max_selector = slice_param->components[component].ac_table_selector;
2582             }
2583
2584             slice_param++;
2585         }
2586     }
2587
2588     assert(max_selector < 2);
2589     gen7_mfd_jpeg_huff_table_state(ctx, decode_state, gen7_mfd_context, max_selector + 1);
2590
2591     for (j = 0; j < decode_state->num_slice_params; j++) {
2592         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
2593         slice_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j]->buffer;
2594         slice_data_bo = decode_state->slice_datas[j]->bo;
2595         gen7_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_JPEG, gen7_mfd_context);
2596
2597         if (j == decode_state->num_slice_params - 1)
2598             next_slice_group_param = NULL;
2599         else
2600             next_slice_group_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j + 1]->buffer;
2601
2602         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
2603             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
2604
2605             if (i < decode_state->slice_params[j]->num_elements - 1)
2606                 next_slice_param = slice_param + 1;
2607             else
2608                 next_slice_param = next_slice_group_param;
2609
2610             gen7_mfd_jpeg_bsd_object(ctx, pic_param, slice_param, next_slice_param, slice_data_bo, gen7_mfd_context);
2611             slice_param++;
2612         }
2613     }
2614
2615     intel_batchbuffer_end_atomic(batch);
2616     intel_batchbuffer_flush(batch);
2617 }
2618
2619 static VAStatus
2620 gen7_mfd_decode_picture(VADriverContextP ctx,
2621                         VAProfile profile,
2622                         union codec_state *codec_state,
2623                         struct hw_context *hw_context)
2624
2625 {
2626     struct gen7_mfd_context *gen7_mfd_context = (struct gen7_mfd_context *)hw_context;
2627     struct decode_state *decode_state = &codec_state->decode;
2628     VAStatus vaStatus;
2629
2630     assert(gen7_mfd_context);
2631
2632     vaStatus = intel_decoder_sanity_check_input(ctx, profile, decode_state);
2633
2634     if (vaStatus != VA_STATUS_SUCCESS)
2635         goto out;
2636
2637     gen7_mfd_context->wa_mpeg2_slice_vertical_position = -1;
2638
2639     switch (profile) {
2640     case VAProfileMPEG2Simple:
2641     case VAProfileMPEG2Main:
2642         gen7_mfd_mpeg2_decode_picture(ctx, decode_state, gen7_mfd_context);
2643         break;
2644
2645     case VAProfileH264ConstrainedBaseline:
2646     case VAProfileH264Main:
2647     case VAProfileH264High:
2648     case VAProfileH264StereoHigh:
2649         gen7_mfd_avc_decode_picture(ctx, decode_state, gen7_mfd_context);
2650         break;
2651
2652     case VAProfileVC1Simple:
2653     case VAProfileVC1Main:
2654     case VAProfileVC1Advanced:
2655         gen7_mfd_vc1_decode_picture(ctx, decode_state, gen7_mfd_context);
2656         break;
2657
2658     case VAProfileJPEGBaseline:
2659         gen7_mfd_jpeg_decode_picture(ctx, decode_state, gen7_mfd_context);
2660         break;
2661
2662     default:
2663         assert(0);
2664         break;
2665     }
2666
2667     vaStatus = VA_STATUS_SUCCESS;
2668
2669 out:
2670     return vaStatus;
2671 }
2672
2673 static void
2674 gen7_mfd_context_destroy(void *hw_context)
2675 {
2676     VADriverContextP ctx;
2677     struct gen7_mfd_context *gen7_mfd_context = (struct gen7_mfd_context *)hw_context;
2678
2679     ctx = (VADriverContextP)(gen7_mfd_context->driver_context);
2680
2681     dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo);
2682     gen7_mfd_context->post_deblocking_output.bo = NULL;
2683
2684     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
2685     gen7_mfd_context->pre_deblocking_output.bo = NULL;
2686
2687     dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo);
2688     gen7_mfd_context->intra_row_store_scratch_buffer.bo = NULL;
2689
2690     dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
2691     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
2692
2693     dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
2694     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
2695
2696     dri_bo_unreference(gen7_mfd_context->mpr_row_store_scratch_buffer.bo);
2697     gen7_mfd_context->mpr_row_store_scratch_buffer.bo = NULL;
2698
2699     dri_bo_unreference(gen7_mfd_context->bitplane_read_buffer.bo);
2700     gen7_mfd_context->bitplane_read_buffer.bo = NULL;
2701
2702     dri_bo_unreference(gen7_mfd_context->jpeg_wa_slice_data_bo);
2703
2704     if (gen7_mfd_context->jpeg_wa_surface_id != VA_INVALID_SURFACE) {
2705         i965_DestroySurfaces(ctx,
2706                              &gen7_mfd_context->jpeg_wa_surface_id,
2707                              1);
2708         gen7_mfd_context->jpeg_wa_surface_object = NULL;
2709     }
2710
2711     intel_batchbuffer_free(gen7_mfd_context->base.batch);
2712     free(gen7_mfd_context);
2713 }
2714
2715 static void gen7_mfd_mpeg2_context_init(VADriverContextP ctx,
2716                                     struct gen7_mfd_context *gen7_mfd_context)
2717 {
2718     gen7_mfd_context->iq_matrix.mpeg2.load_intra_quantiser_matrix = -1;
2719     gen7_mfd_context->iq_matrix.mpeg2.load_non_intra_quantiser_matrix = -1;
2720     gen7_mfd_context->iq_matrix.mpeg2.load_chroma_intra_quantiser_matrix = -1;
2721     gen7_mfd_context->iq_matrix.mpeg2.load_chroma_non_intra_quantiser_matrix = -1;
2722 }
2723
2724 struct hw_context *
2725 gen7_dec_hw_context_init(VADriverContextP ctx, struct object_config *obj_config)
2726 {
2727     struct intel_driver_data *intel = intel_driver_data(ctx);
2728     struct gen7_mfd_context *gen7_mfd_context = calloc(1, sizeof(struct gen7_mfd_context));
2729     int i;
2730
2731     assert(gen7_mfd_context);
2732     gen7_mfd_context->base.destroy = gen7_mfd_context_destroy;
2733     gen7_mfd_context->base.run = gen7_mfd_decode_picture;
2734     gen7_mfd_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER, 0);
2735
2736     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
2737         gen7_mfd_context->reference_surface[i].surface_id = VA_INVALID_ID;
2738         gen7_mfd_context->reference_surface[i].frame_store_id = -1;
2739         gen7_mfd_context->reference_surface[i].obj_surface = NULL;
2740     }
2741
2742     gen7_mfd_context->jpeg_wa_surface_id = VA_INVALID_SURFACE;
2743     gen7_mfd_context->jpeg_wa_surface_object = NULL;
2744
2745     switch (obj_config->profile) {
2746     case VAProfileMPEG2Simple:
2747     case VAProfileMPEG2Main:
2748         gen7_mfd_mpeg2_context_init(ctx, gen7_mfd_context);
2749         break;
2750
2751     case VAProfileH264ConstrainedBaseline:
2752     case VAProfileH264Main:
2753     case VAProfileH264High:
2754     case VAProfileH264StereoHigh:
2755         gen7_mfd_avc_context_init(ctx, gen7_mfd_context);
2756         break;
2757     default:
2758         break;
2759     }
2760
2761     gen7_mfd_context->driver_context = ctx;
2762     return (struct hw_context *)gen7_mfd_context;
2763 }