src/gen7_mfd.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Xiang Haihao <haihao.xiang@intel.com>
  26  *
  27  */
  28
  29 #include "sysdeps.h"
  30
  31 #include <va/va_dec_jpeg.h>
  32
  33 #include "intel_batchbuffer.h"
  34 #include "intel_driver.h"
  35 #include "i965_defines.h"
  36 #include "i965_drv_video.h"
  37 #include "i965_decoder_utils.h"
  38
  39 #include "gen7_mfd.h"
  40 #include "intel_media.h"
  41
  42 static const uint32_t zigzag_direct[64] = {
  43     0,   1,  8, 16,  9,  2,  3, 10,
  44     17, 24, 32, 25, 18, 11,  4,  5,
  45     12, 19, 26, 33, 40, 48, 41, 34,
  46     27, 20, 13,  6,  7, 14, 21, 28,
  47     35, 42, 49, 56, 57, 50, 43, 36,
  48     29, 22, 15, 23, 30, 37, 44, 51,
  49     58, 59, 52, 45, 38, 31, 39, 46,
  50     53, 60, 61, 54, 47, 55, 62, 63
  51 };
  52
  53 static void
  54 gen7_mfd_init_avc_surface(VADriverContextP ctx,
  55                           VAPictureParameterBufferH264 *pic_param,
  56                           struct object_surface *obj_surface)
  57 {
  58     struct i965_driver_data *i965 = i965_driver_data(ctx);
  59     GenAvcSurface *gen7_avc_surface = obj_surface->private_data;
  60     int width_in_mbs, height_in_mbs;
  61
  62     obj_surface->free_private_data = gen_free_avc_surface;
  63     width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
  64     height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; /* frame height */
  65
  66     if (!gen7_avc_surface) {
  67         gen7_avc_surface = calloc(sizeof(GenAvcSurface), 1);
  68         assert(gen7_avc_surface);
  69         gen7_avc_surface->base.frame_store_id = -1;
  70         assert((obj_surface->size & 0x3f) == 0);
  71         obj_surface->private_data = gen7_avc_surface;
  72     }
  73
  74     gen7_avc_surface->dmv_bottom_flag = (pic_param->pic_fields.bits.field_pic_flag &&
  75                                          !pic_param->seq_fields.bits.direct_8x8_inference_flag);
  76
  77     if (gen7_avc_surface->dmv_top == NULL) {
  78         gen7_avc_surface->dmv_top = dri_bo_alloc(i965->intel.bufmgr,
  79                                                  "direct mv w/r buffer",
  80                                                  width_in_mbs * (height_in_mbs + 1) * 64,
  81                                                  0x1000);
  82         assert(gen7_avc_surface->dmv_top);
  83     }
  84
  85     if (gen7_avc_surface->dmv_bottom_flag &&
  86         gen7_avc_surface->dmv_bottom == NULL) {
  87         gen7_avc_surface->dmv_bottom = dri_bo_alloc(i965->intel.bufmgr,
  88                                                     "direct mv w/r buffer",
  89                                                     width_in_mbs * (height_in_mbs + 1) * 64,
  90                                                     0x1000);
  91         assert(gen7_avc_surface->dmv_bottom);
  92     }
  93 }
  94
  95 static void
  96 gen7_mfd_pipe_mode_select(VADriverContextP ctx,
  97                           struct decode_state *decode_state,
  98                           int standard_select,
  99                           struct gen7_mfd_context *gen7_mfd_context)
 100 {
 101     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 102
 103     assert(standard_select == MFX_FORMAT_MPEG2 ||
 104            standard_select == MFX_FORMAT_AVC ||
 105            standard_select == MFX_FORMAT_VC1 ||
 106            standard_select == MFX_FORMAT_JPEG);
 107
 108     BEGIN_BCS_BATCH(batch, 5);
 109     OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2));
 110     OUT_BCS_BATCH(batch,
 111                   (MFX_LONG_MODE << 17) | /* Currently only support long format */
 112                   (MFD_MODE_VLD << 15) | /* VLD mode */
 113                   (0 << 10) | /* disable Stream-Out */
 114                   (gen7_mfd_context->post_deblocking_output.valid << 9)  | /* Post Deblocking Output */
 115                   (gen7_mfd_context->pre_deblocking_output.valid << 8)  | /* Pre Deblocking Output */
 116                   (0 << 5)  | /* not in stitch mode */
 117                   (MFX_CODEC_DECODE << 4)  | /* decoding mode */
 118                   (standard_select << 0));
 119     OUT_BCS_BATCH(batch,
 120                   (0 << 4)  | /* terminate if AVC motion and POC table error occurs */
 121                   (0 << 3)  | /* terminate if AVC mbdata error occurs */
 122                   (0 << 2)  | /* terminate if AVC CABAC/CAVLC decode error occurs */
 123                   (0 << 1)  |
 124                   (0 << 0));
 125     OUT_BCS_BATCH(batch, 0); /* pic status/error report id */
 126     OUT_BCS_BATCH(batch, 0); /* reserved */
 127     ADVANCE_BCS_BATCH(batch);
 128 }
 129
 130 static void
 131 gen7_mfd_surface_state(VADriverContextP ctx,
 132                        struct decode_state *decode_state,
 133                        int standard_select,
 134                        struct gen7_mfd_context *gen7_mfd_context)
 135 {
 136     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 137     struct object_surface *obj_surface = decode_state->render_object;
 138     unsigned int y_cb_offset;
 139     unsigned int y_cr_offset;
 140     unsigned int surface_format;
 141
 142     assert(obj_surface);
 143
 144     y_cb_offset = obj_surface->y_cb_offset;
 145     y_cr_offset = obj_surface->y_cr_offset;
 146
 147     surface_format = obj_surface->fourcc == VA_FOURCC_Y800 ?
 148                      MFX_SURFACE_MONOCHROME : MFX_SURFACE_PLANAR_420_8;
 149
 150     BEGIN_BCS_BATCH(batch, 6);
 151     OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
 152     OUT_BCS_BATCH(batch, 0);
 153     OUT_BCS_BATCH(batch,
 154                   ((obj_surface->orig_height - 1) << 18) |
 155                   ((obj_surface->orig_width - 1) << 4));
 156     OUT_BCS_BATCH(batch,
 157                   (surface_format << 28) | /* 420 planar YUV surface */
 158                   ((standard_select != MFX_FORMAT_JPEG) << 27) | /* interleave chroma, set to 0 for JPEG */
 159                   (0 << 22) | /* surface object control state, ignored */
 160                   ((obj_surface->width - 1) << 3) | /* pitch */
 161                   (0 << 2)  | /* must be 0 */
 162                   (1 << 1)  | /* must be tiled */
 163                   (I965_TILEWALK_YMAJOR << 0));  /* tile walk, must be 1 */
 164     OUT_BCS_BATCH(batch,
 165                   (0 << 16) | /* X offset for U(Cb), must be 0 */
 166                   (y_cb_offset << 0)); /* Y offset for U(Cb) */
 167     OUT_BCS_BATCH(batch,
 168                   (0 << 16) | /* X offset for V(Cr), must be 0 */
 169                   ((standard_select == MFX_FORMAT_JPEG ? y_cr_offset : 0) << 0)); /* Y offset for V(Cr), must be 0 for video codec, non-zoro for JPEG */
 170     ADVANCE_BCS_BATCH(batch);
 171 }
 172
 173 static void
 174 gen7_mfd_pipe_buf_addr_state(VADriverContextP ctx,
 175                              struct decode_state *decode_state,
 176                              int standard_select,
 177                              struct gen7_mfd_context *gen7_mfd_context)
 178 {
 179     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 180     int i;
 181
 182     BEGIN_BCS_BATCH(batch, 24);
 183     OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
 184     if (gen7_mfd_context->pre_deblocking_output.valid)
 185         OUT_BCS_RELOC(batch, gen7_mfd_context->pre_deblocking_output.bo,
 186                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 187                       0);
 188     else
 189         OUT_BCS_BATCH(batch, 0);
 190
 191     if (gen7_mfd_context->post_deblocking_output.valid)
 192         OUT_BCS_RELOC(batch, gen7_mfd_context->post_deblocking_output.bo,
 193                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 194                       0);
 195     else
 196         OUT_BCS_BATCH(batch, 0);
 197
 198     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
 199     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
 200
 201     if (gen7_mfd_context->intra_row_store_scratch_buffer.valid)
 202         OUT_BCS_RELOC(batch, gen7_mfd_context->intra_row_store_scratch_buffer.bo,
 203                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 204                       0);
 205     else
 206         OUT_BCS_BATCH(batch, 0);
 207
 208     if (gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid)
 209         OUT_BCS_RELOC(batch, gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo,
 210                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 211                       0);
 212     else
 213         OUT_BCS_BATCH(batch, 0);
 214
 215     /* DW 7..22 */
 216     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
 217         struct object_surface *obj_surface;
 218
 219         if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID &&
 220             gen7_mfd_context->reference_surface[i].obj_surface &&
 221             gen7_mfd_context->reference_surface[i].obj_surface->bo) {
 222             obj_surface = gen7_mfd_context->reference_surface[i].obj_surface;
 223
 224             OUT_BCS_RELOC(batch, obj_surface->bo,
 225                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 226                           0);
 227         } else {
 228             OUT_BCS_BATCH(batch, 0);
 229         }
 230     }
 231
 232     OUT_BCS_BATCH(batch, 0);   /* ignore DW23 for decoding */
 233     ADVANCE_BCS_BATCH(batch);
 234 }
 235
 236 static void
 237 gen7_mfd_ind_obj_base_addr_state(VADriverContextP ctx,
 238                                  dri_bo *slice_data_bo,
 239                                  int standard_select,
 240                                  struct gen7_mfd_context *gen7_mfd_context)
 241 {
 242     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 243
 244     BEGIN_BCS_BATCH(batch, 11);
 245     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
 246     OUT_BCS_RELOC(batch, slice_data_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); /* MFX Indirect Bitstream Object Base Address */
 247     OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
 248     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 249     OUT_BCS_BATCH(batch, 0);
 250     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 251     OUT_BCS_BATCH(batch, 0);
 252     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 253     OUT_BCS_BATCH(batch, 0);
 254     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 255     OUT_BCS_BATCH(batch, 0);
 256     ADVANCE_BCS_BATCH(batch);
 257 }
 258
 259 static void
 260 gen7_mfd_bsp_buf_base_addr_state(VADriverContextP ctx,
 261                                  struct decode_state *decode_state,
 262                                  int standard_select,
 263                                  struct gen7_mfd_context *gen7_mfd_context)
 264 {
 265     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 266
 267     BEGIN_BCS_BATCH(batch, 4);
 268     OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
 269
 270     if (gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid)
 271         OUT_BCS_RELOC(batch, gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo,
 272                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 273                       0);
 274     else
 275         OUT_BCS_BATCH(batch, 0);
 276
 277     if (gen7_mfd_context->mpr_row_store_scratch_buffer.valid)
 278         OUT_BCS_RELOC(batch, gen7_mfd_context->mpr_row_store_scratch_buffer.bo,
 279                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 280                       0);
 281     else
 282         OUT_BCS_BATCH(batch, 0);
 283
 284     if (gen7_mfd_context->bitplane_read_buffer.valid)
 285         OUT_BCS_RELOC(batch, gen7_mfd_context->bitplane_read_buffer.bo,
 286                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 287                       0);
 288     else
 289         OUT_BCS_BATCH(batch, 0);
 290
 291     ADVANCE_BCS_BATCH(batch);
 292 }
 293
 294 static void
 295 gen7_mfd_qm_state(VADriverContextP ctx,
 296                   int qm_type,
 297                   unsigned char *qm,
 298                   int qm_length,
 299                   struct gen7_mfd_context *gen7_mfd_context)
 300 {
 301     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 302     unsigned int qm_buffer[16];
 303
 304     assert(qm_length <= 16 * 4);
 305     memcpy(qm_buffer, qm, qm_length);
 306
 307     BEGIN_BCS_BATCH(batch, 18);
 308     OUT_BCS_BATCH(batch, MFX_QM_STATE | (18 - 2));
 309     OUT_BCS_BATCH(batch, qm_type << 0);
 310     intel_batchbuffer_data(batch, qm_buffer, 16 * 4);
 311     ADVANCE_BCS_BATCH(batch);
 312 }
 313
 314 static void
 315 gen7_mfd_avc_img_state(VADriverContextP ctx,
 316                        struct decode_state *decode_state,
 317                        struct gen7_mfd_context *gen7_mfd_context)
 318 {
 319     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 320     int img_struct;
 321     int mbaff_frame_flag;
 322     unsigned int width_in_mbs, height_in_mbs;
 323     VAPictureParameterBufferH264 *pic_param;
 324
 325     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 326     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 327
 328     if (pic_param->CurrPic.flags & VA_PICTURE_H264_TOP_FIELD)
 329         img_struct = 1;
 330     else if (pic_param->CurrPic.flags & VA_PICTURE_H264_BOTTOM_FIELD)
 331         img_struct = 3;
 332     else
 333         img_struct = 0;
 334
 335     if ((img_struct & 0x1) == 0x1) {
 336         assert(pic_param->pic_fields.bits.field_pic_flag == 0x1);
 337     } else {
 338         assert(pic_param->pic_fields.bits.field_pic_flag == 0x0);
 339     }
 340
 341     if (pic_param->seq_fields.bits.frame_mbs_only_flag) { /* a frame containing only frame macroblocks */
 342         assert(pic_param->seq_fields.bits.mb_adaptive_frame_field_flag == 0);
 343         assert(pic_param->pic_fields.bits.field_pic_flag == 0);
 344     } else {
 345         assert(pic_param->seq_fields.bits.direct_8x8_inference_flag == 1); /* see H.264 spec */
 346     }
 347
 348     mbaff_frame_flag = (pic_param->seq_fields.bits.mb_adaptive_frame_field_flag &&
 349                         !pic_param->pic_fields.bits.field_pic_flag);
 350
 351     width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
 352     height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; /* frame height */
 353
 354     /* MFX unit doesn't support 4:2:2 and 4:4:4 picture */
 355     assert(pic_param->seq_fields.bits.chroma_format_idc == 0 || /* monochrome picture */
 356            pic_param->seq_fields.bits.chroma_format_idc == 1);  /* 4:2:0 */
 357     assert(pic_param->seq_fields.bits.residual_colour_transform_flag == 0); /* only available for 4:4:4 */
 358
 359     BEGIN_BCS_BATCH(batch, 16);
 360     OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (16 - 2));
 361     OUT_BCS_BATCH(batch,
 362                   (width_in_mbs * height_in_mbs - 1));
 363     OUT_BCS_BATCH(batch,
 364                   ((height_in_mbs - 1) << 16) |
 365                   ((width_in_mbs - 1) << 0));
 366     OUT_BCS_BATCH(batch,
 367                   ((pic_param->second_chroma_qp_index_offset & 0x1f) << 24) |
 368                   ((pic_param->chroma_qp_index_offset & 0x1f) << 16) |
 369                   (0 << 14) | /* Max-bit conformance Intra flag ??? FIXME */
 370                   (0 << 13) | /* Max Macroblock size conformance Inter flag ??? FIXME */
 371                   (pic_param->pic_fields.bits.weighted_pred_flag << 12) | /* differ from GEN6 */
 372                   (pic_param->pic_fields.bits.weighted_bipred_idc << 10) |
 373                   (img_struct << 8));
 374     OUT_BCS_BATCH(batch,
 375                   (pic_param->seq_fields.bits.chroma_format_idc << 10) |
 376                   (pic_param->pic_fields.bits.entropy_coding_mode_flag << 7) |
 377                   ((!pic_param->pic_fields.bits.reference_pic_flag) << 6) |
 378                   (pic_param->pic_fields.bits.constrained_intra_pred_flag << 5) |
 379                   (pic_param->seq_fields.bits.direct_8x8_inference_flag << 4) |
 380                   (pic_param->pic_fields.bits.transform_8x8_mode_flag << 3) |
 381                   (pic_param->seq_fields.bits.frame_mbs_only_flag << 2) |
 382                   (mbaff_frame_flag << 1) |
 383                   (pic_param->pic_fields.bits.field_pic_flag << 0));
 384     OUT_BCS_BATCH(batch, 0);
 385     OUT_BCS_BATCH(batch, 0);
 386     OUT_BCS_BATCH(batch, 0);
 387     OUT_BCS_BATCH(batch, 0);
 388     OUT_BCS_BATCH(batch, 0);
 389     OUT_BCS_BATCH(batch, 0);
 390     OUT_BCS_BATCH(batch, 0);
 391     OUT_BCS_BATCH(batch, 0);
 392     OUT_BCS_BATCH(batch, 0);
 393     OUT_BCS_BATCH(batch, 0);
 394     OUT_BCS_BATCH(batch, 0);
 395     ADVANCE_BCS_BATCH(batch);
 396 }
 397
 398 static void
 399 gen7_mfd_avc_qm_state(VADriverContextP ctx,
 400                       struct decode_state *decode_state,
 401                       struct gen7_mfd_context *gen7_mfd_context)
 402 {
 403     VAIQMatrixBufferH264 *iq_matrix;
 404     VAPictureParameterBufferH264 *pic_param;
 405
 406     if (decode_state->iq_matrix && decode_state->iq_matrix->buffer)
 407         iq_matrix = (VAIQMatrixBufferH264 *)decode_state->iq_matrix->buffer;
 408     else
 409         iq_matrix = &gen7_mfd_context->iq_matrix.h264;
 410
 411     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 412     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 413
 414     gen7_mfd_qm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, &iq_matrix->ScalingList4x4[0][0], 3 * 16, gen7_mfd_context);
 415     gen7_mfd_qm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, &iq_matrix->ScalingList4x4[3][0], 3 * 16, gen7_mfd_context);
 416
 417     if (pic_param->pic_fields.bits.transform_8x8_mode_flag) {
 418         gen7_mfd_qm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, &iq_matrix->ScalingList8x8[0][0], 64, gen7_mfd_context);
 419         gen7_mfd_qm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, &iq_matrix->ScalingList8x8[1][0], 64, gen7_mfd_context);
 420     }
 421 }
 422
 423 static void
 424 gen7_mfd_avc_directmode_state(VADriverContextP ctx,
 425                               struct decode_state *decode_state,
 426                               VAPictureParameterBufferH264 *pic_param,
 427                               VASliceParameterBufferH264 *slice_param,
 428                               struct gen7_mfd_context *gen7_mfd_context)
 429 {
 430     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 431     struct object_surface *obj_surface;
 432     GenAvcSurface *gen7_avc_surface;
 433     VAPictureH264 *va_pic;
 434     int i;
 435
 436     BEGIN_BCS_BATCH(batch, 69);
 437     OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
 438
 439     /* reference surfaces 0..15 */
 440     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
 441         if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID &&
 442             gen7_mfd_context->reference_surface[i].obj_surface &&
 443             gen7_mfd_context->reference_surface[i].obj_surface->private_data) {
 444
 445             obj_surface = gen7_mfd_context->reference_surface[i].obj_surface;
 446             gen7_avc_surface = obj_surface->private_data;
 447             OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
 448                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 449                           0);
 450
 451             if (gen7_avc_surface->dmv_bottom_flag == 1)
 452                 OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_bottom,
 453                               I915_GEM_DOMAIN_INSTRUCTION, 0,
 454                               0);
 455             else
 456                 OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
 457                               I915_GEM_DOMAIN_INSTRUCTION, 0,
 458                               0);
 459         } else {
 460             OUT_BCS_BATCH(batch, 0);
 461             OUT_BCS_BATCH(batch, 0);
 462         }
 463     }
 464
 465     /* the current decoding frame/field */
 466     va_pic = &pic_param->CurrPic;
 467     obj_surface = decode_state->render_object;
 468     assert(obj_surface->bo && obj_surface->private_data);
 469     gen7_avc_surface = obj_surface->private_data;
 470
 471     OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
 472                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 473                   0);
 474
 475     if (gen7_avc_surface->dmv_bottom_flag == 1)
 476         OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_bottom,
 477                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 478                       0);
 479     else
 480         OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
 481                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 482                       0);
 483
 484     /* POC List */
 485     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
 486         obj_surface = gen7_mfd_context->reference_surface[i].obj_surface;
 487
 488         if (obj_surface) {
 489             const VAPictureH264 * const va_pic = avc_find_picture(
 490                                                      obj_surface->base.id, pic_param->ReferenceFrames,
 491                                                      ARRAY_ELEMS(pic_param->ReferenceFrames));
 492
 493             assert(va_pic != NULL);
 494             OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
 495             OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
 496         } else {
 497             OUT_BCS_BATCH(batch, 0);
 498             OUT_BCS_BATCH(batch, 0);
 499         }
 500     }
 501
 502     va_pic = &pic_param->CurrPic;
 503     OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
 504     OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
 505
 506     ADVANCE_BCS_BATCH(batch);
 507 }
 508
 509 static void
 510 gen7_mfd_avc_phantom_slice_first(VADriverContextP ctx,
 511                                  VAPictureParameterBufferH264 *pic_param,
 512                                  VASliceParameterBufferH264 *next_slice_param,
 513                                  struct gen7_mfd_context *gen7_mfd_context)
 514 {
 515     gen6_mfd_avc_phantom_slice(ctx, pic_param, next_slice_param, gen7_mfd_context->base.batch);
 516 }
 517
 518 static void
 519 gen7_mfd_avc_slice_state(VADriverContextP ctx,
 520                          VAPictureParameterBufferH264 *pic_param,
 521                          VASliceParameterBufferH264 *slice_param,
 522                          VASliceParameterBufferH264 *next_slice_param,
 523                          struct gen7_mfd_context *gen7_mfd_context)
 524 {
 525     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 526     int width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
 527     int height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1;
 528     int slice_hor_pos, slice_ver_pos, next_slice_hor_pos, next_slice_ver_pos;
 529     int num_ref_idx_l0, num_ref_idx_l1;
 530     int mbaff_picture = (!pic_param->pic_fields.bits.field_pic_flag &&
 531                          pic_param->seq_fields.bits.mb_adaptive_frame_field_flag);
 532     int first_mb_in_slice = 0, first_mb_in_next_slice = 0;
 533     int slice_type;
 534
 535     if (slice_param->slice_type == SLICE_TYPE_I ||
 536         slice_param->slice_type == SLICE_TYPE_SI) {
 537         slice_type = SLICE_TYPE_I;
 538     } else if (slice_param->slice_type == SLICE_TYPE_P ||
 539                slice_param->slice_type == SLICE_TYPE_SP) {
 540         slice_type = SLICE_TYPE_P;
 541     } else {
 542         assert(slice_param->slice_type == SLICE_TYPE_B);
 543         slice_type = SLICE_TYPE_B;
 544     }
 545
 546     if (slice_type == SLICE_TYPE_I) {
 547         assert(slice_param->num_ref_idx_l0_active_minus1 == 0);
 548         assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
 549         num_ref_idx_l0 = 0;
 550         num_ref_idx_l1 = 0;
 551     } else if (slice_type == SLICE_TYPE_P) {
 552         assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
 553         num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
 554         num_ref_idx_l1 = 0;
 555     } else {
 556         num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
 557         num_ref_idx_l1 = slice_param->num_ref_idx_l1_active_minus1 + 1;
 558     }
 559
 560     first_mb_in_slice = slice_param->first_mb_in_slice;
 561     slice_hor_pos = first_mb_in_slice % width_in_mbs;
 562     slice_ver_pos = first_mb_in_slice / width_in_mbs;
 563
 564     if (mbaff_picture)
 565         slice_ver_pos = slice_ver_pos << 1;
 566
 567     if (next_slice_param) {
 568         first_mb_in_next_slice = next_slice_param->first_mb_in_slice;
 569         next_slice_hor_pos = first_mb_in_next_slice % width_in_mbs;
 570         next_slice_ver_pos = first_mb_in_next_slice / width_in_mbs;
 571
 572         if (mbaff_picture)
 573             next_slice_ver_pos = next_slice_ver_pos << 1;
 574     } else {
 575         next_slice_hor_pos = 0;
 576         next_slice_ver_pos = height_in_mbs / (1 + !!pic_param->pic_fields.bits.field_pic_flag);
 577     }
 578
 579     BEGIN_BCS_BATCH(batch, 11); /* FIXME: is it 10??? */
 580     OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2));
 581     OUT_BCS_BATCH(batch, slice_type);
 582     OUT_BCS_BATCH(batch,
 583                   (num_ref_idx_l1 << 24) |
 584                   (num_ref_idx_l0 << 16) |
 585                   (slice_param->chroma_log2_weight_denom << 8) |
 586                   (slice_param->luma_log2_weight_denom << 0));
 587     OUT_BCS_BATCH(batch,
 588                   (slice_param->direct_spatial_mv_pred_flag << 29) |
 589                   (slice_param->disable_deblocking_filter_idc << 27) |
 590                   (slice_param->cabac_init_idc << 24) |
 591                   ((pic_param->pic_init_qp_minus26 + 26 + slice_param->slice_qp_delta) << 16) |
 592                   ((slice_param->slice_beta_offset_div2 & 0xf) << 8) |
 593                   ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0));
 594     OUT_BCS_BATCH(batch,
 595                   (slice_ver_pos << 24) |
 596                   (slice_hor_pos << 16) |
 597                   (first_mb_in_slice << 0));
 598     OUT_BCS_BATCH(batch,
 599                   (next_slice_ver_pos << 16) |
 600                   (next_slice_hor_pos << 0));
 601     OUT_BCS_BATCH(batch,
 602                   (next_slice_param == NULL) << 19); /* last slice flag */
 603     OUT_BCS_BATCH(batch, 0);
 604     OUT_BCS_BATCH(batch, 0);
 605     OUT_BCS_BATCH(batch, 0);
 606     OUT_BCS_BATCH(batch, 0);
 607     ADVANCE_BCS_BATCH(batch);
 608 }
 609
 610 static inline void
 611 gen7_mfd_avc_ref_idx_state(VADriverContextP ctx,
 612                            VAPictureParameterBufferH264 *pic_param,
 613                            VASliceParameterBufferH264 *slice_param,
 614                            struct gen7_mfd_context *gen7_mfd_context)
 615 {
 616     gen6_send_avc_ref_idx_state(
 617         gen7_mfd_context->base.batch,
 618         slice_param,
 619         gen7_mfd_context->reference_surface
 620     );
 621 }
 622
 623 static void
 624 gen7_mfd_avc_weightoffset_state(VADriverContextP ctx,
 625                                 VAPictureParameterBufferH264 *pic_param,
 626                                 VASliceParameterBufferH264 *slice_param,
 627                                 struct gen7_mfd_context *gen7_mfd_context)
 628 {
 629     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 630     int i, j, num_weight_offset_table = 0;
 631     short weightoffsets[32 * 6];
 632
 633     if ((slice_param->slice_type == SLICE_TYPE_P ||
 634          slice_param->slice_type == SLICE_TYPE_SP) &&
 635         (pic_param->pic_fields.bits.weighted_pred_flag == 1)) {
 636         num_weight_offset_table = 1;
 637     }
 638
 639     if ((slice_param->slice_type == SLICE_TYPE_B) &&
 640         (pic_param->pic_fields.bits.weighted_bipred_idc == 1)) {
 641         num_weight_offset_table = 2;
 642     }
 643
 644     for (i = 0; i < num_weight_offset_table; i++) {
 645         BEGIN_BCS_BATCH(batch, 98);
 646         OUT_BCS_BATCH(batch, MFX_AVC_WEIGHTOFFSET_STATE | (98 - 2));
 647         OUT_BCS_BATCH(batch, i);
 648
 649         if (i == 0) {
 650             for (j = 0; j < 32; j++) {
 651                 weightoffsets[j * 6 + 0] = slice_param->luma_weight_l0[j];
 652                 weightoffsets[j * 6 + 1] = slice_param->luma_offset_l0[j];
 653                 weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l0[j][0];
 654                 weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l0[j][0];
 655                 weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l0[j][1];
 656                 weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l0[j][1];
 657             }
 658         } else {
 659             for (j = 0; j < 32; j++) {
 660                 weightoffsets[j * 6 + 0] = slice_param->luma_weight_l1[j];
 661                 weightoffsets[j * 6 + 1] = slice_param->luma_offset_l1[j];
 662                 weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l1[j][0];
 663                 weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l1[j][0];
 664                 weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l1[j][1];
 665                 weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l1[j][1];
 666             }
 667         }
 668
 669         intel_batchbuffer_data(batch, weightoffsets, sizeof(weightoffsets));
 670         ADVANCE_BCS_BATCH(batch);
 671     }
 672 }
 673
 674 static void
 675 gen7_mfd_avc_bsd_object(VADriverContextP ctx,
 676                         VAPictureParameterBufferH264 *pic_param,
 677                         VASliceParameterBufferH264 *slice_param,
 678                         dri_bo *slice_data_bo,
 679                         VASliceParameterBufferH264 *next_slice_param,
 680                         struct gen7_mfd_context *gen7_mfd_context)
 681 {
 682     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 683     unsigned int slice_data_bit_offset;
 684
 685     slice_data_bit_offset = avc_get_first_mb_bit_offset(
 686                                 slice_data_bo,
 687                                 slice_param,
 688                                 pic_param->pic_fields.bits.entropy_coding_mode_flag
 689                             );
 690
 691     /* the input bitsteam format on GEN7 differs from GEN6 */
 692     BEGIN_BCS_BATCH(batch, 6);
 693     OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2));
 694     OUT_BCS_BATCH(batch,
 695                   (slice_param->slice_data_size - slice_param->slice_data_offset));
 696     OUT_BCS_BATCH(batch, slice_param->slice_data_offset);
 697     OUT_BCS_BATCH(batch,
 698                   (0 << 31) |
 699                   (0 << 14) |
 700                   (0 << 12) |
 701                   (0 << 10) |
 702                   (0 << 8));
 703     OUT_BCS_BATCH(batch,
 704                   ((slice_data_bit_offset >> 3) << 16) |
 705                   (1 << 7)  |
 706                   (0 << 5)  |
 707                   (0 << 4)  |
 708                   ((next_slice_param == NULL) << 3) | /* LastSlice Flag */
 709                   (slice_data_bit_offset & 0x7));
 710     OUT_BCS_BATCH(batch, 0);
 711     ADVANCE_BCS_BATCH(batch);
 712 }
 713
 714 static inline void
 715 gen7_mfd_avc_context_init(
 716     VADriverContextP         ctx,
 717     struct gen7_mfd_context *gen7_mfd_context
 718 )
 719 {
 720     /* Initialize flat scaling lists */
 721     avc_gen_default_iq_matrix(&gen7_mfd_context->iq_matrix.h264);
 722 }
 723
 724 static void
 725 gen7_mfd_avc_decode_init(VADriverContextP ctx,
 726                          struct decode_state *decode_state,
 727                          struct gen7_mfd_context *gen7_mfd_context)
 728 {
 729     VAPictureParameterBufferH264 *pic_param;
 730     VASliceParameterBufferH264 *slice_param;
 731     struct i965_driver_data *i965 = i965_driver_data(ctx);
 732     struct object_surface *obj_surface;
 733     dri_bo *bo;
 734     int i, j, enable_avc_ildb = 0;
 735     unsigned int width_in_mbs, height_in_mbs;
 736
 737     for (j = 0; j < decode_state->num_slice_params && enable_avc_ildb == 0; j++) {
 738         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
 739         slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
 740
 741         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
 742             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
 743             assert((slice_param->slice_type == SLICE_TYPE_I) ||
 744                    (slice_param->slice_type == SLICE_TYPE_SI) ||
 745                    (slice_param->slice_type == SLICE_TYPE_P) ||
 746                    (slice_param->slice_type == SLICE_TYPE_SP) ||
 747                    (slice_param->slice_type == SLICE_TYPE_B));
 748
 749             if (slice_param->disable_deblocking_filter_idc != 1) {
 750                 enable_avc_ildb = 1;
 751                 break;
 752             }
 753
 754             slice_param++;
 755         }
 756     }
 757
 758     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 759     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 760     intel_update_avc_frame_store_index(ctx, decode_state, pic_param,
 761                                        gen7_mfd_context->reference_surface, &gen7_mfd_context->fs_ctx);
 762     width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
 763     height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1;
 764     assert(width_in_mbs > 0 && width_in_mbs <= 256); /* 4K */
 765     assert(height_in_mbs > 0 && height_in_mbs <= 256);
 766
 767     /* Current decoded picture */
 768     obj_surface = decode_state->render_object;
 769     if (pic_param->pic_fields.bits.reference_pic_flag)
 770         obj_surface->flags |= SURFACE_REFERENCED;
 771     else
 772         obj_surface->flags &= ~SURFACE_REFERENCED;
 773
 774     avc_ensure_surface_bo(ctx, decode_state, obj_surface, pic_param);
 775     gen7_mfd_init_avc_surface(ctx, pic_param, obj_surface);
 776
 777     dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo);
 778     gen7_mfd_context->post_deblocking_output.bo = obj_surface->bo;
 779     dri_bo_reference(gen7_mfd_context->post_deblocking_output.bo);
 780     gen7_mfd_context->post_deblocking_output.valid = enable_avc_ildb;
 781
 782     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
 783     gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
 784     dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
 785     gen7_mfd_context->pre_deblocking_output.valid = !enable_avc_ildb;
 786
 787     dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo);
 788     bo = dri_bo_alloc(i965->intel.bufmgr,
 789                       "intra row store",
 790                       width_in_mbs * 64,
 791                       0x1000);
 792     assert(bo);
 793     gen7_mfd_context->intra_row_store_scratch_buffer.bo = bo;
 794     gen7_mfd_context->intra_row_store_scratch_buffer.valid = 1;
 795
 796     dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
 797     bo = dri_bo_alloc(i965->intel.bufmgr,
 798                       "deblocking filter row store",
 799                       width_in_mbs * 64 * 4,
 800                       0x1000);
 801     assert(bo);
 802     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
 803     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1;
 804
 805     dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
 806     bo = dri_bo_alloc(i965->intel.bufmgr,
 807                       "bsd mpc row store",
 808                       width_in_mbs * 64 * 2,
 809                       0x1000);
 810     assert(bo);
 811     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
 812     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
 813
 814     dri_bo_unreference(gen7_mfd_context->mpr_row_store_scratch_buffer.bo);
 815     bo = dri_bo_alloc(i965->intel.bufmgr,
 816                       "mpr row store",
 817                       width_in_mbs * 64 * 2,
 818                       0x1000);
 819     assert(bo);
 820     gen7_mfd_context->mpr_row_store_scratch_buffer.bo = bo;
 821     gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 1;
 822
 823     gen7_mfd_context->bitplane_read_buffer.valid = 0;
 824 }
 825
 826 static void
 827 gen7_mfd_avc_decode_picture(VADriverContextP ctx,
 828                             struct decode_state *decode_state,
 829                             struct gen7_mfd_context *gen7_mfd_context)
 830 {
 831     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 832     VAPictureParameterBufferH264 *pic_param;
 833     VASliceParameterBufferH264 *slice_param, *next_slice_param, *next_slice_group_param;
 834     dri_bo *slice_data_bo;
 835     int i, j;
 836
 837     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 838     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 839     gen7_mfd_avc_decode_init(ctx, decode_state, gen7_mfd_context);
 840
 841     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
 842     intel_batchbuffer_emit_mi_flush(batch);
 843     gen7_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
 844     gen7_mfd_surface_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
 845     gen7_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
 846     gen7_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
 847     gen7_mfd_avc_qm_state(ctx, decode_state, gen7_mfd_context);
 848     gen7_mfd_avc_img_state(ctx, decode_state, gen7_mfd_context);
 849
 850     for (j = 0; j < decode_state->num_slice_params; j++) {
 851         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
 852         slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
 853         slice_data_bo = decode_state->slice_datas[j]->bo;
 854         gen7_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_AVC, gen7_mfd_context);
 855
 856         if (j == decode_state->num_slice_params - 1)
 857             next_slice_group_param = NULL;
 858         else
 859             next_slice_group_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j + 1]->buffer;
 860
 861         if (j == 0 && slice_param->first_mb_in_slice)
 862             gen7_mfd_avc_phantom_slice_first(ctx, pic_param, slice_param, gen7_mfd_context);
 863
 864         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
 865             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
 866             assert((slice_param->slice_type == SLICE_TYPE_I) ||
 867                    (slice_param->slice_type == SLICE_TYPE_SI) ||
 868                    (slice_param->slice_type == SLICE_TYPE_P) ||
 869                    (slice_param->slice_type == SLICE_TYPE_SP) ||
 870                    (slice_param->slice_type == SLICE_TYPE_B));
 871
 872             if (i < decode_state->slice_params[j]->num_elements - 1)
 873                 next_slice_param = slice_param + 1;
 874             else
 875                 next_slice_param = next_slice_group_param;
 876
 877             gen7_mfd_avc_directmode_state(ctx, decode_state, pic_param, slice_param, gen7_mfd_context);
 878             gen7_mfd_avc_ref_idx_state(ctx, pic_param, slice_param, gen7_mfd_context);
 879             gen7_mfd_avc_weightoffset_state(ctx, pic_param, slice_param, gen7_mfd_context);
 880             gen7_mfd_avc_slice_state(ctx, pic_param, slice_param, next_slice_param, gen7_mfd_context);
 881             gen7_mfd_avc_bsd_object(ctx, pic_param, slice_param, slice_data_bo, next_slice_param, gen7_mfd_context);
 882             slice_param++;
 883         }
 884     }
 885
 886     intel_batchbuffer_end_atomic(batch);
 887     intel_batchbuffer_flush(batch);
 888 }
 889
 890 static void
 891 gen7_mfd_mpeg2_decode_init(VADriverContextP ctx,
 892                            struct decode_state *decode_state,
 893                            struct gen7_mfd_context *gen7_mfd_context)
 894 {
 895     VAPictureParameterBufferMPEG2 *pic_param;
 896     struct i965_driver_data *i965 = i965_driver_data(ctx);
 897     struct object_surface *obj_surface;
 898     dri_bo *bo;
 899     unsigned int width_in_mbs;
 900
 901     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 902     pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
 903     width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16;
 904
 905     mpeg2_set_reference_surfaces(
 906         ctx,
 907         gen7_mfd_context->reference_surface,
 908         decode_state,
 909         pic_param
 910     );
 911
 912     /* Current decoded picture */
 913     obj_surface = decode_state->render_object;
 914     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
 915
 916     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
 917     gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
 918     dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
 919     gen7_mfd_context->pre_deblocking_output.valid = 1;
 920
 921     dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
 922     bo = dri_bo_alloc(i965->intel.bufmgr,
 923                       "bsd mpc row store",
 924                       width_in_mbs * 96,
 925                       0x1000);
 926     assert(bo);
 927     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
 928     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
 929
 930     gen7_mfd_context->post_deblocking_output.valid = 0;
 931     gen7_mfd_context->intra_row_store_scratch_buffer.valid = 0;
 932     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 0;
 933     gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
 934     gen7_mfd_context->bitplane_read_buffer.valid = 0;
 935 }
 936
 937 static void
 938 gen7_mfd_mpeg2_pic_state(VADriverContextP ctx,
 939                          struct decode_state *decode_state,
 940                          struct gen7_mfd_context *gen7_mfd_context)
 941 {
 942     struct i965_driver_data * const i965 = i965_driver_data(ctx);
 943     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 944     VAPictureParameterBufferMPEG2 *pic_param;
 945     unsigned int slice_concealment_disable_bit = 0;
 946
 947     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 948     pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
 949
 950     if (IS_HASWELL(i965->intel.device_info)) {
 951         /* XXX: disable concealment for now */
 952         slice_concealment_disable_bit = 1;
 953     }
 954
 955     BEGIN_BCS_BATCH(batch, 13);
 956     OUT_BCS_BATCH(batch, MFX_MPEG2_PIC_STATE | (13 - 2));
 957     OUT_BCS_BATCH(batch,
 958                   (pic_param->f_code & 0xf) << 28 | /* f_code[1][1] */
 959                   ((pic_param->f_code >> 4) & 0xf) << 24 | /* f_code[1][0] */
 960                   ((pic_param->f_code >> 8) & 0xf) << 20 | /* f_code[0][1] */
 961                   ((pic_param->f_code >> 12) & 0xf) << 16 | /* f_code[0][0] */
 962                   pic_param->picture_coding_extension.bits.intra_dc_precision << 14 |
 963                   pic_param->picture_coding_extension.bits.picture_structure << 12 |
 964                   pic_param->picture_coding_extension.bits.top_field_first << 11 |
 965                   pic_param->picture_coding_extension.bits.frame_pred_frame_dct << 10 |
 966                   pic_param->picture_coding_extension.bits.concealment_motion_vectors << 9 |
 967                   pic_param->picture_coding_extension.bits.q_scale_type << 8 |
 968                   pic_param->picture_coding_extension.bits.intra_vlc_format << 7 |
 969                   pic_param->picture_coding_extension.bits.alternate_scan << 6);
 970     OUT_BCS_BATCH(batch,
 971                   pic_param->picture_coding_type << 9);
 972     OUT_BCS_BATCH(batch,
 973                   (slice_concealment_disable_bit << 31) |
 974                   ((ALIGN(pic_param->vertical_size, 16) / 16) - 1) << 16 |
 975                   ((ALIGN(pic_param->horizontal_size, 16) / 16) - 1));
 976     OUT_BCS_BATCH(batch, 0);
 977     OUT_BCS_BATCH(batch, 0);
 978     OUT_BCS_BATCH(batch, 0);
 979     OUT_BCS_BATCH(batch, 0);
 980     OUT_BCS_BATCH(batch, 0);
 981     OUT_BCS_BATCH(batch, 0);
 982     OUT_BCS_BATCH(batch, 0);
 983     OUT_BCS_BATCH(batch, 0);
 984     OUT_BCS_BATCH(batch, 0);
 985     ADVANCE_BCS_BATCH(batch);
 986 }
 987
 988 static void
 989 gen7_mfd_mpeg2_qm_state(VADriverContextP ctx,
 990                         struct decode_state *decode_state,
 991                         struct gen7_mfd_context *gen7_mfd_context)
 992 {
 993     VAIQMatrixBufferMPEG2 * const gen_iq_matrix = &gen7_mfd_context->iq_matrix.mpeg2;
 994     int i, j;
 995
 996     /* Update internal QM state */
 997     if (decode_state->iq_matrix && decode_state->iq_matrix->buffer) {
 998         VAIQMatrixBufferMPEG2 * const iq_matrix =
 999             (VAIQMatrixBufferMPEG2 *)decode_state->iq_matrix->buffer;
1000
1001         if (gen_iq_matrix->load_intra_quantiser_matrix == -1 ||
1002             iq_matrix->load_intra_quantiser_matrix) {
1003             gen_iq_matrix->load_intra_quantiser_matrix =
1004                 iq_matrix->load_intra_quantiser_matrix;
1005             if (iq_matrix->load_intra_quantiser_matrix) {
1006                 for (j = 0; j < 64; j++)
1007                     gen_iq_matrix->intra_quantiser_matrix[zigzag_direct[j]] =
1008                         iq_matrix->intra_quantiser_matrix[j];
1009             }
1010         }
1011
1012         if (gen_iq_matrix->load_non_intra_quantiser_matrix == -1 ||
1013             iq_matrix->load_non_intra_quantiser_matrix) {
1014             gen_iq_matrix->load_non_intra_quantiser_matrix =
1015                 iq_matrix->load_non_intra_quantiser_matrix;
1016             if (iq_matrix->load_non_intra_quantiser_matrix) {
1017                 for (j = 0; j < 64; j++)
1018                     gen_iq_matrix->non_intra_quantiser_matrix[zigzag_direct[j]] =
1019                         iq_matrix->non_intra_quantiser_matrix[j];
1020             }
1021         }
1022     }
1023
1024     /* Commit QM state to HW */
1025     for (i = 0; i < 2; i++) {
1026         unsigned char *qm = NULL;
1027         int qm_type;
1028
1029         if (i == 0) {
1030             if (gen_iq_matrix->load_intra_quantiser_matrix) {
1031                 qm = gen_iq_matrix->intra_quantiser_matrix;
1032                 qm_type = MFX_QM_MPEG_INTRA_QUANTIZER_MATRIX;
1033             }
1034         } else {
1035             if (gen_iq_matrix->load_non_intra_quantiser_matrix) {
1036                 qm = gen_iq_matrix->non_intra_quantiser_matrix;
1037                 qm_type = MFX_QM_MPEG_NON_INTRA_QUANTIZER_MATRIX;
1038             }
1039         }
1040
1041         if (!qm)
1042             continue;
1043
1044         gen7_mfd_qm_state(ctx, qm_type, qm, 64, gen7_mfd_context);
1045     }
1046 }
1047
1048 uint32_t mpeg2_get_slice_data_length(dri_bo *slice_data_bo, VASliceParameterBufferMPEG2 *slice_param)
1049 {
1050     uint8_t *buf;
1051     uint32_t buf_offset = slice_param->slice_data_offset + (slice_param->macroblock_offset >> 3);
1052     uint32_t buf_size = slice_param->slice_data_size - (slice_param->macroblock_offset >> 3);
1053     uint32_t i = 0;
1054
1055     dri_bo_map(slice_data_bo, 0);
1056     buf = (uint8_t *)slice_data_bo->virtual + buf_offset;
1057
1058     if (buf_size < 4)
1059         return buf_size;
1060
1061     while (i <= (buf_size - 4)) {
1062         if (buf[i + 2] > 1) {
1063             i += 3;
1064         } else if (buf[i + 1]) {
1065             i += 2;
1066         } else if (buf[i] || buf[i + 2] != 1) {
1067             i++;
1068         } else {
1069             break;
1070         }
1071     }
1072
1073     if (i <= (buf_size - 4))
1074         buf_size = i;
1075
1076     dri_bo_unmap(slice_data_bo);
1077     return buf_size;
1078 }
1079
1080 static void
1081 gen7_mfd_mpeg2_bsd_object(VADriverContextP ctx,
1082                           VAPictureParameterBufferMPEG2 *pic_param,
1083                           VASliceParameterBufferMPEG2 *slice_param,
1084                           dri_bo *slice_data_bo,
1085                           VASliceParameterBufferMPEG2 *next_slice_param,
1086                           struct gen7_mfd_context *gen7_mfd_context)
1087 {
1088     struct i965_driver_data * const i965 = i965_driver_data(ctx);
1089     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1090     unsigned int width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16;
1091     int mb_count, vpos0, hpos0, vpos1, hpos1, is_field_pic_wa, is_field_pic = 0;
1092
1093     if (pic_param->picture_coding_extension.bits.picture_structure == MPEG_TOP_FIELD ||
1094         pic_param->picture_coding_extension.bits.picture_structure == MPEG_BOTTOM_FIELD)
1095         is_field_pic = 1;
1096     is_field_pic_wa = is_field_pic &&
1097                       gen7_mfd_context->wa_mpeg2_slice_vertical_position > 0;
1098
1099     vpos0 = slice_param->slice_vertical_position / (1 + is_field_pic_wa);
1100     hpos0 = slice_param->slice_horizontal_position;
1101
1102     if (next_slice_param == NULL) {
1103         vpos1 = ALIGN(pic_param->vertical_size, 16) / 16 / (1 + is_field_pic);
1104         hpos1 = 0;
1105     } else {
1106         vpos1 = next_slice_param->slice_vertical_position / (1 + is_field_pic_wa);
1107         hpos1 = next_slice_param->slice_horizontal_position;
1108     }
1109
1110     mb_count = (vpos1 * width_in_mbs + hpos1) - (vpos0 * width_in_mbs + hpos0);
1111
1112     BEGIN_BCS_BATCH(batch, 5);
1113     OUT_BCS_BATCH(batch, MFD_MPEG2_BSD_OBJECT | (5 - 2));
1114     OUT_BCS_BATCH(batch,
1115                   mpeg2_get_slice_data_length(slice_data_bo, slice_param));
1116     OUT_BCS_BATCH(batch,
1117                   slice_param->slice_data_offset + (slice_param->macroblock_offset >> 3));
1118     OUT_BCS_BATCH(batch,
1119                   hpos0 << 24 |
1120                   vpos0 << 16 |
1121                   mb_count << 8 |
1122                   (next_slice_param == NULL) << 5 |
1123                   (next_slice_param == NULL) << 3 |
1124                   (slice_param->macroblock_offset & 0x7));
1125     OUT_BCS_BATCH(batch,
1126                   (slice_param->quantiser_scale_code << 24) |
1127                   (IS_HASWELL(i965->intel.device_info) ? (vpos1 << 8 | hpos1) : 0));
1128     ADVANCE_BCS_BATCH(batch);
1129 }
1130
1131 static void
1132 gen7_mfd_mpeg2_decode_picture(VADriverContextP ctx,
1133                               struct decode_state *decode_state,
1134                               struct gen7_mfd_context *gen7_mfd_context)
1135 {
1136     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1137     VAPictureParameterBufferMPEG2 *pic_param;
1138     VASliceParameterBufferMPEG2 *slice_param, *next_slice_param, *next_slice_group_param;
1139     dri_bo *slice_data_bo;
1140     int i, j;
1141
1142     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1143     pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
1144
1145     gen7_mfd_mpeg2_decode_init(ctx, decode_state, gen7_mfd_context);
1146     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
1147     intel_batchbuffer_emit_mi_flush(batch);
1148     gen7_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1149     gen7_mfd_surface_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1150     gen7_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1151     gen7_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1152     gen7_mfd_mpeg2_pic_state(ctx, decode_state, gen7_mfd_context);
1153     gen7_mfd_mpeg2_qm_state(ctx, decode_state, gen7_mfd_context);
1154
1155     if (gen7_mfd_context->wa_mpeg2_slice_vertical_position < 0)
1156         gen7_mfd_context->wa_mpeg2_slice_vertical_position =
1157             mpeg2_wa_slice_vertical_position(decode_state, pic_param);
1158
1159     for (j = 0; j < decode_state->num_slice_params; j++) {
1160         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
1161         slice_param = (VASliceParameterBufferMPEG2 *)decode_state->slice_params[j]->buffer;
1162         slice_data_bo = decode_state->slice_datas[j]->bo;
1163         gen7_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_MPEG2, gen7_mfd_context);
1164
1165         if (j == decode_state->num_slice_params - 1)
1166             next_slice_group_param = NULL;
1167         else
1168             next_slice_group_param = (VASliceParameterBufferMPEG2 *)decode_state->slice_params[j + 1]->buffer;
1169
1170         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
1171             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
1172
1173             if (i < decode_state->slice_params[j]->num_elements - 1)
1174                 next_slice_param = slice_param + 1;
1175             else
1176                 next_slice_param = next_slice_group_param;
1177
1178             gen7_mfd_mpeg2_bsd_object(ctx, pic_param, slice_param, slice_data_bo, next_slice_param, gen7_mfd_context);
1179             slice_param++;
1180         }
1181     }
1182
1183     intel_batchbuffer_end_atomic(batch);
1184     intel_batchbuffer_flush(batch);
1185 }
1186
1187 static const int va_to_gen7_vc1_mv[4] = {
1188     1, /* 1-MV */
1189     2, /* 1-MV half-pel */
1190     3, /* 1-MV half-pef bilinear */
1191     0, /* Mixed MV */
1192 };
1193
1194 static const int b_picture_scale_factor[21] = {
1195     128, 85,  170, 64,  192,
1196     51,  102, 153, 204, 43,
1197     215, 37,  74,  111, 148,
1198     185, 222, 32,  96,  160,
1199     224,
1200 };
1201
1202 static const int va_to_gen7_vc1_condover[3] = {
1203     0,
1204     2,
1205     3
1206 };
1207
1208 static const int va_to_gen7_vc1_profile[4] = {
1209     GEN7_VC1_SIMPLE_PROFILE,
1210     GEN7_VC1_MAIN_PROFILE,
1211     GEN7_VC1_RESERVED_PROFILE,
1212     GEN7_VC1_ADVANCED_PROFILE
1213 };
1214
1215 static const int fptype_to_picture_type[8][2] = {
1216     {GEN7_VC1_I_PICTURE, GEN7_VC1_I_PICTURE},
1217     {GEN7_VC1_I_PICTURE, GEN7_VC1_P_PICTURE},
1218     {GEN7_VC1_P_PICTURE, GEN7_VC1_I_PICTURE},
1219     {GEN7_VC1_P_PICTURE, GEN7_VC1_P_PICTURE},
1220     {GEN7_VC1_B_PICTURE, GEN7_VC1_B_PICTURE},
1221     {GEN7_VC1_B_PICTURE, GEN7_VC1_BI_PICTURE},
1222     {GEN7_VC1_BI_PICTURE, GEN7_VC1_B_PICTURE},
1223     {GEN7_VC1_BI_PICTURE, GEN7_VC1_BI_PICTURE}
1224 };
1225
1226 static void
1227 gen7_mfd_free_vc1_surface(void **data)
1228 {
1229     struct gen7_vc1_surface *gen7_vc1_surface = *data;
1230
1231     if (!gen7_vc1_surface)
1232         return;
1233
1234     dri_bo_unreference(gen7_vc1_surface->dmv_top);
1235     dri_bo_unreference(gen7_vc1_surface->dmv_bottom);
1236     free(gen7_vc1_surface);
1237     *data = NULL;
1238 }
1239
1240 static void
1241 gen7_mfd_init_vc1_surface(VADriverContextP ctx,
1242                           VAPictureParameterBufferVC1 *pic_param,
1243                           struct object_surface *obj_surface)
1244 {
1245     struct i965_driver_data *i965 = i965_driver_data(ctx);
1246     struct gen7_vc1_surface *gen7_vc1_surface = obj_surface->private_data;
1247     int height_in_mbs;
1248     int picture_type;
1249     int is_first_field = 1;
1250
1251     if (!pic_param->sequence_fields.bits.interlace ||
1252         (pic_param->picture_fields.bits.frame_coding_mode < 2)) { /* Progressive or Frame-Interlace */
1253         picture_type = pic_param->picture_fields.bits.picture_type;
1254     } else {/* Field-Interlace */
1255         is_first_field = pic_param->picture_fields.bits.is_first_field;
1256         picture_type = fptype_to_picture_type[pic_param->picture_fields.bits.picture_type][!is_first_field];
1257     }
1258
1259     obj_surface->free_private_data = gen7_mfd_free_vc1_surface;
1260
1261     if (!gen7_vc1_surface) {
1262         gen7_vc1_surface = calloc(sizeof(struct gen7_vc1_surface), 1);
1263         assert(gen7_vc1_surface);
1264         assert((obj_surface->size & 0x3f) == 0);
1265         obj_surface->private_data = gen7_vc1_surface;
1266     }
1267
1268     if (!pic_param->sequence_fields.bits.interlace ||
1269         pic_param->picture_fields.bits.frame_coding_mode < 2 || /* Progressive or Frame-Interlace */
1270         is_first_field) {
1271         gen7_vc1_surface->picture_type_top = 0;
1272         gen7_vc1_surface->picture_type_bottom = 0;
1273         gen7_vc1_surface->intensity_compensation_top = 0;
1274         gen7_vc1_surface->intensity_compensation_bottom = 0;
1275         gen7_vc1_surface->luma_scale_top[0] = 0;
1276         gen7_vc1_surface->luma_scale_top[1] = 0;
1277         gen7_vc1_surface->luma_scale_bottom[0] = 0;
1278         gen7_vc1_surface->luma_scale_bottom[1] = 0;
1279         gen7_vc1_surface->luma_shift_top[0] = 0;
1280         gen7_vc1_surface->luma_shift_top[1] = 0;
1281         gen7_vc1_surface->luma_shift_bottom[0] = 0;
1282         gen7_vc1_surface->luma_shift_bottom[1] = 0;
1283     }
1284
1285     if (!pic_param->sequence_fields.bits.interlace ||
1286         pic_param->picture_fields.bits.frame_coding_mode < 2) { /* Progressive or Frame-Interlace */
1287         gen7_vc1_surface->picture_type_top = picture_type;
1288         gen7_vc1_surface->picture_type_bottom = picture_type;
1289     } else if (pic_param->picture_fields.bits.top_field_first ^ is_first_field)
1290         gen7_vc1_surface->picture_type_bottom = picture_type;
1291     else
1292         gen7_vc1_surface->picture_type_top = picture_type;
1293
1294     if (gen7_vc1_surface->dmv_top == NULL) {
1295         height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16;
1296         gen7_vc1_surface->dmv_top = dri_bo_alloc(i965->intel.bufmgr,
1297                                              "direct mv w/r buffer",
1298                                              128 * height_in_mbs * 64,
1299                                              0x1000);
1300     }
1301
1302     if (pic_param->sequence_fields.bits.interlace &&
1303         gen7_vc1_surface->dmv_bottom == NULL) {
1304         height_in_mbs = ALIGN(pic_param->coded_height, 32) / 32;
1305         gen7_vc1_surface->dmv_bottom = dri_bo_alloc(i965->intel.bufmgr,
1306                                              "direct mv w/r buffer",
1307                                              128 * height_in_mbs * 64,
1308                                              0x1000);
1309     }
1310 }
1311
1312 static void
1313 gen7_mfd_vc1_decode_init(VADriverContextP ctx,
1314                          struct decode_state *decode_state,
1315                          struct gen7_mfd_context *gen7_mfd_context)
1316 {
1317     VAPictureParameterBufferVC1 *pic_param;
1318     struct i965_driver_data *i965 = i965_driver_data(ctx);
1319     struct object_surface *obj_surface;
1320     struct gen7_vc1_surface *gen7_vc1_current_surface;
1321     struct gen7_vc1_surface *gen7_vc1_forward_surface;
1322     dri_bo *bo;
1323     int width_in_mbs;
1324     int picture_type;
1325     int is_first_field = 1;
1326     int i;
1327
1328     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1329     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1330     width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1331
1332     if (!pic_param->sequence_fields.bits.interlace ||
1333         (pic_param->picture_fields.bits.frame_coding_mode < 2)) { /* Progressive or Frame-Interlace */
1334         picture_type = pic_param->picture_fields.bits.picture_type;
1335     } else {/* Field-Interlace */
1336         is_first_field = pic_param->picture_fields.bits.is_first_field;
1337         picture_type = fptype_to_picture_type[pic_param->picture_fields.bits.picture_type][!is_first_field];
1338     }
1339
1340     /* Current decoded picture */
1341     obj_surface = decode_state->render_object;
1342     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
1343     gen7_mfd_init_vc1_surface(ctx, pic_param, obj_surface);
1344
1345     dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo);
1346     gen7_mfd_context->post_deblocking_output.bo = obj_surface->bo;
1347     dri_bo_reference(gen7_mfd_context->post_deblocking_output.bo);
1348
1349     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
1350     gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
1351     dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
1352
1353     if (picture_type == GEN7_VC1_SKIPPED_PICTURE) {
1354         gen7_mfd_context->post_deblocking_output.valid = 0;
1355         gen7_mfd_context->pre_deblocking_output.valid = 1;
1356     } else {
1357         gen7_mfd_context->post_deblocking_output.valid = pic_param->entrypoint_fields.bits.loopfilter;
1358         gen7_mfd_context->pre_deblocking_output.valid = !pic_param->entrypoint_fields.bits.loopfilter;
1359     }
1360
1361     intel_update_vc1_frame_store_index(ctx,
1362                                        decode_state,
1363                                        pic_param,
1364                                        gen7_mfd_context->reference_surface);
1365
1366     if (picture_type == GEN7_VC1_P_PICTURE) {
1367         obj_surface = decode_state->reference_objects[0];
1368         gen7_vc1_current_surface = (struct gen7_vc1_surface *)(decode_state->render_object->private_data);
1369         if (pic_param->forward_reference_picture != VA_INVALID_ID &&
1370             obj_surface)
1371             gen7_vc1_forward_surface = (struct gen7_vc1_surface *)(obj_surface->private_data);
1372         else
1373             gen7_vc1_forward_surface = NULL;
1374
1375         if (!pic_param->sequence_fields.bits.interlace ||
1376             pic_param->picture_fields.bits.frame_coding_mode == 0) { /* Progressive */
1377             if (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation) {
1378                 if (gen7_vc1_forward_surface) {
1379                     gen7_vc1_forward_surface->intensity_compensation_top = 1;
1380                     gen7_vc1_forward_surface->intensity_compensation_bottom = 1;
1381                     gen7_vc1_forward_surface->luma_scale_top[0] = pic_param->luma_scale;
1382                     gen7_vc1_forward_surface->luma_scale_bottom[0] = pic_param->luma_scale;
1383                     gen7_vc1_forward_surface->luma_shift_top[0] = pic_param->luma_shift;
1384                     gen7_vc1_forward_surface->luma_shift_bottom[0] = pic_param->luma_shift;
1385                 }
1386             }
1387         } else if (pic_param->sequence_fields.bits.interlace &&
1388             pic_param->picture_fields.bits.frame_coding_mode == 1) { /* Frame-Interlace */
1389             if (pic_param->picture_fields.bits.intensity_compensation) {
1390                 if (gen7_vc1_forward_surface) {
1391                     gen7_vc1_forward_surface->intensity_compensation_top = 1;
1392                     gen7_vc1_forward_surface->intensity_compensation_bottom = 1;
1393                     gen7_vc1_forward_surface->luma_scale_top[0] = pic_param->luma_scale;
1394                     gen7_vc1_forward_surface->luma_scale_bottom[0] = pic_param->luma_scale;
1395                     gen7_vc1_forward_surface->luma_shift_top[0] = pic_param->luma_shift;
1396                     gen7_vc1_forward_surface->luma_shift_bottom[0] = pic_param->luma_shift;
1397                 }
1398             }
1399         } else if (pic_param->sequence_fields.bits.interlace &&
1400                    pic_param->picture_fields.bits.frame_coding_mode == 2) { /* Field-Interlace */
1401             if (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation) {
1402                 if (pic_param->intensity_compensation_field == 1 || /* Top field */
1403                     pic_param->intensity_compensation_field == 0) { /* Both fields */
1404                     if (is_first_field) {
1405                         if ((!pic_param->reference_fields.bits.num_reference_pictures &&
1406                              (pic_param->reference_fields.bits.reference_field_pic_indicator ==
1407                              pic_param->picture_fields.bits.top_field_first)) ||
1408                             pic_param->reference_fields.bits.num_reference_pictures) {
1409                             if (gen7_vc1_forward_surface) {
1410                                 i = gen7_vc1_forward_surface->intensity_compensation_top++;
1411                                 gen7_vc1_forward_surface->luma_scale_top[i] = pic_param->luma_scale;
1412                                 gen7_vc1_forward_surface->luma_shift_top[i] = pic_param->luma_shift;
1413                             }
1414                         }
1415                     } else { /* Second field */
1416                         if (pic_param->picture_fields.bits.top_field_first) {
1417                             if ((!pic_param->reference_fields.bits.num_reference_pictures &&
1418                                  !pic_param->reference_fields.bits.reference_field_pic_indicator) ||
1419                                 pic_param->reference_fields.bits.num_reference_pictures) {
1420                                 i = gen7_vc1_current_surface->intensity_compensation_top++;
1421                                 gen7_vc1_current_surface->luma_scale_top[i] = pic_param->luma_scale;
1422                                 gen7_vc1_current_surface->luma_shift_top[i] = pic_param->luma_shift;
1423                             }
1424                         } else {
1425                             if ((!pic_param->reference_fields.bits.num_reference_pictures &&
1426                                  pic_param->reference_fields.bits.reference_field_pic_indicator) ||
1427                                 pic_param->reference_fields.bits.num_reference_pictures) {
1428                                 if (gen7_vc1_forward_surface) {
1429                                     i = gen7_vc1_forward_surface->intensity_compensation_top++;
1430                                     gen7_vc1_forward_surface->luma_scale_top[i] = pic_param->luma_scale;
1431                                     gen7_vc1_forward_surface->luma_shift_top[i] = pic_param->luma_shift;
1432                                 }
1433                             }
1434                         }
1435                     }
1436                 }
1437                 if (pic_param->intensity_compensation_field == 2 || /* Bottom field */
1438                     pic_param->intensity_compensation_field == 0) { /* Both fields */
1439                     if (is_first_field) {
1440                         if ((!pic_param->reference_fields.bits.num_reference_pictures &&
1441                              (pic_param->reference_fields.bits.reference_field_pic_indicator ^
1442                               pic_param->picture_fields.bits.top_field_first)) ||
1443                             pic_param->reference_fields.bits.num_reference_pictures) {
1444                             if (gen7_vc1_forward_surface) {
1445                                 i = gen7_vc1_forward_surface->intensity_compensation_bottom++;
1446                                 if (pic_param->intensity_compensation_field == 2) { /* Bottom field */
1447                                     gen7_vc1_forward_surface->luma_scale_bottom[i] = pic_param->luma_scale;
1448                                     gen7_vc1_forward_surface->luma_shift_bottom[i] = pic_param->luma_shift;
1449                                 } else { /* Both fields */
1450                                     gen7_vc1_forward_surface->luma_scale_bottom[i] = pic_param->luma_scale2;
1451                                     gen7_vc1_forward_surface->luma_shift_bottom[i] = pic_param->luma_shift2;
1452                                 }
1453                             }
1454                         }
1455                     } else { /* Second field */
1456                         if (pic_param->picture_fields.bits.top_field_first) {
1457                             if ((!pic_param->reference_fields.bits.num_reference_pictures &&
1458                                  pic_param->reference_fields.bits.reference_field_pic_indicator) ||
1459                                 pic_param->reference_fields.bits.num_reference_pictures) {
1460                                 if (gen7_vc1_forward_surface) {
1461                                     i = gen7_vc1_forward_surface->intensity_compensation_bottom++;
1462                                     if (pic_param->intensity_compensation_field == 2) { /* Bottom field */
1463                                         gen7_vc1_forward_surface->luma_scale_bottom[i] = pic_param->luma_scale;
1464                                         gen7_vc1_forward_surface->luma_shift_bottom[i] = pic_param->luma_shift;
1465                                     } else { /* Both fields */
1466                                         gen7_vc1_forward_surface->luma_scale_bottom[i] = pic_param->luma_scale2;
1467                                         gen7_vc1_forward_surface->luma_shift_bottom[i] = pic_param->luma_shift2;
1468                                     }
1469                                 }
1470                             }
1471                         } else {
1472                            if ((!pic_param->reference_fields.bits.num_reference_pictures &&
1473                                  !pic_param->reference_fields.bits.reference_field_pic_indicator) ||
1474                                 pic_param->reference_fields.bits.num_reference_pictures) {
1475                                 i = gen7_vc1_current_surface->intensity_compensation_bottom++;
1476                                if (pic_param->intensity_compensation_field == 2) { /* Bottom field */
1477                                    gen7_vc1_current_surface->luma_scale_bottom[i] = pic_param->luma_scale;
1478                                    gen7_vc1_current_surface->luma_shift_bottom[i] = pic_param->luma_shift;
1479                                 } else { /* Both fields */
1480                                     gen7_vc1_current_surface->luma_scale_bottom[i] = pic_param->luma_scale2;
1481                                     gen7_vc1_current_surface->luma_shift_bottom[i] = pic_param->luma_shift2;
1482                                 }
1483                             }
1484                         }
1485                     }
1486                 }
1487             }
1488         }
1489     }
1490
1491     dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo);
1492     bo = dri_bo_alloc(i965->intel.bufmgr,
1493                       "intra row store",
1494                       width_in_mbs * 64,
1495                       0x1000);
1496     assert(bo);
1497     gen7_mfd_context->intra_row_store_scratch_buffer.bo = bo;
1498     gen7_mfd_context->intra_row_store_scratch_buffer.valid = 1;
1499
1500     dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
1501     bo = dri_bo_alloc(i965->intel.bufmgr,
1502                       "deblocking filter row store",
1503                       width_in_mbs * 7 * 64,
1504                       0x1000);
1505     assert(bo);
1506     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
1507     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1;
1508
1509     dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
1510     bo = dri_bo_alloc(i965->intel.bufmgr,
1511                       "bsd mpc row store",
1512                       width_in_mbs * 96,
1513                       0x1000);
1514     assert(bo);
1515     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
1516     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
1517
1518     gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
1519
1520     if (picture_type == GEN7_VC1_SKIPPED_PICTURE)
1521         gen7_mfd_context->bitplane_read_buffer.valid = 1;
1522     else
1523         gen7_mfd_context->bitplane_read_buffer.valid = !!(pic_param->bitplane_present.value & 0x7f);
1524     dri_bo_unreference(gen7_mfd_context->bitplane_read_buffer.bo);
1525
1526     if (gen7_mfd_context->bitplane_read_buffer.valid) {
1527         int width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1528         int height_in_mbs;
1529         int bitplane_width = ALIGN(width_in_mbs, 2) / 2;
1530         int src_w, src_h;
1531         uint8_t *src = NULL, *dst = NULL;
1532
1533         if (!pic_param->sequence_fields.bits.interlace ||
1534             (pic_param->picture_fields.bits.frame_coding_mode < 2)) /* Progressive or Frame-Interlace */
1535             height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16;
1536         else /* Field-Interlace */
1537             height_in_mbs = ALIGN(pic_param->coded_height, 32) / 32;
1538
1539         bo = dri_bo_alloc(i965->intel.bufmgr,
1540                           "VC-1 Bitplane",
1541                           bitplane_width * height_in_mbs,
1542                           0x1000);
1543         assert(bo);
1544         gen7_mfd_context->bitplane_read_buffer.bo = bo;
1545
1546         dri_bo_map(bo, True);
1547         assert(bo->virtual);
1548         dst = bo->virtual;
1549
1550         if (picture_type == GEN7_VC1_SKIPPED_PICTURE) {
1551             for (src_h = 0; src_h < height_in_mbs; src_h++) {
1552                 for (src_w = 0; src_w < width_in_mbs; src_w++) {
1553                     int dst_index;
1554                     uint8_t src_value = 0x2;
1555
1556                     dst_index = src_w / 2;
1557                     dst[dst_index] = ((dst[dst_index] >> 4) | (src_value << 4));
1558                 }
1559
1560                 if (src_w & 1)
1561                     dst[src_w / 2] >>= 4;
1562
1563                 dst += bitplane_width;
1564             }
1565         } else {
1566             assert(decode_state->bit_plane->buffer);
1567             src = decode_state->bit_plane->buffer;
1568
1569             for (src_h = 0; src_h < height_in_mbs; src_h++) {
1570                 for (src_w = 0; src_w < width_in_mbs; src_w++) {
1571                     int src_index, dst_index;
1572                     int src_shift;
1573                     uint8_t src_value;
1574
1575                     src_index = (src_h * width_in_mbs + src_w) / 2;
1576                     src_shift = !((src_h * width_in_mbs + src_w) & 1) * 4;
1577                     src_value = ((src[src_index] >> src_shift) & 0xf);
1578
1579                     dst_index = src_w / 2;
1580                     dst[dst_index] = ((dst[dst_index] >> 4) | (src_value << 4));
1581                 }
1582
1583                 if (src_w & 1)
1584                     dst[src_w / 2] >>= 4;
1585
1586                 dst += bitplane_width;
1587             }
1588         }
1589
1590         dri_bo_unmap(bo);
1591     } else
1592         gen7_mfd_context->bitplane_read_buffer.bo = NULL;
1593 }
1594
1595 static void
1596 gen7_mfd_vc1_pic_state(VADriverContextP ctx,
1597                        struct decode_state *decode_state,
1598                        struct gen7_mfd_context *gen7_mfd_context)
1599 {
1600     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1601     VAPictureParameterBufferVC1 *pic_param;
1602     struct object_surface *obj_surface;
1603     struct gen7_vc1_surface *gen7_vc1_surface;
1604     int alt_pquant_config = 0, alt_pquant_edge_mask = 0, alt_pq;
1605     int dquant, dquantfrm, dqprofile, dqdbedge, dqsbedge, dqbilevel;
1606     int unified_mv_mode = 0;
1607     int ref_field_pic_polarity = 0;
1608     int scale_factor = 0;
1609     int trans_ac_y = 0;
1610     int dmv_surface_valid = 0;
1611     int frfd = 0;
1612     int brfd = 0;
1613     int fcm = 0;
1614     int picture_type;
1615     int ptype;
1616     int profile;
1617     int overlap = 0;
1618     int interpolation_mode = 0;
1619     int height_in_mbs;
1620     int is_first_field = 1;
1621     int loopfilter = 0;
1622     int bitplane_present;
1623     int forward_mb = 0, mv_type_mb = 0, skip_mb = 0, direct_mb = 0;
1624     int overflags = 0, ac_pred = 0, field_tx = 0;
1625
1626     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1627     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1628
1629     if (!pic_param->sequence_fields.bits.interlace ||
1630         (pic_param->picture_fields.bits.frame_coding_mode < 2)) { /* Progressive or Frame-Interlace */
1631         picture_type = pic_param->picture_fields.bits.picture_type;
1632         height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16;
1633     } else {/* Field-Interlace */
1634         is_first_field = pic_param->picture_fields.bits.is_first_field;
1635         picture_type = fptype_to_picture_type[pic_param->picture_fields.bits.picture_type][!is_first_field];
1636         height_in_mbs = ALIGN(pic_param->coded_height, 32) / 32;
1637     }
1638
1639     profile = va_to_gen7_vc1_profile[pic_param->sequence_fields.bits.profile];
1640     dquant = pic_param->pic_quantizer_fields.bits.dquant;
1641     dquantfrm = pic_param->pic_quantizer_fields.bits.dq_frame;
1642     dqprofile = pic_param->pic_quantizer_fields.bits.dq_profile;
1643     dqdbedge = pic_param->pic_quantizer_fields.bits.dq_db_edge;
1644     dqsbedge = pic_param->pic_quantizer_fields.bits.dq_sb_edge;
1645     dqbilevel = pic_param->pic_quantizer_fields.bits.dq_binary_level;
1646     alt_pq = pic_param->pic_quantizer_fields.bits.alt_pic_quantizer;
1647
1648     if (dquant == 0) {
1649         alt_pquant_config = 0;
1650         alt_pquant_edge_mask = 0;
1651     } else if (dquant == 2) {
1652         alt_pquant_config = 1;
1653         alt_pquant_edge_mask = 0xf;
1654     } else {
1655         assert(dquant == 1);
1656         if (dquantfrm == 0) {
1657             alt_pquant_config = 0;
1658             alt_pquant_edge_mask = 0;
1659             alt_pq = 0;
1660         } else {
1661             assert(dquantfrm == 1);
1662             alt_pquant_config = 1;
1663
1664             switch (dqprofile) {
1665             case 3:
1666                 if (dqbilevel == 0) {
1667                     alt_pquant_config = 2;
1668                     alt_pquant_edge_mask = 0;
1669                 } else {
1670                     assert(dqbilevel == 1);
1671                     alt_pquant_config = 3;
1672                     alt_pquant_edge_mask = 0;
1673                 }
1674                 break;
1675
1676             case 0:
1677                 alt_pquant_edge_mask = 0xf;
1678                 break;
1679
1680             case 1:
1681                 if (dqdbedge == 3)
1682                     alt_pquant_edge_mask = 0x9;
1683                 else
1684                     alt_pquant_edge_mask = (0x3 << dqdbedge);
1685
1686                 break;
1687
1688             case 2:
1689                 alt_pquant_edge_mask = (0x1 << dqsbedge);
1690                 break;
1691
1692             default:
1693                 assert(0);
1694             }
1695         }
1696     }
1697
1698     if ((!pic_param->sequence_fields.bits.interlace ||
1699          pic_param->picture_fields.bits.frame_coding_mode != 1) && /* Progressive or Field-Interlace */
1700         (picture_type == GEN7_VC1_P_PICTURE ||
1701          picture_type == GEN7_VC1_B_PICTURE)) {
1702         if (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation) {
1703             assert(pic_param->mv_fields.bits.mv_mode2 < 4);
1704             unified_mv_mode = va_to_gen7_vc1_mv[pic_param->mv_fields.bits.mv_mode2];
1705         } else {
1706             assert(pic_param->mv_fields.bits.mv_mode < 4);
1707             unified_mv_mode = va_to_gen7_vc1_mv[pic_param->mv_fields.bits.mv_mode];
1708         }
1709     }
1710
1711     if (pic_param->sequence_fields.bits.interlace &&
1712         pic_param->picture_fields.bits.frame_coding_mode == 2 && /* Field-Interlace */
1713         picture_type == GEN7_VC1_P_PICTURE &&
1714         !pic_param->reference_fields.bits.num_reference_pictures) {
1715         if (pic_param->reference_fields.bits.reference_field_pic_indicator == 0) {
1716             ref_field_pic_polarity = is_first_field ?
1717                                         pic_param->picture_fields.bits.top_field_first :
1718                                         !pic_param->picture_fields.bits.top_field_first;
1719         } else {
1720             ref_field_pic_polarity = is_first_field ?
1721                                         !pic_param->picture_fields.bits.top_field_first :
1722                                         pic_param->picture_fields.bits.top_field_first;
1723         }
1724     }
1725
1726     if (pic_param->b_picture_fraction < 21)
1727         scale_factor = b_picture_scale_factor[pic_param->b_picture_fraction];
1728
1729     if (picture_type == GEN7_VC1_SKIPPED_PICTURE) {
1730         ptype = GEN7_VC1_P_PICTURE;
1731         bitplane_present = 1;
1732     } else {
1733         ptype = pic_param->picture_fields.bits.picture_type;
1734         bitplane_present = !!(pic_param->bitplane_present.value & 0x7f);
1735         forward_mb = pic_param->raw_coding.flags.forward_mb;
1736         mv_type_mb = pic_param->raw_coding.flags.mv_type_mb;
1737         skip_mb = pic_param->raw_coding.flags.skip_mb;
1738         direct_mb = pic_param->raw_coding.flags.direct_mb;
1739         overflags = pic_param->raw_coding.flags.overflags;
1740         ac_pred = pic_param->raw_coding.flags.ac_pred;
1741         field_tx = pic_param->raw_coding.flags.field_tx;
1742         loopfilter = pic_param->entrypoint_fields.bits.loopfilter;
1743     }
1744
1745     if (picture_type == GEN7_VC1_I_PICTURE || picture_type == GEN7_VC1_BI_PICTURE) /* I picture */
1746         trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx2;
1747     else {
1748         trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx1;
1749         /*
1750          * 8.3.6.2.1 Transform Type Selection
1751          * If variable-sized transform coding is not enabled,
1752          * then the 8x8 transform shall be used for all blocks.
1753          * it is also MFX_VC1_PIC_STATE requirement.
1754          */
1755         if (pic_param->transform_fields.bits.variable_sized_transform_flag == 0) {
1756             pic_param->transform_fields.bits.mb_level_transform_type_flag   = 1;
1757             pic_param->transform_fields.bits.frame_level_transform_type     = 0;
1758         }
1759     }
1760
1761     if (picture_type == GEN7_VC1_B_PICTURE) {
1762         obj_surface = decode_state->reference_objects[1];
1763
1764         if (pic_param->backward_reference_picture != VA_INVALID_ID &&
1765             obj_surface)
1766             gen7_vc1_surface = (struct gen7_vc1_surface *)(obj_surface->private_data);
1767         else
1768             gen7_vc1_surface = NULL;
1769
1770         if (gen7_vc1_surface) {
1771             if (pic_param->sequence_fields.bits.interlace &&
1772                 pic_param->picture_fields.bits.frame_coding_mode == 2 && /* Field-Interlace */
1773                 pic_param->picture_fields.bits.top_field_first ^ is_first_field) {
1774                 if (gen7_vc1_surface->picture_type_bottom == GEN7_VC1_P_PICTURE)
1775                     dmv_surface_valid = 1;
1776             } else if (gen7_vc1_surface->picture_type_top == GEN7_VC1_P_PICTURE)
1777                 dmv_surface_valid = 1;
1778         }
1779     }
1780
1781     assert(pic_param->picture_fields.bits.frame_coding_mode < 3);
1782
1783     if (pic_param->sequence_fields.bits.interlace) {
1784         if (!pic_param->picture_fields.bits.top_field_first)
1785             fcm = 3;
1786         else
1787             fcm = pic_param->picture_fields.bits.frame_coding_mode;
1788     }
1789
1790     if (pic_param->sequence_fields.bits.interlace &&
1791         pic_param->picture_fields.bits.frame_coding_mode == 2) { /* Field-Interlace */
1792         if (picture_type == GEN7_VC1_I_PICTURE ||
1793              picture_type == GEN7_VC1_P_PICTURE) {
1794             gen7_vc1_surface = (struct gen7_vc1_surface *)(decode_state->render_object->private_data);
1795
1796             if (is_first_field)
1797                 gen7_vc1_surface->reference_distance = pic_param->reference_fields.bits.reference_distance;
1798
1799             frfd = gen7_vc1_surface->reference_distance;
1800         } else if (picture_type == GEN7_VC1_B_PICTURE) {
1801             obj_surface = decode_state->reference_objects[1];
1802
1803             if (pic_param->backward_reference_picture != VA_INVALID_ID &&
1804                 obj_surface)
1805                 gen7_vc1_surface = (struct gen7_vc1_surface *)(obj_surface->private_data);
1806             else
1807                 gen7_vc1_surface = NULL;
1808
1809             if (gen7_vc1_surface) {
1810                 frfd = (scale_factor * gen7_vc1_surface->reference_distance) >> 8;
1811
1812                 brfd = gen7_vc1_surface->reference_distance - frfd - 1;
1813                 if (brfd < 0)
1814                     brfd = 0;
1815             }
1816         }
1817     }
1818
1819     if (pic_param->sequence_fields.bits.overlap) {
1820         if (profile == GEN7_VC1_ADVANCED_PROFILE) {
1821             if (picture_type == GEN7_VC1_P_PICTURE &&
1822                 pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9) {
1823                 overlap = 1;
1824             }
1825             if (picture_type == GEN7_VC1_I_PICTURE ||
1826                 picture_type == GEN7_VC1_BI_PICTURE) {
1827                 if (pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9) {
1828                     overlap = 1;
1829                 } else if (pic_param->conditional_overlap_flag == 1 || /* all block boundaries */
1830                            pic_param->conditional_overlap_flag == 2) { /* coded by OVERFLAGSMB bitplane */
1831                     overlap = 1;
1832                 }
1833             }
1834         } else {
1835             if (pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9 &&
1836                 picture_type != GEN7_VC1_B_PICTURE) {
1837                 overlap = 1;
1838             }
1839         }
1840     }
1841
1842     if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPelBilinear ||
1843         (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation &&
1844          pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPelBilinear))
1845         interpolation_mode = 8 | pic_param->fast_uvmc_flag;
1846     else
1847         interpolation_mode = 0 | pic_param->fast_uvmc_flag;
1848
1849     BEGIN_BCS_BATCH(batch, 6);
1850     OUT_BCS_BATCH(batch, MFD_VC1_LONG_PIC_STATE | (6 - 2));
1851     OUT_BCS_BATCH(batch,
1852                   ((height_in_mbs - 1) << 16) |
1853                   ((ALIGN(pic_param->coded_width, 16) / 16) - 1));
1854     OUT_BCS_BATCH(batch,
1855                   ((ALIGN(pic_param->coded_width, 16) / 16 + 1) / 2 - 1) << 24 |
1856                   dmv_surface_valid << 15 |
1857                   (pic_param->pic_quantizer_fields.bits.quantizer == 0) << 14 | /* implicit quantizer */
1858                   pic_param->rounding_control << 13 |
1859                   pic_param->sequence_fields.bits.syncmarker << 12 |
1860                   interpolation_mode << 8 |
1861                   0 << 7 | /* FIXME: scale up or down ??? */
1862                   pic_param->range_reduction_frame << 6 |
1863                   loopfilter << 5 |
1864                   overlap << 4 |
1865                   !is_first_field << 3 |
1866                   (pic_param->sequence_fields.bits.profile == 3) << 0);
1867     OUT_BCS_BATCH(batch,
1868                   va_to_gen7_vc1_condover[pic_param->conditional_overlap_flag] << 29 |
1869                   ptype << 26 |
1870                   fcm << 24 |
1871                   alt_pq << 16 |
1872                   pic_param->pic_quantizer_fields.bits.pic_quantizer_scale << 8 |
1873                   scale_factor << 0);
1874     OUT_BCS_BATCH(batch,
1875                   unified_mv_mode << 28 |
1876                   pic_param->mv_fields.bits.four_mv_switch << 27 |
1877                   pic_param->fast_uvmc_flag << 26 |
1878                   ref_field_pic_polarity << 25 |
1879                   pic_param->reference_fields.bits.num_reference_pictures << 24 |
1880                   brfd << 20 |
1881                   frfd << 16 |
1882                   pic_param->mv_fields.bits.extended_dmv_range << 10 |
1883                   pic_param->mv_fields.bits.extended_mv_range << 8 |
1884                   alt_pquant_edge_mask << 4 |
1885                   alt_pquant_config << 2 |
1886                   pic_param->pic_quantizer_fields.bits.half_qp << 1 |
1887                   pic_param->pic_quantizer_fields.bits.pic_quantizer_type << 0);
1888     OUT_BCS_BATCH(batch,
1889                   bitplane_present << 31 |
1890                   forward_mb << 30 |
1891                   mv_type_mb << 29 |
1892                   skip_mb << 28 |
1893                   direct_mb << 27 |
1894                   overflags << 26 |
1895                   ac_pred << 25 |
1896                   field_tx << 24 |
1897                   pic_param->mv_fields.bits.mv_table << 20 |
1898                   pic_param->mv_fields.bits.four_mv_block_pattern_table << 18 |
1899                   pic_param->mv_fields.bits.two_mv_block_pattern_table << 16 |
1900                   pic_param->transform_fields.bits.frame_level_transform_type << 12 |
1901                   pic_param->transform_fields.bits.mb_level_transform_type_flag << 11 |
1902                   pic_param->mb_mode_table << 8 |
1903                   trans_ac_y << 6 |
1904                   pic_param->transform_fields.bits.transform_ac_codingset_idx1 << 4 |
1905                   pic_param->transform_fields.bits.intra_transform_dc_table << 3 |
1906                   pic_param->cbp_table << 0);
1907     ADVANCE_BCS_BATCH(batch);
1908 }
1909
1910 static void
1911 gen7_mfd_vc1_pred_pipe_state(VADriverContextP ctx,
1912                              struct decode_state *decode_state,
1913                              struct gen7_mfd_context *gen7_mfd_context)
1914 {
1915     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1916     VAPictureParameterBufferVC1 *pic_param;
1917     struct gen7_vc1_surface *gen7_vc1_top_surface;
1918     struct gen7_vc1_surface *gen7_vc1_bottom_surface;
1919     int picture_type;
1920     int is_first_field = 1;
1921     int intensitycomp_single_fwd = 0;
1922     int intensitycomp_single_bwd = 0;
1923     int intensitycomp_double_fwd = 0;
1924     int lumscale1_single_fwd = 0;
1925     int lumscale2_single_fwd = 0;
1926     int lumshift1_single_fwd = 0;
1927     int lumshift2_single_fwd = 0;
1928     int lumscale1_single_bwd = 0;
1929     int lumscale2_single_bwd = 0;
1930     int lumshift1_single_bwd = 0;
1931     int lumshift2_single_bwd = 0;
1932     int lumscale1_double_fwd = 0;
1933     int lumscale2_double_fwd = 0;
1934     int lumshift1_double_fwd = 0;
1935     int lumshift2_double_fwd = 0;
1936     int replication_mode = 0;
1937
1938     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1939     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1940
1941     if (!pic_param->sequence_fields.bits.interlace ||
1942         (pic_param->picture_fields.bits.frame_coding_mode < 2)) { /* Progressive or Frame-Interlace */
1943         picture_type = pic_param->picture_fields.bits.picture_type;
1944     } else {/* Field-Interlace */
1945         is_first_field = pic_param->picture_fields.bits.is_first_field;
1946         picture_type = fptype_to_picture_type[pic_param->picture_fields.bits.picture_type][!is_first_field];
1947     }
1948
1949     if (picture_type == GEN7_VC1_P_PICTURE ||
1950         picture_type == GEN7_VC1_B_PICTURE) {
1951         if (gen7_mfd_context->reference_surface[0].surface_id != VA_INVALID_ID)
1952             gen7_vc1_top_surface = (struct gen7_vc1_surface *)(gen7_mfd_context->reference_surface[0].obj_surface->private_data);
1953         else
1954             gen7_vc1_top_surface = NULL;
1955
1956         if (gen7_vc1_top_surface) {
1957             intensitycomp_single_fwd = !!gen7_vc1_top_surface->intensity_compensation_top;
1958             lumscale1_single_fwd = gen7_vc1_top_surface->luma_scale_top[0];
1959             lumshift1_single_fwd = gen7_vc1_top_surface->luma_shift_top[0];
1960             if (gen7_vc1_top_surface->intensity_compensation_top == 2) {
1961                 intensitycomp_double_fwd = 1;
1962                 lumscale1_double_fwd = gen7_vc1_top_surface->luma_scale_top[1];
1963                 lumshift1_double_fwd = gen7_vc1_top_surface->luma_shift_top[1];
1964             }
1965         }
1966
1967         if (pic_param->sequence_fields.bits.interlace &&
1968             pic_param->picture_fields.bits.frame_coding_mode == 2) { /* Field-Interlace */
1969             if (gen7_mfd_context->reference_surface[2].surface_id != VA_INVALID_ID)
1970                 gen7_vc1_bottom_surface = (struct gen7_vc1_surface *)(gen7_mfd_context->reference_surface[2].obj_surface->private_data);
1971             else
1972                 gen7_vc1_bottom_surface = NULL;
1973
1974             if (gen7_vc1_bottom_surface) {
1975                 intensitycomp_single_fwd |= !!gen7_vc1_bottom_surface->intensity_compensation_bottom << 1;
1976                 lumscale2_single_fwd = gen7_vc1_bottom_surface->luma_scale_bottom[0];
1977                 lumshift2_single_fwd = gen7_vc1_bottom_surface->luma_shift_bottom[0];
1978                 if (gen7_vc1_bottom_surface->intensity_compensation_bottom == 2) {
1979                     intensitycomp_double_fwd |= 2;
1980                     lumscale2_double_fwd = gen7_vc1_bottom_surface->luma_scale_bottom[1];
1981                     lumshift2_double_fwd = gen7_vc1_bottom_surface->luma_shift_bottom[1];
1982                 }
1983             }
1984         }
1985     }
1986
1987     if (picture_type == GEN7_VC1_B_PICTURE) {
1988         if (gen7_mfd_context->reference_surface[1].surface_id != VA_INVALID_ID)
1989             gen7_vc1_top_surface = (struct gen7_vc1_surface *)(gen7_mfd_context->reference_surface[1].obj_surface->private_data);
1990         else
1991             gen7_vc1_top_surface = NULL;
1992
1993         if (gen7_vc1_top_surface) {
1994             intensitycomp_single_bwd = !!gen7_vc1_top_surface->intensity_compensation_top;
1995             lumscale1_single_bwd = gen7_vc1_top_surface->luma_scale_top[0];
1996             lumshift1_single_bwd = gen7_vc1_top_surface->luma_shift_top[0];
1997         }
1998
1999         if (pic_param->sequence_fields.bits.interlace &&
2000             pic_param->picture_fields.bits.frame_coding_mode == 2) { /* Field-Interlace */
2001             if (gen7_mfd_context->reference_surface[3].surface_id != VA_INVALID_ID)
2002                 gen7_vc1_bottom_surface = (struct gen7_vc1_surface *)(gen7_mfd_context->reference_surface[3].obj_surface->private_data);
2003             else
2004                 gen7_vc1_bottom_surface = NULL;
2005
2006             if (gen7_vc1_bottom_surface) {
2007                 intensitycomp_single_bwd |= !!gen7_vc1_bottom_surface->intensity_compensation_bottom << 1;
2008                 lumscale2_single_bwd = gen7_vc1_bottom_surface->luma_scale_bottom[0];
2009                 lumshift2_single_bwd = gen7_vc1_bottom_surface->luma_shift_bottom[0];
2010             }
2011         }
2012     }
2013
2014     if (pic_param->sequence_fields.bits.interlace &&
2015         pic_param->picture_fields.bits.frame_coding_mode > 0) { /* Frame-Interlace or Field-Interlace */
2016         if (picture_type == GEN7_VC1_P_PICTURE)
2017             replication_mode = 0x5;
2018         else if (picture_type == GEN7_VC1_B_PICTURE)
2019             replication_mode = 0xf;
2020     }
2021
2022     BEGIN_BCS_BATCH(batch, 6);
2023     OUT_BCS_BATCH(batch, MFX_VC1_PRED_PIPE_STATE | (6 - 2));
2024     OUT_BCS_BATCH(batch,
2025                   intensitycomp_double_fwd << 14 |
2026                   0 << 12 |
2027                   intensitycomp_single_fwd << 10 |
2028                   intensitycomp_single_bwd << 8 |
2029                   replication_mode << 4 |
2030                   0);
2031     OUT_BCS_BATCH(batch,
2032                   lumshift2_single_fwd << 24 |
2033                   lumshift1_single_fwd << 16 |
2034                   lumscale2_single_fwd << 8 |
2035                   lumscale1_single_fwd << 0);
2036     OUT_BCS_BATCH(batch,
2037                   lumshift2_double_fwd << 24 |
2038                   lumshift1_double_fwd << 16 |
2039                   lumscale2_double_fwd << 8 |
2040                   lumscale1_double_fwd << 0);
2041     OUT_BCS_BATCH(batch,
2042                   lumshift2_single_bwd << 24 |
2043                   lumshift1_single_bwd << 16 |
2044                   lumscale2_single_bwd << 8 |
2045                   lumscale1_single_bwd << 0);
2046     OUT_BCS_BATCH(batch,
2047                   0 << 24 |
2048                   0 << 16 |
2049                   0 << 8 |
2050                   0 << 0);
2051     ADVANCE_BCS_BATCH(batch);
2052 }
2053
2054
2055 static void
2056 gen7_mfd_vc1_directmode_state(VADriverContextP ctx,
2057                               struct decode_state *decode_state,
2058                               struct gen7_mfd_context *gen7_mfd_context)
2059 {
2060     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2061     VAPictureParameterBufferVC1 *pic_param;
2062     struct object_surface *obj_surface;
2063     dri_bo *dmv_read_buffer = NULL, *dmv_write_buffer = NULL;
2064     int picture_type;
2065     int is_first_field = 1;
2066
2067     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
2068
2069     if (!pic_param->sequence_fields.bits.interlace ||
2070         (pic_param->picture_fields.bits.frame_coding_mode < 2)) { /* Progressive or Frame-Interlace */
2071         picture_type = pic_param->picture_fields.bits.picture_type;
2072     } else {/* Field-Interlace */
2073         is_first_field = pic_param->picture_fields.bits.is_first_field;
2074         picture_type = fptype_to_picture_type[pic_param->picture_fields.bits.picture_type][!is_first_field];
2075     }
2076
2077    if (picture_type == GEN7_VC1_P_PICTURE ||
2078         picture_type == GEN7_VC1_SKIPPED_PICTURE) {
2079         obj_surface = decode_state->render_object;
2080
2081         if (pic_param->sequence_fields.bits.interlace &&
2082             (pic_param->picture_fields.bits.frame_coding_mode == 2) && /* Field-Interlace */
2083             (pic_param->picture_fields.bits.top_field_first ^ is_first_field))
2084             dmv_write_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv_bottom;
2085         else
2086             dmv_write_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv_top;
2087     }
2088
2089     if (picture_type == GEN7_VC1_B_PICTURE) {
2090         obj_surface = decode_state->reference_objects[1];
2091         if (pic_param->backward_reference_picture != VA_INVALID_ID &&
2092             obj_surface &&
2093             obj_surface->private_data) {
2094
2095             if (pic_param->sequence_fields.bits.interlace &&
2096                 (pic_param->picture_fields.bits.frame_coding_mode == 2) && /* Field-Interlace */
2097                 (pic_param->picture_fields.bits.top_field_first ^ is_first_field))
2098                 dmv_read_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv_bottom;
2099             else
2100                 dmv_read_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv_top;
2101         }
2102     }
2103
2104     BEGIN_BCS_BATCH(batch, 3);
2105     OUT_BCS_BATCH(batch, MFX_VC1_DIRECTMODE_STATE | (3 - 2));
2106
2107     if (dmv_write_buffer)
2108         OUT_BCS_RELOC(batch, dmv_write_buffer,
2109                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2110                       0);
2111     else
2112         OUT_BCS_BATCH(batch, 0);
2113
2114     if (dmv_read_buffer)
2115         OUT_BCS_RELOC(batch, dmv_read_buffer,
2116                       I915_GEM_DOMAIN_INSTRUCTION, 0,
2117                       0);
2118     else
2119         OUT_BCS_BATCH(batch, 0);
2120
2121     ADVANCE_BCS_BATCH(batch);
2122 }
2123
2124 static int
2125 gen7_mfd_vc1_get_macroblock_bit_offset(uint8_t *buf, int in_slice_data_bit_offset, int profile)
2126 {
2127     int out_slice_data_bit_offset;
2128     int slice_header_size = in_slice_data_bit_offset / 8;
2129     int i, j;
2130
2131     if (profile != 3)
2132         out_slice_data_bit_offset = in_slice_data_bit_offset;
2133     else {
2134         for (i = 0, j = 0; i < slice_header_size; i++, j++) {
2135             if (!buf[j] && !buf[j + 1] && buf[j + 2] == 3 && buf[j + 3] < 4) {
2136                 if (i < slice_header_size - 1)
2137                     i++, j += 2;
2138                 else {
2139                     buf[j + 2] = buf[j + 1];
2140                     j++;
2141                 }
2142             }
2143         }
2144
2145         out_slice_data_bit_offset = 8 * j + in_slice_data_bit_offset % 8;
2146     }
2147
2148     return out_slice_data_bit_offset;
2149 }
2150
2151 static void
2152 gen7_mfd_vc1_bsd_object(VADriverContextP ctx,
2153                         VAPictureParameterBufferVC1 *pic_param,
2154                         VASliceParameterBufferVC1 *slice_param,
2155                         VASliceParameterBufferVC1 *next_slice_param,
2156                         dri_bo *slice_data_bo,
2157                         struct gen7_mfd_context *gen7_mfd_context)
2158 {
2159     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2160     int next_slice_start_vert_pos;
2161     int macroblock_offset;
2162     uint8_t *slice_data = NULL;
2163
2164     dri_bo_map(slice_data_bo, True);
2165     slice_data = (uint8_t *)(slice_data_bo->virtual + slice_param->slice_data_offset);
2166     macroblock_offset = gen7_mfd_vc1_get_macroblock_bit_offset(slice_data,
2167                                                                slice_param->macroblock_offset,
2168                                                                pic_param->sequence_fields.bits.profile);
2169     dri_bo_unmap(slice_data_bo);
2170
2171     if (next_slice_param)
2172         next_slice_start_vert_pos = next_slice_param->slice_vertical_position;
2173     else if (!pic_param->sequence_fields.bits.interlace ||
2174              pic_param->picture_fields.bits.frame_coding_mode < 2) /* Progressive or Frame-Interlace */
2175         next_slice_start_vert_pos = ALIGN(pic_param->coded_height, 16) / 16;
2176     else /* Field-Interlace */
2177         next_slice_start_vert_pos = ALIGN(pic_param->coded_height, 32) / 32;
2178
2179     BEGIN_BCS_BATCH(batch, 5);
2180     OUT_BCS_BATCH(batch, MFD_VC1_BSD_OBJECT | (5 - 2));
2181     OUT_BCS_BATCH(batch,
2182                   slice_param->slice_data_size - (macroblock_offset >> 3));
2183     OUT_BCS_BATCH(batch,
2184                   slice_param->slice_data_offset + (macroblock_offset >> 3));
2185     OUT_BCS_BATCH(batch,
2186                   slice_param->slice_vertical_position << 16 |
2187                   next_slice_start_vert_pos << 0);
2188     OUT_BCS_BATCH(batch,
2189                   (macroblock_offset & 0x7));
2190     ADVANCE_BCS_BATCH(batch);
2191 }
2192
2193 static void
2194 gen7_mfd_vc1_decode_picture(VADriverContextP ctx,
2195                             struct decode_state *decode_state,
2196                             struct gen7_mfd_context *gen7_mfd_context)
2197 {
2198     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2199     VAPictureParameterBufferVC1 *pic_param;
2200     VASliceParameterBufferVC1 *slice_param, *next_slice_param, *next_slice_group_param;
2201     dri_bo *slice_data_bo;
2202     int i, j;
2203
2204     assert(decode_state->pic_param && decode_state->pic_param->buffer);
2205     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
2206
2207     gen7_mfd_vc1_decode_init(ctx, decode_state, gen7_mfd_context);
2208     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
2209     intel_batchbuffer_emit_mi_flush(batch);
2210     gen7_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
2211     gen7_mfd_surface_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
2212     gen7_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
2213     gen7_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
2214     gen7_mfd_vc1_pic_state(ctx, decode_state, gen7_mfd_context);
2215     gen7_mfd_vc1_pred_pipe_state(ctx, decode_state, gen7_mfd_context);
2216     gen7_mfd_vc1_directmode_state(ctx, decode_state, gen7_mfd_context);
2217
2218     for (j = 0; j < decode_state->num_slice_params; j++) {
2219         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
2220         slice_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j]->buffer;
2221         slice_data_bo = decode_state->slice_datas[j]->bo;
2222         gen7_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_VC1, gen7_mfd_context);
2223
2224         if (j == decode_state->num_slice_params - 1)
2225             next_slice_group_param = NULL;
2226         else
2227             next_slice_group_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j + 1]->buffer;
2228
2229         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
2230             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
2231
2232             if (i < decode_state->slice_params[j]->num_elements - 1)
2233                 next_slice_param = slice_param + 1;
2234             else
2235                 next_slice_param = next_slice_group_param;
2236
2237             gen7_mfd_vc1_bsd_object(ctx, pic_param, slice_param, next_slice_param, slice_data_bo, gen7_mfd_context);
2238             slice_param++;
2239         }
2240     }
2241
2242     intel_batchbuffer_end_atomic(batch);
2243     intel_batchbuffer_flush(batch);
2244 }
2245
2246 static void
2247 gen7_mfd_jpeg_decode_init(VADriverContextP ctx,
2248                           struct decode_state *decode_state,
2249                           struct gen7_mfd_context *gen7_mfd_context)
2250 {
2251     struct object_surface *obj_surface;
2252     VAPictureParameterBufferJPEGBaseline *pic_param;
2253     int subsampling = SUBSAMPLE_YUV420;
2254     int fourcc = VA_FOURCC_IMC3;
2255
2256     pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
2257
2258     if (pic_param->num_components == 1) {
2259         subsampling = SUBSAMPLE_YUV400;
2260         fourcc = VA_FOURCC_Y800;
2261     } else if (pic_param->num_components == 3) {
2262         int h1 = pic_param->components[0].h_sampling_factor;
2263         int h2 = pic_param->components[1].h_sampling_factor;
2264         int h3 = pic_param->components[2].h_sampling_factor;
2265         int v1 = pic_param->components[0].v_sampling_factor;
2266         int v2 = pic_param->components[1].v_sampling_factor;
2267         int v3 = pic_param->components[2].v_sampling_factor;
2268
2269         if (h1 == 2 * h2 && h2 == h3 &&
2270             v1 == 2 * v2 && v2 == v3) {
2271             subsampling = SUBSAMPLE_YUV420;
2272             fourcc = VA_FOURCC_IMC3;
2273         } else if (h1 == 2 * h2  && h2 == h3 &&
2274                    v1 == v2 && v2 == v3) {
2275             subsampling = SUBSAMPLE_YUV422H;
2276             fourcc = VA_FOURCC_422H;
2277         } else if (h1 == h2 && h2 == h3 &&
2278                    v1 == v2  && v2 == v3) {
2279             subsampling = SUBSAMPLE_YUV444;
2280             fourcc = VA_FOURCC_444P;
2281         } else if (h1 == 4 * h2 && h2 ==  h3 &&
2282                    v1 == v2 && v2 == v3) {
2283             subsampling = SUBSAMPLE_YUV411;
2284             fourcc = VA_FOURCC_411P;
2285         } else if (h1 == h2 && h2 == h3 &&
2286                    v1 == 2 * v2 && v2 == v3) {
2287             subsampling = SUBSAMPLE_YUV422V;
2288             fourcc = VA_FOURCC_422V;
2289         } else
2290             assert(0);
2291     } else {
2292         assert(0);
2293     }
2294
2295     /* Current decoded picture */
2296     obj_surface = decode_state->render_object;
2297     i965_check_alloc_surface_bo(ctx, obj_surface, 1, fourcc, subsampling);
2298
2299     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
2300     gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
2301     dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
2302     gen7_mfd_context->pre_deblocking_output.valid = 1;
2303
2304     gen7_mfd_context->post_deblocking_output.bo = NULL;
2305     gen7_mfd_context->post_deblocking_output.valid = 0;
2306
2307     gen7_mfd_context->intra_row_store_scratch_buffer.bo = NULL;
2308     gen7_mfd_context->intra_row_store_scratch_buffer.valid = 0;
2309
2310     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
2311     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 0;
2312
2313     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
2314     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 0;
2315
2316     gen7_mfd_context->mpr_row_store_scratch_buffer.bo = NULL;
2317     gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
2318
2319     gen7_mfd_context->bitplane_read_buffer.bo = NULL;
2320     gen7_mfd_context->bitplane_read_buffer.valid = 0;
2321 }
2322
2323 static const int va_to_gen7_jpeg_rotation[4] = {
2324     GEN7_JPEG_ROTATION_0,
2325     GEN7_JPEG_ROTATION_90,
2326     GEN7_JPEG_ROTATION_180,
2327     GEN7_JPEG_ROTATION_270
2328 };
2329
2330 static void
2331 gen7_mfd_jpeg_pic_state(VADriverContextP ctx,
2332                         struct decode_state *decode_state,
2333                         struct gen7_mfd_context *gen7_mfd_context)
2334 {
2335     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2336     VAPictureParameterBufferJPEGBaseline *pic_param;
2337     int chroma_type = GEN7_YUV420;
2338     int frame_width_in_blks;
2339     int frame_height_in_blks;
2340
2341     assert(decode_state->pic_param && decode_state->pic_param->buffer);
2342     pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
2343
2344     if (pic_param->num_components == 1)
2345         chroma_type = GEN7_YUV400;
2346     else if (pic_param->num_components == 3) {
2347         int h1 = pic_param->components[0].h_sampling_factor;
2348         int h2 = pic_param->components[1].h_sampling_factor;
2349         int h3 = pic_param->components[2].h_sampling_factor;
2350         int v1 = pic_param->components[0].v_sampling_factor;
2351         int v2 = pic_param->components[1].v_sampling_factor;
2352         int v3 = pic_param->components[2].v_sampling_factor;
2353
2354         if (h1 == 2 * h2 && h2 == h3 &&
2355             v1 == 2 * v2 && v2 == v3)
2356             chroma_type = GEN7_YUV420;
2357         else if (h1 == 2 && h2 == 1 && h3 == 1 &&
2358                  v1 == 1 && v2 == 1 && v3 == 1)
2359             chroma_type = GEN7_YUV422H_2Y;
2360         else if (h1 == h2 && h2 == h3 &&
2361                  v1 == v2 && v2 == v3)
2362             chroma_type = GEN7_YUV444;
2363         else if (h1 == 4 * h2 && h2 == h3 &&
2364                  v1 == v2 && v2 == v3)
2365             chroma_type = GEN7_YUV411;
2366         else if (h1 == 1 && h2 == 1 && h3 == 1 &&
2367                  v1 == 2 && v2 == 1 && v3 == 1)
2368             chroma_type = GEN7_YUV422V_2Y;
2369         else if (h1 == 2 && h2 == 1 && h3 == 1 &&
2370                  v1 == 2 && v2 == 2 && v3 == 2)
2371             chroma_type = GEN7_YUV422H_4Y;
2372         else if (h2 == 2 && h2 == 2 && h3 == 2 &&
2373                  v1 == 2 && v2 == 1 && v3 == 1)
2374             chroma_type = GEN7_YUV422V_4Y;
2375         else
2376             assert(0);
2377     }
2378
2379     if (chroma_type == GEN7_YUV400 ||
2380         chroma_type == GEN7_YUV444 ||
2381         chroma_type == GEN7_YUV422V_2Y) {
2382         frame_width_in_blks = ((pic_param->picture_width + 7) / 8);
2383         frame_height_in_blks = ((pic_param->picture_height + 7) / 8);
2384     } else if (chroma_type == GEN7_YUV411) {
2385         frame_width_in_blks = ((pic_param->picture_width + 31) / 32) * 4;
2386         frame_height_in_blks = ((pic_param->picture_height + 31) / 32) * 4;
2387     } else {
2388         frame_width_in_blks = ((pic_param->picture_width + 15) / 16) * 2;
2389         frame_height_in_blks = ((pic_param->picture_height + 15) / 16) * 2;
2390     }
2391
2392     BEGIN_BCS_BATCH(batch, 3);
2393     OUT_BCS_BATCH(batch, MFX_JPEG_PIC_STATE | (3 - 2));
2394     OUT_BCS_BATCH(batch,
2395                   (va_to_gen7_jpeg_rotation[0] << 4) |    /* without rotation */
2396                   (chroma_type << 0));
2397     OUT_BCS_BATCH(batch,
2398                   ((frame_height_in_blks - 1) << 16) |   /* FrameHeightInBlks */
2399                   ((frame_width_in_blks - 1) << 0));    /* FrameWidthInBlks */
2400     ADVANCE_BCS_BATCH(batch);
2401 }
2402
2403 static const int va_to_gen7_jpeg_hufftable[2] = {
2404     MFX_HUFFTABLE_ID_Y,
2405     MFX_HUFFTABLE_ID_UV
2406 };
2407
2408 static void
2409 gen7_mfd_jpeg_huff_table_state(VADriverContextP ctx,
2410                                struct decode_state *decode_state,
2411                                struct gen7_mfd_context *gen7_mfd_context,
2412                                int num_tables)
2413 {
2414     VAHuffmanTableBufferJPEGBaseline *huffman_table;
2415     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2416     int index;
2417
2418     if (!decode_state->huffman_table || !decode_state->huffman_table->buffer)
2419         return;
2420
2421     huffman_table = (VAHuffmanTableBufferJPEGBaseline *)decode_state->huffman_table->buffer;
2422
2423     for (index = 0; index < num_tables; index++) {
2424         int id = va_to_gen7_jpeg_hufftable[index];
2425         if (!huffman_table->load_huffman_table[index])
2426             continue;
2427         BEGIN_BCS_BATCH(batch, 53);
2428         OUT_BCS_BATCH(batch, MFX_JPEG_HUFF_TABLE_STATE | (53 - 2));
2429         OUT_BCS_BATCH(batch, id);
2430         intel_batchbuffer_data(batch, huffman_table->huffman_table[index].num_dc_codes, 12);
2431         intel_batchbuffer_data(batch, huffman_table->huffman_table[index].dc_values, 12);
2432         intel_batchbuffer_data(batch, huffman_table->huffman_table[index].num_ac_codes, 16);
2433         intel_batchbuffer_data(batch, huffman_table->huffman_table[index].ac_values, 164);
2434         ADVANCE_BCS_BATCH(batch);
2435     }
2436 }
2437
2438 static const int va_to_gen7_jpeg_qm[5] = {
2439     -1,
2440     MFX_QM_JPEG_LUMA_Y_QUANTIZER_MATRIX,
2441     MFX_QM_JPEG_CHROMA_CB_QUANTIZER_MATRIX,
2442     MFX_QM_JPEG_CHROMA_CR_QUANTIZER_MATRIX,
2443     MFX_QM_JPEG_ALPHA_QUANTIZER_MATRIX
2444 };
2445
2446 static void
2447 gen7_mfd_jpeg_qm_state(VADriverContextP ctx,
2448                        struct decode_state *decode_state,
2449                        struct gen7_mfd_context *gen7_mfd_context)
2450 {
2451     VAPictureParameterBufferJPEGBaseline *pic_param;
2452     VAIQMatrixBufferJPEGBaseline *iq_matrix;
2453     int index;
2454
2455     if (!decode_state->iq_matrix || !decode_state->iq_matrix->buffer)
2456         return;
2457
2458     iq_matrix = (VAIQMatrixBufferJPEGBaseline *)decode_state->iq_matrix->buffer;
2459     pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
2460
2461     assert(pic_param->num_components <= 3);
2462
2463     for (index = 0; index < pic_param->num_components; index++) {
2464         int id = pic_param->components[index].component_id - pic_param->components[0].component_id + 1;
2465         int qm_type;
2466         unsigned char *qm = iq_matrix->quantiser_table[pic_param->components[index].quantiser_table_selector];
2467         unsigned char raster_qm[64];
2468         int j;
2469
2470         if (id > 4 || id < 1)
2471             continue;
2472
2473         if (!iq_matrix->load_quantiser_table[pic_param->components[index].quantiser_table_selector])
2474             continue;
2475
2476         qm_type = va_to_gen7_jpeg_qm[id];
2477
2478         for (j = 0; j < 64; j++)
2479             raster_qm[zigzag_direct[j]] = qm[j];
2480
2481         gen7_mfd_qm_state(ctx, qm_type, raster_qm, 64, gen7_mfd_context);
2482     }
2483 }
2484
2485 static void
2486 gen7_mfd_jpeg_bsd_object(VADriverContextP ctx,
2487                          VAPictureParameterBufferJPEGBaseline *pic_param,
2488                          VASliceParameterBufferJPEGBaseline *slice_param,
2489                          VASliceParameterBufferJPEGBaseline *next_slice_param,
2490                          dri_bo *slice_data_bo,
2491                          struct gen7_mfd_context *gen7_mfd_context)
2492 {
2493     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2494     int scan_component_mask = 0;
2495     int i;
2496
2497     assert(slice_param->num_components > 0);
2498     assert(slice_param->num_components < 4);
2499     assert(slice_param->num_components <= pic_param->num_components);
2500
2501     for (i = 0; i < slice_param->num_components; i++) {
2502         switch (slice_param->components[i].component_selector - pic_param->components[0].component_id + 1) {
2503         case 1:
2504             scan_component_mask |= (1 << 0);
2505             break;
2506         case 2:
2507             scan_component_mask |= (1 << 1);
2508             break;
2509         case 3:
2510             scan_component_mask |= (1 << 2);
2511             break;
2512         default:
2513             assert(0);
2514             break;
2515         }
2516     }
2517
2518     BEGIN_BCS_BATCH(batch, 6);
2519     OUT_BCS_BATCH(batch, MFD_JPEG_BSD_OBJECT | (6 - 2));
2520     OUT_BCS_BATCH(batch,
2521                   slice_param->slice_data_size);
2522     OUT_BCS_BATCH(batch,
2523                   slice_param->slice_data_offset);
2524     OUT_BCS_BATCH(batch,
2525                   slice_param->slice_horizontal_position << 16 |
2526                   slice_param->slice_vertical_position << 0);
2527     OUT_BCS_BATCH(batch,
2528                   ((slice_param->num_components != 1) << 30) |  /* interleaved */
2529                   (scan_component_mask << 27) |                 /* scan components */
2530                   (0 << 26) |   /* disable interrupt allowed */
2531                   (slice_param->num_mcus << 0));                /* MCU count */
2532     OUT_BCS_BATCH(batch,
2533                   (slice_param->restart_interval << 0));    /* RestartInterval */
2534     ADVANCE_BCS_BATCH(batch);
2535 }
2536
2537 /* Workaround for JPEG decoding on Ivybridge */
2538
2539 static struct {
2540     int width;
2541     int height;
2542     unsigned char data[32];
2543     int data_size;
2544     int data_bit_offset;
2545     int qp;
2546 } gen7_jpeg_wa_clip = {
2547     16,
2548     16,
2549     {
2550         0x65, 0xb8, 0x40, 0x32, 0x13, 0xfd, 0x06, 0x6c,
2551         0xfc, 0x0a, 0x50, 0x71, 0x5c, 0x00
2552     },
2553     14,
2554     40,
2555     28,
2556 };
2557
2558 static void
2559 gen7_jpeg_wa_init(VADriverContextP ctx,
2560                   struct gen7_mfd_context *gen7_mfd_context)
2561 {
2562     struct i965_driver_data *i965 = i965_driver_data(ctx);
2563     VAStatus status;
2564     struct object_surface *obj_surface;
2565
2566     if (gen7_mfd_context->jpeg_wa_surface_id != VA_INVALID_SURFACE)
2567         i965_DestroySurfaces(ctx,
2568                              &gen7_mfd_context->jpeg_wa_surface_id,
2569                              1);
2570
2571     status = i965_CreateSurfaces(ctx,
2572                                  gen7_jpeg_wa_clip.width,
2573                                  gen7_jpeg_wa_clip.height,
2574                                  VA_RT_FORMAT_YUV420,
2575                                  1,
2576                                  &gen7_mfd_context->jpeg_wa_surface_id);
2577     assert(status == VA_STATUS_SUCCESS);
2578
2579     obj_surface = SURFACE(gen7_mfd_context->jpeg_wa_surface_id);
2580     assert(obj_surface);
2581     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
2582     gen7_mfd_context->jpeg_wa_surface_object = obj_surface;
2583
2584     if (!gen7_mfd_context->jpeg_wa_slice_data_bo) {
2585         gen7_mfd_context->jpeg_wa_slice_data_bo = dri_bo_alloc(i965->intel.bufmgr,
2586                                                                "JPEG WA data",
2587                                                                0x1000,
2588                                                                0x1000);
2589         dri_bo_subdata(gen7_mfd_context->jpeg_wa_slice_data_bo,
2590                        0,
2591                        gen7_jpeg_wa_clip.data_size,
2592                        gen7_jpeg_wa_clip.data);
2593     }
2594 }
2595
2596 static void
2597 gen7_jpeg_wa_pipe_mode_select(VADriverContextP ctx,
2598                               struct gen7_mfd_context *gen7_mfd_context)
2599 {
2600     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2601
2602     BEGIN_BCS_BATCH(batch, 5);
2603     OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2));
2604     OUT_BCS_BATCH(batch,
2605                   (MFX_LONG_MODE << 17) | /* Currently only support long format */
2606                   (MFD_MODE_VLD << 15) | /* VLD mode */
2607                   (0 << 10) | /* disable Stream-Out */
2608                   (0 << 9)  | /* Post Deblocking Output */
2609                   (1 << 8)  | /* Pre Deblocking Output */
2610                   (0 << 5)  | /* not in stitch mode */
2611                   (MFX_CODEC_DECODE << 4)  | /* decoding mode */
2612                   (MFX_FORMAT_AVC << 0));
2613     OUT_BCS_BATCH(batch,
2614                   (0 << 4)  | /* terminate if AVC motion and POC table error occurs */
2615                   (0 << 3)  | /* terminate if AVC mbdata error occurs */
2616                   (0 << 2)  | /* terminate if AVC CABAC/CAVLC decode error occurs */
2617                   (0 << 1)  |
2618                   (0 << 0));
2619     OUT_BCS_BATCH(batch, 0); /* pic status/error report id */
2620     OUT_BCS_BATCH(batch, 0); /* reserved */
2621     ADVANCE_BCS_BATCH(batch);
2622 }
2623
2624 static void
2625 gen7_jpeg_wa_surface_state(VADriverContextP ctx,
2626                            struct gen7_mfd_context *gen7_mfd_context)
2627 {
2628     struct object_surface *obj_surface = gen7_mfd_context->jpeg_wa_surface_object;
2629     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2630
2631     BEGIN_BCS_BATCH(batch, 6);
2632     OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
2633     OUT_BCS_BATCH(batch, 0);
2634     OUT_BCS_BATCH(batch,
2635                   ((obj_surface->orig_width - 1) << 18) |
2636                   ((obj_surface->orig_height - 1) << 4));
2637     OUT_BCS_BATCH(batch,
2638                   (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
2639                   (1 << 27) | /* interleave chroma, set to 0 for JPEG */
2640                   (0 << 22) | /* surface object control state, ignored */
2641                   ((obj_surface->width - 1) << 3) | /* pitch */
2642                   (0 << 2)  | /* must be 0 */
2643                   (1 << 1)  | /* must be tiled */
2644                   (I965_TILEWALK_YMAJOR << 0));  /* tile walk, must be 1 */
2645     OUT_BCS_BATCH(batch,
2646                   (0 << 16) | /* X offset for U(Cb), must be 0 */
2647                   (obj_surface->y_cb_offset << 0)); /* Y offset for U(Cb) */
2648     OUT_BCS_BATCH(batch,
2649                   (0 << 16) | /* X offset for V(Cr), must be 0 */
2650                   (0 << 0)); /* Y offset for V(Cr), must be 0 for video codec, non-zoro for JPEG */
2651     ADVANCE_BCS_BATCH(batch);
2652 }
2653
2654 static void
2655 gen7_jpeg_wa_pipe_buf_addr_state(VADriverContextP ctx,
2656                                  struct gen7_mfd_context *gen7_mfd_context)
2657 {
2658     struct i965_driver_data *i965 = i965_driver_data(ctx);
2659     struct object_surface *obj_surface = gen7_mfd_context->jpeg_wa_surface_object;
2660     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2661     dri_bo *intra_bo;
2662     int i;
2663
2664     intra_bo = dri_bo_alloc(i965->intel.bufmgr,
2665                             "intra row store",
2666                             128 * 64,
2667                             0x1000);
2668
2669     BEGIN_BCS_BATCH(batch, 24);
2670     OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
2671     OUT_BCS_RELOC(batch,
2672                   obj_surface->bo,
2673                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2674                   0);
2675
2676     OUT_BCS_BATCH(batch, 0); /* post deblocking */
2677
2678     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
2679     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
2680
2681     OUT_BCS_RELOC(batch,
2682                   intra_bo,
2683                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2684                   0);
2685
2686     OUT_BCS_BATCH(batch, 0);
2687
2688     /* DW 7..22 */
2689     for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
2690         OUT_BCS_BATCH(batch, 0);
2691     }
2692
2693     OUT_BCS_BATCH(batch, 0);   /* ignore DW23 for decoding */
2694     ADVANCE_BCS_BATCH(batch);
2695
2696     dri_bo_unreference(intra_bo);
2697 }
2698
2699 static void
2700 gen7_jpeg_wa_bsp_buf_base_addr_state(VADriverContextP ctx,
2701                                      struct gen7_mfd_context *gen7_mfd_context)
2702 {
2703     struct i965_driver_data *i965 = i965_driver_data(ctx);
2704     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2705     dri_bo *bsd_mpc_bo, *mpr_bo;
2706
2707     bsd_mpc_bo = dri_bo_alloc(i965->intel.bufmgr,
2708                               "bsd mpc row store",
2709                               11520, /* 1.5 * 120 * 64 */
2710                               0x1000);
2711
2712     mpr_bo = dri_bo_alloc(i965->intel.bufmgr,
2713                           "mpr row store",
2714                           7680, /* 1. 0 * 120 * 64 */
2715                           0x1000);
2716
2717     BEGIN_BCS_BATCH(batch, 4);
2718     OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
2719
2720     OUT_BCS_RELOC(batch,
2721                   bsd_mpc_bo,
2722                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2723                   0);
2724
2725     OUT_BCS_RELOC(batch,
2726                   mpr_bo,
2727                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2728                   0);
2729     OUT_BCS_BATCH(batch, 0);
2730
2731     ADVANCE_BCS_BATCH(batch);
2732
2733     dri_bo_unreference(bsd_mpc_bo);
2734     dri_bo_unreference(mpr_bo);
2735 }
2736
2737 static void
2738 gen7_jpeg_wa_avc_qm_state(VADriverContextP ctx,
2739                           struct gen7_mfd_context *gen7_mfd_context)
2740 {
2741
2742 }
2743
2744 static void
2745 gen7_jpeg_wa_avc_img_state(VADriverContextP ctx,
2746                            struct gen7_mfd_context *gen7_mfd_context)
2747 {
2748     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2749     int img_struct = 0;
2750     int mbaff_frame_flag = 0;
2751     unsigned int width_in_mbs = 1, height_in_mbs = 1;
2752
2753     BEGIN_BCS_BATCH(batch, 16);
2754     OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (16 - 2));
2755     OUT_BCS_BATCH(batch,
2756                   (width_in_mbs * height_in_mbs - 1));
2757     OUT_BCS_BATCH(batch,
2758                   ((height_in_mbs - 1) << 16) |
2759                   ((width_in_mbs - 1) << 0));
2760     OUT_BCS_BATCH(batch,
2761                   (0 << 24) |
2762                   (0 << 16) |
2763                   (0 << 14) |
2764                   (0 << 13) |
2765                   (0 << 12) | /* differ from GEN6 */
2766                   (0 << 10) |
2767                   (img_struct << 8));
2768     OUT_BCS_BATCH(batch,
2769                   (1 << 10) | /* 4:2:0 */
2770                   (1 << 7) |  /* CABAC */
2771                   (0 << 6) |
2772                   (0 << 5) |
2773                   (0 << 4) |
2774                   (0 << 3) |
2775                   (1 << 2) |
2776                   (mbaff_frame_flag << 1) |
2777                   (0 << 0));
2778     OUT_BCS_BATCH(batch, 0);
2779     OUT_BCS_BATCH(batch, 0);
2780     OUT_BCS_BATCH(batch, 0);
2781     OUT_BCS_BATCH(batch, 0);
2782     OUT_BCS_BATCH(batch, 0);
2783     OUT_BCS_BATCH(batch, 0);
2784     OUT_BCS_BATCH(batch, 0);
2785     OUT_BCS_BATCH(batch, 0);
2786     OUT_BCS_BATCH(batch, 0);
2787     OUT_BCS_BATCH(batch, 0);
2788     OUT_BCS_BATCH(batch, 0);
2789     ADVANCE_BCS_BATCH(batch);
2790 }
2791
2792 static void
2793 gen7_jpeg_wa_avc_directmode_state(VADriverContextP ctx,
2794                                   struct gen7_mfd_context *gen7_mfd_context)
2795 {
2796     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2797     int i;
2798
2799     BEGIN_BCS_BATCH(batch, 69);
2800     OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
2801
2802     /* reference surfaces 0..15 */
2803     for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
2804         OUT_BCS_BATCH(batch, 0); /* top */
2805         OUT_BCS_BATCH(batch, 0); /* bottom */
2806     }
2807
2808     /* the current decoding frame/field */
2809     OUT_BCS_BATCH(batch, 0); /* top */
2810     OUT_BCS_BATCH(batch, 0); /* bottom */
2811
2812     /* POC List */
2813     for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
2814         OUT_BCS_BATCH(batch, 0);
2815         OUT_BCS_BATCH(batch, 0);
2816     }
2817
2818     OUT_BCS_BATCH(batch, 0);
2819     OUT_BCS_BATCH(batch, 0);
2820
2821     ADVANCE_BCS_BATCH(batch);
2822 }
2823
2824 static void
2825 gen7_jpeg_wa_ind_obj_base_addr_state(VADriverContextP ctx,
2826                                      struct gen7_mfd_context *gen7_mfd_context)
2827 {
2828     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2829
2830     BEGIN_BCS_BATCH(batch, 11);
2831     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
2832     OUT_BCS_RELOC(batch,
2833                   gen7_mfd_context->jpeg_wa_slice_data_bo,
2834                   I915_GEM_DOMAIN_INSTRUCTION, 0,
2835                   0);
2836     OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
2837     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
2838     OUT_BCS_BATCH(batch, 0);
2839     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
2840     OUT_BCS_BATCH(batch, 0);
2841     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
2842     OUT_BCS_BATCH(batch, 0);
2843     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
2844     OUT_BCS_BATCH(batch, 0);
2845     ADVANCE_BCS_BATCH(batch);
2846 }
2847
2848 static void
2849 gen7_jpeg_wa_avc_bsd_object(VADriverContextP ctx,
2850                             struct gen7_mfd_context *gen7_mfd_context)
2851 {
2852     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2853
2854     /* the input bitsteam format on GEN7 differs from GEN6 */
2855     BEGIN_BCS_BATCH(batch, 6);
2856     OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2));
2857     OUT_BCS_BATCH(batch, gen7_jpeg_wa_clip.data_size);
2858     OUT_BCS_BATCH(batch, 0);
2859     OUT_BCS_BATCH(batch,
2860                   (0 << 31) |
2861                   (0 << 14) |
2862                   (0 << 12) |
2863                   (0 << 10) |
2864                   (0 << 8));
2865     OUT_BCS_BATCH(batch,
2866                   ((gen7_jpeg_wa_clip.data_bit_offset >> 3) << 16) |
2867                   (0 << 5)  |
2868                   (0 << 4)  |
2869                   (1 << 3) | /* LastSlice Flag */
2870                   (gen7_jpeg_wa_clip.data_bit_offset & 0x7));
2871     OUT_BCS_BATCH(batch, 0);
2872     ADVANCE_BCS_BATCH(batch);
2873 }
2874
2875 static void
2876 gen7_jpeg_wa_avc_slice_state(VADriverContextP ctx,
2877                              struct gen7_mfd_context *gen7_mfd_context)
2878 {
2879     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2880     int slice_hor_pos = 0, slice_ver_pos = 0, next_slice_hor_pos = 0, next_slice_ver_pos = 1;
2881     int num_ref_idx_l0 = 0, num_ref_idx_l1 = 0;
2882     int first_mb_in_slice = 0;
2883     int slice_type = SLICE_TYPE_I;
2884
2885     BEGIN_BCS_BATCH(batch, 11);
2886     OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2));
2887     OUT_BCS_BATCH(batch, slice_type);
2888     OUT_BCS_BATCH(batch,
2889                   (num_ref_idx_l1 << 24) |
2890                   (num_ref_idx_l0 << 16) |
2891                   (0 << 8) |
2892                   (0 << 0));
2893     OUT_BCS_BATCH(batch,
2894                   (0 << 29) |
2895                   (1 << 27) |   /* disable Deblocking */
2896                   (0 << 24) |
2897                   (gen7_jpeg_wa_clip.qp << 16) |
2898                   (0 << 8) |
2899                   (0 << 0));
2900     OUT_BCS_BATCH(batch,
2901                   (slice_ver_pos << 24) |
2902                   (slice_hor_pos << 16) |
2903                   (first_mb_in_slice << 0));
2904     OUT_BCS_BATCH(batch,
2905                   (next_slice_ver_pos << 16) |
2906                   (next_slice_hor_pos << 0));
2907     OUT_BCS_BATCH(batch, (1 << 19)); /* last slice flag */
2908     OUT_BCS_BATCH(batch, 0);
2909     OUT_BCS_BATCH(batch, 0);
2910     OUT_BCS_BATCH(batch, 0);
2911     OUT_BCS_BATCH(batch, 0);
2912     ADVANCE_BCS_BATCH(batch);
2913 }
2914
2915 static void
2916 gen7_mfd_jpeg_wa(VADriverContextP ctx,
2917                  struct gen7_mfd_context *gen7_mfd_context)
2918 {
2919     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2920     gen7_jpeg_wa_init(ctx, gen7_mfd_context);
2921     intel_batchbuffer_emit_mi_flush(batch);
2922     gen7_jpeg_wa_pipe_mode_select(ctx, gen7_mfd_context);
2923     gen7_jpeg_wa_surface_state(ctx, gen7_mfd_context);
2924     gen7_jpeg_wa_pipe_buf_addr_state(ctx, gen7_mfd_context);
2925     gen7_jpeg_wa_bsp_buf_base_addr_state(ctx, gen7_mfd_context);
2926     gen7_jpeg_wa_avc_qm_state(ctx, gen7_mfd_context);
2927     gen7_jpeg_wa_avc_img_state(ctx, gen7_mfd_context);
2928     gen7_jpeg_wa_ind_obj_base_addr_state(ctx, gen7_mfd_context);
2929
2930     gen7_jpeg_wa_avc_directmode_state(ctx, gen7_mfd_context);
2931     gen7_jpeg_wa_avc_slice_state(ctx, gen7_mfd_context);
2932     gen7_jpeg_wa_avc_bsd_object(ctx, gen7_mfd_context);
2933 }
2934
2935 void
2936 gen7_mfd_jpeg_decode_picture(VADriverContextP ctx,
2937                              struct decode_state *decode_state,
2938                              struct gen7_mfd_context *gen7_mfd_context)
2939 {
2940     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2941     VAPictureParameterBufferJPEGBaseline *pic_param;
2942     VASliceParameterBufferJPEGBaseline *slice_param, *next_slice_param, *next_slice_group_param;
2943     dri_bo *slice_data_bo;
2944     int i, j, max_selector = 0;
2945
2946     assert(decode_state->pic_param && decode_state->pic_param->buffer);
2947     pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
2948
2949     /* Currently only support Baseline DCT */
2950     gen7_mfd_jpeg_decode_init(ctx, decode_state, gen7_mfd_context);
2951     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
2952     gen7_mfd_jpeg_wa(ctx, gen7_mfd_context);
2953     intel_batchbuffer_emit_mi_flush(batch);
2954     gen7_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_JPEG, gen7_mfd_context);
2955     gen7_mfd_surface_state(ctx, decode_state, MFX_FORMAT_JPEG, gen7_mfd_context);
2956     gen7_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_JPEG, gen7_mfd_context);
2957     gen7_mfd_jpeg_pic_state(ctx, decode_state, gen7_mfd_context);
2958     gen7_mfd_jpeg_qm_state(ctx, decode_state, gen7_mfd_context);
2959
2960     for (j = 0; j < decode_state->num_slice_params; j++) {
2961         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
2962         slice_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j]->buffer;
2963         slice_data_bo = decode_state->slice_datas[j]->bo;
2964         gen7_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_JPEG, gen7_mfd_context);
2965
2966         if (j == decode_state->num_slice_params - 1)
2967             next_slice_group_param = NULL;
2968         else
2969             next_slice_group_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j + 1]->buffer;
2970
2971         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
2972             int component;
2973
2974             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
2975
2976             if (i < decode_state->slice_params[j]->num_elements - 1)
2977                 next_slice_param = slice_param + 1;
2978             else
2979                 next_slice_param = next_slice_group_param;
2980
2981             for (component = 0; component < slice_param->num_components; component++) {
2982                 if (max_selector < slice_param->components[component].dc_table_selector)
2983                     max_selector = slice_param->components[component].dc_table_selector;
2984
2985                 if (max_selector < slice_param->components[component].ac_table_selector)
2986                     max_selector = slice_param->components[component].ac_table_selector;
2987             }
2988
2989             slice_param++;
2990         }
2991     }
2992
2993     assert(max_selector < 2);
2994     gen7_mfd_jpeg_huff_table_state(ctx, decode_state, gen7_mfd_context, max_selector + 1);
2995
2996     for (j = 0; j < decode_state->num_slice_params; j++) {
2997         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
2998         slice_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j]->buffer;
2999         slice_data_bo = decode_state->slice_datas[j]->bo;
3000         gen7_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_JPEG, gen7_mfd_context);
3001
3002         if (j == decode_state->num_slice_params - 1)
3003             next_slice_group_param = NULL;
3004         else
3005             next_slice_group_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j + 1]->buffer;
3006
3007         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
3008             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
3009
3010             if (i < decode_state->slice_params[j]->num_elements - 1)
3011                 next_slice_param = slice_param + 1;
3012             else
3013                 next_slice_param = next_slice_group_param;
3014
3015             gen7_mfd_jpeg_bsd_object(ctx, pic_param, slice_param, next_slice_param, slice_data_bo, gen7_mfd_context);
3016             slice_param++;
3017         }
3018     }
3019
3020     intel_batchbuffer_end_atomic(batch);
3021     intel_batchbuffer_flush(batch);
3022 }
3023
3024 static VAStatus
3025 gen7_mfd_decode_picture(VADriverContextP ctx,
3026                         VAProfile profile,
3027                         union codec_state *codec_state,
3028                         struct hw_context *hw_context)
3029
3030 {
3031     struct gen7_mfd_context *gen7_mfd_context = (struct gen7_mfd_context *)hw_context;
3032     struct decode_state *decode_state = &codec_state->decode;
3033     VAStatus vaStatus;
3034
3035     assert(gen7_mfd_context);
3036
3037     vaStatus = intel_decoder_sanity_check_input(ctx, profile, decode_state);
3038
3039     if (vaStatus != VA_STATUS_SUCCESS)
3040         goto out;
3041
3042     gen7_mfd_context->wa_mpeg2_slice_vertical_position = -1;
3043
3044     switch (profile) {
3045     case VAProfileMPEG2Simple:
3046     case VAProfileMPEG2Main:
3047         gen7_mfd_mpeg2_decode_picture(ctx, decode_state, gen7_mfd_context);
3048         break;
3049
3050     case VAProfileH264ConstrainedBaseline:
3051     case VAProfileH264Main:
3052     case VAProfileH264High:
3053     case VAProfileH264StereoHigh:
3054         gen7_mfd_avc_decode_picture(ctx, decode_state, gen7_mfd_context);
3055         break;
3056
3057     case VAProfileVC1Simple:
3058     case VAProfileVC1Main:
3059     case VAProfileVC1Advanced:
3060         gen7_mfd_vc1_decode_picture(ctx, decode_state, gen7_mfd_context);
3061         break;
3062
3063     case VAProfileJPEGBaseline:
3064         gen7_mfd_jpeg_decode_picture(ctx, decode_state, gen7_mfd_context);
3065         break;
3066
3067     default:
3068         assert(0);
3069         break;
3070     }
3071
3072     vaStatus = VA_STATUS_SUCCESS;
3073
3074 out:
3075     return vaStatus;
3076 }
3077
3078 static void
3079 gen7_mfd_context_destroy(void *hw_context)
3080 {
3081     VADriverContextP ctx;
3082     struct gen7_mfd_context *gen7_mfd_context = (struct gen7_mfd_context *)hw_context;
3083
3084     ctx = (VADriverContextP)(gen7_mfd_context->driver_context);
3085
3086     dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo);
3087     gen7_mfd_context->post_deblocking_output.bo = NULL;
3088
3089     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
3090     gen7_mfd_context->pre_deblocking_output.bo = NULL;
3091
3092     dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo);
3093     gen7_mfd_context->intra_row_store_scratch_buffer.bo = NULL;
3094
3095     dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
3096     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
3097
3098     dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
3099     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
3100
3101     dri_bo_unreference(gen7_mfd_context->mpr_row_store_scratch_buffer.bo);
3102     gen7_mfd_context->mpr_row_store_scratch_buffer.bo = NULL;
3103
3104     dri_bo_unreference(gen7_mfd_context->bitplane_read_buffer.bo);
3105     gen7_mfd_context->bitplane_read_buffer.bo = NULL;
3106
3107     dri_bo_unreference(gen7_mfd_context->jpeg_wa_slice_data_bo);
3108
3109     if (gen7_mfd_context->jpeg_wa_surface_id != VA_INVALID_SURFACE) {
3110         i965_DestroySurfaces(ctx,
3111                              &gen7_mfd_context->jpeg_wa_surface_id,
3112                              1);
3113         gen7_mfd_context->jpeg_wa_surface_object = NULL;
3114     }
3115
3116     intel_batchbuffer_free(gen7_mfd_context->base.batch);
3117     free(gen7_mfd_context);
3118 }
3119
3120 static void gen7_mfd_mpeg2_context_init(VADriverContextP ctx,
3121                                         struct gen7_mfd_context *gen7_mfd_context)
3122 {
3123     gen7_mfd_context->iq_matrix.mpeg2.load_intra_quantiser_matrix = -1;
3124     gen7_mfd_context->iq_matrix.mpeg2.load_non_intra_quantiser_matrix = -1;
3125     gen7_mfd_context->iq_matrix.mpeg2.load_chroma_intra_quantiser_matrix = -1;
3126     gen7_mfd_context->iq_matrix.mpeg2.load_chroma_non_intra_quantiser_matrix = -1;
3127 }
3128
3129 struct hw_context *
3130 gen7_dec_hw_context_init(VADriverContextP ctx, struct object_config *obj_config)
3131 {
3132     struct intel_driver_data *intel = intel_driver_data(ctx);
3133     struct gen7_mfd_context *gen7_mfd_context = calloc(1, sizeof(struct gen7_mfd_context));
3134     int i;
3135
3136     assert(gen7_mfd_context);
3137     gen7_mfd_context->base.destroy = gen7_mfd_context_destroy;
3138     gen7_mfd_context->base.run = gen7_mfd_decode_picture;
3139     gen7_mfd_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER, 0);
3140
3141     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
3142         gen7_mfd_context->reference_surface[i].surface_id = VA_INVALID_ID;
3143         gen7_mfd_context->reference_surface[i].frame_store_id = -1;
3144         gen7_mfd_context->reference_surface[i].obj_surface = NULL;
3145     }
3146
3147     gen7_mfd_context->jpeg_wa_surface_id = VA_INVALID_SURFACE;
3148     gen7_mfd_context->jpeg_wa_surface_object = NULL;
3149
3150     switch (obj_config->profile) {
3151     case VAProfileMPEG2Simple:
3152     case VAProfileMPEG2Main:
3153         gen7_mfd_mpeg2_context_init(ctx, gen7_mfd_context);
3154         break;
3155
3156     case VAProfileH264ConstrainedBaseline:
3157     case VAProfileH264Main:
3158     case VAProfileH264High:
3159     case VAProfileH264StereoHigh:
3160         gen7_mfd_avc_context_init(ctx, gen7_mfd_context);
3161         break;
3162     default:
3163         break;
3164     }
3165
3166     gen7_mfd_context->driver_context = ctx;
3167     return (struct hw_context *)gen7_mfd_context;
3168 }