2 * Copyright © 2010-2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Zhao Yakui <yakui.zhao@intel.com>
35 #include "intel_batchbuffer.h"
36 #include "intel_driver.h"
38 #include "i965_defines.h"
39 #include "i965_drv_video.h"
40 #include "i965_encoder.h"
43 #ifdef SURFACE_STATE_PADDED_SIZE
44 #undef SURFACE_STATE_PADDED_SIZE
47 #define VME_MSG_LENGTH 32
49 #define SURFACE_STATE_PADDED_SIZE SURFACE_STATE_PADDED_SIZE_GEN7
50 #define SURFACE_STATE_OFFSET(index) (SURFACE_STATE_PADDED_SIZE * index)
51 #define BINDING_TABLE_OFFSET(index) (SURFACE_STATE_OFFSET(MAX_MEDIA_SURFACES_GEN6) + sizeof(unsigned int) * index)
53 #define CURBE_ALLOCATION_SIZE 37 /* in 256-bit */
54 #define CURBE_TOTAL_DATA_LENGTH (4 * 32) /* in byte, it should be less than or equal to CURBE_ALLOCATION_SIZE * 32 */
55 #define CURBE_URB_ENTRY_LENGTH 4 /* in 256-bit, it should be less than or equal to CURBE_TOTAL_DATA_LENGTH / 32 */
57 enum VIDEO_CODING_TYPE{
63 enum AVC_VME_KERNEL_TYPE{
64 AVC_VME_INTRA_SHADER = 0,
67 AVC_VME_BINTER_SHADER,
71 enum MPEG2_VME_KERNEL_TYPE{
72 MPEG2_VME_INTER_SHADER = 0,
73 MPEG2_VME_BATCHBUFFER,
78 static const uint32_t gen7_vme_intra_frame[][4] = {
79 #include "shaders/vme/intra_frame_ivb.g7b"
82 static const uint32_t gen7_vme_inter_frame[][4] = {
83 #include "shaders/vme/inter_frame_ivb.g7b"
86 static const uint32_t gen7_vme_batchbuffer[][4] = {
87 #include "shaders/vme/batchbuffer.g7b"
90 static const uint32_t gen7_vme_binter_frame[][4] = {
91 #include "shaders/vme/inter_bframe_ivb.g7b"
94 static struct i965_kernel gen7_vme_kernels[] = {
96 "AVC VME Intra Frame",
97 AVC_VME_INTRA_SHADER, /*index*/
99 sizeof(gen7_vme_intra_frame),
103 "AVC VME inter Frame",
104 AVC_VME_INTER_SHADER,
105 gen7_vme_inter_frame,
106 sizeof(gen7_vme_inter_frame),
110 "AVC VME BATCHBUFFER",
112 gen7_vme_batchbuffer,
113 sizeof(gen7_vme_batchbuffer),
117 "AVC VME binter Frame",
118 AVC_VME_BINTER_SHADER,
119 gen7_vme_binter_frame,
120 sizeof(gen7_vme_binter_frame),
125 static const uint32_t gen7_vme_mpeg2_inter_frame[][4] = {
126 #include "shaders/vme/mpeg2_inter_ivb.g7b"
129 static const uint32_t gen7_vme_mpeg2_batchbuffer[][4] = {
130 #include "shaders/vme/batchbuffer.g7b"
133 static struct i965_kernel gen7_vme_mpeg2_kernels[] = {
135 "MPEG2 VME inter Frame",
136 MPEG2_VME_INTER_SHADER,
137 gen7_vme_mpeg2_inter_frame,
138 sizeof(gen7_vme_mpeg2_inter_frame),
142 "MPEG2 VME BATCHBUFFER",
143 MPEG2_VME_BATCHBUFFER,
144 gen7_vme_mpeg2_batchbuffer,
145 sizeof(gen7_vme_mpeg2_batchbuffer),
150 /* only used for VME source surface state */
152 gen7_vme_source_surface_state(VADriverContextP ctx,
154 struct object_surface *obj_surface,
155 struct intel_encoder_context *encoder_context)
157 struct gen6_vme_context *vme_context = encoder_context->vme_context;
159 vme_context->vme_surface2_setup(ctx,
160 &vme_context->gpe_context,
162 BINDING_TABLE_OFFSET(index),
163 SURFACE_STATE_OFFSET(index));
167 gen7_vme_media_source_surface_state(VADriverContextP ctx,
169 struct object_surface *obj_surface,
170 struct intel_encoder_context *encoder_context)
172 struct gen6_vme_context *vme_context = encoder_context->vme_context;
174 vme_context->vme_media_rw_surface_setup(ctx,
175 &vme_context->gpe_context,
177 BINDING_TABLE_OFFSET(index),
178 SURFACE_STATE_OFFSET(index));
182 gen7_vme_output_buffer_setup(VADriverContextP ctx,
183 struct encode_state *encode_state,
185 struct intel_encoder_context *encoder_context)
188 struct i965_driver_data *i965 = i965_driver_data(ctx);
189 struct gen6_vme_context *vme_context = encoder_context->vme_context;
190 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
191 VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
192 int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
193 int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
194 int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
196 vme_context->vme_output.num_blocks = width_in_mbs * height_in_mbs;
197 vme_context->vme_output.pitch = 16; /* in bytes, always 16 */
200 vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES;
202 vme_context->vme_output.size_block = INTER_VME_OUTPUT_IN_BYTES;
204 vme_context->vme_output.bo = dri_bo_alloc(i965->intel.bufmgr,
206 vme_context->vme_output.num_blocks * vme_context->vme_output.size_block,
208 assert(vme_context->vme_output.bo);
209 vme_context->vme_buffer_suface_setup(ctx,
210 &vme_context->gpe_context,
211 &vme_context->vme_output,
212 BINDING_TABLE_OFFSET(index),
213 SURFACE_STATE_OFFSET(index));
217 gen7_vme_output_vme_batchbuffer_setup(VADriverContextP ctx,
218 struct encode_state *encode_state,
220 struct intel_encoder_context *encoder_context)
223 struct i965_driver_data *i965 = i965_driver_data(ctx);
224 struct gen6_vme_context *vme_context = encoder_context->vme_context;
225 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
226 int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
227 int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
229 vme_context->vme_batchbuffer.num_blocks = width_in_mbs * height_in_mbs + 1;
230 vme_context->vme_batchbuffer.size_block = 32; /* 2 OWORDs */
231 vme_context->vme_batchbuffer.pitch = 16;
232 vme_context->vme_batchbuffer.bo = dri_bo_alloc(i965->intel.bufmgr,
234 vme_context->vme_batchbuffer.num_blocks * vme_context->vme_batchbuffer.size_block,
236 vme_context->vme_buffer_suface_setup(ctx,
237 &vme_context->gpe_context,
238 &vme_context->vme_batchbuffer,
239 BINDING_TABLE_OFFSET(index),
240 SURFACE_STATE_OFFSET(index));
244 gen7_vme_surface_setup(VADriverContextP ctx,
245 struct encode_state *encode_state,
247 struct intel_encoder_context *encoder_context)
249 struct object_surface *obj_surface;
251 /*Setup surfaces state*/
252 /* current picture for encoding */
253 obj_surface = encode_state->input_yuv_object;
254 gen7_vme_source_surface_state(ctx, 0, obj_surface, encoder_context);
255 gen7_vme_media_source_surface_state(ctx, 4, obj_surface, encoder_context);
258 VAEncSliceParameterBufferH264 *slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
261 slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type);
262 assert(slice_type != SLICE_TYPE_I && slice_type != SLICE_TYPE_SI);
264 intel_avc_vme_reference_state(ctx, encode_state, encoder_context, 0, 1, gen7_vme_source_surface_state);
266 if (slice_type == SLICE_TYPE_B)
267 intel_avc_vme_reference_state(ctx, encode_state, encoder_context, 1, 2, gen7_vme_source_surface_state);
271 gen7_vme_output_buffer_setup(ctx, encode_state, 3, encoder_context);
272 gen7_vme_output_vme_batchbuffer_setup(ctx, encode_state, 5, encoder_context);
274 return VA_STATUS_SUCCESS;
277 static VAStatus gen7_vme_interface_setup(VADriverContextP ctx,
278 struct encode_state *encode_state,
279 struct intel_encoder_context *encoder_context)
281 struct gen6_vme_context *vme_context = encoder_context->vme_context;
282 struct gen6_interface_descriptor_data *desc;
286 bo = vme_context->gpe_context.idrt.bo;
291 for (i = 0; i < vme_context->vme_kernel_sum; i++) {
292 struct i965_kernel *kernel;
293 kernel = &vme_context->gpe_context.kernels[i];
294 assert(sizeof(*desc) == 32);
295 /*Setup the descritor table*/
296 memset(desc, 0, sizeof(*desc));
297 desc->desc0.kernel_start_pointer = (kernel->bo->offset >> 6);
298 desc->desc2.sampler_count = 1; /* FIXME: */
299 desc->desc2.sampler_state_pointer = (vme_context->vme_state.bo->offset >> 5);
300 desc->desc3.binding_table_entry_count = 1; /* FIXME: */
301 desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET(0) >> 5);
302 desc->desc4.constant_urb_entry_read_offset = 0;
303 desc->desc4.constant_urb_entry_read_length = CURBE_URB_ENTRY_LENGTH;
306 dri_bo_emit_reloc(bo,
307 I915_GEM_DOMAIN_INSTRUCTION, 0,
309 i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc0),
311 /*Sampler State(VME state pointer)*/
312 dri_bo_emit_reloc(bo,
313 I915_GEM_DOMAIN_INSTRUCTION, 0,
315 i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc2),
316 vme_context->vme_state.bo);
321 return VA_STATUS_SUCCESS;
324 static VAStatus gen7_vme_constant_setup(VADriverContextP ctx,
325 struct encode_state *encode_state,
326 struct intel_encoder_context *encoder_context)
328 struct gen6_vme_context *vme_context = encoder_context->vme_context;
329 unsigned char *constant_buffer;
330 unsigned int *vme_state_message;
333 vme_state_message = (unsigned int *)vme_context->vme_state_message;
336 if (encoder_context->codec == CODEC_H264) {
337 if (vme_context->h264_level >= 30) {
340 if (vme_context->h264_level >= 31)
343 } else if (encoder_context->codec == CODEC_MPEG2) {
348 vme_state_message[31] = mv_num;
350 dri_bo_map(vme_context->gpe_context.curbe.bo, 1);
351 assert(vme_context->gpe_context.curbe.bo->virtual);
352 constant_buffer = vme_context->gpe_context.curbe.bo->virtual;
354 /* Pass the required constant info into the constant buffer */
355 memcpy(constant_buffer, (char *)vme_context->vme_state_message, 128);
357 dri_bo_unmap( vme_context->gpe_context.curbe.bo);
359 return VA_STATUS_SUCCESS;
363 static VAStatus gen7_vme_avc_state_setup(VADriverContextP ctx,
364 struct encode_state *encode_state,
366 struct intel_encoder_context *encoder_context)
368 struct gen6_vme_context *vme_context = encoder_context->vme_context;
369 unsigned int *vme_state_message;
370 unsigned int *mb_cost_table;
372 VAEncSliceParameterBufferH264 *slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
374 mb_cost_table = (unsigned int *)vme_context->vme_state_message;
375 //building VME state message
376 dri_bo_map(vme_context->vme_state.bo, 1);
377 assert(vme_context->vme_state.bo->virtual);
378 vme_state_message = (unsigned int *)vme_context->vme_state.bo->virtual;
380 if ((slice_param->slice_type == SLICE_TYPE_P) ||
381 (slice_param->slice_type == SLICE_TYPE_SP)) {
382 vme_state_message[0] = 0x01010101;
383 vme_state_message[1] = 0x10010101;
384 vme_state_message[2] = 0x0F0F0F0F;
385 vme_state_message[3] = 0x100F0F0F;
386 vme_state_message[4] = 0x01010101;
387 vme_state_message[5] = 0x10010101;
388 vme_state_message[6] = 0x0F0F0F0F;
389 vme_state_message[7] = 0x100F0F0F;
390 vme_state_message[8] = 0x01010101;
391 vme_state_message[9] = 0x10010101;
392 vme_state_message[10] = 0x0F0F0F0F;
393 vme_state_message[11] = 0x000F0F0F;
394 vme_state_message[12] = 0x00;
395 vme_state_message[13] = 0x00;
397 vme_state_message[0] = 0x10010101;
398 vme_state_message[1] = 0x100F0F0F;
399 vme_state_message[2] = 0x10010101;
400 vme_state_message[3] = 0x000F0F0F;
401 vme_state_message[4] = 0;
402 vme_state_message[5] = 0;
403 vme_state_message[6] = 0;
404 vme_state_message[7] = 0;
405 vme_state_message[8] = 0;
406 vme_state_message[9] = 0;
407 vme_state_message[10] = 0;
408 vme_state_message[11] = 0;
409 vme_state_message[12] = 0;
410 vme_state_message[13] = 0;
413 vme_state_message[14] = (mb_cost_table[2] & 0xFFFF);
414 vme_state_message[15] = 0;
415 vme_state_message[16] = mb_cost_table[0];
416 vme_state_message[17] = mb_cost_table[1];
417 vme_state_message[18] = mb_cost_table[3];
418 vme_state_message[19] = mb_cost_table[4];
420 for(i = 20; i < 32; i++) {
421 vme_state_message[i] = 0;
424 dri_bo_unmap( vme_context->vme_state.bo);
425 return VA_STATUS_SUCCESS;
428 static VAStatus gen7_vme_mpeg2_state_setup(VADriverContextP ctx,
429 struct encode_state *encode_state,
431 struct intel_encoder_context *encoder_context)
433 struct gen6_vme_context *vme_context = encoder_context->vme_context;
434 unsigned int *vme_state_message;
436 unsigned int *mb_cost_table;
438 mb_cost_table = (unsigned int *)vme_context->vme_state_message;
440 //building VME state message
441 dri_bo_map(vme_context->vme_state.bo, 1);
442 assert(vme_context->vme_state.bo->virtual);
443 vme_state_message = (unsigned int *)vme_context->vme_state.bo->virtual;
445 vme_state_message[0] = 0x01010101;
446 vme_state_message[1] = 0x10010101;
447 vme_state_message[2] = 0x0F0F0F0F;
448 vme_state_message[3] = 0x100F0F0F;
449 vme_state_message[4] = 0x01010101;
450 vme_state_message[5] = 0x10010101;
451 vme_state_message[6] = 0x0F0F0F0F;
452 vme_state_message[7] = 0x100F0F0F;
453 vme_state_message[8] = 0x01010101;
454 vme_state_message[9] = 0x10010101;
455 vme_state_message[10] = 0x0F0F0F0F;
456 vme_state_message[11] = 0x000F0F0F;
457 vme_state_message[12] = 0x00;
458 vme_state_message[13] = 0x00;
460 vme_state_message[14] = (mb_cost_table[2] & 0xFFFF);
461 vme_state_message[15] = 0;
462 vme_state_message[16] = mb_cost_table[0];
463 vme_state_message[17] = 0;
464 vme_state_message[18] = mb_cost_table[3];
465 vme_state_message[19] = mb_cost_table[4];
467 for(i = 20; i < 32; i++) {
468 vme_state_message[i] = 0;
470 //vme_state_message[16] = 0x42424242; //cost function LUT set 0 for Intra
472 dri_bo_unmap( vme_context->vme_state.bo);
473 return VA_STATUS_SUCCESS;
477 gen7_vme_fill_vme_batchbuffer(VADriverContextP ctx,
478 struct encode_state *encode_state,
479 int mb_width, int mb_height,
481 int transform_8x8_mode_flag,
482 struct intel_encoder_context *encoder_context)
484 struct gen6_vme_context *vme_context = encoder_context->vme_context;
485 int mb_x = 0, mb_y = 0;
487 unsigned int *command_ptr;
490 dri_bo_map(vme_context->vme_batchbuffer.bo, 1);
491 command_ptr = vme_context->vme_batchbuffer.bo->virtual;
493 for (s = 0; s < encode_state->num_slice_params_ext; s++) {
494 VAEncSliceParameterBufferMPEG2 *slice_param = (VAEncSliceParameterBufferMPEG2 *)encode_state->slice_params_ext[s]->buffer;
496 for (j = 0; j < encode_state->slice_params_ext[s]->num_elements; j++) {
497 int slice_mb_begin = slice_param->macroblock_address;
498 int slice_mb_number = slice_param->num_macroblocks;
499 unsigned int mb_intra_ub;
500 int slice_mb_x = slice_param->macroblock_address % mb_width;
502 for (i = 0; i < slice_mb_number;) {
503 int mb_count = i + slice_mb_begin;
505 mb_x = mb_count % mb_width;
506 mb_y = mb_count / mb_width;
510 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_AE;
514 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_B;
517 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_D;
519 if (mb_x != (mb_width -1))
520 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C;
525 mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_AE);
527 mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_BCD_MASK);
529 if ((i == (mb_width - 1)) && slice_mb_x) {
530 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C;
534 if ((i == mb_width) && slice_mb_x) {
535 mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_D);
538 *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2));
539 *command_ptr++ = kernel;
546 *command_ptr++ = (mb_width << 16 | mb_y << 8 | mb_x);
547 *command_ptr++ = ( (1 << 16) | transform_8x8_mode_flag | (mb_intra_ub << 8));
557 *command_ptr++ = MI_BATCH_BUFFER_END;
559 dri_bo_unmap(vme_context->vme_batchbuffer.bo);
563 static void gen7_vme_media_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
565 struct i965_driver_data *i965 = i965_driver_data(ctx);
566 struct gen6_vme_context *vme_context = encoder_context->vme_context;
569 i965_gpe_context_init(ctx, &vme_context->gpe_context);
571 /* VME output buffer */
572 dri_bo_unreference(vme_context->vme_output.bo);
573 vme_context->vme_output.bo = NULL;
575 dri_bo_unreference(vme_context->vme_batchbuffer.bo);
576 vme_context->vme_batchbuffer.bo = NULL;
579 dri_bo_unreference(vme_context->vme_state.bo);
580 bo = dri_bo_alloc(i965->intel.bufmgr,
584 vme_context->vme_state.bo = bo;
587 static void gen7_vme_pipeline_programing(VADriverContextP ctx,
588 struct encode_state *encode_state,
589 struct intel_encoder_context *encoder_context)
591 struct gen6_vme_context *vme_context = encoder_context->vme_context;
592 struct intel_batchbuffer *batch = encoder_context->base.batch;
593 VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
594 VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
595 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
596 int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
597 int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
599 bool allow_hwscore = true;
602 for (s = 0; s < encode_state->num_slice_params_ext; s++) {
603 pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[s]->buffer;
604 if ((pSliceParameter->macroblock_address % width_in_mbs)) {
605 allow_hwscore = false;
610 if ((pSliceParameter->slice_type == SLICE_TYPE_I) ||
611 (pSliceParameter->slice_type == SLICE_TYPE_I)) {
612 kernel_shader = AVC_VME_INTRA_SHADER;
613 } else if ((pSliceParameter->slice_type == SLICE_TYPE_P) ||
614 (pSliceParameter->slice_type == SLICE_TYPE_SP)) {
615 kernel_shader = AVC_VME_INTER_SHADER;
617 kernel_shader = AVC_VME_BINTER_SHADER;
619 kernel_shader = AVC_VME_INTER_SHADER;
623 gen7_vme_walker_fill_vme_batchbuffer(ctx,
625 width_in_mbs, height_in_mbs,
627 pPicParameter->pic_fields.bits.transform_8x8_mode_flag,
631 gen7_vme_fill_vme_batchbuffer(ctx,
633 width_in_mbs, height_in_mbs,
635 pPicParameter->pic_fields.bits.transform_8x8_mode_flag,
638 intel_batchbuffer_start_atomic(batch, 0x1000);
639 gen6_gpe_pipeline_setup(ctx, &vme_context->gpe_context, batch);
640 BEGIN_BATCH(batch, 2);
641 OUT_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8));
643 vme_context->vme_batchbuffer.bo,
644 I915_GEM_DOMAIN_COMMAND, 0,
646 ADVANCE_BATCH(batch);
648 intel_batchbuffer_end_atomic(batch);
651 static VAStatus gen7_vme_prepare(VADriverContextP ctx,
652 struct encode_state *encode_state,
653 struct intel_encoder_context *encoder_context)
655 VAStatus vaStatus = VA_STATUS_SUCCESS;
656 VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
657 int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
658 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
659 struct gen6_vme_context *vme_context = encoder_context->vme_context;
661 if (!vme_context->h264_level ||
662 (vme_context->h264_level != pSequenceParameter->level_idc)) {
663 vme_context->h264_level = pSequenceParameter->level_idc;
666 intel_vme_update_mbmv_cost(ctx, encode_state, encoder_context);
667 /*Setup all the memory object*/
668 gen7_vme_surface_setup(ctx, encode_state, is_intra, encoder_context);
669 gen7_vme_interface_setup(ctx, encode_state, encoder_context);
670 gen7_vme_constant_setup(ctx, encode_state, encoder_context);
671 gen7_vme_avc_state_setup(ctx, encode_state, is_intra, encoder_context);
673 /*Programing media pipeline*/
674 gen7_vme_pipeline_programing(ctx, encode_state, encoder_context);
679 static VAStatus gen7_vme_run(VADriverContextP ctx,
680 struct encode_state *encode_state,
681 struct intel_encoder_context *encoder_context)
683 struct intel_batchbuffer *batch = encoder_context->base.batch;
685 intel_batchbuffer_flush(batch);
687 return VA_STATUS_SUCCESS;
690 static VAStatus gen7_vme_stop(VADriverContextP ctx,
691 struct encode_state *encode_state,
692 struct intel_encoder_context *encoder_context)
694 return VA_STATUS_SUCCESS;
698 gen7_vme_pipeline(VADriverContextP ctx,
700 struct encode_state *encode_state,
701 struct intel_encoder_context *encoder_context)
703 gen7_vme_media_init(ctx, encoder_context);
704 gen7_vme_prepare(ctx, encode_state, encoder_context);
705 gen7_vme_run(ctx, encode_state, encoder_context);
706 gen7_vme_stop(ctx, encode_state, encoder_context);
708 return VA_STATUS_SUCCESS;
712 gen7_vme_mpeg2_output_buffer_setup(VADriverContextP ctx,
713 struct encode_state *encode_state,
716 struct intel_encoder_context *encoder_context)
719 struct i965_driver_data *i965 = i965_driver_data(ctx);
720 struct gen6_vme_context *vme_context = encoder_context->vme_context;
721 VAEncSequenceParameterBufferMPEG2 *seq_param = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer;
722 int width_in_mbs = ALIGN(seq_param->picture_width, 16) / 16;
723 int height_in_mbs = ALIGN(seq_param->picture_height, 16) / 16;
725 vme_context->vme_output.num_blocks = width_in_mbs * height_in_mbs;
726 vme_context->vme_output.pitch = 16; /* in bytes, always 16 */
729 vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES;
731 vme_context->vme_output.size_block = INTER_VME_OUTPUT_IN_BYTES;
733 vme_context->vme_output.bo = dri_bo_alloc(i965->intel.bufmgr,
735 vme_context->vme_output.num_blocks * vme_context->vme_output.size_block,
737 assert(vme_context->vme_output.bo);
738 vme_context->vme_buffer_suface_setup(ctx,
739 &vme_context->gpe_context,
740 &vme_context->vme_output,
741 BINDING_TABLE_OFFSET(index),
742 SURFACE_STATE_OFFSET(index));
746 gen7_vme_mpeg2_output_vme_batchbuffer_setup(VADriverContextP ctx,
747 struct encode_state *encode_state,
749 struct intel_encoder_context *encoder_context)
752 struct i965_driver_data *i965 = i965_driver_data(ctx);
753 struct gen6_vme_context *vme_context = encoder_context->vme_context;
754 VAEncSequenceParameterBufferMPEG2 *seq_param = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer;
755 int width_in_mbs = ALIGN(seq_param->picture_width, 16) / 16;
756 int height_in_mbs = ALIGN(seq_param->picture_height, 16) / 16;
758 vme_context->vme_batchbuffer.num_blocks = width_in_mbs * height_in_mbs + 1;
759 vme_context->vme_batchbuffer.size_block = 32; /* 4 OWORDs */
760 vme_context->vme_batchbuffer.pitch = 16;
761 vme_context->vme_batchbuffer.bo = dri_bo_alloc(i965->intel.bufmgr,
763 vme_context->vme_batchbuffer.num_blocks * vme_context->vme_batchbuffer.size_block,
765 vme_context->vme_buffer_suface_setup(ctx,
766 &vme_context->gpe_context,
767 &vme_context->vme_batchbuffer,
768 BINDING_TABLE_OFFSET(index),
769 SURFACE_STATE_OFFSET(index));
773 gen7_vme_mpeg2_surface_setup(VADriverContextP ctx,
774 struct encode_state *encode_state,
776 struct intel_encoder_context *encoder_context)
778 struct object_surface *obj_surface;
780 /*Setup surfaces state*/
781 /* current picture for encoding */
782 obj_surface = encode_state->input_yuv_object;
783 gen7_vme_source_surface_state(ctx, 0, obj_surface, encoder_context);
784 gen7_vme_media_source_surface_state(ctx, 4, obj_surface, encoder_context);
788 obj_surface = encode_state->reference_objects[0];
789 if (obj_surface->bo != NULL)
790 gen7_vme_source_surface_state(ctx, 1, obj_surface, encoder_context);
793 obj_surface = encode_state->reference_objects[1];
794 if (obj_surface && obj_surface->bo != NULL)
795 gen7_vme_source_surface_state(ctx, 2, obj_surface, encoder_context);
799 gen7_vme_mpeg2_output_buffer_setup(ctx, encode_state, 3, is_intra, encoder_context);
800 gen7_vme_mpeg2_output_vme_batchbuffer_setup(ctx, encode_state, 5, encoder_context);
802 return VA_STATUS_SUCCESS;
806 gen7_vme_mpeg2_fill_vme_batchbuffer(VADriverContextP ctx,
807 struct encode_state *encode_state,
808 int mb_width, int mb_height,
810 int transform_8x8_mode_flag,
811 struct intel_encoder_context *encoder_context)
813 struct gen6_vme_context *vme_context = encoder_context->vme_context;
814 int mb_x = 0, mb_y = 0;
816 unsigned int *command_ptr;
818 dri_bo_map(vme_context->vme_batchbuffer.bo, 1);
819 command_ptr = vme_context->vme_batchbuffer.bo->virtual;
821 for (s = 0; s < encode_state->num_slice_params_ext; s++) {
822 VAEncSliceParameterBufferMPEG2 *slice_param = (VAEncSliceParameterBufferMPEG2 *)encode_state->slice_params_ext[s]->buffer;
824 for (j = 0; j < encode_state->slice_params_ext[s]->num_elements; j++) {
825 int slice_mb_begin = slice_param->macroblock_address;
826 int slice_mb_number = slice_param->num_macroblocks;
827 unsigned int mb_intra_ub;
829 for (i = 0; i < slice_mb_number;) {
830 int mb_count = i + slice_mb_begin;
832 mb_x = mb_count % mb_width;
833 mb_y = mb_count / mb_width;
837 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_AE;
841 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_B;
844 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_D;
846 if (mb_x != (mb_width -1))
847 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C;
852 *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2));
853 *command_ptr++ = kernel;
860 *command_ptr++ = (mb_width << 16 | mb_y << 8 | mb_x);
861 *command_ptr++ = ( (1 << 16) | transform_8x8_mode_flag | (mb_intra_ub << 8));
871 *command_ptr++ = MI_BATCH_BUFFER_END;
873 dri_bo_unmap(vme_context->vme_batchbuffer.bo);
877 gen7_vme_mpeg2_pipeline_programing(VADriverContextP ctx,
878 struct encode_state *encode_state,
880 struct intel_encoder_context *encoder_context)
882 struct gen6_vme_context *vme_context = encoder_context->vme_context;
883 struct intel_batchbuffer *batch = encoder_context->base.batch;
884 VAEncSequenceParameterBufferMPEG2 *seq_param = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer;
885 int width_in_mbs = ALIGN(seq_param->picture_width, 16) / 16;
886 int height_in_mbs = ALIGN(seq_param->picture_height, 16) / 16;
888 bool allow_hwscore = true;
891 for (s = 0; s < encode_state->num_slice_params_ext; s++) {
893 VAEncSliceParameterBufferMPEG2 *slice_param = (VAEncSliceParameterBufferMPEG2 *)encode_state->slice_params_ext[s]->buffer;
895 for (j = 0; j < encode_state->slice_params_ext[s]->num_elements; j++) {
896 if (slice_param->macroblock_address % width_in_mbs) {
897 allow_hwscore = false;
904 gen7_vme_mpeg2_walker_fill_vme_batchbuffer(ctx,
906 width_in_mbs, height_in_mbs,
907 MPEG2_VME_INTER_SHADER,
910 gen7_vme_mpeg2_fill_vme_batchbuffer(ctx,
912 width_in_mbs, height_in_mbs,
913 MPEG2_VME_INTER_SHADER,
917 intel_batchbuffer_start_atomic(batch, 0x1000);
918 gen6_gpe_pipeline_setup(ctx, &vme_context->gpe_context, batch);
919 BEGIN_BATCH(batch, 2);
920 OUT_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8));
922 vme_context->vme_batchbuffer.bo,
923 I915_GEM_DOMAIN_COMMAND, 0,
925 ADVANCE_BATCH(batch);
927 intel_batchbuffer_end_atomic(batch);
931 gen7_vme_mpeg2_prepare(VADriverContextP ctx,
932 struct encode_state *encode_state,
933 struct intel_encoder_context *encoder_context)
935 VAStatus vaStatus = VA_STATUS_SUCCESS;
936 VAEncSequenceParameterBufferMPEG2 *seq_param = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer;
937 struct gen6_vme_context *vme_context = encoder_context->vme_context;
939 if ((!vme_context->mpeg2_level) ||
940 (vme_context->mpeg2_level != (seq_param->sequence_extension.bits.profile_and_level_indication & MPEG2_LEVEL_MASK))) {
941 vme_context->mpeg2_level = seq_param->sequence_extension.bits.profile_and_level_indication & MPEG2_LEVEL_MASK;
944 /*Setup all the memory object*/
946 intel_vme_mpeg2_state_setup(ctx, encode_state, encoder_context);
947 gen7_vme_mpeg2_surface_setup(ctx, encode_state, 0, encoder_context);
948 gen7_vme_interface_setup(ctx, encode_state, encoder_context);
949 gen7_vme_constant_setup(ctx, encode_state, encoder_context);
950 gen7_vme_mpeg2_state_setup(ctx, encode_state, 0, encoder_context);
952 /*Programing media pipeline*/
953 gen7_vme_mpeg2_pipeline_programing(ctx, encode_state, 0, encoder_context);
959 gen7_vme_mpeg2_pipeline(VADriverContextP ctx,
961 struct encode_state *encode_state,
962 struct intel_encoder_context *encoder_context)
964 struct i965_driver_data *i965 = i965_driver_data(ctx);
965 struct gen6_vme_context *vme_context = encoder_context->vme_context;
966 VAEncSliceParameterBufferMPEG2 *slice_param =
967 (VAEncSliceParameterBufferMPEG2 *)encode_state->slice_params_ext[0]->buffer;
968 VAEncSequenceParameterBufferMPEG2 *seq_param =
969 (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer;
971 /*No need of to exec VME for Intra slice */
972 if (slice_param->is_intra_slice) {
973 if(!vme_context->vme_output.bo) {
974 int w_in_mbs = ALIGN(seq_param->picture_width, 16) / 16;
975 int h_in_mbs = ALIGN(seq_param->picture_height, 16) / 16;
977 vme_context->vme_output.num_blocks = w_in_mbs * h_in_mbs;
978 vme_context->vme_output.pitch = 16; /* in bytes, always 16 */
979 vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES;
980 vme_context->vme_output.bo = dri_bo_alloc(i965->intel.bufmgr,
981 "MPEG2 VME output buffer",
982 vme_context->vme_output.num_blocks
983 * vme_context->vme_output.size_block,
987 return VA_STATUS_SUCCESS;
990 gen7_vme_media_init(ctx, encoder_context);
991 gen7_vme_mpeg2_prepare(ctx, encode_state, encoder_context);
992 gen7_vme_run(ctx, encode_state, encoder_context);
993 gen7_vme_stop(ctx, encode_state, encoder_context);
995 return VA_STATUS_SUCCESS;
999 gen7_vme_context_destroy(void *context)
1001 struct gen6_vme_context *vme_context = context;
1003 i965_gpe_context_destroy(&vme_context->gpe_context);
1005 dri_bo_unreference(vme_context->vme_output.bo);
1006 vme_context->vme_output.bo = NULL;
1008 dri_bo_unreference(vme_context->vme_state.bo);
1009 vme_context->vme_state.bo = NULL;
1011 dri_bo_unreference(vme_context->vme_batchbuffer.bo);
1012 vme_context->vme_batchbuffer.bo = NULL;
1014 if (vme_context->vme_state_message) {
1015 free(vme_context->vme_state_message);
1016 vme_context->vme_state_message = NULL;
1022 Bool gen7_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
1024 struct gen6_vme_context *vme_context = calloc(1, sizeof(struct gen6_vme_context));
1025 struct i965_kernel *vme_kernel_list = NULL;
1027 vme_context->gpe_context.surface_state_binding_table.length =
1028 (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6;
1030 vme_context->gpe_context.idrt.max_entries = MAX_INTERFACE_DESC_GEN6;
1031 vme_context->gpe_context.idrt.entry_size = sizeof(struct gen6_interface_descriptor_data);
1032 vme_context->gpe_context.curbe.length = CURBE_TOTAL_DATA_LENGTH;
1034 vme_context->gpe_context.vfe_state.max_num_threads = 60 - 1;
1035 vme_context->gpe_context.vfe_state.num_urb_entries = 16;
1036 vme_context->gpe_context.vfe_state.gpgpu_mode = 0;
1037 vme_context->gpe_context.vfe_state.urb_entry_size = 59 - 1;
1038 vme_context->gpe_context.vfe_state.curbe_allocation_size = CURBE_ALLOCATION_SIZE - 1;
1040 gen7_vme_scoreboard_init(ctx, vme_context);
1042 if (encoder_context->codec == CODEC_H264) {
1043 vme_kernel_list = gen7_vme_kernels;
1044 vme_context->video_coding_type = VIDEO_CODING_AVC;
1045 vme_context->vme_kernel_sum = AVC_VME_KERNEL_SUM;
1046 encoder_context->vme_pipeline = gen7_vme_pipeline;
1047 } else if (encoder_context->codec == CODEC_MPEG2) {
1048 vme_kernel_list = gen7_vme_mpeg2_kernels;
1049 vme_context->video_coding_type = VIDEO_CODING_MPEG2;
1050 vme_context->vme_kernel_sum = MPEG2_VME_KERNEL_SUM;
1051 encoder_context->vme_pipeline = gen7_vme_mpeg2_pipeline;
1053 /* Unsupported codec */
1057 i965_gpe_load_kernels(ctx,
1058 &vme_context->gpe_context,
1060 vme_context->vme_kernel_sum);
1062 vme_context->vme_surface2_setup = gen7_gpe_surface2_setup;
1063 vme_context->vme_media_rw_surface_setup = gen7_gpe_media_rw_surface_setup;
1064 vme_context->vme_buffer_suface_setup = gen7_gpe_buffer_suface_setup;
1066 encoder_context->vme_context = vme_context;
1067 encoder_context->vme_context_destroy = gen7_vme_context_destroy;
1068 vme_context->vme_state_message = malloc(VME_MSG_LENGTH * sizeof(int));