src/gen8_post_processing.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Xiang Haihao <haihao.xiang@intel.com>
  26  *    Zhao Yakui <yakui.zhao@intel.com>
  27  *
  28  */
  29
  30 #include <stdio.h>
  31 #include <stdlib.h>
  32 #include <string.h>
  33 #include <assert.h>
  34
  35 #include "intel_batchbuffer.h"
  36 #include "intel_driver.h"
  37 #include "i965_defines.h"
  38 #include "i965_structs.h"
  39 #include "i965_drv_video.h"
  40 #include "i965_post_processing.h"
  41 #include "i965_render.h"
  42 #include "i965_yuv_coefs.h"
  43 #include "intel_media.h"
  44
  45 #include "gen75_picture_process.h"
  46 #include "intel_common_vpp_internal.h"
  47
  48 #define SURFACE_STATE_PADDED_SIZE               SURFACE_STATE_PADDED_SIZE_GEN8
  49
  50 #define SURFACE_STATE_OFFSET(index)             (SURFACE_STATE_PADDED_SIZE * index)
  51 #define BINDING_TABLE_OFFSET                    SURFACE_STATE_OFFSET(MAX_PP_SURFACES)
  52
  53 #define GPU_ASM_BLOCK_WIDTH         16
  54 #define GPU_ASM_BLOCK_HEIGHT        8
  55 #define GPU_ASM_X_OFFSET_ALIGNMENT  4
  56
  57 #define VA_STATUS_SUCCESS_1                     0xFFFFFFFE
  58
  59 VAStatus pp_null_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
  60                             const struct i965_surface *src_surface,
  61                             const VARectangle *src_rect,
  62                             struct i965_surface *dst_surface,
  63                             const VARectangle *dst_rect,
  64                             void *filter_param);
  65
  66 VAStatus gen8_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
  67                                     const struct i965_surface *src_surface,
  68                                     const VARectangle *src_rect,
  69                                     struct i965_surface *dst_surface,
  70                                     const VARectangle *dst_rect,
  71                                     void *filter_param);
  72
  73 /* TODO: Modify the shader and then compile it again.
  74  * Currently it is derived from Haswell*/
  75 static const uint32_t pp_null_gen8[][4] = {
  76 };
  77
  78 static const uint32_t pp_nv12_load_save_nv12_gen8[][4] = {
  79 #include "shaders/post_processing/gen8/pl2_to_pl2.g8b"
  80 };
  81
  82 static const uint32_t pp_nv12_load_save_pl3_gen8[][4] = {
  83 #include "shaders/post_processing/gen8/pl2_to_pl3.g8b"
  84 };
  85
  86 static const uint32_t pp_pl3_load_save_nv12_gen8[][4] = {
  87 #include "shaders/post_processing/gen8/pl3_to_pl2.g8b"
  88 };
  89
  90 static const uint32_t pp_pl3_load_save_pl3_gen8[][4] = {
  91 #include "shaders/post_processing/gen8/pl3_to_pl3.g8b"
  92 };
  93
  94 static const uint32_t pp_nv12_scaling_gen8[][4] = {
  95 #include "shaders/post_processing/gen8/pl2_to_pl2.g8b"
  96 };
  97
  98 static const uint32_t pp_nv12_avs_gen8[][4] = {
  99 #include "shaders/post_processing/gen8/pl2_to_pl2.g8b"
 100 };
 101
 102 static const uint32_t pp_nv12_dndi_gen8[][4] = {
 103 // #include "shaders/post_processing/gen7/dndi.g75b"
 104 };
 105
 106 static const uint32_t pp_nv12_dn_gen8[][4] = {
 107 // #include "shaders/post_processing/gen7/nv12_dn_nv12.g75b"
 108 };
 109 static const uint32_t pp_nv12_load_save_pa_gen8[][4] = {
 110 #include "shaders/post_processing/gen8/pl2_to_pa.g8b"
 111 };
 112 static const uint32_t pp_pl3_load_save_pa_gen8[][4] = {
 113 #include "shaders/post_processing/gen8/pl3_to_pa.g8b"
 114 };
 115 static const uint32_t pp_pa_load_save_nv12_gen8[][4] = {
 116 #include "shaders/post_processing/gen8/pa_to_pl2.g8b"
 117 };
 118 static const uint32_t pp_pa_load_save_pl3_gen8[][4] = {
 119 #include "shaders/post_processing/gen8/pa_to_pl3.g8b"
 120 };
 121 static const uint32_t pp_pa_load_save_pa_gen8[][4] = {
 122 #include "shaders/post_processing/gen8/pa_to_pa.g8b"
 123 };
 124 static const uint32_t pp_rgbx_load_save_nv12_gen8[][4] = {
 125 #include "shaders/post_processing/gen8/rgbx_to_nv12.g8b"
 126 };
 127 static const uint32_t pp_nv12_load_save_rgbx_gen8[][4] = {
 128 #include "shaders/post_processing/gen8/pl2_to_rgbx.g8b"
 129 };
 130
 131 static struct pp_module pp_modules_gen8[] = {
 132     {
 133         {
 134             "NULL module (for testing)",
 135             PP_NULL,
 136             pp_null_gen8,
 137             sizeof(pp_null_gen8),
 138             NULL,
 139         },
 140
 141         pp_null_initialize,
 142     },
 143
 144     {
 145         {
 146             "NV12_NV12",
 147             PP_NV12_LOAD_SAVE_N12,
 148             pp_nv12_load_save_nv12_gen8,
 149             sizeof(pp_nv12_load_save_nv12_gen8),
 150             NULL,
 151         },
 152
 153         gen8_pp_plx_avs_initialize,
 154     },
 155
 156     {
 157         {
 158             "NV12_PL3",
 159             PP_NV12_LOAD_SAVE_PL3,
 160             pp_nv12_load_save_pl3_gen8,
 161             sizeof(pp_nv12_load_save_pl3_gen8),
 162             NULL,
 163         },
 164         gen8_pp_plx_avs_initialize,
 165     },
 166
 167     {
 168         {
 169             "PL3_NV12",
 170             PP_PL3_LOAD_SAVE_N12,
 171             pp_pl3_load_save_nv12_gen8,
 172             sizeof(pp_pl3_load_save_nv12_gen8),
 173             NULL,
 174         },
 175
 176         gen8_pp_plx_avs_initialize,
 177     },
 178
 179     {
 180         {
 181             "PL3_PL3",
 182             PP_PL3_LOAD_SAVE_PL3,
 183             pp_pl3_load_save_pl3_gen8,
 184             sizeof(pp_pl3_load_save_pl3_gen8),
 185             NULL,
 186         },
 187
 188         gen8_pp_plx_avs_initialize,
 189     },
 190
 191     {
 192         {
 193             "NV12 Scaling module",
 194             PP_NV12_SCALING,
 195             pp_nv12_scaling_gen8,
 196             sizeof(pp_nv12_scaling_gen8),
 197             NULL,
 198         },
 199
 200         gen8_pp_plx_avs_initialize,
 201     },
 202
 203     {
 204         {
 205             "NV12 AVS module",
 206             PP_NV12_AVS,
 207             pp_nv12_avs_gen8,
 208             sizeof(pp_nv12_avs_gen8),
 209             NULL,
 210         },
 211
 212         gen8_pp_plx_avs_initialize,
 213     },
 214
 215     {
 216         {
 217             "NV12 DNDI module",
 218             PP_NV12_DNDI,
 219             pp_nv12_dndi_gen8,
 220             sizeof(pp_nv12_dndi_gen8),
 221             NULL,
 222         },
 223
 224         pp_null_initialize,
 225     },
 226
 227     {
 228         {
 229             "NV12 DN module",
 230             PP_NV12_DN,
 231             pp_nv12_dn_gen8,
 232             sizeof(pp_nv12_dn_gen8),
 233             NULL,
 234         },
 235
 236         pp_null_initialize,
 237     },
 238     {
 239         {
 240             "NV12_PA module",
 241             PP_NV12_LOAD_SAVE_PA,
 242             pp_nv12_load_save_pa_gen8,
 243             sizeof(pp_nv12_load_save_pa_gen8),
 244             NULL,
 245         },
 246
 247         gen8_pp_plx_avs_initialize,
 248     },
 249
 250     {
 251         {
 252             "PL3_PA module",
 253             PP_PL3_LOAD_SAVE_PA,
 254             pp_pl3_load_save_pa_gen8,
 255             sizeof(pp_pl3_load_save_pa_gen8),
 256             NULL,
 257         },
 258
 259         gen8_pp_plx_avs_initialize,
 260     },
 261
 262     {
 263         {
 264             "PA_NV12 module",
 265             PP_PA_LOAD_SAVE_NV12,
 266             pp_pa_load_save_nv12_gen8,
 267             sizeof(pp_pa_load_save_nv12_gen8),
 268             NULL,
 269         },
 270
 271         gen8_pp_plx_avs_initialize,
 272     },
 273
 274     {
 275         {
 276             "PA_PL3 module",
 277             PP_PA_LOAD_SAVE_PL3,
 278             pp_pa_load_save_pl3_gen8,
 279             sizeof(pp_pa_load_save_pl3_gen8),
 280             NULL,
 281         },
 282
 283         gen8_pp_plx_avs_initialize,
 284     },
 285
 286     {
 287         {
 288             "PA_PA module",
 289             PP_PA_LOAD_SAVE_PA,
 290             pp_pa_load_save_pa_gen8,
 291             sizeof(pp_pa_load_save_pa_gen8),
 292             NULL,
 293         },
 294
 295         gen8_pp_plx_avs_initialize,
 296     },
 297
 298     {
 299         {
 300             "RGBX_NV12 module",
 301             PP_RGBX_LOAD_SAVE_NV12,
 302             pp_rgbx_load_save_nv12_gen8,
 303             sizeof(pp_rgbx_load_save_nv12_gen8),
 304             NULL,
 305         },
 306
 307         gen8_pp_plx_avs_initialize,
 308     },
 309
 310     {
 311         {
 312             "NV12_RGBX module",
 313             PP_NV12_LOAD_SAVE_RGBX,
 314             pp_nv12_load_save_rgbx_gen8,
 315             sizeof(pp_nv12_load_save_rgbx_gen8),
 316             NULL,
 317         },
 318
 319         gen8_pp_plx_avs_initialize,
 320     },
 321 };
 322
 323 #define MAX_SCALING_SURFACES    16
 324
 325 #define DEFAULT_MOCS    0
 326
 327 static const uint32_t pp_yuv420p8_scaling_gen8[][4] = {
 328 #include "shaders/post_processing/gen8/conv_nv12.g8b"
 329 };
 330
 331 static int
 332 pp_get_surface_fourcc(VADriverContextP ctx, const struct i965_surface *surface)
 333 {
 334     int fourcc;
 335
 336     if (surface->type == I965_SURFACE_TYPE_IMAGE) {
 337         struct object_image *obj_image = (struct object_image *)surface->base;
 338         fourcc = obj_image->image.format.fourcc;
 339     } else {
 340         struct object_surface *obj_surface = (struct object_surface *)surface->base;
 341         fourcc = obj_surface->fourcc;
 342     }
 343
 344     return fourcc;
 345 }
 346
 347 static void
 348 gen8_pp_set_surface_tiling(struct gen8_surface_state *ss, unsigned int tiling)
 349 {
 350     switch (tiling) {
 351     case I915_TILING_NONE:
 352         ss->ss0.tiled_surface = 0;
 353         ss->ss0.tile_walk = 0;
 354         break;
 355     case I915_TILING_X:
 356         ss->ss0.tiled_surface = 1;
 357         ss->ss0.tile_walk = I965_TILEWALK_XMAJOR;
 358         break;
 359     case I915_TILING_Y:
 360         ss->ss0.tiled_surface = 1;
 361         ss->ss0.tile_walk = I965_TILEWALK_YMAJOR;
 362         break;
 363     }
 364 }
 365
 366 static void
 367 gen8_pp_set_surface2_tiling(struct gen8_surface_state2 *ss, unsigned int tiling)
 368 {
 369     switch (tiling) {
 370     case I915_TILING_NONE:
 371         ss->ss2.tiled_surface = 0;
 372         ss->ss2.tile_walk = 0;
 373         break;
 374     case I915_TILING_X:
 375         ss->ss2.tiled_surface = 1;
 376         ss->ss2.tile_walk = I965_TILEWALK_XMAJOR;
 377         break;
 378     case I915_TILING_Y:
 379         ss->ss2.tiled_surface = 1;
 380         ss->ss2.tile_walk = I965_TILEWALK_YMAJOR;
 381         break;
 382     }
 383 }
 384
 385
 386 static void
 387 gen8_pp_set_surface_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 388                           dri_bo *surf_bo, unsigned long surf_bo_offset,
 389                           int width, int height, int pitch, int format,
 390                           int index, int is_target)
 391 {
 392     struct i965_driver_data *i965 = i965_driver_data(ctx);
 393     struct gen8_surface_state *ss;
 394     dri_bo *ss_bo;
 395     unsigned int tiling;
 396     unsigned int swizzle;
 397
 398     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
 399     ss_bo = pp_context->surface_state_binding_table.bo;
 400     assert(ss_bo);
 401
 402     dri_bo_map(ss_bo, True);
 403     assert(ss_bo->virtual);
 404     ss = (struct gen8_surface_state *)((char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index));
 405     memset(ss, 0, sizeof(*ss));
 406
 407     if (IS_GEN9(i965->intel.device_info))
 408         ss->ss1.surface_mocs = GEN9_CACHE_PTE;
 409
 410     ss->ss0.surface_type = I965_SURFACE_2D;
 411     ss->ss0.surface_format = format;
 412     ss->ss8.base_addr = surf_bo->offset + surf_bo_offset;
 413     ss->ss2.width = width - 1;
 414     ss->ss2.height = height - 1;
 415     ss->ss3.pitch = pitch - 1;
 416
 417     /* Always set 1(align 4 mode) per B-spec */
 418     ss->ss0.vertical_alignment = 1;
 419     ss->ss0.horizontal_alignment = 1;
 420
 421     gen8_pp_set_surface_tiling(ss, tiling);
 422     gen8_render_set_surface_scs(ss);
 423     dri_bo_emit_reloc(ss_bo,
 424                       I915_GEM_DOMAIN_RENDER, is_target ? I915_GEM_DOMAIN_RENDER : 0,
 425                       surf_bo_offset,
 426                       SURFACE_STATE_OFFSET(index) + offsetof(struct gen8_surface_state, ss8),
 427                       surf_bo);
 428     ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
 429     dri_bo_unmap(ss_bo);
 430 }
 431
 432
 433 static void
 434 gen8_pp_set_surface2_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 435                            dri_bo *surf_bo, unsigned long surf_bo_offset,
 436                            int width, int height, int wpitch,
 437                            int xoffset, int yoffset,
 438                            int format, int interleave_chroma,
 439                            int index)
 440 {
 441     struct i965_driver_data *i965 = i965_driver_data(ctx);
 442     struct gen8_surface_state2 *ss2;
 443     dri_bo *ss2_bo;
 444     unsigned int tiling;
 445     unsigned int swizzle;
 446
 447     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
 448     ss2_bo = pp_context->surface_state_binding_table.bo;
 449     assert(ss2_bo);
 450
 451     dri_bo_map(ss2_bo, True);
 452     assert(ss2_bo->virtual);
 453     ss2 = (struct gen8_surface_state2 *)((char *)ss2_bo->virtual + SURFACE_STATE_OFFSET(index));
 454     memset(ss2, 0, sizeof(*ss2));
 455
 456     if (IS_GEN9(i965->intel.device_info))
 457         ss2->ss5.surface_object_mocs = GEN9_CACHE_PTE;
 458
 459     ss2->ss6.base_addr = surf_bo->offset + surf_bo_offset;
 460     ss2->ss1.cbcr_pixel_offset_v_direction = 0;
 461     ss2->ss1.width = width - 1;
 462     ss2->ss1.height = height - 1;
 463     ss2->ss2.pitch = wpitch - 1;
 464     ss2->ss2.interleave_chroma = interleave_chroma;
 465     ss2->ss2.surface_format = format;
 466     ss2->ss3.x_offset_for_cb = xoffset;
 467     ss2->ss3.y_offset_for_cb = yoffset;
 468     gen8_pp_set_surface2_tiling(ss2, tiling);
 469     dri_bo_emit_reloc(ss2_bo,
 470                       I915_GEM_DOMAIN_RENDER, 0,
 471                       surf_bo_offset,
 472                       SURFACE_STATE_OFFSET(index) + offsetof(struct gen8_surface_state2, ss6),
 473                       surf_bo);
 474     ((unsigned int *)((char *)ss2_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
 475     dri_bo_unmap(ss2_bo);
 476 }
 477
 478 static void
 479 gen8_pp_set_media_rw_message_surface(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 480                                      const struct i965_surface *surface,
 481                                      int base_index, int is_target,
 482                                      const VARectangle *rect,
 483                                      int *width, int *height, int *pitch, int *offset)
 484 {
 485     struct object_surface *obj_surface;
 486     struct object_image *obj_image;
 487     dri_bo *bo;
 488     int fourcc = pp_get_surface_fourcc(ctx, surface);
 489     const i965_fourcc_info *fourcc_info = get_fourcc_info(fourcc);
 490
 491     if (fourcc_info == NULL)
 492         return;
 493
 494     if (surface->type == I965_SURFACE_TYPE_SURFACE) {
 495         obj_surface = (struct object_surface *)surface->base;
 496         bo = obj_surface->bo;
 497         width[0] = MIN(rect->x + rect->width, obj_surface->orig_width);
 498         height[0] = MIN(rect->y + rect->height, obj_surface->orig_height);
 499         pitch[0] = obj_surface->width;
 500         offset[0] = 0;
 501
 502         if (fourcc_info->num_planes == 1 && is_target)
 503             width[0] = width[0] * (fourcc_info->bpp[0] / 8); /* surface format is R8 */
 504
 505         width[1] = MIN(rect->x / fourcc_info->hfactor + rect->width / fourcc_info->hfactor, obj_surface->cb_cr_width);
 506         height[1] = MIN(rect->y / fourcc_info->vfactor + rect->height / fourcc_info->vfactor, obj_surface->cb_cr_height);
 507         pitch[1] = obj_surface->cb_cr_pitch;
 508         offset[1] = obj_surface->y_cb_offset * obj_surface->width;
 509
 510         width[2] = MIN(rect->x / fourcc_info->hfactor + rect->width / fourcc_info->hfactor, obj_surface->cb_cr_width);
 511         height[2] = MIN(rect->y / fourcc_info->vfactor + rect->height / fourcc_info->vfactor, obj_surface->cb_cr_height);
 512         pitch[2] = obj_surface->cb_cr_pitch;
 513         offset[2] = obj_surface->y_cr_offset * obj_surface->width;
 514     } else {
 515         int U = 0, V = 0;
 516
 517         /* FIXME: add support for ARGB/ABGR image */
 518         obj_image = (struct object_image *)surface->base;
 519         bo = obj_image->bo;
 520         width[0] = MIN(rect->x + rect->width, obj_image->image.width);
 521         height[0] = MIN(rect->y + rect->height, obj_image->image.height);
 522         pitch[0] = obj_image->image.pitches[0];
 523         offset[0] = obj_image->image.offsets[0];
 524
 525         if (fourcc_info->num_planes == 1) {
 526             if (is_target)
 527                 width[0] = width[0] * (fourcc_info->bpp[0] / 8); /* surface format is R8 */
 528         } else if (fourcc_info->num_planes == 2) {
 529             U = 1, V = 1;
 530         } else {
 531             assert(fourcc_info->num_components == 3);
 532
 533             U = fourcc_info->components[1].plane;
 534             V = fourcc_info->components[2].plane;
 535             assert((U == 1 && V == 2) ||
 536                    (U == 2 && V == 1));
 537         }
 538
 539         /* Always set width/height although they aren't used for fourcc_info->num_planes == 1 */
 540         width[1] = MIN(rect->x / fourcc_info->hfactor + rect->width / fourcc_info->hfactor, obj_image->image.width / fourcc_info->hfactor);
 541         height[1] = MIN(rect->y / fourcc_info->vfactor + rect->height / fourcc_info->vfactor, obj_image->image.height / fourcc_info->vfactor);
 542         pitch[1] = obj_image->image.pitches[U];
 543         offset[1] = obj_image->image.offsets[U];
 544
 545         width[2] = MIN(rect->x / fourcc_info->hfactor + rect->width / fourcc_info->hfactor, obj_image->image.width / fourcc_info->hfactor);
 546         height[2] = MIN(rect->y / fourcc_info->vfactor + rect->height / fourcc_info->vfactor, obj_image->image.height / fourcc_info->vfactor);
 547         pitch[2] = obj_image->image.pitches[V];
 548         offset[2] = obj_image->image.offsets[V];
 549     }
 550
 551     if (is_target) {
 552         gen8_pp_set_surface_state(ctx, pp_context,
 553                                   bo, 0,
 554                                   ALIGN(width[0], 4) / 4, height[0], pitch[0],
 555                                   I965_SURFACEFORMAT_R8_UINT,
 556                                   base_index, 1);
 557
 558         if (fourcc_info->num_planes == 2) {
 559             gen8_pp_set_surface_state(ctx, pp_context,
 560                                       bo, offset[1],
 561                                       ALIGN(width[1], 2) / 2, height[1], pitch[1],
 562                                       I965_SURFACEFORMAT_R8G8_SINT,
 563                                       base_index + 1, 1);
 564         } else if (fourcc_info->num_planes == 3) {
 565             gen8_pp_set_surface_state(ctx, pp_context,
 566                                       bo, offset[1],
 567                                       ALIGN(width[1], 4) / 4, height[1], pitch[1],
 568                                       I965_SURFACEFORMAT_R8_SINT,
 569                                       base_index + 1, 1);
 570             gen8_pp_set_surface_state(ctx, pp_context,
 571                                       bo, offset[2],
 572                                       ALIGN(width[2], 4) / 4, height[2], pitch[2],
 573                                       I965_SURFACEFORMAT_R8_SINT,
 574                                       base_index + 2, 1);
 575         }
 576
 577         if (fourcc_info->format == I965_COLOR_RGB) {
 578             struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
 579             /* the format is MSB: X-B-G-R */
 580             pp_static_parameter->grf2.save_avs_rgb_swap = 0;
 581             if ((fourcc == VA_FOURCC_BGRA) ||
 582                 (fourcc == VA_FOURCC_BGRX)) {
 583                 /* It is stored as MSB: X-R-G-B */
 584                 pp_static_parameter->grf2.save_avs_rgb_swap = 1;
 585             }
 586         }
 587     } else {
 588         int format0 = SURFACE_FORMAT_Y8_UNORM;
 589
 590         switch (fourcc) {
 591         case VA_FOURCC_YUY2:
 592             format0 = SURFACE_FORMAT_YCRCB_NORMAL;
 593             break;
 594
 595         case VA_FOURCC_UYVY:
 596             format0 = SURFACE_FORMAT_YCRCB_SWAPY;
 597             break;
 598
 599         default:
 600             break;
 601         }
 602
 603         if (fourcc_info->format == I965_COLOR_RGB) {
 604             struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
 605             /* Only R8G8B8A8_UNORM is supported for BGRX or RGBX */
 606             format0 = SURFACE_FORMAT_R8G8B8A8_UNORM;
 607             pp_static_parameter->grf2.src_avs_rgb_swap = 0;
 608             if ((fourcc == VA_FOURCC_BGRA) ||
 609                 (fourcc == VA_FOURCC_BGRX)) {
 610                 pp_static_parameter->grf2.src_avs_rgb_swap = 1;
 611             }
 612         }
 613
 614         gen8_pp_set_surface2_state(ctx, pp_context,
 615                                    bo, offset[0],
 616                                    width[0], height[0], pitch[0],
 617                                    0, 0,
 618                                    format0, 0,
 619                                    base_index);
 620
 621         if (fourcc_info->num_planes == 2) {
 622             gen8_pp_set_surface2_state(ctx, pp_context,
 623                                        bo, offset[1],
 624                                        width[1], height[1], pitch[1],
 625                                        0, 0,
 626                                        SURFACE_FORMAT_R8B8_UNORM, 0,
 627                                        base_index + 1);
 628         } else if (fourcc_info->num_planes == 3) {
 629             gen8_pp_set_surface2_state(ctx, pp_context,
 630                                        bo, offset[1],
 631                                        width[1], height[1], pitch[1],
 632                                        0, 0,
 633                                        SURFACE_FORMAT_R8_UNORM, 0,
 634                                        base_index + 1);
 635             gen8_pp_set_surface2_state(ctx, pp_context,
 636                                        bo, offset[2],
 637                                        width[2], height[2], pitch[2],
 638                                        0, 0,
 639                                        SURFACE_FORMAT_R8_UNORM, 0,
 640                                        base_index + 2);
 641         }
 642
 643         gen8_pp_set_surface_state(ctx, pp_context,
 644                                   bo, 0,
 645                                   ALIGN(width[0], 4) / 4, height[0], pitch[0],
 646                                   I965_SURFACEFORMAT_R8_UINT,
 647                                   base_index + 3, 1);
 648
 649         if (fourcc_info->num_planes == 2) {
 650             gen8_pp_set_surface_state(ctx, pp_context,
 651                                       bo, offset[1],
 652                                       ALIGN(width[1], 2) / 2, height[1], pitch[1],
 653                                       I965_SURFACEFORMAT_R8G8_SINT,
 654                                       base_index + 4, 1);
 655         } else if (fourcc_info->num_planes == 3) {
 656             gen8_pp_set_surface_state(ctx, pp_context,
 657                                       bo, offset[1],
 658                                       ALIGN(width[1], 4) / 4, height[1], pitch[1],
 659                                       I965_SURFACEFORMAT_R8_SINT,
 660                                       base_index + 4, 1);
 661             gen8_pp_set_surface_state(ctx, pp_context,
 662                                       bo, offset[2],
 663                                       ALIGN(width[2], 4) / 4, height[2], pitch[2],
 664                                       I965_SURFACEFORMAT_R8_SINT,
 665                                       base_index + 5, 1);
 666         }
 667     }
 668 }
 669
 670 static int
 671 pp_null_x_steps(void *private_context)
 672 {
 673     return 1;
 674 }
 675
 676 static int
 677 pp_null_y_steps(void *private_context)
 678 {
 679     return 1;
 680 }
 681
 682 static int
 683 pp_null_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
 684 {
 685     return 0;
 686 }
 687
 688 VAStatus
 689 pp_null_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 690                    const struct i965_surface *src_surface,
 691                    const VARectangle *src_rect,
 692                    struct i965_surface *dst_surface,
 693                    const VARectangle *dst_rect,
 694                    void *filter_param)
 695 {
 696     /* private function & data */
 697     pp_context->pp_x_steps = pp_null_x_steps;
 698     pp_context->pp_y_steps = pp_null_y_steps;
 699     pp_context->private_context = NULL;
 700     pp_context->pp_set_block_parameter = pp_null_set_block_parameter;
 701
 702     dst_surface->flags = src_surface->flags;
 703
 704     return VA_STATUS_SUCCESS;
 705 }
 706
 707 static void calculate_boundary_block_mask(struct i965_post_processing_context *pp_context, const VARectangle *dst_rect)
 708 {
 709     int i, dst_width_adjust;
 710     /* x offset of dest surface must be dword aligned.
 711      * so we have to extend dst surface on left edge, and mask out pixels not interested
 712      */
 713     if (dst_rect->x % GPU_ASM_X_OFFSET_ALIGNMENT) {
 714         pp_context->block_horizontal_mask_left = 0;
 715         for (i = dst_rect->x % GPU_ASM_X_OFFSET_ALIGNMENT; i < GPU_ASM_BLOCK_WIDTH; i++) {
 716             pp_context->block_horizontal_mask_left |= 1 << i;
 717         }
 718     } else {
 719         pp_context->block_horizontal_mask_left = 0xffff;
 720     }
 721
 722     dst_width_adjust = dst_rect->width + dst_rect->x % GPU_ASM_X_OFFSET_ALIGNMENT;
 723     if (dst_width_adjust % GPU_ASM_BLOCK_WIDTH) {
 724         pp_context->block_horizontal_mask_right = (1 << (dst_width_adjust % GPU_ASM_BLOCK_WIDTH)) - 1;
 725     } else {
 726         pp_context->block_horizontal_mask_right = 0xffff;
 727     }
 728
 729     if (dst_rect->height % GPU_ASM_BLOCK_HEIGHT) {
 730         pp_context->block_vertical_mask_bottom = (1 << (dst_rect->height % GPU_ASM_BLOCK_HEIGHT)) - 1;
 731     } else {
 732         pp_context->block_vertical_mask_bottom = 0xff;
 733     }
 734
 735 }
 736
 737 static int
 738 gen7_pp_avs_x_steps(void *private_context)
 739 {
 740     struct pp_avs_context *pp_avs_context = private_context;
 741
 742     return pp_avs_context->dest_w / 16;
 743 }
 744
 745 static int
 746 gen7_pp_avs_y_steps(void *private_context)
 747 {
 748     struct pp_avs_context *pp_avs_context = private_context;
 749
 750     return pp_avs_context->dest_h / 16;
 751 }
 752
 753 static int
 754 gen7_pp_avs_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
 755 {
 756     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)pp_context->private_context;
 757     struct gen7_pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
 758
 759     pp_inline_parameter->grf9.destination_block_horizontal_origin = x * 16 + pp_avs_context->dest_x;
 760     pp_inline_parameter->grf9.destination_block_vertical_origin = y * 16 + pp_avs_context->dest_y;
 761     pp_inline_parameter->grf9.constant_0 = 0xffffffff;
 762     pp_inline_parameter->grf9.sampler_load_main_video_x_scaling_step = pp_avs_context->horiz_range / pp_avs_context->src_w;
 763
 764     return 0;
 765 }
 766
 767 static void gen7_update_src_surface_uv_offset(VADriverContextP    ctx,
 768                                               struct i965_post_processing_context *pp_context,
 769                                               const struct i965_surface *surface)
 770 {
 771     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
 772     int fourcc = pp_get_surface_fourcc(ctx, surface);
 773
 774     if (fourcc == VA_FOURCC_YUY2) {
 775         pp_static_parameter->grf2.di_destination_packed_y_component_offset = 0;
 776         pp_static_parameter->grf2.di_destination_packed_u_component_offset = 1;
 777         pp_static_parameter->grf2.di_destination_packed_v_component_offset = 3;
 778     } else if (fourcc == VA_FOURCC_UYVY) {
 779         pp_static_parameter->grf2.di_destination_packed_y_component_offset = 1;
 780         pp_static_parameter->grf2.di_destination_packed_u_component_offset = 0;
 781         pp_static_parameter->grf2.di_destination_packed_v_component_offset = 2;
 782     }
 783 }
 784
 785 static const AVSConfig gen8_avs_config = {
 786     .coeff_frac_bits = 6,
 787     .coeff_epsilon = 1.0f / (1U << 6),
 788     .num_phases = 16,
 789     .num_luma_coeffs = 8,
 790     .num_chroma_coeffs = 4,
 791
 792     .coeff_range = {
 793         .lower_bound = {
 794             .y_k_h = { -2, -2, -2, -2, -2, -2, -2, -2 },
 795             .y_k_v = { -2, -2, -2, -2, -2, -2, -2, -2 },
 796             .uv_k_h = { -1, -2, -2, -1 },
 797             .uv_k_v = { -1, -2, -2, -1 },
 798         },
 799         .upper_bound = {
 800             .y_k_h = { 2, 2, 2, 2, 2, 2, 2, 2 },
 801             .y_k_v = { 2, 2, 2, 2, 2, 2, 2, 2 },
 802             .uv_k_h = { 1, 2, 2, 1 },
 803             .uv_k_v = { 1, 2, 2, 1 },
 804         },
 805     },
 806 };
 807
 808 static int
 809 gen8_pp_get_8tap_filter_mode(VADriverContextP ctx,
 810                              const struct i965_surface *surface)
 811 {
 812     int fourcc = pp_get_surface_fourcc(ctx, surface);
 813
 814     if (fourcc == VA_FOURCC_YUY2 ||
 815         fourcc == VA_FOURCC_UYVY)
 816         return 1;
 817     else
 818         return 3;
 819 }
 820
 821 static int
 822 gen8_pp_kernel_use_media_read_msg(VADriverContextP ctx,
 823                                   const struct i965_surface *src_surface,
 824                                   const VARectangle *src_rect,
 825                                   const struct i965_surface *dst_surface,
 826                                   const VARectangle *dst_rect)
 827 {
 828     int src_fourcc = pp_get_surface_fourcc(ctx, src_surface);
 829     int dst_fourcc = pp_get_surface_fourcc(ctx, dst_surface);
 830     const i965_fourcc_info *src_fourcc_info = get_fourcc_info(src_fourcc);
 831     const i965_fourcc_info *dst_fourcc_info = get_fourcc_info(dst_fourcc);
 832
 833     if (!src_fourcc_info ||
 834         src_fourcc_info->subsampling != SUBSAMPLE_YUV420 ||
 835         !dst_fourcc_info ||
 836         dst_fourcc_info->subsampling != SUBSAMPLE_YUV420)
 837         return 0;
 838
 839     if (src_rect->x == dst_rect->x &&
 840         src_rect->y == dst_rect->y &&
 841         src_rect->width == dst_rect->width &&
 842         src_rect->height == dst_rect->height)
 843         return 1;
 844
 845     return 0;
 846 }
 847
 848 VAStatus
 849 gen8_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 850                            const struct i965_surface *src_surface,
 851                            const VARectangle *src_rect,
 852                            struct i965_surface *dst_surface,
 853                            const VARectangle *dst_rect,
 854                            void *filter_param)
 855 {
 856     /* TODO: Add the sampler_8x8 state */
 857     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->pp_avs_context;
 858     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
 859     struct gen8_sampler_8x8_avs *sampler_8x8;
 860     int i;
 861     int width[3], height[3], pitch[3], offset[3];
 862     int src_width, src_height;
 863     unsigned char *cc_ptr;
 864     AVSState * const avs = &pp_avs_context->state;
 865     float sx, sy;
 866     const float * yuv_to_rgb_coefs;
 867     size_t yuv_to_rgb_coefs_size;
 868
 869     memset(pp_static_parameter, 0, sizeof(struct gen7_pp_static_parameter));
 870
 871     /* source surface */
 872     gen8_pp_set_media_rw_message_surface(ctx, pp_context, src_surface, 0, 0,
 873                                          src_rect,
 874                                          width, height, pitch, offset);
 875     src_height = height[0];
 876     src_width  = width[0];
 877
 878     /* destination surface */
 879     gen8_pp_set_media_rw_message_surface(ctx, pp_context, dst_surface, 24, 1,
 880                                          dst_rect,
 881                                          width, height, pitch, offset);
 882
 883     /* sampler 8x8 state */
 884     dri_bo_map(pp_context->dynamic_state.bo, True);
 885     assert(pp_context->dynamic_state.bo->virtual);
 886
 887     cc_ptr = (unsigned char *) pp_context->dynamic_state.bo->virtual +
 888              pp_context->sampler_offset;
 889     /* Currently only one gen8 sampler_8x8 is initialized */
 890     sampler_8x8 = (struct gen8_sampler_8x8_avs *) cc_ptr;
 891     memset(sampler_8x8, 0, sizeof(*sampler_8x8));
 892
 893     sampler_8x8->dw0.gain_factor = 44;
 894     sampler_8x8->dw0.weak_edge_threshold = 1;
 895     sampler_8x8->dw0.strong_edge_threshold = 8;
 896     /* Use the value like that on Ivy instead of default
 897      * sampler_8x8->dw0.r3x_coefficient = 5;
 898      */
 899     sampler_8x8->dw0.r3x_coefficient = 27;
 900     sampler_8x8->dw0.r3c_coefficient = 5;
 901
 902     sampler_8x8->dw2.global_noise_estimation = 255;
 903     sampler_8x8->dw2.non_edge_weight = 1;
 904     sampler_8x8->dw2.regular_weight = 2;
 905     sampler_8x8->dw2.strong_edge_weight = 7;
 906     /* Use the value like that on Ivy instead of default
 907      * sampler_8x8->dw2.r5x_coefficient = 7;
 908      * sampler_8x8->dw2.r5cx_coefficient = 7;
 909      * sampler_8x8->dw2.r5c_coefficient = 7;
 910      */
 911     sampler_8x8->dw2.r5x_coefficient = 9;
 912     sampler_8x8->dw2.r5cx_coefficient = 8;
 913     sampler_8x8->dw2.r5c_coefficient = 3;
 914
 915     sampler_8x8->dw3.sin_alpha = 101; /* sin_alpha = 0 */
 916     sampler_8x8->dw3.cos_alpha = 79; /* cos_alpha = 0 */
 917     sampler_8x8->dw3.sat_max = 0x1f;
 918     sampler_8x8->dw3.hue_max = 14;
 919     /* The 8tap filter will determine whether the adaptive Filter is
 920      * applied for all channels(dw153).
 921      * If the 8tap filter is disabled, the adaptive filter should be disabled.
 922      * Only when 8tap filter is enabled, it can be enabled or not.
 923      */
 924     sampler_8x8->dw3.enable_8tap_filter = gen8_pp_get_8tap_filter_mode(ctx, src_surface);
 925     sampler_8x8->dw3.ief4_smooth_enable = 0;
 926
 927     sampler_8x8->dw4.s3u = 0;
 928     sampler_8x8->dw4.diamond_margin = 4;
 929     sampler_8x8->dw4.vy_std_enable = 0;
 930     sampler_8x8->dw4.umid = 110;
 931     sampler_8x8->dw4.vmid = 154;
 932
 933     sampler_8x8->dw5.diamond_dv = 0;
 934     sampler_8x8->dw5.diamond_th = 35;
 935     sampler_8x8->dw5.diamond_alpha = 100; /* diamond_alpha = 0 */
 936     sampler_8x8->dw5.hs_margin = 3;
 937     sampler_8x8->dw5.diamond_du = 2;
 938
 939     sampler_8x8->dw6.y_point1 = 46;
 940     sampler_8x8->dw6.y_point2 = 47;
 941     sampler_8x8->dw6.y_point3 = 254;
 942     sampler_8x8->dw6.y_point4 = 255;
 943
 944     sampler_8x8->dw7.inv_margin_vyl = 3300; /* inv_margin_vyl = 0 */
 945
 946     sampler_8x8->dw8.inv_margin_vyu = 1600; /* inv_margin_vyu = 0 */
 947     sampler_8x8->dw8.p0l = 46;
 948     sampler_8x8->dw8.p1l = 216;
 949
 950     sampler_8x8->dw9.p2l = 236;
 951     sampler_8x8->dw9.p3l = 236;
 952     sampler_8x8->dw9.b0l = 133;
 953     sampler_8x8->dw9.b1l = 130;
 954
 955     sampler_8x8->dw10.b2l = 130;
 956     sampler_8x8->dw10.b3l = 130;
 957     /* s0l = -5 / 256. s2.8 */
 958     sampler_8x8->dw10.s0l = 1029;    /* s0l = 0 */
 959     sampler_8x8->dw10.y_slope2 = 31; /* y_slop2 = 0 */
 960
 961     sampler_8x8->dw11.s1l = 0;
 962     sampler_8x8->dw11.s2l = 0;
 963
 964     sampler_8x8->dw12.s3l = 0;
 965     sampler_8x8->dw12.p0u = 46;
 966     sampler_8x8->dw12.p1u = 66;
 967     sampler_8x8->dw12.y_slope1 = 31; /* y_slope1 = 0 */
 968
 969     sampler_8x8->dw13.p2u = 130;
 970     sampler_8x8->dw13.p3u = 236;
 971     sampler_8x8->dw13.b0u = 143;
 972     sampler_8x8->dw13.b1u = 163;
 973
 974     sampler_8x8->dw14.b2u = 200;
 975     sampler_8x8->dw14.b3u = 140;
 976     sampler_8x8->dw14.s0u = 256;  /* s0u = 0 */
 977
 978     sampler_8x8->dw15.s1u = 113; /* s1u = 0 */
 979     sampler_8x8->dw15.s2u = 1203; /* s2u = 0 */
 980
 981     sx = (float)dst_rect->width / src_rect->width;
 982     sy = (float)dst_rect->height / src_rect->height;
 983     avs_update_coefficients(avs, sx, sy, pp_context->filter_flags);
 984
 985     assert(avs->config->num_phases >= 16);
 986     for (i = 0; i <= 16; i++) {
 987         struct gen8_sampler_8x8_avs_coefficients * const sampler_8x8_state =
 988                     &sampler_8x8->coefficients[i];
 989         const AVSCoeffs * const coeffs = &avs->coeffs[i];
 990
 991         sampler_8x8_state->dw0.table_0x_filter_c0 =
 992             intel_format_convert(coeffs->y_k_h[0], 1, 6, 1);
 993         sampler_8x8_state->dw0.table_0y_filter_c0 =
 994             intel_format_convert(coeffs->y_k_v[0], 1, 6, 1);
 995         sampler_8x8_state->dw0.table_0x_filter_c1 =
 996             intel_format_convert(coeffs->y_k_h[1], 1, 6, 1);
 997         sampler_8x8_state->dw0.table_0y_filter_c1 =
 998             intel_format_convert(coeffs->y_k_v[1], 1, 6, 1);
 999
1000         sampler_8x8_state->dw1.table_0x_filter_c2 =
1001             intel_format_convert(coeffs->y_k_h[2], 1, 6, 1);
1002         sampler_8x8_state->dw1.table_0y_filter_c2 =
1003             intel_format_convert(coeffs->y_k_v[2], 1, 6, 1);
1004         sampler_8x8_state->dw1.table_0x_filter_c3 =
1005             intel_format_convert(coeffs->y_k_h[3], 1, 6, 1);
1006         sampler_8x8_state->dw1.table_0y_filter_c3 =
1007             intel_format_convert(coeffs->y_k_v[3], 1, 6, 1);
1008
1009         sampler_8x8_state->dw2.table_0x_filter_c4 =
1010             intel_format_convert(coeffs->y_k_h[4], 1, 6, 1);
1011         sampler_8x8_state->dw2.table_0y_filter_c4 =
1012             intel_format_convert(coeffs->y_k_v[4], 1, 6, 1);
1013         sampler_8x8_state->dw2.table_0x_filter_c5 =
1014             intel_format_convert(coeffs->y_k_h[5], 1, 6, 1);
1015         sampler_8x8_state->dw2.table_0y_filter_c5 =
1016             intel_format_convert(coeffs->y_k_v[5], 1, 6, 1);
1017
1018         sampler_8x8_state->dw3.table_0x_filter_c6 =
1019             intel_format_convert(coeffs->y_k_h[6], 1, 6, 1);
1020         sampler_8x8_state->dw3.table_0y_filter_c6 =
1021             intel_format_convert(coeffs->y_k_v[6], 1, 6, 1);
1022         sampler_8x8_state->dw3.table_0x_filter_c7 =
1023             intel_format_convert(coeffs->y_k_h[7], 1, 6, 1);
1024         sampler_8x8_state->dw3.table_0y_filter_c7 =
1025             intel_format_convert(coeffs->y_k_v[7], 1, 6, 1);
1026
1027         sampler_8x8_state->dw4.pad0 = 0;
1028         sampler_8x8_state->dw5.pad0 = 0;
1029         sampler_8x8_state->dw4.table_1x_filter_c2 =
1030             intel_format_convert(coeffs->uv_k_h[0], 1, 6, 1);
1031         sampler_8x8_state->dw4.table_1x_filter_c3 =
1032             intel_format_convert(coeffs->uv_k_h[1], 1, 6, 1);
1033         sampler_8x8_state->dw5.table_1x_filter_c4 =
1034             intel_format_convert(coeffs->uv_k_h[2], 1, 6, 1);
1035         sampler_8x8_state->dw5.table_1x_filter_c5 =
1036             intel_format_convert(coeffs->uv_k_h[3], 1, 6, 1);
1037
1038         sampler_8x8_state->dw6.pad0 =
1039             sampler_8x8_state->dw7.pad0 =
1040                 sampler_8x8_state->dw6.table_1y_filter_c2 =
1041                     intel_format_convert(coeffs->uv_k_v[0], 1, 6, 1);
1042         sampler_8x8_state->dw6.table_1y_filter_c3 =
1043             intel_format_convert(coeffs->uv_k_v[1], 1, 6, 1);
1044         sampler_8x8_state->dw7.table_1y_filter_c4 =
1045             intel_format_convert(coeffs->uv_k_v[2], 1, 6, 1);
1046         sampler_8x8_state->dw7.table_1y_filter_c5 =
1047             intel_format_convert(coeffs->uv_k_v[3], 1, 6, 1);
1048     }
1049
1050     sampler_8x8->dw152.default_sharpness_level =
1051         -avs_is_needed(pp_context->filter_flags);
1052     sampler_8x8->dw153.adaptive_filter_for_all_channel = 1;
1053     sampler_8x8->dw153.bypass_y_adaptive_filtering = 1;
1054     sampler_8x8->dw153.bypass_x_adaptive_filtering = 1;
1055
1056     for (; i <= avs->config->num_phases; i++) {
1057         struct gen8_sampler_8x8_avs_coefficients * const sampler_8x8_state =
1058                     &sampler_8x8->coefficients1[i - 17];
1059         const AVSCoeffs * const coeffs = &avs->coeffs[i];
1060
1061         sampler_8x8_state->dw0.table_0x_filter_c0 =
1062             intel_format_convert(coeffs->y_k_h[0], 1, 6, 1);
1063         sampler_8x8_state->dw0.table_0y_filter_c0 =
1064             intel_format_convert(coeffs->y_k_v[0], 1, 6, 1);
1065         sampler_8x8_state->dw0.table_0x_filter_c1 =
1066             intel_format_convert(coeffs->y_k_h[1], 1, 6, 1);
1067         sampler_8x8_state->dw0.table_0y_filter_c1 =
1068             intel_format_convert(coeffs->y_k_v[1], 1, 6, 1);
1069
1070         sampler_8x8_state->dw1.table_0x_filter_c2 =
1071             intel_format_convert(coeffs->y_k_h[2], 1, 6, 1);
1072         sampler_8x8_state->dw1.table_0y_filter_c2 =
1073             intel_format_convert(coeffs->y_k_v[2], 1, 6, 1);
1074         sampler_8x8_state->dw1.table_0x_filter_c3 =
1075             intel_format_convert(coeffs->y_k_h[3], 1, 6, 1);
1076         sampler_8x8_state->dw1.table_0y_filter_c3 =
1077             intel_format_convert(coeffs->y_k_v[3], 1, 6, 1);
1078
1079         sampler_8x8_state->dw2.table_0x_filter_c4 =
1080             intel_format_convert(coeffs->y_k_h[4], 1, 6, 1);
1081         sampler_8x8_state->dw2.table_0y_filter_c4 =
1082             intel_format_convert(coeffs->y_k_v[4], 1, 6, 1);
1083         sampler_8x8_state->dw2.table_0x_filter_c5 =
1084             intel_format_convert(coeffs->y_k_h[5], 1, 6, 1);
1085         sampler_8x8_state->dw2.table_0y_filter_c5 =
1086             intel_format_convert(coeffs->y_k_v[5], 1, 6, 1);
1087
1088         sampler_8x8_state->dw3.table_0x_filter_c6 =
1089             intel_format_convert(coeffs->y_k_h[6], 1, 6, 1);
1090         sampler_8x8_state->dw3.table_0y_filter_c6 =
1091             intel_format_convert(coeffs->y_k_v[6], 1, 6, 1);
1092         sampler_8x8_state->dw3.table_0x_filter_c7 =
1093             intel_format_convert(coeffs->y_k_h[7], 1, 6, 1);
1094         sampler_8x8_state->dw3.table_0y_filter_c7 =
1095             intel_format_convert(coeffs->y_k_v[7], 1, 6, 1);
1096
1097         sampler_8x8_state->dw4.pad0 = 0;
1098         sampler_8x8_state->dw5.pad0 = 0;
1099         sampler_8x8_state->dw4.table_1x_filter_c2 =
1100             intel_format_convert(coeffs->uv_k_h[0], 1, 6, 1);
1101         sampler_8x8_state->dw4.table_1x_filter_c3 =
1102             intel_format_convert(coeffs->uv_k_h[1], 1, 6, 1);
1103         sampler_8x8_state->dw5.table_1x_filter_c4 =
1104             intel_format_convert(coeffs->uv_k_h[2], 1, 6, 1);
1105         sampler_8x8_state->dw5.table_1x_filter_c5 =
1106             intel_format_convert(coeffs->uv_k_h[3], 1, 6, 1);
1107
1108         sampler_8x8_state->dw6.pad0 =
1109             sampler_8x8_state->dw7.pad0 =
1110                 sampler_8x8_state->dw6.table_1y_filter_c2 =
1111                     intel_format_convert(coeffs->uv_k_v[0], 1, 6, 1);
1112         sampler_8x8_state->dw6.table_1y_filter_c3 =
1113             intel_format_convert(coeffs->uv_k_v[1], 1, 6, 1);
1114         sampler_8x8_state->dw7.table_1y_filter_c4 =
1115             intel_format_convert(coeffs->uv_k_v[2], 1, 6, 1);
1116         sampler_8x8_state->dw7.table_1y_filter_c5 =
1117             intel_format_convert(coeffs->uv_k_v[3], 1, 6, 1);
1118     }
1119
1120     dri_bo_unmap(pp_context->dynamic_state.bo);
1121
1122
1123     /* private function & data */
1124     pp_context->pp_x_steps = gen7_pp_avs_x_steps;
1125     pp_context->pp_y_steps = gen7_pp_avs_y_steps;
1126     pp_context->private_context = &pp_context->pp_avs_context;
1127     pp_context->pp_set_block_parameter = gen7_pp_avs_set_block_parameter;
1128
1129     int dst_left_edge_extend = dst_rect->x % GPU_ASM_X_OFFSET_ALIGNMENT;
1130     pp_avs_context->dest_x = dst_rect->x - dst_left_edge_extend;
1131     pp_avs_context->dest_y = dst_rect->y;
1132     pp_avs_context->dest_w = ALIGN(dst_rect->width + dst_left_edge_extend, 16);
1133     pp_avs_context->dest_h = ALIGN(dst_rect->height, 16);
1134     pp_avs_context->src_w = src_rect->width;
1135     pp_avs_context->src_h = src_rect->height;
1136     pp_avs_context->horiz_range = (float)src_rect->width / src_width;
1137
1138     int dw = (pp_avs_context->src_w - 1) / 16 + 1;
1139     dw = MAX(dw, dst_rect->width + dst_left_edge_extend);
1140
1141     pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
1142     pp_static_parameter->grf2.avs_wa_enable = gen8_pp_kernel_use_media_read_msg(ctx,
1143                                                                                 src_surface, src_rect,
1144                                                                                 dst_surface, dst_rect); /* reuse this flag for media block reading on gen8+ */
1145     pp_static_parameter->grf2.alpha = 255;
1146
1147     pp_static_parameter->grf3.sampler_load_horizontal_scaling_step_ratio = (float) pp_avs_context->src_w / dw;
1148     pp_static_parameter->grf4.sampler_load_vertical_scaling_step = (float) src_rect->height / src_height / dst_rect->height;
1149     pp_static_parameter->grf5.sampler_load_vertical_frame_origin = (float) src_rect->y / src_height -
1150                                                                    (float) pp_avs_context->dest_y * pp_static_parameter->grf4.sampler_load_vertical_scaling_step;
1151     pp_static_parameter->grf6.sampler_load_horizontal_frame_origin = (float) src_rect->x / src_width -
1152                                                                      (float) pp_avs_context->dest_x * pp_avs_context->horiz_range / dw;
1153
1154     gen7_update_src_surface_uv_offset(ctx, pp_context, dst_surface);
1155
1156     yuv_to_rgb_coefs = i915_color_standard_to_coefs(i915_filter_to_color_standard(src_surface->flags &
1157                                                                                   VA_SRC_COLOR_MASK),
1158                                                     &yuv_to_rgb_coefs_size);
1159     memcpy(&pp_static_parameter->grf7, yuv_to_rgb_coefs, yuv_to_rgb_coefs_size);
1160
1161     dst_surface->flags = src_surface->flags;
1162
1163     return VA_STATUS_SUCCESS;
1164 }
1165
1166 VAStatus
1167 gen8_pp_initialize(
1168     VADriverContextP   ctx,
1169     struct i965_post_processing_context *pp_context,
1170     const struct i965_surface *src_surface,
1171     const VARectangle *src_rect,
1172     struct i965_surface *dst_surface,
1173     const VARectangle *dst_rect,
1174     int                pp_index,
1175     void * filter_param
1176 )
1177 {
1178     VAStatus va_status;
1179     struct i965_driver_data *i965 = i965_driver_data(ctx);
1180     dri_bo *bo;
1181     int bo_size;
1182     unsigned int end_offset;
1183     struct pp_module *pp_module;
1184     int static_param_size, inline_param_size;
1185
1186     dri_bo_unreference(pp_context->surface_state_binding_table.bo);
1187     bo = dri_bo_alloc(i965->intel.bufmgr,
1188                       "surface state & binding table",
1189                       (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_PP_SURFACES,
1190                       4096);
1191     assert(bo);
1192     pp_context->surface_state_binding_table.bo = bo;
1193
1194     pp_context->idrt.num_interface_descriptors = 0;
1195
1196     pp_context->sampler_size = 4 * 4096;
1197
1198     bo_size = 4096 + pp_context->curbe_size + pp_context->sampler_size
1199               + pp_context->idrt_size;
1200
1201     dri_bo_unreference(pp_context->dynamic_state.bo);
1202     bo = dri_bo_alloc(i965->intel.bufmgr,
1203                       "dynamic_state",
1204                       bo_size,
1205                       4096);
1206
1207     assert(bo);
1208     pp_context->dynamic_state.bo = bo;
1209     pp_context->dynamic_state.bo_size = bo_size;
1210
1211     end_offset = 0;
1212     pp_context->dynamic_state.end_offset = 0;
1213
1214     /* Constant buffer offset */
1215     pp_context->curbe_offset = ALIGN(end_offset, 64);
1216     end_offset = pp_context->curbe_offset + pp_context->curbe_size;
1217
1218     /* Interface descriptor offset */
1219     pp_context->idrt_offset = ALIGN(end_offset, 64);
1220     end_offset = pp_context->idrt_offset + pp_context->idrt_size;
1221
1222     /* Sampler state offset */
1223     pp_context->sampler_offset = ALIGN(end_offset, 64);
1224     end_offset = pp_context->sampler_offset + pp_context->sampler_size;
1225
1226     /* update the end offset of dynamic_state */
1227     pp_context->dynamic_state.end_offset = ALIGN(end_offset, 64);
1228
1229     static_param_size = sizeof(struct gen7_pp_static_parameter);
1230     inline_param_size = sizeof(struct gen7_pp_inline_parameter);
1231
1232     memset(pp_context->pp_static_parameter, 0, static_param_size);
1233     memset(pp_context->pp_inline_parameter, 0, inline_param_size);
1234
1235     assert(pp_index >= PP_NULL && pp_index < NUM_PP_MODULES);
1236     pp_context->current_pp = pp_index;
1237     pp_module = &pp_context->pp_modules[pp_index];
1238
1239     if (pp_module->initialize)
1240         va_status = pp_module->initialize(ctx, pp_context,
1241                                           src_surface,
1242                                           src_rect,
1243                                           dst_surface,
1244                                           dst_rect,
1245                                           filter_param);
1246     else
1247         va_status = VA_STATUS_ERROR_UNIMPLEMENTED;
1248
1249     calculate_boundary_block_mask(pp_context, dst_rect);
1250
1251     return va_status;
1252 }
1253
1254 static void
1255 gen8_pp_interface_descriptor_table(VADriverContextP   ctx,
1256                                    struct i965_post_processing_context *pp_context)
1257 {
1258     struct gen8_interface_descriptor_data *desc;
1259     dri_bo *bo;
1260     int pp_index = pp_context->current_pp;
1261     unsigned char *cc_ptr;
1262
1263     bo = pp_context->dynamic_state.bo;
1264
1265     dri_bo_map(bo, 1);
1266     assert(bo->virtual);
1267     cc_ptr = (unsigned char *)bo->virtual + pp_context->idrt_offset;
1268
1269     desc = (struct gen8_interface_descriptor_data *) cc_ptr +
1270            pp_context->idrt.num_interface_descriptors;
1271
1272     memset(desc, 0, sizeof(*desc));
1273     desc->desc0.kernel_start_pointer =
1274         pp_context->pp_modules[pp_index].kernel.kernel_offset >> 6; /* reloc */
1275     desc->desc2.single_program_flow = 1;
1276     desc->desc2.floating_point_mode = FLOATING_POINT_IEEE_754;
1277     desc->desc3.sampler_count = 0;      /* 1 - 4 samplers used */
1278     desc->desc3.sampler_state_pointer = pp_context->sampler_offset >> 5;
1279     desc->desc4.binding_table_entry_count = 0;
1280     desc->desc4.binding_table_pointer = (BINDING_TABLE_OFFSET >> 5);
1281     desc->desc5.constant_urb_entry_read_offset = 0;
1282
1283     desc->desc5.constant_urb_entry_read_length = 8; /* grf 1-8 */
1284
1285     dri_bo_unmap(bo);
1286     pp_context->idrt.num_interface_descriptors++;
1287 }
1288
1289
1290 static void
1291 gen8_pp_upload_constants(VADriverContextP ctx,
1292                          struct i965_post_processing_context *pp_context)
1293 {
1294     unsigned char *constant_buffer;
1295     int param_size;
1296
1297     assert(sizeof(struct gen7_pp_static_parameter) == 256);
1298
1299     param_size = sizeof(struct gen7_pp_static_parameter);
1300
1301     dri_bo_map(pp_context->dynamic_state.bo, 1);
1302     assert(pp_context->dynamic_state.bo->virtual);
1303     constant_buffer = (unsigned char *) pp_context->dynamic_state.bo->virtual +
1304                       pp_context->curbe_offset;
1305
1306     memcpy(constant_buffer, pp_context->pp_static_parameter, param_size);
1307     dri_bo_unmap(pp_context->dynamic_state.bo);
1308     return;
1309 }
1310
1311 void
1312 gen8_pp_states_setup(VADriverContextP ctx,
1313                      struct i965_post_processing_context *pp_context)
1314 {
1315     gen8_pp_interface_descriptor_table(ctx, pp_context);
1316     gen8_pp_upload_constants(ctx, pp_context);
1317 }
1318
1319 static void
1320 gen6_pp_pipeline_select(VADriverContextP ctx,
1321                         struct i965_post_processing_context *pp_context)
1322 {
1323     struct intel_batchbuffer *batch = pp_context->batch;
1324
1325     BEGIN_BATCH(batch, 1);
1326     OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
1327     ADVANCE_BATCH(batch);
1328 }
1329
1330 static void
1331 gen8_pp_state_base_address(VADriverContextP ctx,
1332                            struct i965_post_processing_context *pp_context)
1333 {
1334     struct intel_batchbuffer *batch = pp_context->batch;
1335
1336     BEGIN_BATCH(batch, 16);
1337     OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | (16 - 2));
1338     /* DW1 Generate state address */
1339     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1340     OUT_BATCH(batch, 0);
1341     OUT_BATCH(batch, 0);
1342
1343     /* DW4-5. Surface state address */
1344     OUT_RELOC64(batch, pp_context->surface_state_binding_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
1345
1346     /* DW6-7. Dynamic state address */
1347     OUT_RELOC64(batch, pp_context->dynamic_state.bo, I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_SAMPLER,
1348                 0, 0 | BASE_ADDRESS_MODIFY);
1349
1350     /* DW8. Indirect object address */
1351     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1352     OUT_BATCH(batch, 0);
1353
1354     /* DW10-11. Instruction base address */
1355     OUT_RELOC64(batch, pp_context->instruction_state.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
1356
1357     OUT_BATCH(batch, 0xFFFF0000 | BASE_ADDRESS_MODIFY);
1358     OUT_BATCH(batch, 0xFFFF0000 | BASE_ADDRESS_MODIFY);
1359     OUT_BATCH(batch, 0xFFFF0000 | BASE_ADDRESS_MODIFY);
1360     OUT_BATCH(batch, 0xFFFF0000 | BASE_ADDRESS_MODIFY);
1361     ADVANCE_BATCH(batch);
1362 }
1363
1364 void
1365 gen8_pp_vfe_state(VADriverContextP ctx,
1366                   struct i965_post_processing_context *pp_context)
1367 {
1368     struct intel_batchbuffer *batch = pp_context->batch;
1369
1370     BEGIN_BATCH(batch, 9);
1371     OUT_BATCH(batch, CMD_MEDIA_VFE_STATE | (9 - 2));
1372     OUT_BATCH(batch, 0);
1373     OUT_BATCH(batch, 0);
1374     OUT_BATCH(batch,
1375               (pp_context->vfe_gpu_state.max_num_threads - 1) << 16 |
1376               pp_context->vfe_gpu_state.num_urb_entries << 8);
1377     OUT_BATCH(batch, 0);
1378     OUT_BATCH(batch,
1379               (pp_context->vfe_gpu_state.urb_entry_size) << 16 |
1380               /* URB Entry Allocation Size, in 256 bits unit */
1381               (pp_context->vfe_gpu_state.curbe_allocation_size));
1382     /* CURBE Allocation Size, in 256 bits unit */
1383     OUT_BATCH(batch, 0);
1384     OUT_BATCH(batch, 0);
1385     OUT_BATCH(batch, 0);
1386     ADVANCE_BATCH(batch);
1387 }
1388
1389 void
1390 gen8_interface_descriptor_load(VADriverContextP ctx,
1391                                struct i965_post_processing_context *pp_context)
1392 {
1393     struct intel_batchbuffer *batch = pp_context->batch;
1394
1395     BEGIN_BATCH(batch, 6);
1396
1397     OUT_BATCH(batch, CMD_MEDIA_STATE_FLUSH);
1398     OUT_BATCH(batch, 0);
1399
1400     OUT_BATCH(batch, CMD_MEDIA_INTERFACE_DESCRIPTOR_LOAD | (4 - 2));
1401     OUT_BATCH(batch, 0);
1402     OUT_BATCH(batch,
1403               pp_context->idrt.num_interface_descriptors * sizeof(struct gen8_interface_descriptor_data));
1404     OUT_BATCH(batch, pp_context->idrt_offset);
1405     ADVANCE_BATCH(batch);
1406 }
1407
1408 void
1409 gen8_pp_curbe_load(VADriverContextP ctx,
1410                    struct i965_post_processing_context *pp_context)
1411 {
1412     struct intel_batchbuffer *batch = pp_context->batch;
1413     int param_size = 64;
1414
1415     param_size = sizeof(struct gen7_pp_static_parameter);
1416
1417     BEGIN_BATCH(batch, 4);
1418     OUT_BATCH(batch, CMD_MEDIA_CURBE_LOAD | (4 - 2));
1419     OUT_BATCH(batch, 0);
1420     OUT_BATCH(batch,
1421               param_size);
1422     OUT_BATCH(batch, pp_context->curbe_offset);
1423     ADVANCE_BATCH(batch);
1424 }
1425
1426 void
1427 gen8_pp_object_walker(VADriverContextP ctx,
1428                       struct i965_post_processing_context *pp_context)
1429 {
1430     struct i965_driver_data *i965 = i965_driver_data(ctx);
1431     struct intel_batchbuffer *batch = pp_context->batch;
1432     int x, x_steps, y, y_steps;
1433     int param_size, command_length_in_dws, extra_cmd_in_dws;
1434     dri_bo *command_buffer;
1435     unsigned int *command_ptr;
1436
1437     param_size = sizeof(struct gen7_pp_inline_parameter);
1438
1439     x_steps = pp_context->pp_x_steps(pp_context->private_context);
1440     y_steps = pp_context->pp_y_steps(pp_context->private_context);
1441     command_length_in_dws = 6 + (param_size >> 2);
1442     extra_cmd_in_dws = 2;
1443     command_buffer = dri_bo_alloc(i965->intel.bufmgr,
1444                                   "command objects buffer",
1445                                   (command_length_in_dws + extra_cmd_in_dws) * 4 * x_steps * y_steps + 64,
1446                                   4096);
1447
1448     dri_bo_map(command_buffer, 1);
1449     command_ptr = command_buffer->virtual;
1450
1451     for (y = 0; y < y_steps; y++) {
1452         for (x = 0; x < x_steps; x++) {
1453             if (!pp_context->pp_set_block_parameter(pp_context, x, y)) {
1454
1455                 *command_ptr++ = (CMD_MEDIA_OBJECT | (command_length_in_dws - 2));
1456                 *command_ptr++ = 0;
1457                 *command_ptr++ = 0;
1458                 *command_ptr++ = 0;
1459                 *command_ptr++ = 0;
1460                 *command_ptr++ = 0;
1461                 memcpy(command_ptr, pp_context->pp_inline_parameter, param_size);
1462                 command_ptr += (param_size >> 2);
1463
1464                 *command_ptr++ = CMD_MEDIA_STATE_FLUSH;
1465                 *command_ptr++ = 0;
1466             }
1467         }
1468     }
1469
1470     if ((command_length_in_dws + extra_cmd_in_dws) * x_steps * y_steps % 2 == 0)
1471         *command_ptr++ = 0;
1472
1473     *command_ptr++ = MI_BATCH_BUFFER_END;
1474     *command_ptr++ = 0;
1475
1476     dri_bo_unmap(command_buffer);
1477
1478     BEGIN_BATCH(batch, 3);
1479     OUT_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8) | (1 << 0));
1480     OUT_RELOC64(batch, command_buffer,
1481                 I915_GEM_DOMAIN_COMMAND, 0, 0);
1482     ADVANCE_BATCH(batch);
1483
1484     dri_bo_unreference(command_buffer);
1485
1486     /* Have to execute the batch buffer here becuase MI_BATCH_BUFFER_END
1487      * will cause control to pass back to ring buffer
1488      */
1489     intel_batchbuffer_end_atomic(batch);
1490     intel_batchbuffer_flush(batch);
1491     intel_batchbuffer_start_atomic(batch, 0x1000);
1492 }
1493
1494 static void
1495 gen8_pp_pipeline_setup(VADriverContextP ctx,
1496                        struct i965_post_processing_context *pp_context)
1497 {
1498     struct intel_batchbuffer *batch = pp_context->batch;
1499
1500     intel_batchbuffer_start_atomic(batch, 0x1000);
1501     intel_batchbuffer_emit_mi_flush(batch);
1502     gen6_pp_pipeline_select(ctx, pp_context);
1503     gen8_pp_state_base_address(ctx, pp_context);
1504     gen8_pp_vfe_state(ctx, pp_context);
1505     gen8_pp_curbe_load(ctx, pp_context);
1506     gen8_interface_descriptor_load(ctx, pp_context);
1507     gen8_pp_vfe_state(ctx, pp_context);
1508     gen8_pp_object_walker(ctx, pp_context);
1509     intel_batchbuffer_end_atomic(batch);
1510 }
1511
1512 static VAStatus
1513 gen8_post_processing(
1514     VADriverContextP   ctx,
1515     struct i965_post_processing_context *pp_context,
1516     const struct i965_surface *src_surface,
1517     const VARectangle *src_rect,
1518     struct i965_surface *dst_surface,
1519     const VARectangle *dst_rect,
1520     int                pp_index,
1521     void * filter_param
1522 )
1523 {
1524     VAStatus va_status;
1525
1526     va_status = gen8_pp_initialize(ctx, pp_context,
1527                                    src_surface,
1528                                    src_rect,
1529                                    dst_surface,
1530                                    dst_rect,
1531                                    pp_index,
1532                                    filter_param);
1533
1534     if (va_status == VA_STATUS_SUCCESS) {
1535         gen8_pp_states_setup(ctx, pp_context);
1536         gen8_pp_pipeline_setup(ctx, pp_context);
1537     }
1538
1539     return va_status;
1540 }
1541
1542 static void
1543 gen8_post_processing_context_finalize(VADriverContextP ctx,
1544                                       struct i965_post_processing_context *pp_context)
1545 {
1546     if (pp_context->scaling_context_initialized) {
1547         gen8_gpe_context_destroy(&pp_context->scaling_10bit_context);
1548         pp_context->scaling_context_initialized = 0;
1549     }
1550
1551     if (pp_context->scaling_8bit_initialized & VPPGPE_8BIT_420) {
1552         gen8_gpe_context_destroy(&pp_context->scaling_yuv420p8_context);
1553         pp_context->scaling_8bit_initialized &= ~(VPPGPE_8BIT_420);
1554     }
1555
1556     if (pp_context->vebox_proc_ctx) {
1557         gen75_vebox_context_destroy(ctx, pp_context->vebox_proc_ctx);
1558         pp_context->vebox_proc_ctx = NULL;
1559     }
1560
1561     dri_bo_unreference(pp_context->surface_state_binding_table.bo);
1562     pp_context->surface_state_binding_table.bo = NULL;
1563
1564     dri_bo_unreference(pp_context->pp_dn_context.stmm_bo);
1565     pp_context->pp_dn_context.stmm_bo = NULL;
1566
1567     if (pp_context->instruction_state.bo) {
1568         dri_bo_unreference(pp_context->instruction_state.bo);
1569         pp_context->instruction_state.bo = NULL;
1570     }
1571
1572     if (pp_context->indirect_state.bo) {
1573         dri_bo_unreference(pp_context->indirect_state.bo);
1574         pp_context->indirect_state.bo = NULL;
1575     }
1576
1577     if (pp_context->dynamic_state.bo) {
1578         dri_bo_unreference(pp_context->dynamic_state.bo);
1579         pp_context->dynamic_state.bo = NULL;
1580     }
1581
1582     free(pp_context->pp_static_parameter);
1583     free(pp_context->pp_inline_parameter);
1584     pp_context->pp_static_parameter = NULL;
1585     pp_context->pp_inline_parameter = NULL;
1586 }
1587
1588 #define VPP_CURBE_ALLOCATION_SIZE   32
1589
1590 void
1591 gen8_post_processing_context_common_init(VADriverContextP ctx,
1592                                          void *data,
1593                                          struct pp_module *pp_modules,
1594                                          int num_pp_modules,
1595                                          struct intel_batchbuffer *batch)
1596 {
1597     struct i965_driver_data *i965 = i965_driver_data(ctx);
1598     int i, kernel_size;
1599     unsigned int kernel_offset, end_offset;
1600     unsigned char *kernel_ptr;
1601     struct pp_module *pp_module;
1602     struct i965_post_processing_context *pp_context = data;
1603
1604     if (i965->intel.eu_total > 0)
1605         pp_context->vfe_gpu_state.max_num_threads = 6 * i965->intel.eu_total;
1606     else
1607         pp_context->vfe_gpu_state.max_num_threads = 60;
1608     pp_context->vfe_gpu_state.num_urb_entries = 59;
1609     pp_context->vfe_gpu_state.gpgpu_mode = 0;
1610     pp_context->vfe_gpu_state.urb_entry_size = 16 - 1;
1611     pp_context->vfe_gpu_state.curbe_allocation_size = VPP_CURBE_ALLOCATION_SIZE;
1612
1613     pp_context->intel_post_processing = gen8_post_processing;
1614     pp_context->finalize = gen8_post_processing_context_finalize;
1615
1616     assert(ARRAY_ELEMS(pp_context->pp_modules) == num_pp_modules);
1617
1618     memcpy(pp_context->pp_modules, pp_modules, sizeof(pp_context->pp_modules));
1619
1620     kernel_size = 4096 ;
1621
1622     for (i = 0; i < NUM_PP_MODULES; i++) {
1623         pp_module = &pp_context->pp_modules[i];
1624
1625         if (pp_module->kernel.bin && pp_module->kernel.size) {
1626             kernel_size += pp_module->kernel.size;
1627         }
1628     }
1629
1630     pp_context->instruction_state.bo = dri_bo_alloc(i965->intel.bufmgr,
1631                                                     "kernel shader",
1632                                                     kernel_size,
1633                                                     0x1000);
1634     if (pp_context->instruction_state.bo == NULL) {
1635         WARN_ONCE("failure to allocate the buffer space for kernel shader in VPP\n");
1636         return;
1637     }
1638
1639     assert(pp_context->instruction_state.bo);
1640
1641
1642     pp_context->instruction_state.bo_size = kernel_size;
1643     pp_context->instruction_state.end_offset = 0;
1644     end_offset = 0;
1645
1646     dri_bo_map(pp_context->instruction_state.bo, 1);
1647     kernel_ptr = (unsigned char *)(pp_context->instruction_state.bo->virtual);
1648
1649     for (i = 0; i < NUM_PP_MODULES; i++) {
1650         pp_module = &pp_context->pp_modules[i];
1651
1652         kernel_offset = ALIGN(end_offset, 64);
1653         pp_module->kernel.kernel_offset = kernel_offset;
1654
1655         if (pp_module->kernel.bin && pp_module->kernel.size) {
1656
1657             memcpy(kernel_ptr + kernel_offset, pp_module->kernel.bin, pp_module->kernel.size);
1658             end_offset = kernel_offset + pp_module->kernel.size;
1659         }
1660     }
1661
1662     pp_context->instruction_state.end_offset = ALIGN(end_offset, 64);
1663
1664     dri_bo_unmap(pp_context->instruction_state.bo);
1665
1666     /* static & inline parameters */
1667     pp_context->pp_static_parameter = calloc(sizeof(struct gen7_pp_static_parameter), 1);
1668     pp_context->pp_inline_parameter = calloc(sizeof(struct gen7_pp_inline_parameter), 1);
1669
1670     pp_context->batch = batch;
1671
1672     pp_context->idrt_size = 5 * sizeof(struct gen8_interface_descriptor_data);
1673     pp_context->curbe_size = 256;
1674
1675 }
1676
1677 void
1678 gen8_post_processing_context_init(VADriverContextP ctx,
1679                                   void *data,
1680                                   struct intel_batchbuffer *batch)
1681 {
1682     struct i965_driver_data *i965 = i965_driver_data(ctx);
1683     struct i965_post_processing_context *pp_context = data;
1684     struct i965_gpe_context *gpe_context;
1685     struct i965_kernel scaling_kernel;
1686
1687     gen8_post_processing_context_common_init(ctx, data, pp_modules_gen8, ARRAY_ELEMS(pp_modules_gen8), batch);
1688     avs_init_state(&pp_context->pp_avs_context.state, &gen8_avs_config);
1689
1690     /* initialize the YUV420 8-Bit scaling context. The below is supported.
1691      * NV12 ->NV12
1692      * NV12 ->I420
1693      * I420 ->I420
1694      * I420 ->NV12
1695      */
1696     gpe_context = &pp_context->scaling_yuv420p8_context;
1697     memset(&scaling_kernel, 0, sizeof(scaling_kernel));
1698     scaling_kernel.bin = pp_yuv420p8_scaling_gen8;
1699     scaling_kernel.size = sizeof(pp_yuv420p8_scaling_gen8);
1700     gen8_gpe_load_kernels(ctx, gpe_context, &scaling_kernel, 1);
1701     gpe_context->idrt.entry_size = ALIGN(sizeof(struct gen8_interface_descriptor_data), 64);
1702     gpe_context->idrt.max_entries = 1;
1703     gpe_context->sampler.entry_size = ALIGN(sizeof(struct gen8_sampler_state), 64);
1704     gpe_context->sampler.max_entries = 1;
1705     gpe_context->curbe.length = ALIGN(sizeof(struct scaling_input_parameter), 32);
1706
1707     gpe_context->surface_state_binding_table.max_entries = MAX_SCALING_SURFACES;
1708     gpe_context->surface_state_binding_table.binding_table_offset = 0;
1709     gpe_context->surface_state_binding_table.surface_state_offset = ALIGN(MAX_SCALING_SURFACES * 4, 64);
1710     gpe_context->surface_state_binding_table.length = ALIGN(MAX_SCALING_SURFACES * 4, 64) + ALIGN(MAX_SCALING_SURFACES * SURFACE_STATE_PADDED_SIZE_GEN8, 64);
1711
1712     if (i965->intel.eu_total > 0) {
1713         gpe_context->vfe_state.max_num_threads = i965->intel.eu_total * 6;
1714     } else {
1715         if (i965->intel.has_bsd2)
1716             gpe_context->vfe_state.max_num_threads = 300;
1717         else
1718             gpe_context->vfe_state.max_num_threads = 60;
1719     }
1720
1721     gpe_context->vfe_state.curbe_allocation_size = 37;
1722     gpe_context->vfe_state.urb_entry_size = 16;
1723     if (i965->intel.has_bsd2)
1724         gpe_context->vfe_state.num_urb_entries = 127;
1725     else
1726         gpe_context->vfe_state.num_urb_entries = 64;
1727
1728     gpe_context->vfe_state.gpgpu_mode = 0;
1729
1730     gen8_gpe_context_init(ctx, gpe_context);
1731     pp_context->scaling_8bit_initialized = VPPGPE_8BIT_420;
1732     return;
1733 }
1734
1735 static void
1736 gen8_run_kernel_media_object_walker(VADriverContextP ctx,
1737                                     struct intel_batchbuffer *batch,
1738                                     struct i965_gpe_context *gpe_context,
1739                                     struct gpe_media_object_walker_parameter *param)
1740 {
1741     if (!batch || !gpe_context || !param)
1742         return;
1743
1744     intel_batchbuffer_start_atomic(batch, 0x1000);
1745
1746     intel_batchbuffer_emit_mi_flush(batch);
1747
1748     gen8_gpe_pipeline_setup(ctx, gpe_context, batch);
1749     gen8_gpe_media_object_walker(ctx, gpe_context, batch, param);
1750     gen8_gpe_media_state_flush(ctx, gpe_context, batch);
1751
1752
1753     intel_batchbuffer_end_atomic(batch);
1754
1755     intel_batchbuffer_flush(batch);
1756     return;
1757 }
1758
1759 static void
1760 gen8_add_dri_buffer_2d_gpe_surface(VADriverContextP ctx,
1761                                    struct i965_gpe_context *gpe_context,
1762                                    dri_bo *bo,
1763                                    unsigned int bo_offset,
1764                                    unsigned int width,
1765                                    unsigned int height,
1766                                    unsigned int pitch,
1767                                    int is_media_block_rw,
1768                                    unsigned int format,
1769                                    int index,
1770                                    int is_10bit)
1771 {
1772     struct i965_gpe_resource gpe_resource;
1773     struct i965_gpe_surface gpe_surface;
1774
1775     i965_dri_object_to_2d_gpe_resource(&gpe_resource, bo, width, height, pitch);
1776     memset(&gpe_surface, 0, sizeof(gpe_surface));
1777     gpe_surface.gpe_resource = &gpe_resource;
1778     gpe_surface.is_2d_surface = 1;
1779     gpe_surface.is_media_block_rw = !!is_media_block_rw;
1780     gpe_surface.cacheability_control = DEFAULT_MOCS;
1781     gpe_surface.format = format;
1782     gpe_surface.is_override_offset = 1;
1783     gpe_surface.offset = bo_offset;
1784     gpe_surface.is_16bpp = is_10bit;
1785
1786     gen9_gpe_context_add_surface(gpe_context, &gpe_surface, index);
1787
1788     i965_free_gpe_resource(&gpe_resource);
1789 }
1790
1791 static void
1792 gen8_vpp_scaling_sample_state(VADriverContextP ctx,
1793                               struct i965_gpe_context *gpe_context,
1794                               VARectangle *src_rect,
1795                               VARectangle *dst_rect)
1796 {
1797     struct gen8_sampler_state *sampler_state;
1798
1799     if (gpe_context == NULL || !src_rect || !dst_rect)
1800         return;
1801     dri_bo_map(gpe_context->sampler.bo, 1);
1802
1803     if (gpe_context->sampler.bo->virtual == NULL)
1804         return;
1805
1806     assert(gpe_context->sampler.bo->virtual);
1807
1808     sampler_state = (struct gen8_sampler_state *)
1809                     (gpe_context->sampler.bo->virtual + gpe_context->sampler.offset);
1810
1811     memset(sampler_state, 0, sizeof(*sampler_state));
1812
1813     if ((src_rect->width == dst_rect->width) &&
1814         (src_rect->height == dst_rect->height)) {
1815         sampler_state->ss0.min_filter = I965_MAPFILTER_NEAREST;
1816         sampler_state->ss0.mag_filter = I965_MAPFILTER_NEAREST;
1817     } else {
1818         sampler_state->ss0.min_filter = I965_MAPFILTER_LINEAR;
1819         sampler_state->ss0.mag_filter = I965_MAPFILTER_LINEAR;
1820     }
1821
1822     sampler_state->ss3.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1823     sampler_state->ss3.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1824     sampler_state->ss3.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1825
1826     dri_bo_unmap(gpe_context->sampler.bo);
1827 }
1828
1829 static void
1830 gen8_gpe_context_yuv420p8_scaling_curbe(VADriverContextP ctx,
1831                                         struct i965_gpe_context *gpe_context,
1832                                         VARectangle *src_rect,
1833                                         struct i965_surface *src_surface,
1834                                         VARectangle *dst_rect,
1835                                         struct i965_surface *dst_surface)
1836 {
1837     struct scaling_input_parameter *scaling_curbe;
1838     float src_width, src_height;
1839     float coeff;
1840     unsigned int fourcc;
1841
1842     if ((gpe_context == NULL) ||
1843         (src_rect == NULL) || (src_surface == NULL) ||
1844         (dst_rect == NULL) || (dst_surface == NULL))
1845         return;
1846
1847     scaling_curbe = i965_gpe_context_map_curbe(gpe_context);
1848
1849     if (!scaling_curbe)
1850         return;
1851
1852     memset(scaling_curbe, 0, sizeof(struct scaling_input_parameter));
1853
1854     scaling_curbe->bti_input = BTI_SCALING_INPUT_Y;
1855     scaling_curbe->bti_output = BTI_SCALING_OUTPUT_Y;
1856
1857     /* As the src_rect/dst_rect is already checked, it is skipped.*/
1858     scaling_curbe->x_dst     = dst_rect->x;
1859     scaling_curbe->y_dst     = dst_rect->y;
1860
1861     src_width = src_rect->x + src_rect->width;
1862     src_height = src_rect->y + src_rect->height;
1863
1864     scaling_curbe->inv_width = 1 / src_width;
1865     scaling_curbe->inv_height = 1 / src_height;
1866
1867     coeff = (float)(src_rect->width) / dst_rect->width;
1868     scaling_curbe->x_factor = coeff / src_width;
1869     scaling_curbe->x_orig = (float)(src_rect->x) / src_width;
1870
1871     coeff = (float)(src_rect->height) / dst_rect->height;
1872     scaling_curbe->y_factor = coeff / src_height;
1873     scaling_curbe->y_orig = (float)(src_rect->y) / src_height;
1874
1875     fourcc = pp_get_surface_fourcc(ctx, src_surface);
1876     if (fourcc == VA_FOURCC_NV12) {
1877         scaling_curbe->dw7.src_packed = 1;
1878     }
1879
1880     fourcc = pp_get_surface_fourcc(ctx, dst_surface);
1881
1882     if (fourcc == VA_FOURCC_NV12) {
1883         scaling_curbe->dw7.dst_packed = 1;
1884     }
1885
1886     i965_gpe_context_unmap_curbe(gpe_context);
1887 }
1888
1889 static bool
1890 gen8_pp_context_get_surface_conf(VADriverContextP ctx,
1891                                  struct i965_surface *surface,
1892                                  VARectangle *rect,
1893                                  int *width,
1894                                  int *height,
1895                                  int *pitch,
1896                                  int *bo_offset)
1897 {
1898     unsigned int fourcc;
1899     if (!rect || !surface || !width || !height || !pitch || !bo_offset)
1900         return false;
1901
1902     if (surface->base == NULL)
1903         return false;
1904
1905     fourcc = pp_get_surface_fourcc(ctx, surface);
1906     if (surface->type == I965_SURFACE_TYPE_SURFACE) {
1907         struct object_surface *obj_surface;
1908
1909         obj_surface = (struct object_surface *)surface->base;
1910         width[0] = MIN(rect->x + rect->width, obj_surface->orig_width);
1911         height[0] = MIN(rect->y + rect->height, obj_surface->orig_height);
1912         pitch[0] = obj_surface->width;
1913         bo_offset[0] = 0;
1914
1915         if (fourcc == VA_FOURCC_P010 || fourcc == VA_FOURCC_NV12) {
1916             width[1] = width[0] / 2;
1917             height[1] = height[0] / 2;
1918             pitch[1] = obj_surface->cb_cr_pitch;
1919             bo_offset[1] = obj_surface->width * obj_surface->y_cb_offset;
1920         } else {
1921             /* I010/I420 format */
1922             width[1] = width[0] / 2;
1923             height[1] = height[0] / 2;
1924             pitch[1] = obj_surface->cb_cr_pitch;
1925             bo_offset[1] = obj_surface->width * obj_surface->y_cb_offset;
1926             width[2] = width[0] / 2;
1927             height[2] = height[0] / 2;
1928             pitch[2] = obj_surface->cb_cr_pitch;
1929             bo_offset[2] = obj_surface->width * obj_surface->y_cr_offset;
1930         }
1931
1932     } else {
1933         struct object_image *obj_image;
1934
1935         obj_image = (struct object_image *)surface->base;
1936
1937         width[0] = MIN(rect->x + rect->width, obj_image->image.width);
1938         height[0] = MIN(rect->y + rect->height, obj_image->image.height);
1939         pitch[0] = obj_image->image.pitches[0];
1940         bo_offset[0] = obj_image->image.offsets[0];
1941
1942         if (fourcc == VA_FOURCC_P010 || fourcc == VA_FOURCC_NV12) {
1943             width[1] = width[0] / 2;
1944             height[1] = height[0] / 2;
1945             pitch[1] = obj_image->image.pitches[1];
1946             bo_offset[1] = obj_image->image.offsets[1];
1947         } else {
1948             /* I010/I420 format */
1949             /* YV12 is TBD */
1950             width[1] = width[0] / 2;
1951             height[1] = height[0] / 2;
1952             pitch[1] = obj_image->image.pitches[1];
1953             bo_offset[1] = obj_image->image.offsets[1];
1954             width[2] = width[0] / 2;
1955             height[2] = height[0] / 2;
1956             pitch[2] = obj_image->image.pitches[2];
1957             bo_offset[2] = obj_image->image.offsets[2];
1958         }
1959
1960     }
1961     return true;
1962 }
1963
1964 static void
1965 gen8_gpe_context_yuv420p8_scaling_surfaces(VADriverContextP ctx,
1966                                            struct i965_gpe_context *gpe_context,
1967                                            VARectangle *src_rect,
1968                                            struct i965_surface *src_surface,
1969                                            VARectangle *dst_rect,
1970                                            struct i965_surface *dst_surface)
1971 {
1972     unsigned int fourcc;
1973     int width[3], height[3], pitch[3], bo_offset[3];
1974     dri_bo *bo;
1975     struct object_surface *obj_surface;
1976     struct object_image *obj_image;
1977     int bti;
1978
1979     if ((gpe_context == NULL) ||
1980         (src_rect == NULL) || (src_surface == NULL) ||
1981         (dst_rect == NULL) || (dst_surface == NULL))
1982         return;
1983
1984     if (src_surface->base == NULL || dst_surface->base == NULL)
1985         return;
1986
1987     fourcc = pp_get_surface_fourcc(ctx, src_surface);
1988
1989     if (src_surface->type == I965_SURFACE_TYPE_SURFACE) {
1990         obj_surface = (struct object_surface *)src_surface->base;
1991         bo = obj_surface->bo;
1992     } else {
1993         obj_image = (struct object_image *)src_surface->base;
1994         bo = obj_image->bo;
1995     }
1996
1997     bti = 0;
1998     if (gen8_pp_context_get_surface_conf(ctx, src_surface, src_rect,
1999                                          width, height, pitch,
2000                                          bo_offset)) {
2001         bti = BTI_SCALING_INPUT_Y;
2002         /* Input surface */
2003         gen8_add_dri_buffer_2d_gpe_surface(ctx, gpe_context, bo,
2004                                            bo_offset[0],
2005                                            width[0], height[0],
2006                                            pitch[0], 0,
2007                                            I965_SURFACEFORMAT_R8_UNORM,
2008                                            bti, 0);
2009         if (fourcc == VA_FOURCC_NV12) {
2010             gen8_add_dri_buffer_2d_gpe_surface(ctx, gpe_context, bo,
2011                                                bo_offset[1],
2012                                                width[1], height[1],
2013                                                pitch[1], 0,
2014                                                I965_SURFACEFORMAT_R8G8_UNORM,
2015                                                bti + 1, 0);
2016         } else {
2017             gen8_add_dri_buffer_2d_gpe_surface(ctx, gpe_context, bo,
2018                                                bo_offset[1],
2019                                                width[1], height[1],
2020                                                pitch[1], 0,
2021                                                I965_SURFACEFORMAT_R8_UNORM,
2022                                                bti + 1, 0);
2023
2024             gen8_add_dri_buffer_2d_gpe_surface(ctx, gpe_context, bo,
2025                                                bo_offset[2],
2026                                                width[2], height[2],
2027                                                pitch[2], 0,
2028                                                I965_SURFACEFORMAT_R8_UNORM,
2029                                                bti + 2, 0);
2030         }
2031     }
2032
2033     fourcc = pp_get_surface_fourcc(ctx, dst_surface);
2034
2035     if (dst_surface->type == I965_SURFACE_TYPE_SURFACE) {
2036         obj_surface = (struct object_surface *)dst_surface->base;
2037         bo = obj_surface->bo;
2038     } else {
2039         obj_image = (struct object_image *)dst_surface->base;
2040         bo = obj_image->bo;
2041     }
2042
2043     if (gen8_pp_context_get_surface_conf(ctx, dst_surface, dst_rect,
2044                                          width, height, pitch,
2045                                          bo_offset)) {
2046         bti = BTI_SCALING_OUTPUT_Y;
2047         /* Input surface */
2048         gen8_add_dri_buffer_2d_gpe_surface(ctx, gpe_context, bo,
2049                                            bo_offset[0],
2050                                            width[0], height[0],
2051                                            pitch[0], 1,
2052                                            I965_SURFACEFORMAT_R8_UINT,
2053                                            bti, 0);
2054         if (fourcc == VA_FOURCC_NV12) {
2055             gen8_add_dri_buffer_2d_gpe_surface(ctx, gpe_context, bo,
2056                                                bo_offset[1],
2057                                                width[1] * 2, height[1],
2058                                                pitch[1], 1,
2059                                                I965_SURFACEFORMAT_R16_UINT,
2060                                                bti + 1, 0);
2061         } else {
2062             gen8_add_dri_buffer_2d_gpe_surface(ctx, gpe_context, bo,
2063                                                bo_offset[1],
2064                                                width[1], height[1],
2065                                                pitch[1], 1,
2066                                                I965_SURFACEFORMAT_R8_UINT,
2067                                                bti + 1, 0);
2068
2069             gen8_add_dri_buffer_2d_gpe_surface(ctx, gpe_context, bo,
2070                                                bo_offset[2],
2071                                                width[2], height[2],
2072                                                pitch[2], 1,
2073                                                I965_SURFACEFORMAT_R8_UINT,
2074                                                bti + 2, 0);
2075         }
2076     }
2077
2078     return;
2079 }
2080
2081 VAStatus
2082 gen8_yuv420p8_scaling_post_processing(
2083     VADriverContextP   ctx,
2084     struct i965_post_processing_context *pp_context,
2085     struct i965_surface *src_surface,
2086     VARectangle *src_rect,
2087     struct i965_surface *dst_surface,
2088     VARectangle *dst_rect)
2089 {
2090     struct i965_gpe_context *gpe_context;
2091     struct gpe_media_object_walker_parameter media_object_walker_param;
2092     struct intel_vpp_kernel_walker_parameter kernel_walker_param;
2093
2094     if (!pp_context || !src_surface || !src_rect || !dst_surface || !dst_rect)
2095         return VA_STATUS_ERROR_INVALID_PARAMETER;
2096
2097     if (!(pp_context->scaling_8bit_initialized & VPPGPE_8BIT_420))
2098         return VA_STATUS_ERROR_UNIMPLEMENTED;
2099
2100     gpe_context = &pp_context->scaling_yuv420p8_context;
2101
2102     gen8_gpe_context_init(ctx, gpe_context);
2103     gen8_vpp_scaling_sample_state(ctx, gpe_context, src_rect, dst_rect);
2104     gen8_gpe_reset_binding_table(ctx, gpe_context);
2105     gen8_gpe_context_yuv420p8_scaling_curbe(ctx, gpe_context,
2106                                             src_rect, src_surface,
2107                                             dst_rect, dst_surface);
2108
2109     gen8_gpe_context_yuv420p8_scaling_surfaces(ctx, gpe_context,
2110                                                src_rect, src_surface,
2111                                                dst_rect, dst_surface);
2112
2113     gen8_gpe_setup_interface_data(ctx, gpe_context);
2114
2115     memset(&kernel_walker_param, 0, sizeof(kernel_walker_param));
2116     kernel_walker_param.resolution_x = ALIGN(dst_rect->width, 16) >> 4;
2117     kernel_walker_param.resolution_y = ALIGN(dst_rect->height, 16) >> 4;
2118     kernel_walker_param.no_dependency = 1;
2119
2120     intel_vpp_init_media_object_walker_parameter(&kernel_walker_param, &media_object_walker_param);
2121
2122     gen8_run_kernel_media_object_walker(ctx, pp_context->batch,
2123                                         gpe_context,
2124                                         &media_object_walker_param);
2125
2126     return VA_STATUS_SUCCESS;
2127 }