src/gen9_avc_encoder.c

   1 /*
   2  * Copyright @ 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWAR OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Pengfei Qu <Pengfei.qu@intel.com>
  26  *
  27  */
  28
  29 #include <stdio.h>
  30 #include <stdlib.h>
  31 #include <stdbool.h>
  32 #include <string.h>
  33 #include <math.h>
  34 #include <assert.h>
  35 #include <va/va.h>
  36
  37 #include "intel_batchbuffer.h"
  38 #include "intel_driver.h"
  39
  40 #include "i965_defines.h"
  41 #include "i965_structs.h"
  42 #include "i965_drv_video.h"
  43 #include "i965_encoder.h"
  44 #include "i965_encoder_utils.h"
  45 #include "intel_media.h"
  46
  47 #include "i965_gpe_utils.h"
  48 #include "i965_encoder_common.h"
  49 #include "i965_avc_encoder_common.h"
  50 #include "gen9_avc_encoder_kernels.h"
  51 #include "gen9_avc_encoder.h"
  52 #include "gen9_avc_const_def.h"
  53
  54 #define MAX_URB_SIZE                    4096 /* In register */
  55 #define NUM_KERNELS_PER_GPE_CONTEXT     1
  56 #define MBENC_KERNEL_BASE GEN9_AVC_KERNEL_MBENC_QUALITY_I
  57 #define GPE_RESOURCE_ALIGNMENT 4  /* 4 means 16 = 1 << 4) */
  58
  59 #define OUT_BUFFER_2DW(batch, bo, is_target, delta)  do {               \
  60         if (bo) {                                                       \
  61             OUT_BCS_RELOC64(batch,                                        \
  62                             bo,                                         \
  63                             I915_GEM_DOMAIN_INSTRUCTION,                \
  64                             is_target ? I915_GEM_DOMAIN_RENDER : 0,     \
  65                             delta);                                     \
  66         } else {                                                        \
  67             OUT_BCS_BATCH(batch, 0);                                    \
  68             OUT_BCS_BATCH(batch, 0);                                    \
  69         }                                                               \
  70     } while (0)
  71
  72 #define OUT_BUFFER_3DW(batch, bo, is_target, delta, attr)  do { \
  73         OUT_BUFFER_2DW(batch, bo, is_target, delta);            \
  74         OUT_BCS_BATCH(batch, attr);                             \
  75     } while (0)
  76
  77 static const uint32_t qm_flat[16] = {
  78     0x10101010, 0x10101010, 0x10101010, 0x10101010,
  79     0x10101010, 0x10101010, 0x10101010, 0x10101010,
  80     0x10101010, 0x10101010, 0x10101010, 0x10101010,
  81     0x10101010, 0x10101010, 0x10101010, 0x10101010
  82 };
  83
  84 static const uint32_t fqm_flat[32] = {
  85     0x10001000, 0x10001000, 0x10001000, 0x10001000,
  86     0x10001000, 0x10001000, 0x10001000, 0x10001000,
  87     0x10001000, 0x10001000, 0x10001000, 0x10001000,
  88     0x10001000, 0x10001000, 0x10001000, 0x10001000,
  89     0x10001000, 0x10001000, 0x10001000, 0x10001000,
  90     0x10001000, 0x10001000, 0x10001000, 0x10001000,
  91     0x10001000, 0x10001000, 0x10001000, 0x10001000,
  92     0x10001000, 0x10001000, 0x10001000, 0x10001000
  93 };
  94
  95 static const unsigned int slice_type_kernel[3] = {1,2,0};
  96
  97 static const gen9_avc_brc_init_reset_curbe_data gen9_avc_brc_init_reset_curbe_init_data =
  98 {
  99     // unsigned int 0
 100     {
 101             0
 102     },
 103
 104     // unsigned int 1
 105     {
 106             0
 107     },
 108
 109     // unsigned int 2
 110     {
 111             0
 112     },
 113
 114     // unsigned int 3
 115     {
 116             0
 117     },
 118
 119     // unsigned int 4
 120     {
 121             0
 122     },
 123
 124     // unsigned int 5
 125     {
 126             0
 127     },
 128
 129     // unsigned int 6
 130     {
 131             0
 132     },
 133
 134     // unsigned int 7
 135     {
 136             0
 137     },
 138
 139     // unsigned int 8
 140     {
 141             0,
 142             0
 143     },
 144
 145     // unsigned int 9
 146     {
 147             0,
 148             0
 149     },
 150
 151     // unsigned int 10
 152     {
 153             0,
 154             0
 155     },
 156
 157     // unsigned int 11
 158     {
 159             0,
 160             1
 161     },
 162
 163     // unsigned int 12
 164     {
 165             51,
 166             0
 167     },
 168
 169     // unsigned int 13
 170     {
 171             40,
 172             60,
 173             80,
 174             120
 175     },
 176
 177     // unsigned int 14
 178     {
 179             35,
 180             60,
 181             80,
 182             120
 183     },
 184
 185     // unsigned int 15
 186     {
 187             40,
 188             60,
 189             90,
 190             115
 191     },
 192
 193     // unsigned int 16
 194     {
 195             0,
 196             0,
 197             0,
 198             0
 199     },
 200
 201     // unsigned int 17
 202     {
 203             0,
 204             0,
 205             0,
 206             0
 207     },
 208
 209     // unsigned int 18
 210     {
 211             0,
 212             0,
 213             0,
 214             0
 215     },
 216
 217     // unsigned int 19
 218     {
 219             0,
 220             0,
 221             0,
 222             0
 223     },
 224
 225     // unsigned int 20
 226     {
 227             0,
 228             0,
 229             0,
 230             0
 231     },
 232
 233     // unsigned int 21
 234     {
 235             0,
 236             0,
 237             0,
 238             0
 239     },
 240
 241     // unsigned int 22
 242     {
 243             0,
 244             0,
 245             0,
 246             0
 247     },
 248
 249     // unsigned int 23
 250     {
 251             0
 252     }
 253 };
 254
 255 static const gen9_avc_frame_brc_update_curbe_data gen9_avc_frame_brc_update_curbe_init_data =
 256 {
 257     // unsigned int 0
 258     {
 259             0
 260     },
 261
 262     // unsigned int 1
 263     {
 264             0
 265     },
 266
 267     // unsigned int 2
 268     {
 269             0
 270     },
 271
 272     // unsigned int 3
 273     {
 274             10,
 275             50
 276     },
 277
 278     // unsigned int 4
 279     {
 280             100,
 281             150
 282     },
 283
 284     // unsigned int 5
 285     {
 286             0,
 287             0,
 288             0,
 289             0
 290     },
 291
 292     // unsigned int 6
 293     {
 294             0,
 295             0,
 296             0,
 297             0,
 298             0,
 299             0
 300     },
 301
 302     // unsigned int 7
 303     {
 304             0
 305     },
 306
 307     // unsigned int 8
 308     {
 309             1,
 310             1,
 311             3,
 312             2
 313     },
 314
 315     // unsigned int 9
 316     {
 317             1,
 318             40,
 319             5,
 320             5
 321     },
 322
 323     // unsigned int 10
 324     {
 325             3,
 326             1,
 327             7,
 328             18
 329     },
 330
 331     // unsigned int 11
 332     {
 333             25,
 334             37,
 335             40,
 336             75
 337     },
 338
 339     // unsigned int 12
 340     {
 341             97,
 342             103,
 343             125,
 344             160
 345     },
 346
 347     // unsigned int 13
 348     {
 349             -3,
 350             -2,
 351             -1,
 352             0
 353     },
 354
 355     // unsigned int 14
 356     {
 357             1,
 358             2,
 359             3,
 360             0xff
 361     },
 362
 363     // unsigned int 15
 364     {
 365             0,
 366             0,
 367             0,
 368             0
 369     },
 370
 371     // unsigned int 16
 372     {
 373             0
 374     },
 375
 376     // unsigned int 17
 377     {
 378             0
 379     },
 380
 381     // unsigned int 18
 382     {
 383             0
 384     },
 385
 386     // unsigned int 19
 387     {
 388             0
 389     },
 390
 391     // unsigned int 20
 392     {
 393             0
 394     },
 395
 396     // unsigned int 21
 397     {
 398             0
 399     },
 400
 401     // unsigned int 22
 402     {
 403             0
 404     },
 405
 406     // unsigned int 23
 407     {
 408             0
 409     },
 410
 411 };
 412
 413 static void
 414 gen9_avc_update_misc_parameters(VADriverContextP ctx,
 415                                 struct encode_state *encode_state,
 416                                 struct intel_encoder_context *encoder_context)
 417 {
 418     struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
 419     struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
 420     int i;
 421
 422     /* brc */
 423     generic_state->max_bit_rate = (encoder_context->brc.bits_per_second[0] + 1000 - 1) / 1000;
 424
 425     generic_state->brc_need_reset = encoder_context->brc.need_reset;
 426
 427     if (generic_state->internal_rate_mode == VA_RC_CBR) {
 428         generic_state->min_bit_rate = generic_state->max_bit_rate;
 429         generic_state->mb_brc_enabled = encoder_context->brc.mb_rate_control[0];
 430
 431         if (generic_state->target_bit_rate != generic_state->max_bit_rate) {
 432             generic_state->target_bit_rate = generic_state->max_bit_rate;
 433             generic_state->brc_need_reset = 1;
 434         }
 435     } else if (generic_state->internal_rate_mode == VA_RC_VBR) {
 436         generic_state->min_bit_rate = generic_state->max_bit_rate * (2 * encoder_context->brc.target_percentage[0] - 100) / 100;
 437         generic_state->mb_brc_enabled = encoder_context->brc.mb_rate_control[0];
 438
 439         if (generic_state->target_bit_rate != generic_state->max_bit_rate * encoder_context->brc.target_percentage[0] / 100) {
 440             generic_state->target_bit_rate = generic_state->max_bit_rate * encoder_context->brc.target_percentage[0] / 100;
 441             generic_state->brc_need_reset = 1;
 442         }
 443     }
 444
 445     /*  frame rate */
 446     if (generic_state->internal_rate_mode != VA_RC_CQP)
 447     {
 448         generic_state->frames_per_100s = encoder_context->brc.framerate[0].num * 100/encoder_context->brc.framerate[0].den ;
 449         generic_state->frame_rate = encoder_context->brc.framerate[0].num/encoder_context->brc.framerate[0].den ;
 450         generic_state->frames_per_window_size = (int)(encoder_context->brc.window_size * generic_state->frame_rate /1000);// brc.windows size in ms as the unit
 451     }else
 452     {
 453         generic_state->frames_per_100s = 30 * 100;
 454         generic_state->frame_rate = 30 ;
 455         generic_state->frames_per_window_size = 30;
 456     }
 457
 458     /*  HRD */
 459     if (generic_state->internal_rate_mode != VA_RC_CQP)
 460     {
 461         generic_state->vbv_buffer_size_in_bit = encoder_context->brc.hrd_buffer_size;//misc->buffer_size;
 462         generic_state->init_vbv_buffer_fullness_in_bit = encoder_context->brc.hrd_initial_buffer_fullness;//misc->initial_buffer_fullness;
 463     }
 464
 465     /* ROI */
 466     generic_state->num_roi = MIN(encoder_context->brc.num_roi, 3);
 467     if (generic_state->num_roi > 0) {
 468         generic_state->max_delta_qp = encoder_context->brc.roi_max_delta_qp;
 469         generic_state->min_delta_qp = encoder_context->brc.roi_min_delta_qp;
 470
 471         for (i = 0; i < generic_state->num_roi; i++) {
 472             generic_state->roi[i].left   = encoder_context->brc.roi[i].left;
 473             generic_state->roi[i].right  = encoder_context->brc.roi[i].right;
 474             generic_state->roi[i].top    = encoder_context->brc.roi[i].top;
 475             generic_state->roi[i].bottom = encoder_context->brc.roi[i].bottom;
 476             generic_state->roi[i].value  = encoder_context->brc.roi[i].value;
 477
 478             generic_state->roi[i].left /= 16;
 479             generic_state->roi[i].right /= 16;
 480             generic_state->roi[i].top /= 16;
 481             generic_state->roi[i].bottom /= 16;
 482         }
 483     }
 484
 485 }
 486
 487 static bool
 488 intel_avc_get_kernel_header_and_size(void *pvbinary,
 489                                      int binary_size,
 490                                      INTEL_GENERIC_ENC_OPERATION operation,
 491                                      int krnstate_idx,
 492                                      struct i965_kernel *ret_kernel)
 493 {
 494     typedef uint32_t BIN_PTR[4];
 495
 496     char *bin_start;
 497     gen9_avc_encoder_kernel_header      *pkh_table;
 498     kernel_header          *pcurr_header, *pinvalid_entry, *pnext_header;
 499     int next_krnoffset;
 500
 501     if (!pvbinary || !ret_kernel)
 502         return false;
 503
 504     bin_start = (char *)pvbinary;
 505     pkh_table = (gen9_avc_encoder_kernel_header *)pvbinary;
 506     pinvalid_entry = &(pkh_table->static_detection) + 1;
 507     next_krnoffset = binary_size;
 508
 509     if (operation == INTEL_GENERIC_ENC_SCALING4X)
 510     {
 511         pcurr_header = &pkh_table->ply_dscale_ply;
 512     }
 513     else if (operation == INTEL_GENERIC_ENC_SCALING2X)
 514     {
 515         pcurr_header = &pkh_table->ply_2xdscale_ply;
 516     }
 517     else if (operation == INTEL_GENERIC_ENC_ME)
 518     {
 519         pcurr_header = &pkh_table->me_p;
 520     }
 521     else if (operation == INTEL_GENERIC_ENC_BRC)
 522     {
 523         pcurr_header = &pkh_table->frame_brc_init;
 524     }
 525     else if (operation == INTEL_GENERIC_ENC_MBENC)
 526     {
 527         pcurr_header = &pkh_table->mbenc_quality_I;
 528     }
 529     else if (operation == INTEL_GENERIC_ENC_WP)
 530     {
 531         pcurr_header = &pkh_table->wp;
 532     }
 533     else if (operation == INTEL_GENERIC_ENC_SFD)
 534     {
 535         pcurr_header = &pkh_table->static_detection;
 536     }
 537     else
 538     {
 539         return false;
 540     }
 541
 542     pcurr_header += krnstate_idx;
 543     ret_kernel->bin = (const BIN_PTR *)(bin_start + (pcurr_header->kernel_start_pointer << 6));
 544
 545     pnext_header = (pcurr_header + 1);
 546     if (pnext_header < pinvalid_entry)
 547     {
 548         next_krnoffset = pnext_header->kernel_start_pointer << 6;
 549     }
 550     ret_kernel->size = next_krnoffset - (pcurr_header->kernel_start_pointer << 6);
 551
 552     return true;
 553 }
 554 static void
 555 gen9_free_surfaces_avc(void **data)
 556 {
 557     struct gen9_surface_avc *avc_surface;
 558
 559     if (!data || !*data)
 560         return;
 561
 562     avc_surface = *data;
 563
 564     if (avc_surface->scaled_4x_surface_obj) {
 565         i965_DestroySurfaces(avc_surface->ctx, &avc_surface->scaled_4x_surface_id, 1);
 566         avc_surface->scaled_4x_surface_id = VA_INVALID_SURFACE;
 567         avc_surface->scaled_4x_surface_obj = NULL;
 568     }
 569
 570     if (avc_surface->scaled_16x_surface_obj) {
 571         i965_DestroySurfaces(avc_surface->ctx, &avc_surface->scaled_16x_surface_id, 1);
 572         avc_surface->scaled_16x_surface_id = VA_INVALID_SURFACE;
 573         avc_surface->scaled_16x_surface_obj = NULL;
 574     }
 575
 576     if (avc_surface->scaled_32x_surface_obj) {
 577         i965_DestroySurfaces(avc_surface->ctx, &avc_surface->scaled_32x_surface_id, 1);
 578         avc_surface->scaled_32x_surface_id = VA_INVALID_SURFACE;
 579         avc_surface->scaled_32x_surface_obj = NULL;
 580     }
 581
 582     i965_free_gpe_resource(&avc_surface->res_mb_code_surface);
 583     i965_free_gpe_resource(&avc_surface->res_mv_data_surface);
 584     i965_free_gpe_resource(&avc_surface->res_ref_pic_select_surface);
 585
 586     dri_bo_unreference(avc_surface->dmv_top);
 587     avc_surface->dmv_top = NULL;
 588     dri_bo_unreference(avc_surface->dmv_bottom);
 589     avc_surface->dmv_bottom = NULL;
 590
 591     free(avc_surface);
 592
 593     *data = NULL;
 594
 595     return;
 596 }
 597
 598 static VAStatus
 599 gen9_avc_init_check_surfaces(VADriverContextP ctx,
 600                              struct object_surface *obj_surface,
 601                              struct intel_encoder_context *encoder_context,
 602                              struct avc_surface_param *surface_param)
 603 {
 604     struct i965_driver_data *i965 = i965_driver_data(ctx);
 605     struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
 606     struct avc_enc_state * avc_state = (struct avc_enc_state * )vme_context->private_enc_state;
 607     struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
 608
 609     struct gen9_surface_avc *avc_surface;
 610     int downscaled_width_4x, downscaled_height_4x;
 611     int downscaled_width_16x, downscaled_height_16x;
 612     int downscaled_width_32x, downscaled_height_32x;
 613     int size = 0;
 614     unsigned int frame_width_in_mbs = ALIGN(surface_param->frame_width,16) / 16;
 615     unsigned int frame_height_in_mbs = ALIGN(surface_param->frame_height,16) / 16;
 616     unsigned int frame_mb_nums = frame_width_in_mbs * frame_height_in_mbs;
 617     int allocate_flag = 1;
 618     int width,height;
 619
 620     if (!obj_surface || !obj_surface->bo)
 621         return VA_STATUS_ERROR_INVALID_SURFACE;
 622
 623     if (obj_surface->private_data) {
 624         return VA_STATUS_SUCCESS;
 625     }
 626
 627     avc_surface = calloc(1, sizeof(struct gen9_surface_avc));
 628
 629     if (!avc_surface)
 630         return VA_STATUS_ERROR_ALLOCATION_FAILED;
 631
 632     avc_surface->ctx = ctx;
 633     obj_surface->private_data = avc_surface;
 634     obj_surface->free_private_data = gen9_free_surfaces_avc;
 635
 636     downscaled_width_4x = generic_state->frame_width_4x;
 637     downscaled_height_4x = generic_state->frame_height_4x;
 638
 639     i965_CreateSurfaces(ctx,
 640                         downscaled_width_4x,
 641                         downscaled_height_4x,
 642                         VA_RT_FORMAT_YUV420,
 643                         1,
 644                         &avc_surface->scaled_4x_surface_id);
 645
 646     avc_surface->scaled_4x_surface_obj = SURFACE(avc_surface->scaled_4x_surface_id);
 647
 648     if (!avc_surface->scaled_4x_surface_obj) {
 649         return VA_STATUS_ERROR_ALLOCATION_FAILED;
 650     }
 651
 652     i965_check_alloc_surface_bo(ctx, avc_surface->scaled_4x_surface_obj, 1,
 653                                 VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420);
 654
 655     downscaled_width_16x = generic_state->frame_width_16x;
 656     downscaled_height_16x = generic_state->frame_height_16x;
 657     i965_CreateSurfaces(ctx,
 658                         downscaled_width_16x,
 659                         downscaled_height_16x,
 660                         VA_RT_FORMAT_YUV420,
 661                         1,
 662                         &avc_surface->scaled_16x_surface_id);
 663     avc_surface->scaled_16x_surface_obj = SURFACE(avc_surface->scaled_16x_surface_id);
 664
 665     if (!avc_surface->scaled_16x_surface_obj) {
 666         return VA_STATUS_ERROR_ALLOCATION_FAILED;
 667     }
 668
 669     i965_check_alloc_surface_bo(ctx, avc_surface->scaled_16x_surface_obj, 1,
 670                                 VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420);
 671
 672     if(generic_state->b32xme_supported ||
 673        generic_state->b32xme_enabled)
 674     {
 675         downscaled_width_32x = generic_state->frame_width_32x;
 676         downscaled_height_32x = generic_state->frame_height_32x;
 677         i965_CreateSurfaces(ctx,
 678                             downscaled_width_32x,
 679                             downscaled_height_32x,
 680                             VA_RT_FORMAT_YUV420,
 681                             1,
 682                             &avc_surface->scaled_32x_surface_id);
 683         avc_surface->scaled_32x_surface_obj = SURFACE(avc_surface->scaled_32x_surface_id);
 684
 685         if (!avc_surface->scaled_32x_surface_obj) {
 686             return VA_STATUS_ERROR_ALLOCATION_FAILED;
 687         }
 688
 689         i965_check_alloc_surface_bo(ctx, avc_surface->scaled_32x_surface_obj, 1,
 690                                     VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420);
 691     }
 692
 693     /*mb code and mv data for each frame*/
 694     size = frame_mb_nums * 16 * 4;
 695     allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
 696         &avc_surface->res_mb_code_surface,
 697         ALIGN(size,0x1000),
 698         "mb code buffer");
 699     if (!allocate_flag)
 700         goto failed_allocation;
 701
 702     size = frame_mb_nums * 32 * 4;
 703     allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
 704         &avc_surface->res_mv_data_surface,
 705         ALIGN(size,0x1000),
 706         "mv data buffer");
 707     if (!allocate_flag)
 708         goto failed_allocation;
 709
 710     /* ref pic list*/
 711     if(avc_state->ref_pic_select_list_supported)
 712     {
 713         width = ALIGN(frame_width_in_mbs * 8,64);
 714         height= frame_height_in_mbs ;
 715         allocate_flag = i965_gpe_allocate_2d_resource(i965->intel.bufmgr,
 716                                      &avc_surface->res_ref_pic_select_surface,
 717                                      width, height,
 718                                      width,
 719                                      "Ref pic select list buffer");
 720         if (!allocate_flag)
 721             goto failed_allocation;
 722     }
 723
 724     /*direct mv*/
 725     avc_surface->dmv_top =
 726         dri_bo_alloc(i965->intel.bufmgr,
 727         "direct mv top Buffer",
 728         68 * frame_mb_nums,
 729         64);
 730     avc_surface->dmv_bottom =
 731         dri_bo_alloc(i965->intel.bufmgr,
 732         "direct mv bottom Buffer",
 733         68 * frame_mb_nums,
 734         64);
 735     assert(avc_surface->dmv_top);
 736     assert(avc_surface->dmv_bottom);
 737
 738     return VA_STATUS_SUCCESS;
 739
 740 failed_allocation:
 741     return VA_STATUS_ERROR_ALLOCATION_FAILED;
 742 }
 743
 744 static VAStatus
 745 gen9_avc_allocate_resources(VADriverContextP ctx,
 746                             struct encode_state *encode_state,
 747                             struct intel_encoder_context *encoder_context)
 748 {
 749     struct i965_driver_data *i965 = i965_driver_data(ctx);
 750     struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
 751     struct i965_avc_encoder_context * avc_ctx = (struct i965_avc_encoder_context * )vme_context->private_enc_ctx;
 752     struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
 753     struct avc_enc_state * avc_state = (struct avc_enc_state * )vme_context->private_enc_state;
 754     unsigned int size  = 0;
 755     unsigned int width  = 0;
 756     unsigned int height  = 0;
 757     unsigned char * data  = NULL;
 758     int allocate_flag = 1;
 759     int i = 0;
 760
 761     /*all the surface/buffer are allocated here*/
 762
 763     /*second level batch buffer for image state write when cqp etc*/
 764     i965_free_gpe_resource(&avc_ctx->res_image_state_batch_buffer_2nd_level);
 765     size = INTEL_AVC_IMAGE_STATE_CMD_SIZE ;
 766     allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
 767                              &avc_ctx->res_image_state_batch_buffer_2nd_level,
 768                              ALIGN(size,0x1000),
 769                              "second levle batch (image state write) buffer");
 770     if (!allocate_flag)
 771         goto failed_allocation;
 772
 773     /* scaling related surface   */
 774     if(avc_state->mb_status_supported)
 775     {
 776         i965_free_gpe_resource(&avc_ctx->res_mb_status_buffer);
 777         size = (generic_state->frame_width_in_mbs * generic_state->frame_height_in_mbs * 16 * 4 + 1023)&~0x3ff;
 778         allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
 779                                  &avc_ctx->res_mb_status_buffer,
 780                                  ALIGN(size,0x1000),
 781                                  "MB statistics output buffer");
 782         if (!allocate_flag)
 783             goto failed_allocation;
 784         i965_zero_gpe_resource(&avc_ctx->res_mb_status_buffer);
 785     }
 786
 787     if(avc_state->flatness_check_supported)
 788     {
 789         width = generic_state->frame_width_in_mbs * 4;
 790         height= generic_state->frame_height_in_mbs * 4;
 791         i965_free_gpe_resource(&avc_ctx->res_flatness_check_surface);
 792         allocate_flag = i965_gpe_allocate_2d_resource(i965->intel.bufmgr,
 793                                      &avc_ctx->res_flatness_check_surface,
 794                                      width, height,
 795                                      ALIGN(width,64),
 796                                      "Flatness check buffer");
 797         if (!allocate_flag)
 798             goto failed_allocation;
 799     }
 800     /* me related surface */
 801     width = generic_state->downscaled_width_4x_in_mb * 8;
 802     height= generic_state->downscaled_height_4x_in_mb * 4 * 10;
 803     i965_free_gpe_resource(&avc_ctx->s4x_memv_distortion_buffer);
 804     allocate_flag = i965_gpe_allocate_2d_resource(i965->intel.bufmgr,
 805                                  &avc_ctx->s4x_memv_distortion_buffer,
 806                                  width, height,
 807                                  ALIGN(width,64),
 808                                  "4x MEMV distortion buffer");
 809     if (!allocate_flag)
 810         goto failed_allocation;
 811     i965_zero_gpe_resource(&avc_ctx->s4x_memv_distortion_buffer);
 812
 813     width = (generic_state->downscaled_width_4x_in_mb + 7)/8 * 64;
 814     height= (generic_state->downscaled_height_4x_in_mb + 1)/2 * 8;
 815     i965_free_gpe_resource(&avc_ctx->s4x_memv_min_distortion_brc_buffer);
 816     allocate_flag = i965_gpe_allocate_2d_resource(i965->intel.bufmgr,
 817                                  &avc_ctx->s4x_memv_min_distortion_brc_buffer,
 818                                  width, height,
 819                                  width,
 820                                  "4x MEMV min distortion brc buffer");
 821     if (!allocate_flag)
 822         goto failed_allocation;
 823     i965_zero_gpe_resource(&avc_ctx->s4x_memv_min_distortion_brc_buffer);
 824
 825
 826     width = ALIGN(generic_state->downscaled_width_4x_in_mb * 32,64);
 827     height= generic_state->downscaled_height_4x_in_mb * 4 * 2 * 10;
 828     i965_free_gpe_resource(&avc_ctx->s4x_memv_data_buffer);
 829     allocate_flag = i965_gpe_allocate_2d_resource(i965->intel.bufmgr,
 830                                  &avc_ctx->s4x_memv_data_buffer,
 831                                  width, height,
 832                                  width,
 833                                  "4x MEMV data buffer");
 834     if (!allocate_flag)
 835         goto failed_allocation;
 836     i965_zero_gpe_resource(&avc_ctx->s4x_memv_data_buffer);
 837
 838
 839     width = ALIGN(generic_state->downscaled_width_16x_in_mb * 32,64);
 840     height= generic_state->downscaled_height_16x_in_mb * 4 * 2 * 10 ;
 841     i965_free_gpe_resource(&avc_ctx->s16x_memv_data_buffer);
 842     allocate_flag = i965_gpe_allocate_2d_resource(i965->intel.bufmgr,
 843                                  &avc_ctx->s16x_memv_data_buffer,
 844                                  width, height,
 845                                  width,
 846                                  "16x MEMV data buffer");
 847     if (!allocate_flag)
 848         goto failed_allocation;
 849     i965_zero_gpe_resource(&avc_ctx->s16x_memv_data_buffer);
 850
 851
 852     width = ALIGN(generic_state->downscaled_width_32x_in_mb * 32,64);
 853     height= generic_state->downscaled_height_32x_in_mb * 4 * 2 * 10 ;
 854     i965_free_gpe_resource(&avc_ctx->s32x_memv_data_buffer);
 855     allocate_flag = i965_gpe_allocate_2d_resource(i965->intel.bufmgr,
 856                                  &avc_ctx->s32x_memv_data_buffer,
 857                                  width, height,
 858                                  width,
 859                                  "32x MEMV data buffer");
 860     if (!allocate_flag)
 861         goto failed_allocation;
 862     i965_zero_gpe_resource(&avc_ctx->s32x_memv_data_buffer);
 863
 864
 865     if(!generic_state->brc_allocated)
 866     {
 867         /*brc related surface */
 868         i965_free_gpe_resource(&avc_ctx->res_brc_history_buffer);
 869         size = 864;
 870         allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
 871                                  &avc_ctx->res_brc_history_buffer,
 872                                  ALIGN(size,0x1000),
 873                                  "brc history buffer");
 874         if (!allocate_flag)
 875             goto failed_allocation;
 876
 877         i965_free_gpe_resource(&avc_ctx->res_brc_pre_pak_statistics_output_buffer);
 878         size = 64;//44
 879         allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
 880                                  &avc_ctx->res_brc_pre_pak_statistics_output_buffer,
 881                                  ALIGN(size,0x1000),
 882                                  "brc pak statistic buffer");
 883         if (!allocate_flag)
 884             goto failed_allocation;
 885
 886         i965_free_gpe_resource(&avc_ctx->res_brc_image_state_read_buffer);
 887         size = INTEL_AVC_IMAGE_STATE_CMD_SIZE * 7;
 888         allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
 889                                  &avc_ctx->res_brc_image_state_read_buffer,
 890                                  ALIGN(size,0x1000),
 891                                  "brc image state read buffer");
 892         if (!allocate_flag)
 893             goto failed_allocation;
 894
 895         i965_free_gpe_resource(&avc_ctx->res_brc_image_state_write_buffer);
 896         size = INTEL_AVC_IMAGE_STATE_CMD_SIZE * 7;
 897         allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
 898                                  &avc_ctx->res_brc_image_state_write_buffer,
 899                                  ALIGN(size,0x1000),
 900                                  "brc image state write buffer");
 901         if (!allocate_flag)
 902             goto failed_allocation;
 903
 904         width = ALIGN(64,64);
 905         height= 44;
 906         i965_free_gpe_resource(&avc_ctx->res_brc_const_data_buffer);
 907         allocate_flag = i965_gpe_allocate_2d_resource(i965->intel.bufmgr,
 908                                      &avc_ctx->res_brc_const_data_buffer,
 909                                      width, height,
 910                                      width,
 911                                      "brc const data buffer");
 912         if (!allocate_flag)
 913             goto failed_allocation;
 914
 915         if(generic_state->brc_distortion_buffer_supported)
 916         {
 917             width = ALIGN(generic_state->downscaled_width_4x_in_mb * 8,64);
 918             height= ALIGN(generic_state->downscaled_height_4x_in_mb * 4,8);
 919             width = (generic_state->downscaled_width_4x_in_mb + 7)/8 * 64;
 920             height= (generic_state->downscaled_height_4x_in_mb + 1)/2 * 8;
 921             i965_free_gpe_resource(&avc_ctx->res_brc_dist_data_surface);
 922             allocate_flag = i965_gpe_allocate_2d_resource(i965->intel.bufmgr,
 923                                          &avc_ctx->res_brc_dist_data_surface,
 924                                          width, height,
 925                                          width,
 926                                          "brc dist data buffer");
 927             if (!allocate_flag)
 928                 goto failed_allocation;
 929             i965_zero_gpe_resource(&avc_ctx->res_brc_dist_data_surface);
 930         }
 931
 932         if(generic_state->brc_roi_enable)
 933         {
 934             width = ALIGN(generic_state->downscaled_width_4x_in_mb * 16,64);
 935             height= ALIGN(generic_state->downscaled_height_4x_in_mb * 4,8);
 936             i965_free_gpe_resource(&avc_ctx->res_mbbrc_roi_surface);
 937             allocate_flag = i965_gpe_allocate_2d_resource(i965->intel.bufmgr,
 938                                          &avc_ctx->res_mbbrc_roi_surface,
 939                                          width, height,
 940                                          width,
 941                                          "mbbrc roi buffer");
 942             if (!allocate_flag)
 943                 goto failed_allocation;
 944             i965_zero_gpe_resource(&avc_ctx->res_mbbrc_roi_surface);
 945         }
 946
 947         /*mb qp in mb brc*/
 948         width = ALIGN(generic_state->downscaled_width_4x_in_mb * 4,64);
 949         height= ALIGN(generic_state->downscaled_height_4x_in_mb * 4,8);
 950         i965_free_gpe_resource(&avc_ctx->res_mbbrc_mb_qp_data_surface);
 951         allocate_flag = i965_gpe_allocate_2d_resource(i965->intel.bufmgr,
 952                                      &avc_ctx->res_mbbrc_mb_qp_data_surface,
 953                                      width, height,
 954                                      width,
 955                                      "mbbrc mb qp buffer");
 956         if (!allocate_flag)
 957             goto failed_allocation;
 958
 959         i965_free_gpe_resource(&avc_ctx->res_mbbrc_const_data_buffer);
 960         size = 16 * 52 * 4;
 961         allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
 962                                  &avc_ctx->res_mbbrc_const_data_buffer,
 963                                  ALIGN(size,0x1000),
 964                                  "mbbrc const data buffer");
 965         if (!allocate_flag)
 966             goto failed_allocation;
 967
 968         generic_state->brc_allocated = 1;
 969     }
 970
 971     /*mb qp external*/
 972     if(avc_state->mb_qp_data_enable)
 973     {
 974         width = ALIGN(generic_state->downscaled_width_4x_in_mb * 4,64);
 975         height= ALIGN(generic_state->downscaled_height_4x_in_mb * 4,8);
 976         i965_free_gpe_resource(&avc_ctx->res_mb_qp_data_surface);
 977         allocate_flag = i965_gpe_allocate_2d_resource(i965->intel.bufmgr,
 978                                      &avc_ctx->res_mb_qp_data_surface,
 979                                      width, height,
 980                                      width,
 981                                      "external mb qp buffer");
 982         if (!allocate_flag)
 983             goto failed_allocation;
 984     }
 985
 986     /*     mbenc related surface. it share most of surface with other kernels     */
 987     if(avc_state->arbitrary_num_mbs_in_slice)
 988     {
 989         width = (generic_state->frame_width_in_mbs + 1) * 64;
 990         height= generic_state->frame_height_in_mbs ;
 991         i965_free_gpe_resource(&avc_ctx->res_mbenc_slice_map_surface);
 992         allocate_flag = i965_gpe_allocate_2d_resource(i965->intel.bufmgr,
 993                                      &avc_ctx->res_mbenc_slice_map_surface,
 994                                      width, height,
 995                                      width,
 996                                      "slice map buffer");
 997         if (!allocate_flag)
 998             goto failed_allocation;
 999
1000         /*generate slice map,default one slice per frame.*/
1001     }
1002
1003     /* sfd related surface  */
1004     if(avc_state->sfd_enable)
1005     {
1006         i965_free_gpe_resource(&avc_ctx->res_sfd_output_buffer);
1007         size = 128;
1008         allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
1009                                  &avc_ctx->res_sfd_output_buffer,
1010                                  size,
1011                                  "sfd output buffer");
1012         if (!allocate_flag)
1013             goto failed_allocation;
1014
1015         i965_free_gpe_resource(&avc_ctx->res_sfd_cost_table_p_frame_buffer);
1016         size = ALIGN(52,64);
1017         allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
1018                                  &avc_ctx->res_sfd_cost_table_p_frame_buffer,
1019                                  size,
1020                                  "sfd P frame cost table buffer");
1021         if (!allocate_flag)
1022             goto failed_allocation;
1023         data = i965_map_gpe_resource(&(avc_ctx->res_sfd_cost_table_p_frame_buffer));
1024         assert(data);
1025         memcpy(data,gen9_avc_sfd_cost_table_p_frame,sizeof(unsigned char) *52);
1026         i965_unmap_gpe_resource(&(avc_ctx->res_sfd_cost_table_p_frame_buffer));
1027
1028         i965_free_gpe_resource(&avc_ctx->res_sfd_cost_table_b_frame_buffer);
1029         size = ALIGN(52,64);
1030         allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
1031                                  &avc_ctx->res_sfd_cost_table_b_frame_buffer,
1032                                  size,
1033                                  "sfd B frame cost table buffer");
1034         if (!allocate_flag)
1035             goto failed_allocation;
1036         data = i965_map_gpe_resource(&(avc_ctx->res_sfd_cost_table_b_frame_buffer));
1037         assert(data);
1038         memcpy(data,gen9_avc_sfd_cost_table_b_frame,sizeof(unsigned char) *52);
1039         i965_unmap_gpe_resource(&(avc_ctx->res_sfd_cost_table_b_frame_buffer));
1040     }
1041
1042     /* wp related surfaces */
1043     if(avc_state->weighted_prediction_supported)
1044     {
1045         for(i = 0; i < 2 ; i++)
1046         {
1047             if (avc_ctx->wp_output_pic_select_surface_obj[i]) {
1048                 continue;
1049             }
1050
1051             width = generic_state->frame_width_in_pixel;
1052             height= generic_state->frame_height_in_pixel ;
1053             i965_CreateSurfaces(ctx,
1054                                 width,
1055                                 height,
1056                                 VA_RT_FORMAT_YUV420,
1057                                 1,
1058                                 &avc_ctx->wp_output_pic_select_surface_id[i]);
1059             avc_ctx->wp_output_pic_select_surface_obj[i] = SURFACE(avc_ctx->wp_output_pic_select_surface_id[i]);
1060
1061             if (!avc_ctx->wp_output_pic_select_surface_obj[i]) {
1062                 goto failed_allocation;
1063             }
1064
1065             i965_check_alloc_surface_bo(ctx, avc_ctx->wp_output_pic_select_surface_obj[i], 1,
1066                                 VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420);
1067         }
1068         i965_free_gpe_resource(&avc_ctx->res_wp_output_pic_select_surface_list[0]);
1069         i965_object_surface_to_2d_gpe_resource_with_align(&avc_ctx->res_wp_output_pic_select_surface_list[0], avc_ctx->wp_output_pic_select_surface_obj[0],GPE_RESOURCE_ALIGNMENT);
1070         i965_free_gpe_resource(&avc_ctx->res_wp_output_pic_select_surface_list[1]);
1071         i965_object_surface_to_2d_gpe_resource_with_align(&avc_ctx->res_wp_output_pic_select_surface_list[1], avc_ctx->wp_output_pic_select_surface_obj[1],GPE_RESOURCE_ALIGNMENT);
1072     }
1073
1074     /* other   */
1075
1076     i965_free_gpe_resource(&avc_ctx->res_mad_data_buffer);
1077     size = 4 * 1;
1078     allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
1079                                  &avc_ctx->res_mad_data_buffer,
1080                                  ALIGN(size,0x1000),
1081                                  "MAD data buffer");
1082     if (!allocate_flag)
1083         goto failed_allocation;
1084
1085     return VA_STATUS_SUCCESS;
1086
1087 failed_allocation:
1088     return VA_STATUS_ERROR_ALLOCATION_FAILED;
1089 }
1090
1091 static void
1092 gen9_avc_free_resources(struct encoder_vme_mfc_context * vme_context)
1093 {
1094     if(!vme_context)
1095         return;
1096
1097     struct i965_avc_encoder_context * avc_ctx = (struct i965_avc_encoder_context * )vme_context->private_enc_ctx;
1098     VADriverContextP ctx = avc_ctx->ctx;
1099     int i = 0;
1100
1101     /* free all the surface/buffer here*/
1102     i965_free_gpe_resource(&avc_ctx->res_image_state_batch_buffer_2nd_level);
1103     i965_free_gpe_resource(&avc_ctx->res_mb_status_buffer);
1104     i965_free_gpe_resource(&avc_ctx->res_flatness_check_surface);
1105     i965_free_gpe_resource(&avc_ctx->s4x_memv_distortion_buffer);
1106     i965_free_gpe_resource(&avc_ctx->s4x_memv_min_distortion_brc_buffer);
1107     i965_free_gpe_resource(&avc_ctx->s4x_memv_data_buffer);
1108     i965_free_gpe_resource(&avc_ctx->s16x_memv_data_buffer);
1109     i965_free_gpe_resource(&avc_ctx->s32x_memv_data_buffer);
1110     i965_free_gpe_resource(&avc_ctx->res_brc_history_buffer);
1111     i965_free_gpe_resource(&avc_ctx->res_brc_pre_pak_statistics_output_buffer);
1112     i965_free_gpe_resource(&avc_ctx->res_brc_image_state_read_buffer);
1113     i965_free_gpe_resource(&avc_ctx->res_brc_image_state_write_buffer);
1114     i965_free_gpe_resource(&avc_ctx->res_brc_const_data_buffer);
1115     i965_free_gpe_resource(&avc_ctx->res_brc_dist_data_surface);
1116     i965_free_gpe_resource(&avc_ctx->res_mbbrc_roi_surface);
1117     i965_free_gpe_resource(&avc_ctx->res_mbbrc_mb_qp_data_surface);
1118     i965_free_gpe_resource(&avc_ctx->res_mb_qp_data_surface);
1119     i965_free_gpe_resource(&avc_ctx->res_mbbrc_const_data_buffer);
1120     i965_free_gpe_resource(&avc_ctx->res_mbenc_slice_map_surface);
1121     i965_free_gpe_resource(&avc_ctx->res_sfd_output_buffer);
1122     i965_free_gpe_resource(&avc_ctx->res_sfd_cost_table_p_frame_buffer);
1123     i965_free_gpe_resource(&avc_ctx->res_sfd_cost_table_b_frame_buffer);
1124     i965_free_gpe_resource(&avc_ctx->res_wp_output_pic_select_surface_list[0]);
1125     i965_free_gpe_resource(&avc_ctx->res_wp_output_pic_select_surface_list[1]);
1126     i965_free_gpe_resource(&avc_ctx->res_mad_data_buffer);
1127
1128     for(i = 0;i < 2 ; i++)
1129     {
1130         if (avc_ctx->wp_output_pic_select_surface_obj[i]) {
1131             i965_DestroySurfaces(ctx, &avc_ctx->wp_output_pic_select_surface_id[i], 1);
1132             avc_ctx->wp_output_pic_select_surface_id[i] = VA_INVALID_SURFACE;
1133             avc_ctx->wp_output_pic_select_surface_obj[i] = NULL;
1134         }
1135     }
1136
1137 }
1138
1139 static void
1140 gen9_avc_run_kernel_media_object(VADriverContextP ctx,
1141                              struct intel_encoder_context *encoder_context,
1142                              struct i965_gpe_context *gpe_context,
1143                              int media_function,
1144                              struct gpe_media_object_parameter *param)
1145 {
1146     struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
1147     struct i965_avc_encoder_context * avc_ctx = (struct i965_avc_encoder_context * )vme_context->private_enc_ctx;
1148
1149     struct intel_batchbuffer *batch = encoder_context->base.batch;
1150     struct encoder_status_buffer_internal *status_buffer;
1151     struct gpe_mi_store_data_imm_parameter mi_store_data_imm;
1152
1153     if (!batch)
1154         return;
1155
1156     intel_batchbuffer_start_atomic(batch, 0x1000);
1157     intel_batchbuffer_emit_mi_flush(batch);
1158
1159     status_buffer = &(avc_ctx->status_buffer);
1160     memset(&mi_store_data_imm, 0, sizeof(mi_store_data_imm));
1161     mi_store_data_imm.bo = status_buffer->bo;
1162     mi_store_data_imm.offset = status_buffer->media_index_offset;
1163     mi_store_data_imm.dw0 = media_function;
1164     gen8_gpe_mi_store_data_imm(ctx, batch, &mi_store_data_imm);
1165
1166     gen9_gpe_pipeline_setup(ctx, gpe_context, batch);
1167     gen8_gpe_media_object(ctx, gpe_context, batch, param);
1168     gen8_gpe_media_state_flush(ctx, gpe_context, batch);
1169
1170     gen9_gpe_pipeline_end(ctx, gpe_context, batch);
1171
1172     intel_batchbuffer_end_atomic(batch);
1173
1174     intel_batchbuffer_flush(batch);
1175 }
1176
1177 static void
1178 gen9_avc_run_kernel_media_object_walker(VADriverContextP ctx,
1179                                     struct intel_encoder_context *encoder_context,
1180                                     struct i965_gpe_context *gpe_context,
1181                                     int media_function,
1182                                     struct gpe_media_object_walker_parameter *param)
1183 {
1184     struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
1185     struct i965_avc_encoder_context * avc_ctx = (struct i965_avc_encoder_context * )vme_context->private_enc_ctx;
1186
1187     struct intel_batchbuffer *batch = encoder_context->base.batch;
1188     struct encoder_status_buffer_internal *status_buffer;
1189     struct gpe_mi_store_data_imm_parameter mi_store_data_imm;
1190
1191     if (!batch)
1192         return;
1193
1194     intel_batchbuffer_start_atomic(batch, 0x1000);
1195
1196     intel_batchbuffer_emit_mi_flush(batch);
1197
1198     status_buffer = &(avc_ctx->status_buffer);
1199     memset(&mi_store_data_imm, 0, sizeof(mi_store_data_imm));
1200     mi_store_data_imm.bo = status_buffer->bo;
1201     mi_store_data_imm.offset = status_buffer->media_index_offset;
1202     mi_store_data_imm.dw0 = media_function;
1203     gen8_gpe_mi_store_data_imm(ctx, batch, &mi_store_data_imm);
1204
1205     gen9_gpe_pipeline_setup(ctx, gpe_context, batch);
1206     gen8_gpe_media_object_walker(ctx, gpe_context, batch, param);
1207     gen8_gpe_media_state_flush(ctx, gpe_context, batch);
1208
1209     gen9_gpe_pipeline_end(ctx, gpe_context, batch);
1210
1211     intel_batchbuffer_end_atomic(batch);
1212
1213     intel_batchbuffer_flush(batch);
1214 }
1215
1216 static void
1217 gen9_init_gpe_context_avc(VADriverContextP ctx,
1218                           struct i965_gpe_context *gpe_context,
1219                           struct encoder_kernel_parameter *kernel_param)
1220 {
1221     struct i965_driver_data *i965 = i965_driver_data(ctx);
1222
1223     gpe_context->curbe.length = kernel_param->curbe_size; // in bytes
1224
1225     gpe_context->sampler.entry_size = 0;
1226     gpe_context->sampler.max_entries = 0;
1227
1228     if (kernel_param->sampler_size) {
1229         gpe_context->sampler.entry_size = ALIGN(kernel_param->sampler_size, 64);
1230         gpe_context->sampler.max_entries = 1;
1231     }
1232
1233     gpe_context->idrt.entry_size = ALIGN(sizeof(struct gen8_interface_descriptor_data), 64); // 8 dws, 1 register
1234     gpe_context->idrt.max_entries = NUM_KERNELS_PER_GPE_CONTEXT;
1235
1236     gpe_context->surface_state_binding_table.max_entries = MAX_AVC_ENCODER_SURFACES;
1237     gpe_context->surface_state_binding_table.binding_table_offset = 0;
1238     gpe_context->surface_state_binding_table.surface_state_offset = ALIGN(MAX_AVC_ENCODER_SURFACES * 4, 64);
1239     gpe_context->surface_state_binding_table.length = ALIGN(MAX_AVC_ENCODER_SURFACES * 4, 64) + ALIGN(MAX_AVC_ENCODER_SURFACES * SURFACE_STATE_PADDED_SIZE_GEN9, 64);
1240
1241     if (i965->intel.eu_total > 0)
1242         gpe_context->vfe_state.max_num_threads = 6 * i965->intel.eu_total;
1243     else
1244         gpe_context->vfe_state.max_num_threads = 112; // 16 EU * 7 threads
1245
1246     gpe_context->vfe_state.curbe_allocation_size = MAX(1, ALIGN(gpe_context->curbe.length, 32) >> 5); // in registers
1247     gpe_context->vfe_state.urb_entry_size = MAX(1, ALIGN(kernel_param->inline_data_size, 32) >> 5); // in registers
1248     gpe_context->vfe_state.num_urb_entries = (MAX_URB_SIZE -
1249                                               gpe_context->vfe_state.curbe_allocation_size -
1250                                               ((gpe_context->idrt.entry_size >> 5) *
1251                                                gpe_context->idrt.max_entries)) / gpe_context->vfe_state.urb_entry_size;
1252     gpe_context->vfe_state.num_urb_entries = CLAMP(1, 127, gpe_context->vfe_state.num_urb_entries);
1253     gpe_context->vfe_state.gpgpu_mode = 0;
1254 }
1255
1256 static void
1257 gen9_init_vfe_scoreboard_avc(struct i965_gpe_context *gpe_context,
1258                              struct encoder_scoreboard_parameter *scoreboard_param)
1259 {
1260     gpe_context->vfe_desc5.scoreboard0.mask = scoreboard_param->mask;
1261     gpe_context->vfe_desc5.scoreboard0.type = scoreboard_param->type;
1262     gpe_context->vfe_desc5.scoreboard0.enable = scoreboard_param->enable;
1263
1264     if (scoreboard_param->walkpat_flag) {
1265         gpe_context->vfe_desc5.scoreboard0.mask = 0x0F;
1266         gpe_context->vfe_desc5.scoreboard0.type = 1;
1267
1268         gpe_context->vfe_desc6.scoreboard1.delta_x0 = 0x0;
1269         gpe_context->vfe_desc6.scoreboard1.delta_y0 = 0xF;
1270
1271         gpe_context->vfe_desc6.scoreboard1.delta_x1 = 0x0;
1272         gpe_context->vfe_desc6.scoreboard1.delta_y1 = 0xE;
1273
1274         gpe_context->vfe_desc6.scoreboard1.delta_x2 = 0xF;
1275         gpe_context->vfe_desc6.scoreboard1.delta_y2 = 0x3;
1276
1277         gpe_context->vfe_desc6.scoreboard1.delta_x3 = 0xF;
1278         gpe_context->vfe_desc6.scoreboard1.delta_y3 = 0x1;
1279     } else {
1280         // Scoreboard 0
1281         gpe_context->vfe_desc6.scoreboard1.delta_x0 = 0xF;
1282         gpe_context->vfe_desc6.scoreboard1.delta_y0 = 0x0;
1283
1284         // Scoreboard 1
1285         gpe_context->vfe_desc6.scoreboard1.delta_x1 = 0x0;
1286         gpe_context->vfe_desc6.scoreboard1.delta_y1 = 0xF;
1287
1288         // Scoreboard 2
1289         gpe_context->vfe_desc6.scoreboard1.delta_x2 = 0x1;
1290         gpe_context->vfe_desc6.scoreboard1.delta_y2 = 0xF;
1291
1292         // Scoreboard 3
1293         gpe_context->vfe_desc6.scoreboard1.delta_x3 = 0xF;
1294         gpe_context->vfe_desc6.scoreboard1.delta_y3 = 0xF;
1295
1296         // Scoreboard 4
1297         gpe_context->vfe_desc7.scoreboard2.delta_x4 = 0xF;
1298         gpe_context->vfe_desc7.scoreboard2.delta_y4 = 0x1;
1299
1300         // Scoreboard 5
1301         gpe_context->vfe_desc7.scoreboard2.delta_x5 = 0x0;
1302         gpe_context->vfe_desc7.scoreboard2.delta_y5 = 0xE;
1303
1304         // Scoreboard 6
1305         gpe_context->vfe_desc7.scoreboard2.delta_x6 = 0x1;
1306         gpe_context->vfe_desc7.scoreboard2.delta_y6 = 0xE;
1307
1308         // Scoreboard 7
1309         gpe_context->vfe_desc7.scoreboard2.delta_x6 = 0xF;
1310         gpe_context->vfe_desc7.scoreboard2.delta_y6 = 0xE;
1311     }
1312 }
1313 /*
1314 VME pipeline related function
1315 */
1316
1317 /*
1318 scaling kernel related function
1319 */
1320 static void
1321 gen9_avc_set_curbe_scaling4x(VADriverContextP ctx,
1322                            struct encode_state *encode_state,
1323                            struct i965_gpe_context *gpe_context,
1324                            struct intel_encoder_context *encoder_context,
1325                            void *param)
1326 {
1327     gen9_avc_scaling4x_curbe_data *curbe_cmd;
1328     struct scaling_param *surface_param = (struct scaling_param *)param;
1329
1330     curbe_cmd = i965_gpe_context_map_curbe(gpe_context);
1331
1332     if (!curbe_cmd)
1333         return;
1334
1335     memset(curbe_cmd, 0, sizeof(gen9_avc_scaling4x_curbe_data));
1336
1337     curbe_cmd->dw0.input_picture_width  = surface_param->input_frame_width;
1338     curbe_cmd->dw0.input_picture_height = surface_param->input_frame_height;
1339
1340     curbe_cmd->dw1.input_y_bti = GEN9_AVC_SCALING_FRAME_SRC_Y_INDEX;
1341     curbe_cmd->dw2.output_y_bti = GEN9_AVC_SCALING_FRAME_DST_Y_INDEX;
1342
1343
1344     curbe_cmd->dw5.flatness_threshold = 128;
1345     curbe_cmd->dw6.enable_mb_flatness_check = surface_param->enable_mb_flatness_check;
1346     curbe_cmd->dw7.enable_mb_variance_output = surface_param->enable_mb_variance_output;
1347     curbe_cmd->dw8.enable_mb_pixel_average_output = surface_param->enable_mb_pixel_average_output;
1348
1349     if (curbe_cmd->dw6.enable_mb_flatness_check ||
1350         curbe_cmd->dw7.enable_mb_variance_output ||
1351         curbe_cmd->dw8.enable_mb_pixel_average_output)
1352     {
1353         curbe_cmd->dw10.mbv_proc_stat_bti = GEN9_AVC_SCALING_FRAME_MBVPROCSTATS_DST_INDEX;
1354     }
1355
1356     i965_gpe_context_unmap_curbe(gpe_context);
1357     return;
1358 }
1359
1360 static void
1361 gen9_avc_set_curbe_scaling2x(VADriverContextP ctx,
1362                            struct encode_state *encode_state,
1363                            struct i965_gpe_context *gpe_context,
1364                            struct intel_encoder_context *encoder_context,
1365                            void *param)
1366 {
1367     gen9_avc_scaling2x_curbe_data *curbe_cmd;
1368     struct scaling_param *surface_param = (struct scaling_param *)param;
1369
1370     curbe_cmd = i965_gpe_context_map_curbe(gpe_context);
1371
1372     if (!curbe_cmd)
1373         return;
1374
1375     memset(curbe_cmd, 0, sizeof(gen9_avc_scaling2x_curbe_data));
1376
1377     curbe_cmd->dw0.input_picture_width  = surface_param->input_frame_width;
1378     curbe_cmd->dw0.input_picture_height = surface_param->input_frame_height;
1379
1380     curbe_cmd->dw8.input_y_bti = GEN9_AVC_SCALING_FRAME_SRC_Y_INDEX;
1381     curbe_cmd->dw9.output_y_bti = GEN9_AVC_SCALING_FRAME_DST_Y_INDEX;
1382
1383     i965_gpe_context_unmap_curbe(gpe_context);
1384     return;
1385 }
1386
1387 static void
1388 gen9_avc_send_surface_scaling(VADriverContextP ctx,
1389                               struct encode_state *encode_state,
1390                               struct i965_gpe_context *gpe_context,
1391                               struct intel_encoder_context *encoder_context,
1392                               void *param)
1393 {
1394     struct scaling_param *surface_param = (struct scaling_param *)param;
1395     unsigned int surface_format;
1396     unsigned int res_size;
1397
1398     if (surface_param->scaling_out_use_32unorm_surf_fmt)
1399         surface_format = I965_SURFACEFORMAT_R32_UNORM;
1400     else if (surface_param->scaling_out_use_16unorm_surf_fmt)
1401         surface_format = I965_SURFACEFORMAT_R16_UNORM;
1402     else
1403         surface_format = I965_SURFACEFORMAT_R8_UNORM;
1404
1405     gen9_add_2d_gpe_surface(ctx, gpe_context,
1406                             surface_param->input_surface,
1407                             0, 1, surface_format,
1408                             GEN9_AVC_SCALING_FRAME_SRC_Y_INDEX);
1409
1410     gen9_add_2d_gpe_surface(ctx, gpe_context,
1411                             surface_param->output_surface,
1412                             0, 1, surface_format,
1413                             GEN9_AVC_SCALING_FRAME_DST_Y_INDEX);
1414
1415     /*add buffer mv_proc_stat, here need change*/
1416     if (surface_param->mbv_proc_stat_enabled)
1417     {
1418         res_size = 16 * (surface_param->input_frame_width/16) * (surface_param->input_frame_height/16) * sizeof(unsigned int);
1419
1420         gen9_add_buffer_gpe_surface(ctx,
1421                                     gpe_context,
1422                                     surface_param->pres_mbv_proc_stat_buffer,
1423                                     0,
1424                                     res_size/4,
1425                                     0,
1426                                     GEN9_AVC_SCALING_FRAME_MBVPROCSTATS_DST_INDEX);
1427     }else if(surface_param->enable_mb_flatness_check)
1428     {
1429         gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
1430                                        surface_param->pres_flatness_check_surface,
1431                                        1,
1432                                        I965_SURFACEFORMAT_R8_UNORM,
1433                                        GEN9_AVC_SCALING_FRAME_MBVPROCSTATS_DST_INDEX);
1434     }
1435
1436     return;
1437 }
1438
1439 static VAStatus
1440 gen9_avc_kernel_scaling(VADriverContextP ctx,
1441                         struct encode_state *encode_state,
1442                         struct intel_encoder_context *encoder_context,
1443                         int hme_type)
1444 {
1445     struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
1446     struct i965_avc_encoder_context * avc_ctx = (struct i965_avc_encoder_context * )vme_context->private_enc_ctx;
1447     struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
1448     struct avc_enc_state * avc_state = (struct avc_enc_state * )vme_context->private_enc_state;
1449     struct generic_encoder_context * generic_ctx = (struct generic_encoder_context * )vme_context->generic_enc_ctx;
1450
1451     struct i965_gpe_context *gpe_context;
1452     struct scaling_param surface_param;
1453     struct object_surface *obj_surface;
1454     struct gen9_surface_avc *avc_priv_surface;
1455     struct gpe_media_object_walker_parameter media_object_walker_param;
1456     struct gpe_encoder_kernel_walker_parameter kernel_walker_param;
1457     unsigned int downscaled_width_in_mb, downscaled_height_in_mb;
1458     int media_function = 0;
1459     int kernel_idx = 0;
1460
1461     obj_surface = encode_state->reconstructed_object;
1462     avc_priv_surface = obj_surface->private_data;
1463
1464     memset(&surface_param,0,sizeof(struct scaling_param));
1465     switch(hme_type)
1466     {
1467     case INTEL_ENC_HME_4x :
1468         {
1469             media_function = INTEL_MEDIA_STATE_4X_SCALING;
1470             kernel_idx = GEN9_AVC_KERNEL_SCALING_4X_IDX;
1471             downscaled_width_in_mb = generic_state->downscaled_width_4x_in_mb;
1472             downscaled_height_in_mb = generic_state->downscaled_height_4x_in_mb;
1473
1474             surface_param.input_surface = encode_state->input_yuv_object ;
1475             surface_param.input_frame_width = generic_state->frame_width_in_pixel ;
1476             surface_param.input_frame_height = generic_state->frame_height_in_pixel ;
1477
1478             surface_param.output_surface = avc_priv_surface->scaled_4x_surface_obj ;
1479             surface_param.output_frame_width = generic_state->frame_width_4x ;
1480             surface_param.output_frame_height = generic_state->frame_height_4x ;
1481
1482             surface_param.enable_mb_flatness_check = avc_state->flatness_check_enable;
1483             surface_param.enable_mb_variance_output = avc_state->mb_status_enable;
1484             surface_param.enable_mb_pixel_average_output = avc_state->mb_status_enable;
1485
1486             surface_param.blk8x8_stat_enabled = 0 ;
1487             surface_param.use_4x_scaling  = 1 ;
1488             surface_param.use_16x_scaling = 0 ;
1489             surface_param.use_32x_scaling = 0 ;
1490             break;
1491         }
1492     case INTEL_ENC_HME_16x :
1493         {
1494             media_function = INTEL_MEDIA_STATE_16X_SCALING;
1495             kernel_idx = GEN9_AVC_KERNEL_SCALING_4X_IDX;
1496             downscaled_width_in_mb = generic_state->downscaled_width_16x_in_mb;
1497             downscaled_height_in_mb = generic_state->downscaled_height_16x_in_mb;
1498
1499             surface_param.input_surface = avc_priv_surface->scaled_4x_surface_obj ;
1500             surface_param.input_frame_width = generic_state->frame_width_4x ;
1501             surface_param.input_frame_height = generic_state->frame_height_4x ;
1502
1503             surface_param.output_surface = avc_priv_surface->scaled_16x_surface_obj ;
1504             surface_param.output_frame_width = generic_state->frame_width_16x ;
1505             surface_param.output_frame_height = generic_state->frame_height_16x ;
1506
1507             surface_param.enable_mb_flatness_check = 0 ;
1508             surface_param.enable_mb_variance_output = 0 ;
1509             surface_param.enable_mb_pixel_average_output = 0 ;
1510
1511             surface_param.blk8x8_stat_enabled = 0 ;
1512             surface_param.use_4x_scaling  = 0 ;
1513             surface_param.use_16x_scaling = 1 ;
1514             surface_param.use_32x_scaling = 0 ;
1515
1516             break;
1517         }
1518     case INTEL_ENC_HME_32x :
1519         {
1520             media_function = INTEL_MEDIA_STATE_32X_SCALING;
1521             kernel_idx = GEN9_AVC_KERNEL_SCALING_2X_IDX;
1522             downscaled_width_in_mb = generic_state->downscaled_width_32x_in_mb;
1523             downscaled_height_in_mb = generic_state->downscaled_height_32x_in_mb;
1524
1525             surface_param.input_surface = avc_priv_surface->scaled_16x_surface_obj ;
1526             surface_param.input_frame_width = generic_state->frame_width_16x ;
1527             surface_param.input_frame_height = generic_state->frame_height_16x ;
1528
1529             surface_param.output_surface = avc_priv_surface->scaled_32x_surface_obj ;
1530             surface_param.output_frame_width = generic_state->frame_width_32x ;
1531             surface_param.output_frame_height = generic_state->frame_height_32x ;
1532
1533             surface_param.enable_mb_flatness_check = 0 ;
1534             surface_param.enable_mb_variance_output = 0 ;
1535             surface_param.enable_mb_pixel_average_output = 0 ;
1536
1537             surface_param.blk8x8_stat_enabled = 0 ;
1538             surface_param.use_4x_scaling  = 0 ;
1539             surface_param.use_16x_scaling = 0 ;
1540             surface_param.use_32x_scaling = 1 ;
1541             break;
1542         }
1543     default :
1544         assert(0);
1545
1546     }
1547
1548     gpe_context = &(avc_ctx->context_scaling.gpe_contexts[kernel_idx]);
1549
1550     gen8_gpe_context_init(ctx, gpe_context);
1551     gen9_gpe_reset_binding_table(ctx, gpe_context);
1552
1553     if(surface_param.use_32x_scaling)
1554     {
1555         generic_ctx->pfn_set_curbe_scaling2x(ctx,encode_state,gpe_context,encoder_context,&surface_param);
1556     }else
1557     {
1558         generic_ctx->pfn_set_curbe_scaling4x(ctx,encode_state,gpe_context,encoder_context,&surface_param);
1559     }
1560
1561     if(surface_param.use_32x_scaling)
1562     {
1563         surface_param.scaling_out_use_16unorm_surf_fmt = 1 ;
1564         surface_param.scaling_out_use_32unorm_surf_fmt = 0 ;
1565     }else
1566     {
1567         surface_param.scaling_out_use_16unorm_surf_fmt = 0 ;
1568         surface_param.scaling_out_use_32unorm_surf_fmt = 1 ;
1569     }
1570
1571     if(surface_param.use_4x_scaling)
1572     {
1573         if(avc_state->mb_status_supported)
1574         {
1575             surface_param.enable_mb_flatness_check = 0;
1576             surface_param.mbv_proc_stat_enabled = (surface_param.use_4x_scaling)?(avc_state->mb_status_enable || avc_state->flatness_check_enable):0 ;
1577             surface_param.pres_mbv_proc_stat_buffer = &(avc_ctx->res_mb_status_buffer);
1578
1579         }else
1580         {
1581             surface_param.enable_mb_flatness_check = (surface_param.use_4x_scaling)?avc_state->flatness_check_enable:0;
1582             surface_param.mbv_proc_stat_enabled = 0 ;
1583             surface_param.pres_flatness_check_surface = &(avc_ctx->res_flatness_check_surface);
1584         }
1585     }
1586
1587     generic_ctx->pfn_send_scaling_surface(ctx,encode_state,gpe_context,encoder_context,&surface_param);
1588
1589     /* setup the interface data */
1590     gen8_gpe_setup_interface_data(ctx, gpe_context);
1591
1592     memset(&kernel_walker_param, 0, sizeof(kernel_walker_param));
1593     if(surface_param.use_32x_scaling)
1594     {
1595         kernel_walker_param.resolution_x = downscaled_width_in_mb ;
1596         kernel_walker_param.resolution_y = downscaled_height_in_mb ;
1597     }else
1598     {
1599         /* the scaling is based on 8x8 blk level */
1600         kernel_walker_param.resolution_x = downscaled_width_in_mb * 2;
1601         kernel_walker_param.resolution_y = downscaled_height_in_mb * 2;
1602     }
1603     kernel_walker_param.no_dependency = 1;
1604
1605     i965_init_media_object_walker_parameter(&kernel_walker_param, &media_object_walker_param);
1606
1607     gen9_avc_run_kernel_media_object_walker(ctx, encoder_context,
1608                                         gpe_context,
1609                                         media_function,
1610                                         &media_object_walker_param);
1611
1612     return VA_STATUS_SUCCESS;
1613 }
1614
1615 /*
1616 frame/mb brc related function
1617 */
1618 static void
1619 gen9_avc_init_mfx_avc_img_state(VADriverContextP ctx,
1620                                 struct encode_state *encode_state,
1621                                 struct intel_encoder_context *encoder_context,
1622                                 struct gen9_mfx_avc_img_state *pstate)
1623 {
1624     struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
1625     struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
1626     struct avc_enc_state * avc_state = (struct avc_enc_state * )vme_context->private_enc_state;
1627
1628     VAEncSequenceParameterBufferH264 *seq_param = avc_state->seq_param;
1629     VAEncPictureParameterBufferH264  *pic_param = avc_state->pic_param;
1630
1631     memset(pstate, 0, sizeof(*pstate));
1632
1633     pstate->dw0.dword_length = (sizeof(struct gen9_mfx_avc_img_state)) / 4 -2;
1634     pstate->dw0.sub_opcode_b = 0;
1635     pstate->dw0.sub_opcode_a = 0;
1636     pstate->dw0.command_opcode = 1;
1637     pstate->dw0.pipeline = 2;
1638     pstate->dw0.command_type = 3;
1639
1640     pstate->dw1.frame_size_in_mbs = generic_state->frame_width_in_mbs * generic_state->frame_height_in_mbs ;
1641
1642     pstate->dw2.frame_width_in_mbs_minus1 = generic_state->frame_width_in_mbs - 1;
1643     pstate->dw2.frame_height_in_mbs_minus1 = generic_state->frame_height_in_mbs - 1;
1644
1645     pstate->dw3.image_structure = 0;//frame is zero
1646     pstate->dw3.weighted_bipred_idc = pic_param->pic_fields.bits.weighted_bipred_idc;
1647     pstate->dw3.weighted_pred_flag = pic_param->pic_fields.bits.weighted_pred_flag;
1648     pstate->dw3.brc_domain_rate_control_enable = 0;//0,set for non-vdenc mode;
1649     pstate->dw3.chroma_qp_offset = pic_param->chroma_qp_index_offset;
1650     pstate->dw3.second_chroma_qp_offset = pic_param->second_chroma_qp_index_offset;
1651
1652     pstate->dw4.field_picture_flag = 0;
1653     pstate->dw4.mbaff_mode_active = seq_param->seq_fields.bits.mb_adaptive_frame_field_flag;
1654     pstate->dw4.frame_mb_only_flag = seq_param->seq_fields.bits.frame_mbs_only_flag;
1655     pstate->dw4.transform_8x8_idct_mode_flag = pic_param->pic_fields.bits.transform_8x8_mode_flag;
1656     pstate->dw4.direct_8x8_interface_flag = seq_param->seq_fields.bits.direct_8x8_inference_flag;
1657     pstate->dw4.constrained_intra_prediction_flag = pic_param->pic_fields.bits.constrained_intra_pred_flag;
1658     pstate->dw4.entropy_coding_flag = pic_param->pic_fields.bits.entropy_coding_mode_flag;
1659     pstate->dw4.mb_mv_format_flag = 1;
1660     pstate->dw4.chroma_format_idc = seq_param->seq_fields.bits.chroma_format_idc;
1661     pstate->dw4.mv_unpacked_flag = 1;
1662     pstate->dw4.insert_test_flag = 0;
1663     pstate->dw4.load_slice_pointer_flag = 0;
1664     pstate->dw4.macroblock_stat_enable = 0;        /* disable in the first pass */
1665     pstate->dw4.minimum_frame_size = 0;
1666     pstate->dw5.intra_mb_max_bit_flag = 1;
1667     pstate->dw5.inter_mb_max_bit_flag = 1;
1668     pstate->dw5.frame_size_over_flag = 1;
1669     pstate->dw5.frame_size_under_flag = 1;
1670     pstate->dw5.intra_mb_ipcm_flag = 1;
1671     pstate->dw5.mb_rate_ctrl_flag = 0;
1672     pstate->dw5.non_first_pass_flag = 0;
1673     pstate->dw5.aq_enable = pstate->dw5.aq_rounding = 0;
1674     pstate->dw5.aq_chroma_disable = 1;
1675     if(pstate->dw4.entropy_coding_flag && (avc_state->tq_enable))
1676     {
1677         pstate->dw5.aq_enable = avc_state->tq_enable;
1678         pstate->dw5.aq_rounding = avc_state->tq_rounding;
1679     }else
1680     {
1681         pstate->dw5.aq_rounding = 0;
1682     }
1683
1684     pstate->dw6.intra_mb_max_size = 2700;
1685     pstate->dw6.inter_mb_max_size = 4095;
1686
1687     pstate->dw8.slice_delta_qp_max0 = 0;
1688     pstate->dw8.slice_delta_qp_max1 = 0;
1689     pstate->dw8.slice_delta_qp_max2 = 0;
1690     pstate->dw8.slice_delta_qp_max3 = 0;
1691
1692     pstate->dw9.slice_delta_qp_min0 = 0;
1693     pstate->dw9.slice_delta_qp_min1 = 0;
1694     pstate->dw9.slice_delta_qp_min2 = 0;
1695     pstate->dw9.slice_delta_qp_min3 = 0;
1696
1697     pstate->dw10.frame_bitrate_min = 0;
1698     pstate->dw10.frame_bitrate_min_unit = 1;
1699     pstate->dw10.frame_bitrate_min_unit_mode = 1;
1700     pstate->dw10.frame_bitrate_max = (1 << 14) - 1;
1701     pstate->dw10.frame_bitrate_max_unit = 1;
1702     pstate->dw10.frame_bitrate_max_unit_mode = 1;
1703
1704     pstate->dw11.frame_bitrate_min_delta = 0;
1705     pstate->dw11.frame_bitrate_max_delta = 0;
1706
1707     pstate->dw12.vad_error_logic = 1;
1708     /* set paramters DW19/DW20 for slices */
1709 }
1710
1711 void gen9_avc_set_image_state(VADriverContextP ctx,
1712                               struct encode_state *encode_state,
1713                               struct intel_encoder_context *encoder_context,
1714                               struct i965_gpe_resource *gpe_resource)
1715 {
1716     struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
1717     struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )pak_context->generic_enc_state;
1718     char *pdata;
1719     int i;
1720     unsigned int * data;
1721     struct gen9_mfx_avc_img_state cmd;
1722
1723     pdata = i965_map_gpe_resource(gpe_resource);
1724
1725     if (!pdata)
1726         return;
1727
1728     gen9_avc_init_mfx_avc_img_state(ctx,encode_state,encoder_context,&cmd);
1729     for(i = 0; i < generic_state->num_pak_passes;i++)
1730     {
1731
1732         if(i == 0)
1733         {
1734             cmd.dw4.macroblock_stat_enable = 0;
1735             cmd.dw5.non_first_pass_flag = 0;
1736         }else
1737         {
1738             cmd.dw4.macroblock_stat_enable = 1;
1739             cmd.dw5.non_first_pass_flag = 1;
1740             cmd.dw5.intra_mb_ipcm_flag = 1;
1741
1742         }
1743          cmd.dw5.mb_rate_ctrl_flag = 0;
1744          memcpy(pdata,&cmd,sizeof(struct gen9_mfx_avc_img_state));
1745          data = (unsigned int *)(pdata + sizeof(struct gen9_mfx_avc_img_state));
1746         *data = MI_BATCH_BUFFER_END;
1747
1748          pdata += INTEL_AVC_IMAGE_STATE_CMD_SIZE;
1749     }
1750     i965_unmap_gpe_resource(gpe_resource);
1751     return;
1752 }
1753
1754 void gen9_avc_set_image_state_non_brc(VADriverContextP ctx,
1755                                       struct encode_state *encode_state,
1756                                       struct intel_encoder_context *encoder_context,
1757                                       struct i965_gpe_resource *gpe_resource)
1758 {
1759     struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
1760     struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )pak_context->generic_enc_state;
1761     char *pdata;
1762
1763     unsigned int * data;
1764     struct gen9_mfx_avc_img_state cmd;
1765
1766     pdata = i965_map_gpe_resource(gpe_resource);
1767
1768     if (!pdata)
1769         return;
1770
1771     gen9_avc_init_mfx_avc_img_state(ctx,encode_state,encoder_context,&cmd);
1772
1773     if(generic_state->curr_pak_pass == 0)
1774     {
1775         cmd.dw4.macroblock_stat_enable = 0;
1776         cmd.dw5.non_first_pass_flag = 0;
1777
1778     }
1779     else
1780     {
1781         cmd.dw4.macroblock_stat_enable = 1;
1782         cmd.dw5.non_first_pass_flag = 0;
1783         cmd.dw5.intra_mb_ipcm_flag = 1;
1784     }
1785
1786     cmd.dw5.mb_rate_ctrl_flag = 0;
1787     memcpy(pdata,&cmd,sizeof(struct gen9_mfx_avc_img_state));
1788     data = (unsigned int *)(pdata + sizeof(struct gen9_mfx_avc_img_state));
1789     *data = MI_BATCH_BUFFER_END;
1790
1791     i965_unmap_gpe_resource(gpe_resource);
1792     return;
1793 }
1794
1795 static void
1796 gen9_avc_init_brc_const_data(VADriverContextP ctx,
1797                              struct encode_state *encode_state,
1798                              struct intel_encoder_context *encoder_context)
1799 {
1800     struct i965_driver_data *i965 = i965_driver_data(ctx);
1801     struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
1802     struct i965_avc_encoder_context * avc_ctx = (struct i965_avc_encoder_context * )vme_context->private_enc_ctx;
1803     struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
1804     struct avc_enc_state * avc_state = (struct avc_enc_state * )vme_context->private_enc_state;
1805
1806     struct i965_gpe_resource *gpe_resource = NULL;
1807     unsigned char * data =NULL;
1808     unsigned char * data_tmp = NULL;
1809     unsigned int size = 0;
1810     unsigned int table_idx = 0;
1811     unsigned int block_based_skip_enable = avc_state->block_based_skip_enable;
1812     int i = 0;
1813
1814     struct object_surface *obj_surface;
1815     VAEncPictureParameterBufferH264  *pic_param = avc_state->pic_param;
1816     VAEncSliceParameterBufferH264 * slice_param = avc_state->slice_param[0];
1817     VASurfaceID surface_id;
1818     unsigned int transform_8x8_mode_flag = pic_param->pic_fields.bits.transform_8x8_mode_flag;
1819
1820     gpe_resource = &(avc_ctx->res_brc_const_data_buffer);
1821     assert(gpe_resource);
1822
1823     i965_zero_gpe_resource(gpe_resource);
1824
1825     data = i965_map_gpe_resource(gpe_resource);
1826     assert(data);
1827
1828     table_idx = slice_type_kernel[generic_state->frame_type];
1829
1830     /* Fill surface with QP Adjustment table, Distortion threshold table, MaxFrame threshold table, Distortion QP Adjustment Table*/
1831     size = sizeof(gen9_avc_qp_adjustment_dist_threshold_max_frame_threshold_dist_qp_adjustment_ipb);
1832     memcpy(data,gen9_avc_qp_adjustment_dist_threshold_max_frame_threshold_dist_qp_adjustment_ipb,size*sizeof(unsigned char));
1833
1834     data += size;
1835
1836     /* skip threshold table*/
1837     size = 128;
1838     switch(generic_state->frame_type)
1839     {
1840     case SLICE_TYPE_P:
1841         memcpy(data,gen9_avc_skip_value_p[block_based_skip_enable][transform_8x8_mode_flag],size * sizeof(unsigned char));
1842         break;
1843     case SLICE_TYPE_B:
1844         memcpy(data,gen9_avc_skip_value_b[block_based_skip_enable][transform_8x8_mode_flag],size * sizeof(unsigned char));
1845         break;
1846     default:
1847         /*SLICE_TYPE_I,no change */
1848         break;
1849     }
1850
1851     if((generic_state->frame_type != SLICE_TYPE_I) && avc_state->non_ftq_skip_threshold_lut_input_enable)
1852     {
1853         for(i = 0; i< 52 ; i++)
1854         {
1855             *(data + 1 + (i * 2)) = (unsigned char)i965_avc_calc_skip_value(block_based_skip_enable,transform_8x8_mode_flag,avc_state->non_ftq_skip_threshold_lut[i]);
1856         }
1857     }
1858     data += size;
1859
1860     /*fill the qp for ref list*/
1861     size = 32 + 32 +32 +160;
1862     memset(data,0xff,32);
1863     memset(data+32+32,0xff,32);
1864     switch(generic_state->frame_type)
1865     {
1866     case SLICE_TYPE_P:
1867         {
1868             for(i = 0 ; i <  slice_param->num_ref_idx_l0_active_minus1 + 1; i++)
1869             {
1870                surface_id = slice_param->RefPicList0[i].picture_id;
1871                obj_surface = SURFACE(surface_id);
1872                if (!obj_surface)
1873                    break;
1874                *(data + i) = avc_state->list_ref_idx[0][i];//?
1875             }
1876         }
1877         break;
1878     case SLICE_TYPE_B:
1879         {
1880             data = data + 32 + 32;
1881             for(i = 0 ; i <  slice_param->num_ref_idx_l1_active_minus1 + 1; i++)
1882             {
1883                surface_id = slice_param->RefPicList1[i].picture_id;
1884                obj_surface = SURFACE(surface_id);
1885                if (!obj_surface)
1886                    break;
1887                *(data + i) = avc_state->list_ref_idx[1][i];//?
1888             }
1889
1890             data = data - 32 - 32;
1891
1892             for(i = 0 ; i <  slice_param->num_ref_idx_l0_active_minus1 + 1; i++)
1893             {
1894                surface_id = slice_param->RefPicList0[i].picture_id;
1895                obj_surface = SURFACE(surface_id);
1896                if (!obj_surface)
1897                    break;
1898                *(data + i) = avc_state->list_ref_idx[0][i];//?
1899             }
1900         }
1901         break;
1902     default:
1903         /*SLICE_TYPE_I,no change */
1904         break;
1905     }
1906     data += size;
1907
1908     /*mv cost and mode cost*/
1909     size = 1664;
1910     memcpy(data,(unsigned char *)&gen9_avc_mode_mv_cost_table[table_idx][0][0],size * sizeof(unsigned char));
1911
1912     if(avc_state->old_mode_cost_enable)
1913     {   data_tmp = data;
1914         for(i = 0; i < 52 ; i++)
1915         {
1916             *(data_tmp +3) = (unsigned int)gen9_avc_old_intra_mode_cost[i];
1917             data_tmp += 16;
1918         }
1919     }
1920
1921     if(avc_state->ftq_skip_threshold_lut_input_enable)
1922     {
1923         for(i = 0; i < 52 ; i++)
1924         {
1925             *(data + (i * 32) + 24) =
1926             *(data + (i * 32) + 25) =
1927             *(data + (i * 32) + 27) =
1928             *(data + (i * 32) + 28) =
1929             *(data + (i * 32) + 29) =
1930             *(data + (i * 32) + 30) =
1931             *(data + (i * 32) + 31) = avc_state->ftq_skip_threshold_lut[i];
1932         }
1933
1934     }
1935     data += size;
1936
1937     /*ref cost*/
1938     size = 128;
1939     memcpy(data,(unsigned char *)&gen9_avc_ref_cost[table_idx][0],size * sizeof(unsigned char));
1940     data += size;
1941
1942     /*scaling factor*/
1943     size = 64;
1944     if(avc_state->adaptive_intra_scaling_enable)
1945     {
1946         memcpy(data,(unsigned char *)&gen9_avc_adaptive_intra_scaling_factor,size * sizeof(unsigned char));
1947     }else
1948     {
1949         memcpy(data,(unsigned char *)&gen9_avc_intra_scaling_factor,size * sizeof(unsigned char));
1950     }
1951     i965_unmap_gpe_resource(gpe_resource);
1952 }
1953
1954 static void
1955 gen9_avc_init_brc_const_data_old(VADriverContextP ctx,
1956                                  struct encode_state *encode_state,
1957                                  struct intel_encoder_context *encoder_context)
1958 {
1959     struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
1960     struct i965_avc_encoder_context * avc_ctx = (struct i965_avc_encoder_context * )vme_context->private_enc_ctx;
1961     struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
1962     struct avc_enc_state * avc_state = (struct avc_enc_state * )vme_context->private_enc_state;
1963
1964     struct i965_gpe_resource *gpe_resource = NULL;
1965     unsigned int * data =NULL;
1966     unsigned int * data_tmp = NULL;
1967     unsigned int size = 0;
1968     unsigned int table_idx = 0;
1969     VAEncPictureParameterBufferH264  *pic_param = avc_state->pic_param;
1970     unsigned int block_based_skip_enable = avc_state->block_based_skip_enable;
1971     unsigned int transform_8x8_mode_flag = pic_param->pic_fields.bits.transform_8x8_mode_flag;
1972     int i = 0;
1973
1974     gpe_resource = &(avc_ctx->res_brc_const_data_buffer);
1975     assert(gpe_resource);
1976
1977     i965_zero_gpe_resource(gpe_resource);
1978
1979     data = i965_map_gpe_resource(gpe_resource);
1980     assert(data);
1981
1982     table_idx = slice_type_kernel[generic_state->frame_type];
1983
1984     /* Fill surface with QP Adjustment table, Distortion threshold table, MaxFrame threshold table, Distortion QP Adjustment Table*/
1985     size = sizeof(gen75_avc_qp_adjustment_dist_threshold_max_frame_threshold_dist_qp_adjustment_ipb);
1986     memcpy(data,gen75_avc_qp_adjustment_dist_threshold_max_frame_threshold_dist_qp_adjustment_ipb,size*sizeof(unsigned char));
1987
1988     data += size;
1989
1990     /* skip threshold table*/
1991     size = 128;
1992     switch(generic_state->frame_type)
1993     {
1994     case SLICE_TYPE_P:
1995         memcpy(data,gen9_avc_skip_value_p[block_based_skip_enable][transform_8x8_mode_flag],size * sizeof(unsigned char));
1996         break;
1997     case SLICE_TYPE_B:
1998         memcpy(data,gen9_avc_skip_value_b[block_based_skip_enable][transform_8x8_mode_flag],size * sizeof(unsigned char));
1999         break;
2000     default:
2001         /*SLICE_TYPE_I,no change */
2002         break;
2003     }
2004
2005     if((generic_state->frame_type != SLICE_TYPE_I) && avc_state->non_ftq_skip_threshold_lut_input_enable)
2006     {
2007         for(i = 0; i< 52 ; i++)
2008         {
2009             *(data + 1 + (i * 2)) = (unsigned char)i965_avc_calc_skip_value(block_based_skip_enable,transform_8x8_mode_flag,avc_state->non_ftq_skip_threshold_lut[i]);
2010         }
2011     }
2012     data += size;
2013
2014     /*fill the qp for ref list*/
2015     size = 128;
2016     data += size;
2017     size = 128;
2018     data += size;
2019
2020     /*mv cost and mode cost*/
2021     size = 1664;
2022     memcpy(data,(unsigned char *)&gen75_avc_mode_mv_cost_table[table_idx][0][0],size * sizeof(unsigned char));
2023
2024     if(avc_state->old_mode_cost_enable)
2025     {   data_tmp = data;
2026         for(i = 0; i < 52 ; i++)
2027         {
2028             *(data_tmp +3) = (unsigned int)gen9_avc_old_intra_mode_cost[i];
2029             data_tmp += 16;
2030         }
2031     }
2032
2033     if(avc_state->ftq_skip_threshold_lut_input_enable)
2034     {
2035         for(i = 0; i < 52 ; i++)
2036         {
2037             *(data + (i * 32) + 24) =
2038             *(data + (i * 32) + 25) =
2039             *(data + (i * 32) + 27) =
2040             *(data + (i * 32) + 28) =
2041             *(data + (i * 32) + 29) =
2042             *(data + (i * 32) + 30) =
2043             *(data + (i * 32) + 31) = avc_state->ftq_skip_threshold_lut[i];
2044         }
2045
2046     }
2047     data += size;
2048
2049     /*ref cost*/
2050     size = 128;
2051     memcpy(data,(unsigned char *)&gen9_avc_ref_cost[table_idx][0],size * sizeof(unsigned char));
2052
2053     i965_unmap_gpe_resource(gpe_resource);
2054 }
2055 static void
2056 gen9_avc_set_curbe_brc_init_reset(VADriverContextP ctx,
2057                                   struct encode_state *encode_state,
2058                                   struct i965_gpe_context *gpe_context,
2059                                   struct intel_encoder_context *encoder_context,
2060                                   void * param)
2061 {
2062     gen9_avc_brc_init_reset_curbe_data *cmd;
2063     struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
2064     struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
2065     struct avc_enc_state * avc_state = (struct avc_enc_state * )vme_context->private_enc_state;
2066     double input_bits_per_frame = 0;
2067     double bps_ratio = 0;
2068     VAEncSequenceParameterBufferH264 * seq_param = avc_state->seq_param;
2069     struct avc_param common_param;
2070
2071     cmd = i965_gpe_context_map_curbe(gpe_context);
2072
2073     if (!cmd)
2074         return;
2075
2076     memcpy(cmd,&gen9_avc_brc_init_reset_curbe_init_data,sizeof(gen9_avc_brc_init_reset_curbe_data));
2077
2078     memset(&common_param,0,sizeof(common_param));
2079     common_param.frame_width_in_pixel = generic_state->frame_width_in_pixel;
2080     common_param.frame_height_in_pixel = generic_state->frame_height_in_pixel;
2081     common_param.frame_width_in_mbs = generic_state->frame_width_in_mbs;
2082     common_param.frame_height_in_mbs = generic_state->frame_height_in_mbs;
2083     common_param.frames_per_100s = generic_state->frames_per_100s;
2084     common_param.vbv_buffer_size_in_bit = generic_state->vbv_buffer_size_in_bit;
2085     common_param.target_bit_rate = generic_state->target_bit_rate;
2086
2087     cmd->dw0.profile_level_max_frame = i965_avc_get_profile_level_max_frame(&common_param,seq_param->level_idc);
2088     cmd->dw1.init_buf_full_in_bits = generic_state->init_vbv_buffer_fullness_in_bit;
2089     cmd->dw2.buf_size_in_bits = generic_state->vbv_buffer_size_in_bit;
2090     cmd->dw3.average_bit_rate = generic_state->target_bit_rate * 1000;
2091     cmd->dw4.max_bit_rate = generic_state->max_bit_rate * 1000;
2092     cmd->dw8.gop_p = (generic_state->gop_ref_distance)?((generic_state->gop_size -1)/generic_state->gop_ref_distance):0;
2093     cmd->dw9.gop_b = (generic_state->gop_size - 1 - cmd->dw8.gop_p);
2094     cmd->dw9.frame_width_in_bytes = generic_state->frame_width_in_pixel;
2095     cmd->dw10.frame_height_in_bytes = generic_state->frame_height_in_pixel;
2096     cmd->dw12.no_slices = avc_state->slice_num;
2097
2098     //VUI
2099     if(seq_param->vui_parameters_present_flag && generic_state->internal_rate_mode != INTEL_BRC_AVBR )
2100     {
2101         cmd->dw4.max_bit_rate = cmd->dw4.max_bit_rate;
2102         if(generic_state->internal_rate_mode == VA_RC_CBR)
2103         {
2104             cmd->dw3.average_bit_rate = cmd->dw4.max_bit_rate;
2105
2106         }
2107
2108     }
2109     cmd->dw6.frame_rate_m = generic_state->frames_per_100s;
2110     cmd->dw7.frame_rate_d = 100;
2111     cmd->dw8.brc_flag = 0;
2112     cmd->dw8.brc_flag |= (generic_state->mb_brc_enabled)? 0 : 0x8000;
2113
2114
2115     if(generic_state->internal_rate_mode == VA_RC_CBR)
2116     { //CBR
2117         cmd->dw4.max_bit_rate = cmd->dw3.average_bit_rate;
2118         cmd->dw8.brc_flag = cmd->dw8.brc_flag |INTEL_ENCODE_BRCINIT_ISCBR;
2119
2120     }else if(generic_state->internal_rate_mode == VA_RC_VBR)
2121     {//VBR
2122         if(cmd->dw4.max_bit_rate < cmd->dw3.average_bit_rate)
2123         {
2124             cmd->dw4.max_bit_rate = cmd->dw3.average_bit_rate << 1;
2125         }
2126         cmd->dw8.brc_flag = cmd->dw8.brc_flag |INTEL_ENCODE_BRCINIT_ISVBR;
2127
2128     }else if(generic_state->internal_rate_mode == INTEL_BRC_AVBR)
2129     { //AVBR
2130         cmd->dw4.max_bit_rate =cmd->dw3.average_bit_rate;
2131         cmd->dw8.brc_flag = cmd->dw8.brc_flag |INTEL_ENCODE_BRCINIT_ISAVBR;
2132
2133     }
2134     //igonre icq/vcm/qvbr
2135
2136     cmd->dw10.avbr_accuracy = generic_state->avbr_curracy;
2137     cmd->dw11.avbr_convergence = generic_state->avbr_convergence;
2138
2139     //frame bits
2140     input_bits_per_frame = (double)(cmd->dw4.max_bit_rate) * (double)(cmd->dw7.frame_rate_d)/(double)(cmd->dw6.frame_rate_m);;
2141
2142     if(cmd->dw2.buf_size_in_bits == 0)
2143     {
2144        cmd->dw2.buf_size_in_bits = (unsigned int)(input_bits_per_frame * 4);
2145     }
2146
2147     if(cmd->dw1.init_buf_full_in_bits == 0)
2148     {
2149        cmd->dw1.init_buf_full_in_bits = cmd->dw2.buf_size_in_bits * 7/8;
2150     }
2151     if(cmd->dw1.init_buf_full_in_bits < (unsigned int)(input_bits_per_frame * 2))
2152     {
2153        cmd->dw1.init_buf_full_in_bits = (unsigned int)(input_bits_per_frame * 2);
2154     }
2155     if(cmd->dw1.init_buf_full_in_bits > cmd->dw2.buf_size_in_bits)
2156     {
2157        cmd->dw1.init_buf_full_in_bits = cmd->dw2.buf_size_in_bits;
2158     }
2159
2160     //AVBR
2161     if(generic_state->internal_rate_mode == INTEL_BRC_AVBR)
2162     {
2163        cmd->dw2.buf_size_in_bits = 2 * generic_state->target_bit_rate * 1000;
2164        cmd->dw1.init_buf_full_in_bits = (unsigned int)(3 * cmd->dw2.buf_size_in_bits/4);
2165
2166     }
2167
2168     bps_ratio = input_bits_per_frame / (cmd->dw2.buf_size_in_bits/30.0);
2169     bps_ratio = (bps_ratio < 0.1)? 0.1:(bps_ratio > 3.5)?3.5:bps_ratio;
2170
2171
2172     cmd->dw16.deviation_threshold_0_pand_b = (unsigned int)(-50 * pow(0.90,bps_ratio));
2173     cmd->dw16.deviation_threshold_1_pand_b = (unsigned int)(-50 * pow(0.66,bps_ratio));
2174     cmd->dw16.deviation_threshold_2_pand_b = (unsigned int)(-50 * pow(0.46,bps_ratio));
2175     cmd->dw16.deviation_threshold_3_pand_b = (unsigned int)(-50 * pow(0.3, bps_ratio));
2176     cmd->dw17.deviation_threshold_4_pand_b = (unsigned int)(50 *  pow(0.3, bps_ratio));
2177     cmd->dw17.deviation_threshold_5_pand_b = (unsigned int)(50 * pow(0.46, bps_ratio));
2178     cmd->dw17.deviation_threshold_6_pand_b = (unsigned int)(50 * pow(0.7,  bps_ratio));
2179     cmd->dw17.deviation_threshold_7_pand_b = (unsigned int)(50 * pow(0.9,  bps_ratio));
2180     cmd->dw18.deviation_threshold_0_vbr = (unsigned int)(-50 * pow(0.9, bps_ratio));
2181     cmd->dw18.deviation_threshold_1_vbr = (unsigned int)(-50 * pow(0.7, bps_ratio));
2182     cmd->dw18.deviation_threshold_2_vbr = (unsigned int)(-50 * pow(0.5, bps_ratio));
2183     cmd->dw18.deviation_threshold_3_vbr = (unsigned int)(-50 * pow(0.3, bps_ratio));
2184     cmd->dw19.deviation_threshold_4_vbr = (unsigned int)(100 * pow(0.4, bps_ratio));
2185     cmd->dw19.deviation_threshold_5_vbr = (unsigned int)(100 * pow(0.5, bps_ratio));
2186     cmd->dw19.deviation_threshold_6_vbr = (unsigned int)(100 * pow(0.75,bps_ratio));
2187     cmd->dw19.deviation_threshold_7_vbr = (unsigned int)(100 * pow(0.9, bps_ratio));
2188     cmd->dw20.deviation_threshold_0_i = (unsigned int)(-50 * pow(0.8, bps_ratio));
2189     cmd->dw20.deviation_threshold_1_i = (unsigned int)(-50 * pow(0.6, bps_ratio));
2190     cmd->dw20.deviation_threshold_2_i = (unsigned int)(-50 * pow(0.34,bps_ratio));
2191     cmd->dw20.deviation_threshold_3_i = (unsigned int)(-50 * pow(0.2, bps_ratio));
2192     cmd->dw21.deviation_threshold_4_i = (unsigned int)(50 * pow(0.2,  bps_ratio));
2193     cmd->dw21.deviation_threshold_5_i = (unsigned int)(50 * pow(0.4,  bps_ratio));
2194     cmd->dw21.deviation_threshold_6_i = (unsigned int)(50 * pow(0.66, bps_ratio));
2195     cmd->dw21.deviation_threshold_7_i = (unsigned int)(50 * pow(0.9,  bps_ratio));
2196
2197     cmd->dw22.sliding_window_size = generic_state->frames_per_window_size;
2198
2199     i965_gpe_context_unmap_curbe(gpe_context);
2200
2201     return;
2202 }
2203
2204 static void
2205 gen9_avc_send_surface_brc_init_reset(VADriverContextP ctx,
2206                                      struct encode_state *encode_state,
2207                                      struct i965_gpe_context *gpe_context,
2208                                      struct intel_encoder_context *encoder_context,
2209                                      void * param_mbenc)
2210 {
2211     struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
2212     struct i965_avc_encoder_context * avc_ctx = (struct i965_avc_encoder_context * )vme_context->private_enc_ctx;
2213
2214     gen9_add_buffer_gpe_surface(ctx,
2215                                 gpe_context,
2216                                 &avc_ctx->res_brc_history_buffer,
2217                                 0,
2218                                 avc_ctx->res_brc_history_buffer.size,
2219                                 0,
2220                                 GEN9_AVC_BRC_INIT_RESET_HISTORY_INDEX);
2221
2222     gen9_add_buffer_2d_gpe_surface(ctx,
2223                                    gpe_context,
2224                                    &avc_ctx->res_brc_dist_data_surface,
2225                                    1,
2226                                    I965_SURFACEFORMAT_R8_UNORM,
2227                                    GEN9_AVC_BRC_INIT_RESET_DISTORTION_INDEX);
2228
2229     return;
2230 }
2231
2232 static VAStatus
2233 gen9_avc_kernel_brc_init_reset(VADriverContextP ctx,
2234                                struct encode_state *encode_state,
2235                                struct intel_encoder_context *encoder_context)
2236 {
2237     struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
2238     struct i965_avc_encoder_context * avc_ctx = (struct i965_avc_encoder_context * )vme_context->private_enc_ctx;
2239     struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
2240     struct generic_encoder_context * generic_ctx = (struct generic_encoder_context * )vme_context->generic_enc_ctx;
2241
2242     struct i965_gpe_context *gpe_context;
2243     struct gpe_media_object_parameter media_object_param;
2244     struct gpe_media_object_inline_data media_object_inline_data;
2245     int media_function = 0;
2246     int kernel_idx = GEN9_AVC_KERNEL_BRC_INIT;
2247
2248     media_function = INTEL_MEDIA_STATE_BRC_INIT_RESET;
2249
2250     if(generic_state->brc_inited)
2251         kernel_idx = GEN9_AVC_KERNEL_BRC_RESET;
2252
2253     gpe_context = &(avc_ctx->context_brc.gpe_contexts[kernel_idx]);
2254
2255     gen8_gpe_context_init(ctx, gpe_context);
2256     gen9_gpe_reset_binding_table(ctx, gpe_context);
2257
2258     generic_ctx->pfn_set_curbe_brc_init_reset(ctx,encode_state,gpe_context,encoder_context,NULL);
2259
2260     generic_ctx->pfn_send_brc_init_reset_surface(ctx,encode_state,gpe_context,encoder_context,NULL);
2261
2262     gen8_gpe_setup_interface_data(ctx, gpe_context);
2263
2264     memset(&media_object_param, 0, sizeof(media_object_param));
2265     memset(&media_object_inline_data, 0, sizeof(media_object_inline_data));
2266     media_object_param.pinline_data = &media_object_inline_data;
2267     media_object_param.inline_size = sizeof(media_object_inline_data);
2268
2269     gen9_avc_run_kernel_media_object(ctx, encoder_context,
2270                                         gpe_context,
2271                                         media_function,
2272                                         &media_object_param);
2273
2274     return VA_STATUS_SUCCESS;
2275 }
2276
2277 static void
2278 gen9_avc_set_curbe_brc_frame_update(VADriverContextP ctx,
2279                                     struct encode_state *encode_state,
2280                                     struct i965_gpe_context *gpe_context,
2281                                     struct intel_encoder_context *encoder_context,
2282                                     void * param)
2283 {
2284     gen9_avc_frame_brc_update_curbe_data *cmd;
2285     struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
2286     struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
2287     struct avc_enc_state * avc_state = (struct avc_enc_state * )vme_context->private_enc_state;
2288     struct object_surface *obj_surface;
2289     struct gen9_surface_avc *avc_priv_surface;
2290     struct avc_param common_param;
2291     VAEncSequenceParameterBufferH264 * seq_param = avc_state->seq_param;
2292
2293     obj_surface = encode_state->reconstructed_object;
2294
2295     if (!obj_surface || !obj_surface->private_data)
2296         return;
2297     avc_priv_surface = obj_surface->private_data;
2298
2299     cmd = i965_gpe_context_map_curbe(gpe_context);
2300
2301     if (!cmd)
2302         return;
2303
2304     memcpy(cmd,&gen9_avc_frame_brc_update_curbe_init_data,sizeof(gen9_avc_frame_brc_update_curbe_data));
2305
2306     cmd->dw5.target_size_flag = 0 ;
2307     if(generic_state->brc_init_current_target_buf_full_in_bits > (double)generic_state->brc_init_reset_buf_size_in_bits)
2308     {
2309         /*overflow*/
2310         generic_state->brc_init_current_target_buf_full_in_bits -= (double)generic_state->brc_init_reset_buf_size_in_bits;
2311         cmd->dw5.target_size_flag = 1 ;
2312     }
2313
2314     if(generic_state->skip_frame_enbale)
2315     {
2316         cmd->dw6.num_skip_frames = generic_state->num_skip_frames ;
2317         cmd->dw7.size_skip_frames = generic_state->size_skip_frames;
2318
2319         generic_state->brc_init_current_target_buf_full_in_bits += generic_state->brc_init_reset_input_bits_per_frame * generic_state->num_skip_frames;
2320
2321     }
2322     cmd->dw0.target_size = (unsigned int)generic_state->brc_init_current_target_buf_full_in_bits ;
2323     cmd->dw1.frame_number = generic_state->seq_frame_number ;
2324     cmd->dw2.size_of_pic_headers = generic_state->herder_bytes_inserted << 3 ;
2325     cmd->dw5.cur_frame_type = generic_state->frame_type ;
2326     cmd->dw5.brc_flag = 0 ;
2327     cmd->dw5.brc_flag |= (avc_priv_surface->is_as_ref)?INTEL_ENCODE_BRCUPDATE_IS_REFERENCE:0 ;
2328
2329     if(avc_state->multi_pre_enable)
2330     {
2331         cmd->dw5.brc_flag  |= INTEL_ENCODE_BRCUPDATE_IS_ACTUALQP ;
2332         cmd->dw14.qp_index_of_cur_pic = avc_priv_surface->frame_idx ; //do not know this. use -1
2333     }
2334
2335     cmd->dw5.max_num_paks = generic_state->num_pak_passes ;
2336     if(avc_state->min_max_qp_enable)
2337     {
2338         switch(generic_state->frame_type)
2339         {
2340         case SLICE_TYPE_I:
2341             cmd->dw6.minimum_qp = avc_state->min_qp_i ;
2342             cmd->dw6.maximum_qp = avc_state->max_qp_i ;
2343             break;
2344         case SLICE_TYPE_P:
2345             cmd->dw6.minimum_qp = avc_state->min_qp_p ;
2346             cmd->dw6.maximum_qp = avc_state->max_qp_p ;
2347             break;
2348         case SLICE_TYPE_B:
2349             cmd->dw6.minimum_qp = avc_state->min_qp_b ;
2350             cmd->dw6.maximum_qp = avc_state->max_qp_b ;
2351             break;
2352         }
2353     }else
2354     {
2355         cmd->dw6.minimum_qp = 0 ;
2356         cmd->dw6.maximum_qp = 0 ;
2357     }
2358     cmd->dw6.enable_force_skip = avc_state->enable_force_skip ;
2359     cmd->dw6.enable_sliding_window = 0 ;
2360
2361     generic_state->brc_init_current_target_buf_full_in_bits += generic_state->brc_init_reset_input_bits_per_frame;
2362
2363     if(generic_state->internal_rate_mode == INTEL_BRC_AVBR)
2364     {
2365         cmd->dw3.start_gadj_frame0 = (unsigned int)((10 *   generic_state->avbr_convergence) / (double)150);
2366         cmd->dw3.start_gadj_frame1 = (unsigned int)((50 *   generic_state->avbr_convergence) / (double)150);
2367         cmd->dw4.start_gadj_frame2 = (unsigned int)((100 *  generic_state->avbr_convergence) / (double)150);
2368         cmd->dw4.start_gadj_frame3 = (unsigned int)((150 *  generic_state->avbr_convergence) / (double)150);
2369         cmd->dw11.g_rate_ratio_threshold_0 = (unsigned int)((100 - (generic_state->avbr_curracy / (double)30)*(100 - 40)));
2370         cmd->dw11.g_rate_ratio_threshold_1 = (unsigned int)((100 - (generic_state->avbr_curracy / (double)30)*(100 - 75)));
2371         cmd->dw12.g_rate_ratio_threshold_2 = (unsigned int)((100 - (generic_state->avbr_curracy / (double)30)*(100 - 97)));
2372         cmd->dw12.g_rate_ratio_threshold_3 = (unsigned int)((100 + (generic_state->avbr_curracy / (double)30)*(103 - 100)));
2373         cmd->dw12.g_rate_ratio_threshold_4 = (unsigned int)((100 + (generic_state->avbr_curracy / (double)30)*(125 - 100)));
2374         cmd->dw12.g_rate_ratio_threshold_5 = (unsigned int)((100 + (generic_state->avbr_curracy / (double)30)*(160 - 100)));
2375
2376     }
2377     cmd->dw15.enable_roi = generic_state->brc_roi_enable ;
2378
2379     memset(&common_param,0,sizeof(common_param));
2380     common_param.frame_width_in_pixel = generic_state->frame_width_in_pixel;
2381     common_param.frame_height_in_pixel = generic_state->frame_height_in_pixel;
2382     common_param.frame_width_in_mbs = generic_state->frame_width_in_mbs;
2383     common_param.frame_height_in_mbs = generic_state->frame_height_in_mbs;
2384     common_param.frames_per_100s = generic_state->frames_per_100s;
2385     common_param.vbv_buffer_size_in_bit = generic_state->vbv_buffer_size_in_bit;
2386     common_param.target_bit_rate = generic_state->target_bit_rate;
2387
2388     cmd->dw19.user_max_frame = i965_avc_get_profile_level_max_frame(&common_param,seq_param->level_idc);
2389     i965_gpe_context_unmap_curbe(gpe_context);
2390
2391     return;
2392 }
2393
2394 static void
2395 gen9_avc_send_surface_brc_frame_update(VADriverContextP ctx,
2396                                        struct encode_state *encode_state,
2397                                        struct i965_gpe_context *gpe_context,
2398                                        struct intel_encoder_context *encoder_context,
2399                                        void * param_brc)
2400 {
2401     struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
2402     struct i965_avc_encoder_context * avc_ctx = (struct i965_avc_encoder_context * )vme_context->private_enc_ctx;
2403     struct brc_param * param = (struct brc_param *)param_brc ;
2404     struct i965_gpe_context * gpe_context_mbenc = param->gpe_context_mbenc;
2405
2406
2407     /* brc history buffer*/
2408     gen9_add_buffer_gpe_surface(ctx,
2409                                 gpe_context,
2410                                 &avc_ctx->res_brc_history_buffer,
2411                                 0,
2412                                 avc_ctx->res_brc_history_buffer.size,
2413                                 0,
2414                                 GEN9_AVC_FRAME_BRC_UPDATE_HISTORY_INDEX);
2415
2416     /* previous pak buffer*/
2417     gen9_add_buffer_gpe_surface(ctx,
2418                                 gpe_context,
2419                                 &avc_ctx->res_brc_pre_pak_statistics_output_buffer,
2420                                 0,
2421                                 avc_ctx->res_brc_pre_pak_statistics_output_buffer.size,
2422                                 0,
2423                                 GEN9_AVC_FRAME_BRC_UPDATE_PAK_STATISTICS_OUTPUT_INDEX);
2424
2425     /* image state command buffer read only*/
2426     gen9_add_buffer_gpe_surface(ctx,
2427                                 gpe_context,
2428                                 &avc_ctx->res_brc_image_state_read_buffer,
2429                                 0,
2430                                 avc_ctx->res_brc_image_state_read_buffer.size,
2431                                 0,
2432                                 GEN9_AVC_FRAME_BRC_UPDATE_IMAGE_STATE_READ_INDEX);
2433
2434     /* image state command buffer write only*/
2435     gen9_add_buffer_gpe_surface(ctx,
2436                                 gpe_context,
2437                                 &avc_ctx->res_brc_image_state_write_buffer,
2438                                 0,
2439                                 avc_ctx->res_brc_image_state_write_buffer.size,
2440                                 0,
2441                                 GEN9_AVC_FRAME_BRC_UPDATE_IMAGE_STATE_WRITE_INDEX);
2442
2443     /*  Mbenc curbe input buffer */
2444     gen9_add_dri_buffer_gpe_surface(ctx,
2445                                     gpe_context,
2446                                     gpe_context_mbenc->dynamic_state.bo,
2447                                     0,
2448                                     ALIGN(gpe_context_mbenc->curbe.length, 64),
2449                                     gpe_context_mbenc->curbe.offset,
2450                                     GEN9_AVC_FRAME_BRC_UPDATE_MBENC_CURBE_READ_INDEX);
2451     /* Mbenc curbe output buffer */
2452     gen9_add_dri_buffer_gpe_surface(ctx,
2453                                     gpe_context,
2454                                     gpe_context_mbenc->dynamic_state.bo,
2455                                     0,
2456                                     ALIGN(gpe_context_mbenc->curbe.length, 64),
2457                                     gpe_context_mbenc->curbe.offset,
2458                                     GEN9_AVC_FRAME_BRC_UPDATE_MBENC_CURBE_WRITE_INDEX);
2459
2460     /* AVC_ME Distortion 2D surface buffer,input/output. is it res_brc_dist_data_surface*/
2461     gen9_add_buffer_2d_gpe_surface(ctx,
2462                                    gpe_context,
2463                                    &avc_ctx->res_brc_dist_data_surface,
2464                                    1,
2465                                    I965_SURFACEFORMAT_R8_UNORM,
2466                                    GEN9_AVC_FRAME_BRC_UPDATE_DISTORTION_INDEX);
2467
2468     /* BRC const data 2D surface buffer */
2469     gen9_add_buffer_2d_gpe_surface(ctx,
2470                                    gpe_context,
2471                                    &avc_ctx->res_brc_const_data_buffer,
2472                                    1,
2473                                    I965_SURFACEFORMAT_R8_UNORM,
2474                                    GEN9_AVC_FRAME_BRC_UPDATE_CONSTANT_DATA_INDEX);
2475
2476     /* MB statistical data surface*/
2477     gen9_add_buffer_gpe_surface(ctx,
2478                                 gpe_context,
2479                                 &avc_ctx->res_mb_status_buffer,
2480                                 0,
2481                                 avc_ctx->res_mb_status_buffer.size,
2482                                 0,
2483                                 GEN9_AVC_FRAME_BRC_UPDATE_MB_STATUS_INDEX);
2484
2485     return;
2486 }
2487
2488 static VAStatus
2489 gen9_avc_kernel_brc_frame_update(VADriverContextP ctx,
2490                                  struct encode_state *encode_state,
2491                                  struct intel_encoder_context *encoder_context)
2492
2493 {
2494     struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
2495     struct generic_encoder_context * generic_ctx = (struct generic_encoder_context * )vme_context->generic_enc_ctx;
2496     struct i965_avc_encoder_context * avc_ctx = (struct i965_avc_encoder_context * )vme_context->private_enc_ctx;
2497     struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
2498     struct avc_enc_state * avc_state = (struct avc_enc_state * )vme_context->private_enc_state;
2499
2500     struct i965_gpe_context *gpe_context;
2501     struct gpe_media_object_parameter media_object_param;
2502     struct gpe_media_object_inline_data media_object_inline_data;
2503     int media_function = 0;
2504     int kernel_idx = 0;
2505     unsigned int mb_const_data_buffer_in_use,mb_qp_buffer_in_use;
2506     unsigned int brc_enabled = 0;
2507     unsigned int roi_enable = (generic_state->num_roi > 0)?1:0;
2508     unsigned int dirty_roi_enable = ((generic_state->dirty_num_roi > 0) && (generic_state->frame_type == SLICE_TYPE_P) && (0));
2509
2510     /* the following set the mbenc curbe*/
2511     struct mbenc_param curbe_mbenc_param ;
2512     struct brc_param curbe_brc_param ;
2513
2514     mb_const_data_buffer_in_use =
2515         generic_state->mb_brc_enabled ||
2516         roi_enable ||
2517         dirty_roi_enable ||
2518         avc_state->mb_qp_data_enable ||
2519         avc_state->rolling_intra_refresh_enable;
2520     mb_qp_buffer_in_use =
2521         generic_state->mb_brc_enabled ||
2522         generic_state->brc_roi_enable ||
2523         avc_state->mb_qp_data_enable;
2524
2525     switch(generic_state->kernel_mode)
2526     {
2527     case INTEL_ENC_KERNEL_NORMAL :
2528         {
2529             kernel_idx = MBENC_KERNEL_BASE + GEN9_AVC_KERNEL_MBENC_NORMAL_I;
2530             break;
2531         }
2532     case INTEL_ENC_KERNEL_PERFORMANCE :
2533         {
2534             kernel_idx = MBENC_KERNEL_BASE + GEN9_AVC_KERNEL_MBENC_PERFORMANCE_I;
2535             break;
2536         }
2537     case INTEL_ENC_KERNEL_QUALITY :
2538         {
2539             kernel_idx = MBENC_KERNEL_BASE + GEN9_AVC_KERNEL_MBENC_QUALITY_I;
2540             break;
2541         }
2542     default:
2543         assert(0);
2544
2545     }
2546
2547     if(generic_state->frame_type == SLICE_TYPE_P)
2548     {
2549         kernel_idx += 1;
2550     }
2551     else if(generic_state->frame_type == SLICE_TYPE_B)
2552     {
2553         kernel_idx += 2;
2554     }
2555
2556     gpe_context = &(avc_ctx->context_mbenc.gpe_contexts[kernel_idx]);
2557     gen8_gpe_context_init(ctx, gpe_context);
2558
2559     memset(&curbe_mbenc_param,0,sizeof(struct mbenc_param));
2560
2561     curbe_mbenc_param.mb_const_data_buffer_in_use = mb_const_data_buffer_in_use;
2562     curbe_mbenc_param.mb_qp_buffer_in_use = mb_qp_buffer_in_use;
2563     curbe_mbenc_param.mbenc_i_frame_dist_in_use = 0;
2564     curbe_mbenc_param.brc_enabled = brc_enabled;
2565     curbe_mbenc_param.roi_enabled = roi_enable;
2566
2567     /* set curbe mbenc*/
2568     generic_ctx->pfn_set_curbe_mbenc(ctx,encode_state,gpe_context,encoder_context,&curbe_mbenc_param);
2569     avc_state->mbenc_curbe_set_in_brc_update = 1;
2570
2571     /*begin brc frame update*/
2572     memset(&curbe_brc_param,0,sizeof(struct brc_param));
2573     curbe_brc_param.gpe_context_mbenc = gpe_context;
2574     media_function = INTEL_MEDIA_STATE_BRC_UPDATE;
2575     kernel_idx = GEN9_AVC_KERNEL_BRC_FRAME_UPDATE;
2576     gpe_context = &(avc_ctx->context_brc.gpe_contexts[kernel_idx]);
2577     curbe_brc_param.gpe_context_brc_frame_update = gpe_context;
2578
2579     gen8_gpe_context_init(ctx, gpe_context);
2580     gen9_gpe_reset_binding_table(ctx, gpe_context);
2581     /*brc copy ignored*/
2582
2583     /* set curbe frame update*/
2584     generic_ctx->pfn_set_curbe_brc_frame_update(ctx,encode_state,gpe_context,encoder_context,&curbe_brc_param);
2585
2586     /* load brc constant data, is it same as mbenc mb brc constant data? no.*/
2587     if(avc_state->multi_pre_enable)
2588     {
2589         gen9_avc_init_brc_const_data(ctx,encode_state,encoder_context);
2590     }else
2591     {
2592         gen9_avc_init_brc_const_data_old(ctx,encode_state,encoder_context);
2593     }
2594     /* image state construct*/
2595     gen9_avc_set_image_state(ctx,encode_state,encoder_context,&(avc_ctx->res_brc_image_state_read_buffer));
2596     /* set surface frame mbenc*/
2597     generic_ctx->pfn_send_brc_frame_update_surface(ctx,encode_state,gpe_context,encoder_context,&curbe_brc_param);
2598
2599
2600     gen8_gpe_setup_interface_data(ctx, gpe_context);
2601
2602     memset(&media_object_param, 0, sizeof(media_object_param));
2603     memset(&media_object_inline_data, 0, sizeof(media_object_inline_data));
2604     media_object_param.pinline_data = &media_object_inline_data;
2605     media_object_param.inline_size = sizeof(media_object_inline_data);
2606
2607     gen9_avc_run_kernel_media_object(ctx, encoder_context,
2608                                         gpe_context,
2609                                         media_function,
2610                                         &media_object_param);
2611
2612     return VA_STATUS_SUCCESS;
2613 }
2614
2615 static void
2616 gen9_avc_set_curbe_brc_mb_update(VADriverContextP ctx,
2617                                  struct encode_state *encode_state,
2618                                  struct i965_gpe_context *gpe_context,
2619                                  struct intel_encoder_context *encoder_context,
2620                                  void * param)
2621 {
2622     gen9_avc_mb_brc_curbe_data *cmd;
2623     struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
2624     struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
2625
2626     cmd = i965_gpe_context_map_curbe(gpe_context);
2627
2628     if (!cmd)
2629         return;
2630
2631     memset(cmd,0,sizeof(gen9_avc_mb_brc_curbe_data));
2632
2633     cmd->dw0.cur_frame_type = generic_state->frame_type;
2634     if(generic_state->brc_roi_enable)
2635     {
2636         cmd->dw0.enable_roi = 1;
2637     }else
2638     {
2639         cmd->dw0.enable_roi = 0;
2640     }
2641
2642     i965_gpe_context_unmap_curbe(gpe_context);
2643
2644     return;
2645 }
2646
2647 static void
2648 gen9_avc_send_surface_brc_mb_update(VADriverContextP ctx,
2649                                     struct encode_state *encode_state,
2650                                     struct i965_gpe_context *gpe_context,
2651                                     struct intel_encoder_context *encoder_context,
2652                                     void * param_mbenc)
2653 {
2654     struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
2655     struct i965_avc_encoder_context * avc_ctx = (struct i965_avc_encoder_context * )vme_context->private_enc_ctx;
2656     struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
2657
2658     /* brc history buffer*/
2659     gen9_add_buffer_gpe_surface(ctx,
2660                                 gpe_context,
2661                                 &avc_ctx->res_brc_history_buffer,
2662                                 0,
2663                                 avc_ctx->res_brc_history_buffer.size,
2664                                 0,
2665                                 GEN9_AVC_MB_BRC_UPDATE_HISTORY_INDEX);
2666
2667     /* MB qp data buffer is it same as res_mbbrc_mb_qp_data_surface*/
2668     if(generic_state->mb_brc_enabled)
2669     {
2670         gen9_add_buffer_2d_gpe_surface(ctx,
2671                                        gpe_context,
2672                                        &avc_ctx->res_mbbrc_mb_qp_data_surface,
2673                                        1,
2674                                        I965_SURFACEFORMAT_R8_UNORM,
2675                                        GEN9_AVC_MB_BRC_UPDATE_MB_QP_INDEX);
2676
2677     }
2678
2679     /* BRC roi feature*/
2680     if(generic_state->brc_roi_enable)
2681     {
2682         gen9_add_buffer_gpe_surface(ctx,
2683                                     gpe_context,
2684                                     &avc_ctx->res_mbbrc_roi_surface,
2685                                     0,
2686                                     avc_ctx->res_mbbrc_roi_surface.size,
2687                                     0,
2688                                     GEN9_AVC_MB_BRC_UPDATE_ROI_INDEX);
2689
2690     }
2691
2692     /* MB statistical data surface*/
2693     gen9_add_buffer_gpe_surface(ctx,
2694                                 gpe_context,
2695                                 &avc_ctx->res_mb_status_buffer,
2696                                 0,
2697                                 avc_ctx->res_mb_status_buffer.size,
2698                                 0,
2699                                 GEN9_AVC_MB_BRC_UPDATE_MB_STATUS_INDEX);
2700
2701     return;
2702 }
2703
2704 static VAStatus
2705 gen9_avc_kernel_brc_mb_update(VADriverContextP ctx,
2706                               struct encode_state *encode_state,
2707                               struct intel_encoder_context *encoder_context)
2708
2709 {
2710     struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
2711     struct i965_avc_encoder_context * avc_ctx = (struct i965_avc_encoder_context * )vme_context->private_enc_ctx;
2712     struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
2713     struct generic_encoder_context * generic_ctx = (struct generic_encoder_context * )vme_context->generic_enc_ctx;
2714
2715     struct i965_gpe_context *gpe_context;
2716     struct gpe_media_object_walker_parameter media_object_walker_param;
2717     struct gpe_encoder_kernel_walker_parameter kernel_walker_param;
2718     int media_function = 0;
2719     int kernel_idx = 0;
2720
2721     media_function = INTEL_MEDIA_STATE_MB_BRC_UPDATE;
2722     kernel_idx = GEN9_AVC_KERNEL_BRC_MB_UPDATE;
2723     gpe_context = &(avc_ctx->context_brc.gpe_contexts[kernel_idx]);
2724
2725     gen8_gpe_context_init(ctx, gpe_context);
2726     gen9_gpe_reset_binding_table(ctx, gpe_context);
2727
2728     /* set curbe brc mb update*/
2729     generic_ctx->pfn_set_curbe_brc_mb_update(ctx,encode_state,gpe_context,encoder_context,NULL);
2730
2731
2732     /* set surface brc mb update*/
2733     generic_ctx->pfn_send_brc_mb_update_surface(ctx,encode_state,gpe_context,encoder_context,NULL);
2734
2735
2736     gen8_gpe_setup_interface_data(ctx, gpe_context);
2737
2738     memset(&kernel_walker_param, 0, sizeof(kernel_walker_param));
2739     /* the scaling is based on 8x8 blk level */
2740     kernel_walker_param.resolution_x = (generic_state->frame_width_in_mbs + 1)/2;
2741     kernel_walker_param.resolution_y = (generic_state->frame_height_in_mbs + 1)/2 ;
2742     kernel_walker_param.no_dependency = 1;
2743
2744     i965_init_media_object_walker_parameter(&kernel_walker_param, &media_object_walker_param);
2745
2746     gen9_avc_run_kernel_media_object_walker(ctx, encoder_context,
2747                                         gpe_context,
2748                                         media_function,
2749                                         &media_object_walker_param);
2750
2751     return VA_STATUS_SUCCESS;
2752 }
2753
2754 /*
2755 mbenc kernel related function,it include intra dist kernel
2756 */
2757 static int
2758 gen9_avc_get_biweight(int dist_scale_factor_ref_id0_list0, unsigned short weighted_bipredidc)
2759 {
2760     int biweight = 32;      // default value
2761
2762     /* based on kernel HLD*/
2763     if (weighted_bipredidc != INTEL_AVC_WP_MODE_IMPLICIT)
2764     {
2765         biweight = 32;
2766     }
2767     else
2768     {
2769         biweight = (dist_scale_factor_ref_id0_list0 + 2) >> 2;
2770
2771         if (biweight != 16 && biweight != 21 &&
2772             biweight != 32 && biweight != 43 && biweight != 48)
2773         {
2774             biweight = 32;        // If # of B-pics between two refs is more than 3. VME does not support it.
2775         }
2776     }
2777
2778     return biweight;
2779 }
2780
2781 static void
2782 gen9_avc_get_dist_scale_factor(VADriverContextP ctx,
2783                                struct encode_state *encode_state,
2784                                struct intel_encoder_context *encoder_context)
2785 {
2786     struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
2787     struct avc_enc_state * avc_state = (struct avc_enc_state * )vme_context->private_enc_state;
2788     VAEncSliceParameterBufferH264 * slice_param = avc_state->slice_param[0];
2789     VAEncPictureParameterBufferH264  *pic_param = avc_state->pic_param;
2790
2791     int max_num_references;
2792     VAPictureH264 *curr_pic;
2793     VAPictureH264 *ref_pic_l0;
2794     VAPictureH264 *ref_pic_l1;
2795     int i = 0;
2796     int tb = 0;
2797     int td = 0;
2798     int tx = 0;
2799     int tmp = 0;
2800     int poc0 = 0;
2801     int poc1 = 0;
2802
2803     max_num_references = pic_param->num_ref_idx_l0_active_minus1 + 1;
2804
2805     memset(avc_state->dist_scale_factor_list0,0,32*sizeof(unsigned int));
2806     curr_pic = &pic_param->CurrPic;
2807     for(i = 0; i < max_num_references; i++)
2808     {
2809         ref_pic_l0 = &(slice_param->RefPicList0[i]);
2810
2811         if((ref_pic_l0->flags & VA_PICTURE_H264_INVALID) ||
2812            (ref_pic_l0->picture_id == VA_INVALID_SURFACE) )
2813             break;
2814         ref_pic_l1 = &(slice_param->RefPicList1[0]);
2815         if((ref_pic_l0->flags & VA_PICTURE_H264_INVALID) ||
2816            (ref_pic_l0->picture_id == VA_INVALID_SURFACE) )
2817             break;
2818
2819         poc0 = (curr_pic->TopFieldOrderCnt - ref_pic_l0->TopFieldOrderCnt);
2820         poc1 = (ref_pic_l1->TopFieldOrderCnt - ref_pic_l0->TopFieldOrderCnt);
2821         CLIP(poc0,-128,127);
2822         CLIP(poc1,-128,127);
2823         tb = poc0;
2824         td = poc1;
2825
2826         if(td == 0)
2827         {
2828             td = 1;
2829         }
2830         tmp = (td/2 > 0)?(td/2):(-(td/2));
2831         tx = (16384 + tmp)/td ;
2832         tmp = (tb*tx+32)>>6;
2833         CLIP(tmp,-1024,1023);
2834         avc_state->dist_scale_factor_list0[i] = tmp;
2835     }
2836     return;
2837 }
2838
2839 static unsigned int
2840 gen9_avc_get_qp_from_ref_list(VADriverContextP ctx,
2841                               VAEncSliceParameterBufferH264 *slice_param,
2842                               int list,
2843                               int ref_frame_idx)
2844 {
2845     struct i965_driver_data *i965 = i965_driver_data(ctx);
2846     struct object_surface *obj_surface;
2847     struct gen9_surface_avc *avc_priv_surface;
2848     VASurfaceID surface_id;
2849
2850     assert(slice_param);
2851     assert(list < 2);
2852
2853     if(list == 0)
2854     {
2855         if(ref_frame_idx < slice_param->num_ref_idx_l0_active_minus1 + 1)
2856             surface_id = slice_param->RefPicList0[ref_frame_idx].picture_id;
2857         else
2858             return 0;
2859     }else
2860     {
2861         if(ref_frame_idx < slice_param->num_ref_idx_l1_active_minus1 + 1)
2862             surface_id = slice_param->RefPicList1[ref_frame_idx].picture_id;
2863         else
2864             return 0;
2865     }
2866     obj_surface = SURFACE(surface_id);
2867     if(obj_surface && obj_surface->private_data)
2868     {
2869         avc_priv_surface = obj_surface->private_data;
2870         return avc_priv_surface->qp_value;
2871     }else
2872     {
2873         return 0;
2874     }
2875 }
2876
2877 static void
2878 gen9_avc_load_mb_brc_const_data(VADriverContextP ctx,
2879                         struct encode_state *encode_state,
2880                         struct intel_encoder_context *encoder_context)
2881 {
2882     struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
2883     struct i965_avc_encoder_context * avc_ctx = (struct i965_avc_encoder_context * )vme_context->private_enc_ctx;
2884     struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
2885     struct avc_enc_state * avc_state = (struct avc_enc_state * )vme_context->private_enc_state;
2886     VAEncPictureParameterBufferH264  *pic_param = avc_state->pic_param;
2887
2888     struct i965_gpe_resource *gpe_resource = NULL;
2889     unsigned int * data =NULL;
2890     unsigned int * data_tmp = NULL;
2891     unsigned int size = 16 * 52;
2892     unsigned int table_idx = 0;
2893     unsigned int block_based_skip_enable = avc_state->block_based_skip_enable;
2894     unsigned int transform_8x8_mode_flag = pic_param->pic_fields.bits.transform_8x8_mode_flag;
2895     int i = 0;
2896
2897     gpe_resource = &(avc_ctx->res_mbbrc_const_data_buffer);
2898     assert(gpe_resource);
2899     data = i965_map_gpe_resource(gpe_resource);
2900     assert(data);
2901
2902     table_idx = slice_type_kernel[generic_state->frame_type];
2903
2904     memcpy(data,gen9_avc_mb_brc_const_data[table_idx][0],size*sizeof(unsigned int));
2905
2906     data_tmp = data;
2907
2908     switch(generic_state->frame_type)
2909     {
2910     case SLICE_TYPE_I:
2911         for(i = 0; i < 52 ; i++)
2912         {
2913             if(avc_state->old_mode_cost_enable)
2914                 *data = (unsigned int)gen9_avc_old_intra_mode_cost[i];
2915             data += 16;
2916         }
2917         break;
2918     case SLICE_TYPE_P:
2919     case SLICE_TYPE_B:
2920         for(i = 0; i < 52 ; i++)
2921         {
2922             if(generic_state->frame_type == SLICE_TYPE_P)
2923             {
2924                 if(avc_state->skip_bias_adjustment_enable)
2925                     *(data + 3) = (unsigned int)gen9_avc_mv_cost_p_skip_adjustment[i];
2926             }
2927             if(avc_state->non_ftq_skip_threshold_lut_input_enable)
2928             {
2929                 *(data + 9) = (unsigned int)i965_avc_calc_skip_value(block_based_skip_enable,transform_8x8_mode_flag,avc_state->non_ftq_skip_threshold_lut[i]);
2930             }else if(generic_state->frame_type == SLICE_TYPE_P)
2931             {
2932                 *(data + 9) = (unsigned int)gen9_avc_skip_value_p[block_based_skip_enable][transform_8x8_mode_flag][i];
2933             }else
2934             {
2935                 *(data + 9) = (unsigned int)gen9_avc_skip_value_b[block_based_skip_enable][transform_8x8_mode_flag][i];
2936             }
2937
2938             if(avc_state->adaptive_intra_scaling_enable)
2939             {
2940                 *(data + 10) = (unsigned int)gen9_avc_adaptive_intra_scaling_factor[i];
2941             }else
2942             {
2943                 *(data + 10) = (unsigned int)gen9_avc_intra_scaling_factor[i];
2944
2945             }
2946             data += 16;
2947
2948         }
2949         break;
2950     default:
2951         assert(0);
2952     }
2953
2954     data = data_tmp;
2955     for(i = 0; i < 52 ; i++)
2956     {
2957         if(avc_state->ftq_skip_threshold_lut_input_enable)
2958         {
2959             *(data + 6) =  (avc_state->ftq_skip_threshold_lut[i] |
2960                 (avc_state->ftq_skip_threshold_lut[i] <<16) |
2961                 (avc_state->ftq_skip_threshold_lut[i] <<24) );
2962             *(data + 7) =  (avc_state->ftq_skip_threshold_lut[i] |
2963                 (avc_state->ftq_skip_threshold_lut[i] <<8) |
2964                 (avc_state->ftq_skip_threshold_lut[i] <<16) |
2965                 (avc_state->ftq_skip_threshold_lut[i] <<24) );
2966         }
2967
2968         if(avc_state->kernel_trellis_enable)
2969         {
2970             *(data + 11) = (unsigned int)avc_state->lamda_value_lut[i][0];
2971             *(data + 12) = (unsigned int)avc_state->lamda_value_lut[i][1];
2972
2973         }
2974         data += 16;
2975
2976     }
2977     i965_unmap_gpe_resource(gpe_resource);
2978 }
2979
2980 static void
2981 gen9_avc_set_curbe_mbenc(VADriverContextP ctx,
2982                          struct encode_state *encode_state,
2983                          struct i965_gpe_context *gpe_context,
2984                          struct intel_encoder_context *encoder_context,
2985                          void * param)
2986 {
2987     struct i965_driver_data *i965 = i965_driver_data(ctx);
2988     gen9_avc_mbenc_curbe_data *cmd;
2989     struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
2990     struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
2991     struct avc_enc_state * avc_state = (struct avc_enc_state * )vme_context->private_enc_state;
2992
2993     VAEncSliceParameterBufferH264 * slice_param = avc_state->slice_param[0];
2994     VAEncPictureParameterBufferH264  *pic_param = avc_state->pic_param;
2995     VASurfaceID surface_id;
2996     struct object_surface *obj_surface;
2997
2998     struct mbenc_param * curbe_param = (struct mbenc_param *)param ;
2999     unsigned char qp = 0;
3000     unsigned char me_method = 0;
3001     unsigned int mbenc_i_frame_dist_in_use = curbe_param->mbenc_i_frame_dist_in_use;
3002     unsigned int table_idx = 0;
3003
3004     unsigned int preset = generic_state->preset;
3005     me_method = (generic_state->frame_type == SLICE_TYPE_B)? gen9_avc_b_me_method[preset]:gen9_avc_p_me_method[preset];
3006     qp = pic_param->pic_init_qp + slice_param->slice_qp_delta;
3007
3008     cmd = (gen9_avc_mbenc_curbe_data *)i965_gpe_context_map_curbe(gpe_context);
3009
3010     if (!cmd)
3011         return;
3012
3013     memset(cmd,0,sizeof(gen9_avc_mbenc_curbe_data));
3014
3015     if(mbenc_i_frame_dist_in_use)
3016     {
3017         memcpy(cmd,gen9_avc_mbenc_curbe_i_frame_dist_init_data,sizeof(gen9_avc_mbenc_curbe_data));
3018
3019     }else
3020     {
3021         switch(generic_state->frame_type)
3022         {
3023         case SLICE_TYPE_I:
3024             memcpy(cmd,gen9_avc_mbenc_curbe_normal_i_frame_init_data,sizeof(gen9_avc_mbenc_curbe_data));
3025             break;
3026         case SLICE_TYPE_P:
3027             memcpy(cmd,gen9_avc_mbenc_curbe_normal_p_frame_init_data,sizeof(gen9_avc_mbenc_curbe_data));
3028             break;
3029         case SLICE_TYPE_B:
3030             memcpy(cmd,gen9_avc_mbenc_curbe_normal_b_frame_init_data,sizeof(gen9_avc_mbenc_curbe_data));
3031             break;
3032         default:
3033             assert(0);
3034         }
3035
3036     }
3037     cmd->dw0.adaptive_enable = gen9_avc_enable_adaptive_search[preset];
3038     cmd->dw37.adaptive_enable = gen9_avc_enable_adaptive_search[preset];
3039     cmd->dw0.t8x8_flag_for_inter_enable = pic_param->pic_fields.bits.transform_8x8_mode_flag;
3040     cmd->dw37.t8x8_flag_for_inter_enable = pic_param->pic_fields.bits.transform_8x8_mode_flag;
3041
3042     cmd->dw2.max_len_sp = gen9_avc_max_len_sp[preset];
3043     cmd->dw38.max_len_sp = 0;
3044
3045     cmd->dw3.src_access = 0;
3046     cmd->dw3.ref_access = 0;
3047
3048     if(avc_state->ftq_enable && (generic_state->frame_type != SLICE_TYPE_I))
3049     {
3050         if(avc_state->ftq_override)
3051         {
3052             cmd->dw3.ftq_enable = avc_state->ftq_enable;
3053
3054         }else
3055         {
3056             if(generic_state->frame_type == SLICE_TYPE_P)
3057             {
3058                 cmd->dw3.ftq_enable = gen9_avc_max_ftq_based_skip[preset] & 0x01;
3059
3060             }else
3061             {
3062                 cmd->dw3.ftq_enable = (gen9_avc_max_ftq_based_skip[preset] >> 1) & 0x01;
3063             }
3064         }
3065     }else
3066     {
3067         cmd->dw3.ftq_enable = 0;
3068     }
3069
3070     if(avc_state->disable_sub_mb_partion)
3071         cmd->dw3.sub_mb_part_mask = 0x7;
3072
3073     if(mbenc_i_frame_dist_in_use)
3074     {
3075         cmd->dw2.pitch_width = generic_state->downscaled_width_4x_in_mb;
3076         cmd->dw4.picture_height_minus1 = generic_state->downscaled_height_4x_in_mb - 1;
3077         cmd->dw5.slice_mb_height = (avc_state->slice_height + 4 - 1)/4;
3078         cmd->dw6.batch_buffer_end = 0;
3079         cmd->dw31.intra_compute_type = 1;
3080
3081     }else
3082     {
3083         cmd->dw2.pitch_width = generic_state->frame_width_in_mbs;
3084         cmd->dw4.picture_height_minus1 = generic_state->frame_height_in_mbs - 1;
3085         cmd->dw5.slice_mb_height = (avc_state->arbitrary_num_mbs_in_slice)?generic_state->frame_height_in_mbs:avc_state->slice_height;
3086
3087         {
3088             memcpy(&(cmd->dw8),gen9_avc_mode_mv_cost_table[slice_type_kernel[generic_state->frame_type]][qp],8*sizeof(unsigned int));
3089             if((generic_state->frame_type == SLICE_TYPE_I) && avc_state->old_mode_cost_enable)
3090             {
3091                 //cmd->dw8 = gen9_avc_old_intra_mode_cost[qp];
3092             }else if(avc_state->skip_bias_adjustment_enable)
3093             {
3094                 /* Load different MvCost for P picture when SkipBiasAdjustment is enabled
3095                 // No need to check for P picture as the flag is only enabled for P picture */
3096                 cmd->dw11.value = gen9_avc_mv_cost_p_skip_adjustment[qp];
3097
3098             }
3099         }
3100
3101         table_idx = (generic_state->frame_type == SLICE_TYPE_B)?1:0;
3102         memcpy(&(cmd->dw16),table_enc_search_path[table_idx][me_method],16*sizeof(unsigned int));
3103     }
3104     cmd->dw4.enable_fbr_bypass = avc_state->fbr_bypass_enable;
3105     cmd->dw4.enable_intra_cost_scaling_for_static_frame = avc_state->sfd_enable && generic_state->hme_enabled;
3106     cmd->dw4.field_parity_flag = 0;//bottom field
3107     cmd->dw4.enable_cur_fld_idr = 0;//field realted
3108     cmd->dw4.contrained_intra_pred_flag = pic_param->pic_fields.bits.constrained_intra_pred_flag;
3109     cmd->dw4.hme_enable = generic_state->hme_enabled;
3110     cmd->dw4.picture_type = slice_type_kernel[generic_state->frame_type];
3111     cmd->dw4.use_actual_ref_qp_value = generic_state->hme_enabled && (gen9_avc_mr_disable_qp_check[preset] == 0);
3112
3113
3114     cmd->dw7.intra_part_mask = pic_param->pic_fields.bits.transform_8x8_mode_flag?0:0x02;
3115     cmd->dw7.src_field_polarity = 0;//field related
3116
3117     /*ftq_skip_threshold_lut set,dw14 /15*/
3118
3119     /*r5 disable NonFTQSkipThresholdLUT*/
3120     if(generic_state->frame_type == SLICE_TYPE_P)
3121     {
3122         cmd->dw32.skip_val = gen9_avc_skip_value_p[avc_state->block_based_skip_enable][pic_param->pic_fields.bits.transform_8x8_mode_flag][qp];
3123
3124     }else if(generic_state->frame_type == SLICE_TYPE_B)
3125     {
3126         cmd->dw32.skip_val = gen9_avc_skip_value_b[avc_state->block_based_skip_enable][pic_param->pic_fields.bits.transform_8x8_mode_flag][qp];
3127
3128     }
3129
3130     cmd->dw13.qp_prime_y = qp;
3131     cmd->dw13.qp_prime_cb = qp;
3132     cmd->dw13.qp_prime_cr = qp;
3133     cmd->dw13.target_size_in_word = 0xff;//hardcode for brc disable
3134
3135
3136     if((generic_state->frame_type != SLICE_TYPE_I)&& avc_state->multi_pre_enable)
3137     {
3138         switch(gen9_avc_multi_pred[preset])
3139         {
3140         case 0:
3141             cmd->dw32.mult_pred_l0_disable = 128;
3142             cmd->dw32.mult_pred_l1_disable = 128;
3143             break;
3144         case 1:
3145             cmd->dw32.mult_pred_l0_disable = (generic_state->frame_type == SLICE_TYPE_P)?1:128;
3146             cmd->dw32.mult_pred_l1_disable = 128;
3147             break;
3148         case 2:
3149             cmd->dw32.mult_pred_l0_disable = (generic_state->frame_type == SLICE_TYPE_B)?1:128;
3150             cmd->dw32.mult_pred_l1_disable = (generic_state->frame_type == SLICE_TYPE_B)?1:128;
3151             break;
3152         case 3:
3153             cmd->dw32.mult_pred_l0_disable = 1;
3154             cmd->dw32.mult_pred_l1_disable = (generic_state->frame_type == SLICE_TYPE_B)?1:128;
3155             break;
3156
3157         }
3158
3159     }else
3160     {
3161         cmd->dw32.mult_pred_l0_disable = 128;
3162         cmd->dw32.mult_pred_l1_disable = 128;
3163     }
3164
3165     /*field setting for dw33 34, ignored*/
3166
3167     if(avc_state->adaptive_transform_decision_enable)
3168     {
3169         if(generic_state->frame_type != SLICE_TYPE_I)
3170         {
3171             cmd->dw34.enable_adaptive_tx_decision = 1;
3172         }
3173
3174         cmd->dw58.mb_texture_threshold = 1024;
3175         cmd->dw58.tx_decision_threshold = 128;
3176     }
3177
3178
3179     if(generic_state->frame_type == SLICE_TYPE_B)
3180     {
3181         cmd->dw34.list1_ref_id0_frm_field_parity = 0; //frame only
3182         cmd->dw34.list1_ref_id0_frm_field_parity = 0;
3183         cmd->dw34.b_direct_mode = slice_param->direct_spatial_mv_pred_flag;
3184     }
3185     cmd->dw34.b_original_bff = 0; //frame only
3186     cmd->dw34.enable_mb_flatness_check_optimization = avc_state->flatness_check_enable;
3187     cmd->dw34.roi_enable_flag = curbe_param->roi_enabled;
3188     cmd->dw34.mad_enable_falg = avc_state->mad_enable;
3189     cmd->dw34.mb_brc_enable = avc_state->mb_qp_data_enable || generic_state->mb_brc_enabled;
3190     cmd->dw34.arbitray_num_mbs_per_slice = avc_state->arbitrary_num_mbs_in_slice;
3191     cmd->dw34.force_non_skip_check = avc_state->mb_disable_skip_map_enable;
3192
3193     if(cmd->dw34.force_non_skip_check)
3194     {
3195        cmd->dw34.disable_enc_skip_check = avc_state->skip_check_disable;
3196     }
3197
3198     cmd->dw36.check_all_fractional_enable = avc_state->caf_enable;
3199     cmd->dw38.ref_threshold = 400;
3200     cmd->dw39.hme_ref_windows_comb_threshold = (generic_state->frame_type == SLICE_TYPE_B)?gen9_avc_hme_b_combine_len[preset]:gen9_avc_hme_combine_len[preset];
3201
3202     /* Default:2 used for MBBRC (MB QP Surface width and height are 4x downscaled picture in MB unit * 4  bytes)
3203        0 used for MBQP data surface (MB QP Surface width and height are same as the input picture size in MB unit * 1bytes)
3204        starting GEN9, BRC use split kernel, MB QP surface is same size as input picture */
3205     cmd->dw47.mb_qp_read_factor = (avc_state->mb_qp_data_enable || generic_state->mb_brc_enabled)?0:2;
3206
3207     if(mbenc_i_frame_dist_in_use)
3208     {
3209         cmd->dw13.qp_prime_y = 0;
3210         cmd->dw13.qp_prime_cb = 0;
3211         cmd->dw13.qp_prime_cr = 0;
3212         cmd->dw33.intra_16x16_nondc_penalty = 0;
3213         cmd->dw33.intra_8x8_nondc_penalty = 0;
3214         cmd->dw33.intra_4x4_nondc_penalty = 0;
3215
3216     }
3217     if(cmd->dw4.use_actual_ref_qp_value)
3218     {
3219         cmd->dw44.actual_qp_value_for_ref_id0_list0 =  gen9_avc_get_qp_from_ref_list(ctx,slice_param,0,0);
3220         cmd->dw44.actual_qp_value_for_ref_id1_list0 =  gen9_avc_get_qp_from_ref_list(ctx,slice_param,0,1);
3221         cmd->dw44.actual_qp_value_for_ref_id2_list0 =  gen9_avc_get_qp_from_ref_list(ctx,slice_param,0,2);
3222         cmd->dw44.actual_qp_value_for_ref_id3_list0 =  gen9_avc_get_qp_from_ref_list(ctx,slice_param,0,3);
3223         cmd->dw45.actual_qp_value_for_ref_id4_list0 =  gen9_avc_get_qp_from_ref_list(ctx,slice_param,0,4);
3224         cmd->dw45.actual_qp_value_for_ref_id5_list0 =  gen9_avc_get_qp_from_ref_list(ctx,slice_param,0,5);
3225         cmd->dw45.actual_qp_value_for_ref_id6_list0 =  gen9_avc_get_qp_from_ref_list(ctx,slice_param,0,6);
3226         cmd->dw45.actual_qp_value_for_ref_id7_list0 =  gen9_avc_get_qp_from_ref_list(ctx,slice_param,0,7);
3227         cmd->dw46.actual_qp_value_for_ref_id0_list1 =  gen9_avc_get_qp_from_ref_list(ctx,slice_param,1,0);
3228         cmd->dw46.actual_qp_value_for_ref_id1_list1 =  gen9_avc_get_qp_from_ref_list(ctx,slice_param,1,1);
3229     }
3230
3231     table_idx = slice_type_kernel[generic_state->frame_type];
3232     cmd->dw46.ref_cost = gen9_avc_ref_cost[table_idx][qp];
3233
3234     if(generic_state->frame_type == SLICE_TYPE_I)
3235     {
3236         cmd->dw0.skip_mode_enable = 0;
3237         cmd->dw37.skip_mode_enable = 0;
3238         cmd->dw36.hme_combine_overlap = 0;
3239         cmd->dw47.intra_cost_sf = 16;
3240         cmd->dw34.enable_direct_bias_adjustment = 0;
3241         cmd->dw34.enable_global_motion_bias_adjustment = 0;
3242
3243     }else if(generic_state->frame_type == SLICE_TYPE_P)
3244     {
3245         cmd->dw1.max_num_mvs = i965_avc_get_max_mv_per_2mb(avc_state->seq_param->level_idc)/2;
3246         cmd->dw3.bme_disable_fbr = 1;
3247         cmd->dw5.ref_width = gen9_avc_search_x[preset];
3248         cmd->dw5.ref_height = gen9_avc_search_y[preset];
3249         cmd->dw7.non_skip_zmv_added = 1;
3250         cmd->dw7.non_skip_mode_added = 1;
3251         cmd->dw7.skip_center_mask = 1;
3252         cmd->dw47.intra_cost_sf = (avc_state->adaptive_intra_scaling_enable)?gen9_avc_adaptive_intra_scaling_factor[qp]:gen9_avc_intra_scaling_factor[qp];
3253         cmd->dw47.max_vmv_r = i965_avc_get_max_mv_len(avc_state->seq_param->level_idc) * 4;//frame onlys
3254         cmd->dw36.hme_combine_overlap = 1;
3255         cmd->dw36.num_ref_idx_l0_minus_one = (avc_state->multi_pre_enable)?slice_param->num_ref_idx_l0_active_minus1:0;
3256         cmd->dw39.ref_width = gen9_avc_search_x[preset];
3257         cmd->dw39.ref_height = gen9_avc_search_y[preset];
3258         cmd->dw34.enable_direct_bias_adjustment = 0;
3259         cmd->dw34.enable_global_motion_bias_adjustment = avc_state->global_motion_bias_adjustment_enable;
3260         if(avc_state->global_motion_bias_adjustment_enable)
3261             cmd->dw59.hme_mv_cost_scaling_factor = avc_state->hme_mv_cost_scaling_factor;
3262
3263     }else
3264     {
3265         cmd->dw1.max_num_mvs = i965_avc_get_max_mv_per_2mb(avc_state->seq_param->level_idc)/2;
3266         cmd->dw1.bi_weight = avc_state->bi_weight;
3267         cmd->dw3.search_ctrl = 7;
3268         cmd->dw3.skip_type = 1;
3269         cmd->dw5.ref_width = gen9_avc_b_search_x[preset];
3270         cmd->dw5.ref_height = gen9_avc_b_search_y[preset];
3271         cmd->dw7.skip_center_mask = 0xff;
3272         cmd->dw47.intra_cost_sf = (avc_state->adaptive_intra_scaling_enable)?gen9_avc_adaptive_intra_scaling_factor[qp]:gen9_avc_intra_scaling_factor[qp];
3273         cmd->dw47.max_vmv_r = i965_avc_get_max_mv_len(avc_state->seq_param->level_idc) * 4;//frame only
3274         cmd->dw36.hme_combine_overlap = 1;
3275         surface_id = slice_param->RefPicList1[0].picture_id;
3276         obj_surface = SURFACE(surface_id);
3277         if (!obj_surface)
3278         {
3279             WARN_ONCE("Invalid backward reference frame\n");
3280             return;
3281         }
3282         cmd->dw36.is_fwd_frame_short_term_ref = !!( slice_param->RefPicList1[0].flags & VA_PICTURE_H264_SHORT_TERM_REFERENCE);
3283
3284         cmd->dw36.num_ref_idx_l0_minus_one = (avc_state->multi_pre_enable)?slice_param->num_ref_idx_l0_active_minus1:0;
3285         cmd->dw36.num_ref_idx_l1_minus_one = (avc_state->multi_pre_enable)?slice_param->num_ref_idx_l1_active_minus1:0;
3286         cmd->dw39.ref_width = gen9_avc_b_search_x[preset];
3287         cmd->dw39.ref_height = gen9_avc_b_search_y[preset];
3288         cmd->dw40.dist_scale_factor_ref_id0_list0 = avc_state->dist_scale_factor_list0[0];
3289         cmd->dw40.dist_scale_factor_ref_id1_list0 = avc_state->dist_scale_factor_list0[1];
3290         cmd->dw41.dist_scale_factor_ref_id2_list0 = avc_state->dist_scale_factor_list0[2];
3291         cmd->dw41.dist_scale_factor_ref_id3_list0 = avc_state->dist_scale_factor_list0[3];
3292         cmd->dw42.dist_scale_factor_ref_id4_list0 = avc_state->dist_scale_factor_list0[4];
3293         cmd->dw42.dist_scale_factor_ref_id5_list0 = avc_state->dist_scale_factor_list0[5];
3294         cmd->dw43.dist_scale_factor_ref_id6_list0 = avc_state->dist_scale_factor_list0[6];
3295         cmd->dw43.dist_scale_factor_ref_id7_list0 = avc_state->dist_scale_factor_list0[7];
3296
3297         cmd->dw34.enable_direct_bias_adjustment = avc_state->direct_bias_adjustment_enable;
3298         if(cmd->dw34.enable_direct_bias_adjustment)
3299         {
3300             cmd->dw7.non_skip_zmv_added = 1;
3301             cmd->dw7.non_skip_mode_added = 1;
3302         }
3303
3304         cmd->dw34.enable_global_motion_bias_adjustment = avc_state->global_motion_bias_adjustment_enable;
3305         if(avc_state->global_motion_bias_adjustment_enable)
3306             cmd->dw59.hme_mv_cost_scaling_factor = avc_state->hme_mv_cost_scaling_factor;
3307
3308     }
3309
3310     avc_state->block_based_skip_enable = cmd->dw3.block_based_skip_enable;
3311
3312     if(avc_state->rolling_intra_refresh_enable)
3313     {
3314         /*by now disable it*/
3315         cmd->dw34.widi_intra_refresh_en = avc_state->rolling_intra_refresh_enable;
3316
3317     }else
3318     {
3319         cmd->dw34.widi_intra_refresh_en = 0;
3320     }
3321
3322     cmd->dw34.enable_per_mb_static_check = avc_state->sfd_enable && generic_state->hme_enabled;
3323     cmd->dw34.enable_adaptive_search_window_size = avc_state->adaptive_search_window_enable;
3324
3325     /*roi set disable by now. 49-56*/
3326     if(curbe_param->roi_enabled)
3327     {
3328         cmd->dw49.roi_1_x_left   = generic_state->roi[0].left;
3329         cmd->dw49.roi_1_y_top    = generic_state->roi[0].top;
3330         cmd->dw50.roi_1_x_right  = generic_state->roi[0].right;
3331         cmd->dw50.roi_1_y_bottom = generic_state->roi[0].bottom;
3332
3333         cmd->dw51.roi_2_x_left   = generic_state->roi[1].left;
3334         cmd->dw51.roi_2_y_top    = generic_state->roi[1].top;
3335         cmd->dw52.roi_2_x_right  = generic_state->roi[1].right;
3336         cmd->dw52.roi_2_y_bottom = generic_state->roi[1].bottom;
3337
3338         cmd->dw53.roi_3_x_left   = generic_state->roi[2].left;
3339         cmd->dw53.roi_3_y_top    = generic_state->roi[2].top;
3340         cmd->dw54.roi_3_x_right  = generic_state->roi[2].right;
3341         cmd->dw54.roi_3_y_bottom = generic_state->roi[2].bottom;
3342
3343         cmd->dw55.roi_4_x_left   = generic_state->roi[3].left;
3344         cmd->dw55.roi_4_y_top    = generic_state->roi[3].top;
3345         cmd->dw56.roi_4_x_right  = generic_state->roi[3].right;
3346         cmd->dw56.roi_4_y_bottom = generic_state->roi[3].bottom;
3347
3348         if(!generic_state->brc_enabled)
3349         {
3350             char tmp = 0;
3351             tmp = generic_state->roi[0].value;
3352             CLIP(tmp,-qp,52-qp);
3353             cmd->dw57.roi_1_dqp_prime_y = tmp;
3354             tmp = generic_state->roi[1].value;
3355             CLIP(tmp,-qp,52-qp);
3356             cmd->dw57.roi_2_dqp_prime_y = tmp;
3357             tmp = generic_state->roi[2].value;
3358             CLIP(tmp,-qp,52-qp);
3359             cmd->dw57.roi_3_dqp_prime_y = tmp;
3360             tmp = generic_state->roi[3].value;
3361             CLIP(tmp,-qp,52-qp);
3362             cmd->dw57.roi_4_dqp_prime_y = tmp;
3363         }else
3364         {
3365             cmd->dw34.roi_enable_flag = 0;
3366         }
3367     }
3368
3369     cmd->dw64.mb_data_surf_index = GEN9_AVC_MBENC_MFC_AVC_PAK_OBJ_INDEX;
3370     cmd->dw65.mv_data_surf_index = GEN9_AVC_MBENC_IND_MV_DATA_INDEX;
3371     cmd->dw66.i_dist_surf_index = GEN9_AVC_MBENC_BRC_DISTORTION_INDEX;
3372     cmd->dw67.src_y_surf_index = GEN9_AVC_MBENC_CURR_Y_INDEX;
3373     cmd->dw68.mb_specific_data_surf_index = GEN9_AVC_MBENC_MB_SPECIFIC_DATA_INDEX;
3374     cmd->dw69.aux_vme_out_surf_index = GEN9_AVC_MBENC_AUX_VME_OUT_INDEX;
3375     cmd->dw70.curr_ref_pic_sel_surf_index = GEN9_AVC_MBENC_REFPICSELECT_L0_INDEX;
3376     cmd->dw71.hme_mv_pred_fwd_bwd_surf_index = GEN9_AVC_MBENC_MV_DATA_FROM_ME_INDEX;
3377     cmd->dw72.hme_dist_surf_index = GEN9_AVC_MBENC_4XME_DISTORTION_INDEX;
3378     cmd->dw73.slice_map_surf_index = GEN9_AVC_MBENC_SLICEMAP_DATA_INDEX;
3379     cmd->dw74.fwd_frm_mb_data_surf_index = GEN9_AVC_MBENC_FWD_MB_DATA_INDEX;
3380     cmd->dw75.fwd_frm_mv_surf_index = GEN9_AVC_MBENC_FWD_MV_DATA_INDEX;
3381     cmd->dw76.mb_qp_buffer = GEN9_AVC_MBENC_MBQP_INDEX;
3382     cmd->dw77.mb_brc_lut = GEN9_AVC_MBENC_MBBRC_CONST_DATA_INDEX;
3383     cmd->dw78.vme_inter_prediction_surf_index = GEN9_AVC_MBENC_VME_INTER_PRED_CURR_PIC_IDX_0_INDEX;
3384     cmd->dw79.vme_inter_prediction_mr_surf_index = GEN9_AVC_MBENC_VME_INTER_PRED_CURR_PIC_IDX_1_INDEX;
3385     cmd->dw80.mb_stats_surf_index = GEN9_AVC_MBENC_MB_STATS_INDEX;
3386     cmd->dw81.mad_surf_index = GEN9_AVC_MBENC_MAD_DATA_INDEX;
3387     cmd->dw82.force_non_skip_mb_map_surface = GEN9_AVC_MBENC_FORCE_NONSKIP_MB_MAP_INDEX;
3388     cmd->dw83.widi_wa_surf_index = GEN9_AVC_MBENC_WIDI_WA_INDEX;
3389     cmd->dw84.brc_curbe_surf_index = GEN9_AVC_MBENC_BRC_CURBE_DATA_INDEX;
3390     cmd->dw85.static_detection_cost_table_index = GEN9_AVC_MBENC_SFD_COST_TABLE_INDEX;
3391
3392     i965_gpe_context_unmap_curbe(gpe_context);
3393
3394     return;
3395 }
3396
3397 static void
3398 gen9_avc_send_surface_mbenc(VADriverContextP ctx,
3399                             struct encode_state *encode_state,
3400                             struct i965_gpe_context *gpe_context,
3401                             struct intel_encoder_context *encoder_context,
3402                             void * param_mbenc)
3403 {
3404     struct i965_driver_data *i965 = i965_driver_data(ctx);
3405     struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
3406     struct i965_avc_encoder_context * avc_ctx = (struct i965_avc_encoder_context * )vme_context->private_enc_ctx;
3407     struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
3408     struct avc_enc_state * avc_state = (struct avc_enc_state * )vme_context->private_enc_state;
3409     struct object_surface *obj_surface;
3410     struct gen9_surface_avc *avc_priv_surface;
3411     struct i965_gpe_resource *gpe_resource;
3412     struct mbenc_param * param = (struct mbenc_param *)param_mbenc ;
3413      VASurfaceID surface_id;
3414     unsigned int mbenc_i_frame_dist_in_use = param->mbenc_i_frame_dist_in_use;
3415     unsigned int size = 0;
3416     unsigned int w_mb = generic_state->frame_width_in_mbs;
3417     unsigned int h_mb = generic_state->frame_height_in_mbs;
3418     int i = 0;
3419     VAEncSliceParameterBufferH264 * slice_param = avc_state->slice_param[0];
3420
3421     obj_surface = encode_state->reconstructed_object;
3422
3423     if (!obj_surface || !obj_surface->private_data)
3424         return;
3425     avc_priv_surface = obj_surface->private_data;
3426
3427     /*pak obj command buffer output*/
3428     size = w_mb * h_mb * 16 * 4;
3429     gpe_resource = &avc_priv_surface->res_mb_code_surface;
3430     gen9_add_buffer_gpe_surface(ctx,
3431                                 gpe_context,
3432                                 gpe_resource,
3433                                 0,
3434                                 size / 4,
3435                                 0,
3436                                 GEN9_AVC_MBENC_MFC_AVC_PAK_OBJ_INDEX);
3437
3438     /*mv data buffer output*/
3439     size = w_mb * h_mb * 32 * 4;
3440     gpe_resource = &avc_priv_surface->res_mv_data_surface;
3441     gen9_add_buffer_gpe_surface(ctx,
3442                                 gpe_context,
3443                                 gpe_resource,
3444                                 0,
3445                                 size / 4,
3446                                 0,
3447                                 GEN9_AVC_MBENC_IND_MV_DATA_INDEX);
3448
3449     /*input current  YUV surface, current input Y/UV object*/
3450     if(mbenc_i_frame_dist_in_use)
3451     {
3452         obj_surface = encode_state->reconstructed_object;
3453         if (!obj_surface || !obj_surface->private_data)
3454             return;
3455         avc_priv_surface = obj_surface->private_data;
3456         obj_surface = avc_priv_surface->scaled_4x_surface_obj;
3457     }else
3458     {
3459         obj_surface = encode_state->input_yuv_object;
3460     }
3461     gen9_add_2d_gpe_surface(ctx,
3462                             gpe_context,
3463                             obj_surface,
3464                             0,
3465                             1,
3466                             I965_SURFACEFORMAT_R8_UNORM,
3467                             GEN9_AVC_MBENC_CURR_Y_INDEX);
3468
3469     gen9_add_2d_gpe_surface(ctx,
3470                             gpe_context,
3471                             obj_surface,
3472                             1,
3473                             1,
3474                             I965_SURFACEFORMAT_R16_UINT,
3475                             GEN9_AVC_MBENC_CURR_UV_INDEX);
3476
3477     if(generic_state->hme_enabled)
3478     {
3479         /*memv input 4x*/
3480         gpe_resource = &(avc_ctx->s4x_memv_data_buffer);
3481         gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
3482                                        gpe_resource,
3483                                        1,
3484                                        I965_SURFACEFORMAT_R8_UNORM,
3485                                        GEN9_AVC_MBENC_MV_DATA_FROM_ME_INDEX);
3486         /* memv distortion input*/
3487         gpe_resource = &(avc_ctx->s4x_memv_distortion_buffer);
3488         gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
3489                                        gpe_resource,
3490                                        1,
3491                                        I965_SURFACEFORMAT_R8_UNORM,
3492                                        GEN9_AVC_MBENC_4XME_DISTORTION_INDEX);
3493     }
3494
3495     /*mbbrc const data_buffer*/
3496     if(param->mb_const_data_buffer_in_use)
3497     {
3498         size = 16 * 52 * sizeof(unsigned int);
3499         gpe_resource = &avc_ctx->res_mbbrc_const_data_buffer;
3500         gen9_add_buffer_gpe_surface(ctx,
3501                                     gpe_context,
3502                                     gpe_resource,
3503                                     0,
3504                                     size / 4,
3505                                     0,
3506                                     GEN9_AVC_MBENC_MBBRC_CONST_DATA_INDEX);
3507
3508     }
3509
3510     /*mb qp data_buffer*/
3511     if(param->mb_qp_buffer_in_use)
3512     {
3513         if(avc_state->mb_qp_data_enable)
3514             gpe_resource = &(avc_ctx->res_mb_qp_data_surface);
3515         else
3516             gpe_resource = &(avc_ctx->res_mbbrc_mb_qp_data_surface);
3517         gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
3518                                        gpe_resource,
3519                                        1,
3520                                        I965_SURFACEFORMAT_R8_UNORM,
3521                                        GEN9_AVC_MBENC_MBQP_INDEX);
3522     }
3523
3524     /*input current  YUV surface, current input Y/UV object*/
3525     if(mbenc_i_frame_dist_in_use)
3526     {
3527         obj_surface = encode_state->reconstructed_object;
3528         if (!obj_surface || !obj_surface->private_data)
3529             return;
3530         avc_priv_surface = obj_surface->private_data;
3531         obj_surface = avc_priv_surface->scaled_4x_surface_obj;
3532     }else
3533     {
3534         obj_surface = encode_state->input_yuv_object;
3535     }
3536     gen9_add_adv_gpe_surface(ctx, gpe_context,
3537                              obj_surface,
3538                              GEN9_AVC_MBENC_VME_INTER_PRED_CURR_PIC_IDX_0_INDEX);
3539     /*input ref YUV surface*/
3540     for(i = 0; i < slice_param->num_ref_idx_l0_active_minus1 + 1; i++)
3541     {
3542         surface_id = slice_param->RefPicList0[i].picture_id;
3543         obj_surface = SURFACE(surface_id);
3544         if (!obj_surface || !obj_surface->private_data)
3545             break;
3546
3547         gen9_add_adv_gpe_surface(ctx, gpe_context,
3548                                  obj_surface,
3549                                  GEN9_AVC_MBENC_VME_INTER_PRED_CURR_PIC_IDX_0_INDEX+i*2 + 1);
3550     }
3551     /*input current  YUV surface, current input Y/UV object*/
3552     if(mbenc_i_frame_dist_in_use)
3553     {
3554         obj_surface = encode_state->reconstructed_object;
3555         if (!obj_surface || !obj_surface->private_data)
3556             return;
3557         avc_priv_surface = obj_surface->private_data;
3558         obj_surface = avc_priv_surface->scaled_4x_surface_obj;
3559     }else
3560     {
3561         obj_surface = encode_state->input_yuv_object;
3562     }
3563     gen9_add_adv_gpe_surface(ctx, gpe_context,
3564                              obj_surface,
3565                              GEN9_AVC_MBENC_VME_INTER_PRED_CURR_PIC_IDX_1_INDEX);
3566
3567     for(i = 0; i < slice_param->num_ref_idx_l1_active_minus1 + 1; i++)
3568     {
3569         if(i > 0) break;// only  one ref supported here for B frame
3570         surface_id = slice_param->RefPicList1[i].picture_id;
3571         obj_surface = SURFACE(surface_id);
3572         if (!obj_surface || !obj_surface->private_data)
3573             break;
3574
3575         gen9_add_adv_gpe_surface(ctx, gpe_context,
3576                                  obj_surface,
3577                                  GEN9_AVC_MBENC_VME_INTER_PRED_CURR_PIC_IDX_1_INDEX+i*2 + 1);
3578         gen9_add_adv_gpe_surface(ctx, gpe_context,
3579                                  obj_surface,
3580                                  GEN9_AVC_MBENC_VME_INTER_PRED_CURR_PIC_IDX_0_INDEX+i*2 + 2);
3581         if(i == 0)
3582         {
3583             avc_priv_surface = obj_surface->private_data;
3584             /*pak obj command buffer output(mb code)*/
3585             size = w_mb * h_mb * 16 * 4;
3586             gpe_resource = &avc_priv_surface->res_mb_code_surface;
3587             gen9_add_buffer_gpe_surface(ctx,
3588                                         gpe_context,
3589                                         gpe_resource,
3590                                         0,
3591                                         size / 4,
3592                                         0,
3593                                         GEN9_AVC_MBENC_FWD_MB_DATA_INDEX);
3594
3595             /*mv data buffer output*/
3596             size = w_mb * h_mb * 32 * 4;
3597             gpe_resource = &avc_priv_surface->res_mv_data_surface;
3598             gen9_add_buffer_gpe_surface(ctx,
3599                                         gpe_context,
3600                                         gpe_resource,
3601                                         0,
3602                                         size / 4,
3603                                         0,
3604                                         GEN9_AVC_MBENC_FWD_MV_DATA_INDEX);
3605
3606         }
3607
3608         if( i < INTEL_AVC_MAX_BWD_REF_NUM)
3609         {
3610             gen9_add_adv_gpe_surface(ctx, gpe_context,
3611                                      obj_surface,
3612                                      GEN9_AVC_MBENC_VME_INTER_PRED_CURR_PIC_IDX_1_INDEX+i*2 + 1 + INTEL_AVC_MAX_BWD_REF_NUM);
3613         }
3614
3615     }
3616
3617     /* BRC distortion data buffer for I frame*/
3618     if(mbenc_i_frame_dist_in_use)
3619     {
3620         gpe_resource = &(avc_ctx->res_brc_dist_data_surface);
3621         gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
3622                                        gpe_resource,
3623                                        1,
3624                                        I965_SURFACEFORMAT_R8_UNORM,
3625                                        GEN9_AVC_MBENC_BRC_DISTORTION_INDEX);
3626     }
3627
3628     /* as ref frame ,update later RefPicSelect of Current Picture*/
3629     obj_surface = encode_state->reconstructed_object;
3630     avc_priv_surface = obj_surface->private_data;
3631     if(avc_state->ref_pic_select_list_supported && avc_priv_surface->is_as_ref)
3632     {
3633         gpe_resource = &(avc_priv_surface->res_ref_pic_select_surface);
3634         gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
3635                                        gpe_resource,
3636                                        1,
3637                                        I965_SURFACEFORMAT_R8_UNORM,
3638                                        GEN9_AVC_MBENC_REFPICSELECT_L0_INDEX);
3639
3640     }
3641
3642     if(param->mb_vproc_stats_enable)
3643     {
3644         /*mb status buffer input*/
3645         size = w_mb * h_mb * 16 * 4;
3646         gpe_resource = &(avc_ctx->res_mb_status_buffer);
3647         gen9_add_buffer_gpe_surface(ctx,
3648                                     gpe_context,
3649                                     gpe_resource,
3650                                     0,
3651                                     size / 4,
3652                                     0,
3653                                     GEN9_AVC_MBENC_MB_STATS_INDEX);
3654
3655     }else if(avc_state->flatness_check_enable)
3656     {
3657
3658         gpe_resource = &(avc_ctx->res_flatness_check_surface);
3659         gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
3660                                        gpe_resource,
3661                                        1,
3662                                        I965_SURFACEFORMAT_R8_UNORM,
3663                                        GEN9_AVC_MBENC_MB_STATS_INDEX);
3664     }
3665
3666     if(param->mad_enable)
3667     {
3668         /*mad buffer input*/
3669         size = 4;
3670         gpe_resource = &(avc_ctx->res_mad_data_buffer);
3671         gen9_add_buffer_gpe_surface(ctx,
3672                                     gpe_context,
3673                                     gpe_resource,
3674                                     0,
3675                                     size / 4,
3676                                     0,
3677                                     GEN9_AVC_MBENC_MAD_DATA_INDEX);
3678         i965_zero_gpe_resource(gpe_resource);
3679     }
3680
3681     /*brc updated mbenc curbe data buffer,it is ignored*/
3682
3683     /*artitratry num mbs in slice*/
3684     if(avc_state->arbitrary_num_mbs_in_slice)
3685     {
3686         /*slice surface input*/
3687         gpe_resource = &(avc_ctx->res_mbenc_slice_map_surface);
3688         gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
3689                                        gpe_resource,
3690                                        1,
3691                                        I965_SURFACEFORMAT_R8_UNORM,
3692                                        GEN9_AVC_MBENC_SLICEMAP_DATA_INDEX);
3693     }
3694
3695     /* BRC distortion data buffer for I frame */
3696     if(!mbenc_i_frame_dist_in_use)
3697     {
3698         if(avc_state->mb_disable_skip_map_enable)
3699         {
3700             gpe_resource = &(avc_ctx->res_mb_disable_skip_map_surface);
3701             gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
3702                                            gpe_resource,
3703                                            1,
3704                                            I965_SURFACEFORMAT_R8_UNORM,
3705                                            GEN9_AVC_MBENC_FORCE_NONSKIP_MB_MAP_INDEX);
3706         }
3707
3708         if(avc_state->sfd_enable && generic_state->hme_enabled)
3709         {
3710             if(generic_state->frame_type == SLICE_TYPE_P)
3711             {
3712                 gpe_resource = &(avc_ctx->res_sfd_cost_table_p_frame_buffer);
3713
3714             }else if(generic_state->frame_type == SLICE_TYPE_B)
3715             {
3716                 gpe_resource = &(avc_ctx->res_sfd_cost_table_b_frame_buffer);
3717             }
3718
3719             if(generic_state->frame_type != SLICE_TYPE_I)
3720             {
3721                 gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
3722                                                gpe_resource,
3723                                                1,
3724                                                I965_SURFACEFORMAT_R8_UNORM,
3725                                                GEN9_AVC_MBENC_SFD_COST_TABLE_INDEX);
3726             }
3727         }
3728     }
3729
3730     return;
3731 }
3732
3733 static VAStatus
3734 gen9_avc_kernel_mbenc(VADriverContextP ctx,
3735                       struct encode_state *encode_state,
3736                       struct intel_encoder_context *encoder_context,
3737                       bool i_frame_dist_in_use)
3738 {
3739     struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
3740     struct generic_encoder_context * generic_ctx = (struct generic_encoder_context * )vme_context->generic_enc_ctx;
3741     struct i965_avc_encoder_context * avc_ctx = (struct i965_avc_encoder_context * )vme_context->private_enc_ctx;
3742     struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
3743     struct avc_enc_state * avc_state = (struct avc_enc_state * )vme_context->private_enc_state;
3744
3745     struct i965_gpe_context *gpe_context;
3746     struct gpe_media_object_walker_parameter media_object_walker_param;
3747     struct gpe_encoder_kernel_walker_parameter kernel_walker_param;
3748     unsigned int downscaled_width_in_mb, downscaled_height_in_mb;
3749     int media_function = 0;
3750     int kernel_idx = 0;
3751     unsigned int mb_const_data_buffer_in_use = 0;
3752     unsigned int mb_qp_buffer_in_use = 0;
3753     unsigned int brc_enabled = 0;
3754     unsigned int roi_enable = (generic_state->num_roi > 0)?1:0;
3755     unsigned int dirty_roi_enable = ((generic_state->dirty_num_roi > 0) && (generic_state->frame_type == SLICE_TYPE_P) && (0));
3756     struct mbenc_param param ;
3757
3758     int mbenc_i_frame_dist_in_use = i_frame_dist_in_use;
3759     int mad_enable = 0;
3760     VAEncSliceParameterBufferH264 * slice_param = avc_state->slice_param[0];
3761
3762     mb_const_data_buffer_in_use =
3763         generic_state->mb_brc_enabled ||
3764         roi_enable ||
3765         dirty_roi_enable ||
3766         avc_state->mb_qp_data_enable ||
3767         avc_state->rolling_intra_refresh_enable;
3768     mb_qp_buffer_in_use =
3769         generic_state->mb_brc_enabled ||
3770         generic_state->brc_roi_enable ||
3771         avc_state->mb_qp_data_enable;
3772
3773     if(mbenc_i_frame_dist_in_use)
3774     {
3775         media_function = INTEL_MEDIA_STATE_ENC_I_FRAME_DIST;
3776         kernel_idx = GEN9_AVC_KERNEL_BRC_I_FRAME_DIST;
3777         downscaled_width_in_mb = generic_state->downscaled_width_4x_in_mb;
3778         downscaled_height_in_mb = generic_state->downscaled_height_4x_in_mb;
3779         mad_enable = 0;
3780         brc_enabled = 0;
3781
3782         gpe_context = &(avc_ctx->context_brc.gpe_contexts[kernel_idx]);
3783     }else
3784     {
3785         switch(generic_state->kernel_mode)
3786         {
3787         case INTEL_ENC_KERNEL_NORMAL :
3788             {
3789                 media_function = INTEL_MEDIA_STATE_ENC_NORMAL;
3790                 kernel_idx = MBENC_KERNEL_BASE + GEN9_AVC_KERNEL_MBENC_NORMAL_I;
3791                 break;
3792             }
3793         case INTEL_ENC_KERNEL_PERFORMANCE :
3794             {
3795                 media_function = INTEL_MEDIA_STATE_ENC_PERFORMANCE;
3796                 kernel_idx = MBENC_KERNEL_BASE + GEN9_AVC_KERNEL_MBENC_PERFORMANCE_I;
3797                 break;
3798             }
3799         case INTEL_ENC_KERNEL_QUALITY :
3800             {
3801                 media_function = INTEL_MEDIA_STATE_ENC_QUALITY;
3802                 kernel_idx = MBENC_KERNEL_BASE + GEN9_AVC_KERNEL_MBENC_QUALITY_I;
3803                 break;
3804             }
3805         default:
3806             assert(0);
3807
3808         }
3809
3810         if(generic_state->frame_type == SLICE_TYPE_P)
3811         {
3812            kernel_idx += 1;
3813         }
3814         else if(generic_state->frame_type == SLICE_TYPE_B)
3815         {
3816            kernel_idx += 2;
3817         }
3818
3819         downscaled_width_in_mb = generic_state->frame_width_in_mbs;
3820         downscaled_height_in_mb = generic_state->frame_height_in_mbs;
3821         mad_enable = avc_state->mad_enable;
3822         brc_enabled = generic_state->brc_enabled;
3823
3824         gpe_context = &(avc_ctx->context_mbenc.gpe_contexts[kernel_idx]);
3825     }
3826
3827     memset(&param,0,sizeof(struct mbenc_param));
3828
3829     param.mb_const_data_buffer_in_use = mb_const_data_buffer_in_use;
3830     param.mb_qp_buffer_in_use = mb_qp_buffer_in_use;
3831     param.mbenc_i_frame_dist_in_use = mbenc_i_frame_dist_in_use;
3832     param.mad_enable = mad_enable;
3833     param.brc_enabled = brc_enabled;
3834     param.roi_enabled = roi_enable;
3835
3836     if(avc_state->mb_status_supported)
3837     {
3838         param.mb_vproc_stats_enable =  avc_state->flatness_check_enable || avc_state->adaptive_transform_decision_enable;
3839     }
3840
3841     if(!avc_state->mbenc_curbe_set_in_brc_update)
3842     {
3843         gen8_gpe_context_init(ctx, gpe_context);
3844     }
3845
3846     gen9_gpe_reset_binding_table(ctx, gpe_context);
3847
3848     if(!avc_state->mbenc_curbe_set_in_brc_update)
3849     {
3850         /*set curbe here*/
3851         generic_ctx->pfn_set_curbe_mbenc(ctx,encode_state,gpe_context,encoder_context,&param);
3852     }
3853
3854     /* MB brc const data buffer set up*/
3855     if(mb_const_data_buffer_in_use)
3856     {
3857         gen9_avc_load_mb_brc_const_data(ctx,encode_state,encoder_context);
3858     }
3859
3860     /*clear the mad buffer*/
3861     if(mad_enable)
3862     {
3863         i965_zero_gpe_resource(&(avc_ctx->res_mad_data_buffer));
3864     }
3865     /*send surface*/
3866     generic_ctx->pfn_send_mbenc_surface(ctx,encode_state,gpe_context,encoder_context,&param);
3867
3868     gen8_gpe_setup_interface_data(ctx, gpe_context);
3869
3870     /*walker setting*/
3871     memset(&kernel_walker_param, 0, sizeof(kernel_walker_param));
3872
3873     kernel_walker_param.use_scoreboard = 1;
3874     kernel_walker_param.resolution_x = downscaled_width_in_mb ;
3875     kernel_walker_param.resolution_y = downscaled_height_in_mb ;
3876     if(mbenc_i_frame_dist_in_use)
3877     {
3878         kernel_walker_param.no_dependency = 1;
3879     }else
3880     {
3881         switch(generic_state->frame_type)
3882         {
3883         case SLICE_TYPE_I:
3884             kernel_walker_param.walker_degree = WALKER_45_DEGREE;
3885             break;
3886         case SLICE_TYPE_P:
3887             kernel_walker_param.walker_degree = WALKER_26_DEGREE;
3888             break;
3889         case SLICE_TYPE_B:
3890             kernel_walker_param.walker_degree = WALKER_26_DEGREE;
3891             if(!slice_param->direct_spatial_mv_pred_flag)
3892             {
3893                 kernel_walker_param.walker_degree = WALKER_45_DEGREE;
3894             }
3895             break;
3896         default:
3897             assert(0);
3898         }
3899         kernel_walker_param.no_dependency = 0;
3900     }
3901
3902     i965_init_media_object_walker_parameter(&kernel_walker_param, &media_object_walker_param);
3903
3904     gen9_avc_run_kernel_media_object_walker(ctx, encoder_context,
3905                                         gpe_context,
3906                                         media_function,
3907                                         &media_object_walker_param);
3908     return VA_STATUS_SUCCESS;
3909 }
3910
3911 /*
3912 me kernle related function
3913 */
3914 static void
3915 gen9_avc_set_curbe_me(VADriverContextP ctx,
3916                       struct encode_state *encode_state,
3917                       struct i965_gpe_context *gpe_context,
3918                       struct intel_encoder_context *encoder_context,
3919                       void * param)
3920 {
3921     gen9_avc_me_curbe_data *curbe_cmd;
3922     struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
3923     struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
3924     struct avc_enc_state * avc_state = (struct avc_enc_state * )vme_context->private_enc_state;
3925
3926     VAEncSliceParameterBufferH264 * slice_param = avc_state->slice_param[0];
3927
3928     struct me_param * curbe_param = (struct me_param *)param ;
3929     unsigned char  use_mv_from_prev_step = 0;
3930     unsigned char write_distortions = 0;
3931     unsigned char qp_prime_y = 0;
3932     unsigned char me_method = gen9_avc_p_me_method[generic_state->preset];
3933     unsigned char seach_table_idx = 0;
3934     unsigned char mv_shift_factor = 0, prev_mv_read_pos_factor = 0;
3935     unsigned int downscaled_width_in_mb, downscaled_height_in_mb;
3936     unsigned int scale_factor = 0;
3937
3938     qp_prime_y = avc_state->pic_param->pic_init_qp + slice_param->slice_qp_delta;
3939     switch(curbe_param->hme_type)
3940     {
3941     case INTEL_ENC_HME_4x :
3942         {
3943             use_mv_from_prev_step = (generic_state->b16xme_enabled)? 1:0;
3944             write_distortions = 1;
3945             mv_shift_factor = 2;
3946             scale_factor = 4;
3947             prev_mv_read_pos_factor = 0;
3948             break;
3949         }
3950     case INTEL_ENC_HME_16x :
3951         {
3952             use_mv_from_prev_step = (generic_state->b32xme_enabled)? 1:0;
3953             write_distortions = 0;
3954             mv_shift_factor = 2;
3955             scale_factor = 16;
3956             prev_mv_read_pos_factor = 1;
3957             break;
3958         }
3959     case INTEL_ENC_HME_32x :
3960         {
3961             use_mv_from_prev_step = 0;
3962             write_distortions = 0;
3963             mv_shift_factor = 1;
3964             scale_factor = 32;
3965             prev_mv_read_pos_factor = 0;
3966             break;
3967         }
3968     default:
3969         assert(0);
3970
3971     }
3972     curbe_cmd = i965_gpe_context_map_curbe(gpe_context);
3973
3974     if (!curbe_cmd)
3975         return;
3976
3977     downscaled_width_in_mb = ALIGN(generic_state->frame_width_in_pixel/scale_factor,16)/16;
3978     downscaled_height_in_mb = ALIGN(generic_state->frame_height_in_pixel/scale_factor,16)/16;
3979
3980     memcpy(curbe_cmd,gen9_avc_me_curbe_init_data,sizeof(gen9_avc_me_curbe_data));
3981
3982     curbe_cmd->dw3.sub_pel_mode = 3;
3983     if(avc_state->field_scaling_output_interleaved)
3984     {
3985         /*frame set to zero,field specified*/
3986         curbe_cmd->dw3.src_access = 0;
3987         curbe_cmd->dw3.ref_access = 0;
3988         curbe_cmd->dw7.src_field_polarity = 0;
3989     }
3990     curbe_cmd->dw4.picture_height_minus1 = downscaled_height_in_mb - 1;
3991     curbe_cmd->dw4.picture_width = downscaled_width_in_mb;
3992     curbe_cmd->dw5.qp_prime_y = qp_prime_y;
3993
3994     curbe_cmd->dw6.use_mv_from_prev_step = use_mv_from_prev_step;
3995     curbe_cmd->dw6.write_distortions = write_distortions;
3996     curbe_cmd->dw6.super_combine_dist = gen9_avc_super_combine_dist[generic_state->preset];
3997     curbe_cmd->dw6.max_vmvr = i965_avc_get_max_mv_len(avc_state->seq_param->level_idc) * 4;//frame only
3998
3999     if(generic_state->frame_type == SLICE_TYPE_B)
4000     {
4001         curbe_cmd->dw1.bi_weight = 32;
4002         curbe_cmd->dw13.num_ref_idx_l1_minus1 = slice_param->num_ref_idx_l1_active_minus1;
4003         me_method = gen9_avc_b_me_method[generic_state->preset];
4004         seach_table_idx = 1;
4005     }
4006
4007     if(generic_state->frame_type == SLICE_TYPE_P ||
4008        generic_state->frame_type == SLICE_TYPE_B )
4009        curbe_cmd->dw13.num_ref_idx_l0_minus1 = slice_param->num_ref_idx_l0_active_minus1;
4010
4011     curbe_cmd->dw13.ref_streamin_cost = 5;
4012     curbe_cmd->dw13.roi_enable = 0;
4013
4014     curbe_cmd->dw15.prev_mv_read_pos_factor = prev_mv_read_pos_factor;
4015     curbe_cmd->dw15.mv_shift_factor = mv_shift_factor;
4016
4017     memcpy(&curbe_cmd->dw16,table_enc_search_path[seach_table_idx][me_method],14*sizeof(int));
4018
4019     curbe_cmd->dw32._4x_memv_output_data_surf_index = GEN9_AVC_ME_MV_DATA_SURFACE_INDEX;
4020     curbe_cmd->dw33._16x_32x_memv_input_data_surf_index = (curbe_param->hme_type == INTEL_ENC_HME_32x)? GEN9_AVC_32XME_MV_DATA_SURFACE_INDEX:GEN9_AVC_16XME_MV_DATA_SURFACE_INDEX ;
4021     curbe_cmd->dw34._4x_me_output_dist_surf_index = GEN9_AVC_ME_DISTORTION_SURFACE_INDEX;
4022     curbe_cmd->dw35._4x_me_output_brc_dist_surf_index = GEN9_AVC_ME_BRC_DISTORTION_INDEX;
4023     curbe_cmd->dw36.vme_fwd_inter_pred_surf_index = GEN9_AVC_ME_CURR_FOR_FWD_REF_INDEX;
4024     curbe_cmd->dw37.vme_bdw_inter_pred_surf_index = GEN9_AVC_ME_CURR_FOR_BWD_REF_INDEX;
4025     curbe_cmd->dw38.reserved = GEN9_AVC_ME_VDENC_STREAMIN_INDEX;
4026
4027     i965_gpe_context_unmap_curbe(gpe_context);
4028     return;
4029 }
4030
4031 static void
4032 gen9_avc_send_surface_me(VADriverContextP ctx,
4033                          struct encode_state *encode_state,
4034                          struct i965_gpe_context *gpe_context,
4035                          struct intel_encoder_context *encoder_context,
4036                          void * param)
4037 {
4038     struct i965_driver_data *i965 = i965_driver_data(ctx);
4039
4040     struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
4041     struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
4042     struct i965_avc_encoder_context * avc_ctx = (struct i965_avc_encoder_context * )vme_context->private_enc_ctx;
4043     struct avc_enc_state * avc_state = (struct avc_enc_state * )vme_context->private_enc_state;
4044
4045     struct object_surface *obj_surface, *input_surface;
4046     struct gen9_surface_avc *avc_priv_surface;
4047     struct i965_gpe_resource *gpe_resource;
4048     struct me_param * curbe_param = (struct me_param *)param ;
4049
4050     VAEncSliceParameterBufferH264 * slice_param = avc_state->slice_param[0];
4051     VASurfaceID surface_id;
4052     int i = 0;
4053
4054     /* all scaled input surface stored in reconstructed_object*/
4055     obj_surface = encode_state->reconstructed_object;
4056     if (!obj_surface || !obj_surface->private_data)
4057         return;
4058     avc_priv_surface = obj_surface->private_data;
4059
4060
4061     switch(curbe_param->hme_type)
4062     {
4063     case INTEL_ENC_HME_4x :
4064         {
4065             /*memv output 4x*/
4066             gpe_resource = &avc_ctx->s4x_memv_data_buffer;
4067             gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
4068                                            gpe_resource,
4069                                            1,
4070                                            I965_SURFACEFORMAT_R8_UNORM,
4071                                            GEN9_AVC_ME_MV_DATA_SURFACE_INDEX);
4072
4073             /*memv input 16x*/
4074             if(generic_state->b16xme_enabled)
4075             {
4076                 gpe_resource = &avc_ctx->s16x_memv_data_buffer;
4077                 gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
4078                                                gpe_resource,
4079                                                1,
4080                                                I965_SURFACEFORMAT_R8_UNORM,
4081                                                GEN9_AVC_16XME_MV_DATA_SURFACE_INDEX);
4082             }
4083             /* brc distortion  output*/
4084             gpe_resource = &avc_ctx->res_brc_dist_data_surface;
4085             gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
4086                                            gpe_resource,
4087                                            1,
4088                                            I965_SURFACEFORMAT_R8_UNORM,
4089                                            GEN9_AVC_ME_BRC_DISTORTION_INDEX);
4090            /* memv distortion output*/
4091             gpe_resource = &avc_ctx->s4x_memv_distortion_buffer;
4092             gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
4093                                            gpe_resource,
4094                                            1,
4095                                            I965_SURFACEFORMAT_R8_UNORM,
4096                                            GEN9_AVC_ME_DISTORTION_SURFACE_INDEX);
4097             /*input current down scaled YUV surface*/
4098             obj_surface = encode_state->reconstructed_object;
4099             avc_priv_surface = obj_surface->private_data;
4100             input_surface = avc_priv_surface->scaled_4x_surface_obj;
4101             gen9_add_adv_gpe_surface(ctx, gpe_context,
4102                                      input_surface,
4103                                      GEN9_AVC_ME_CURR_FOR_FWD_REF_INDEX);
4104             /*input ref scaled YUV surface*/
4105             for(i = 0; i < slice_param->num_ref_idx_l0_active_minus1 + 1; i++)
4106             {
4107                 surface_id = slice_param->RefPicList0[i].picture_id;
4108                 obj_surface = SURFACE(surface_id);
4109                 if (!obj_surface || !obj_surface->private_data)
4110                     break;
4111                 avc_priv_surface = obj_surface->private_data;
4112
4113                 input_surface = avc_priv_surface->scaled_4x_surface_obj;
4114
4115                 gen9_add_adv_gpe_surface(ctx, gpe_context,
4116                                          input_surface,
4117                                          GEN9_AVC_ME_CURR_FOR_FWD_REF_INDEX+i*2 + 1);
4118             }
4119
4120             obj_surface = encode_state->reconstructed_object;
4121             avc_priv_surface = obj_surface->private_data;
4122             input_surface = avc_priv_surface->scaled_4x_surface_obj;
4123
4124             gen9_add_adv_gpe_surface(ctx, gpe_context,
4125                                      input_surface,
4126                                      GEN9_AVC_ME_CURR_FOR_BWD_REF_INDEX);
4127
4128             for(i = 0; i < slice_param->num_ref_idx_l1_active_minus1 + 1; i++)
4129             {
4130                 surface_id = slice_param->RefPicList1[i].picture_id;
4131                 obj_surface = SURFACE(surface_id);
4132                 if (!obj_surface || !obj_surface->private_data)
4133                     break;
4134                 avc_priv_surface = obj_surface->private_data;
4135
4136                 input_surface = avc_priv_surface->scaled_4x_surface_obj;
4137
4138                 gen9_add_adv_gpe_surface(ctx, gpe_context,
4139                                          input_surface,
4140                                          GEN9_AVC_ME_CURR_FOR_BWD_REF_INDEX+i*2 + 1);
4141             }
4142             break;
4143
4144         }
4145     case INTEL_ENC_HME_16x :
4146         {
4147             gpe_resource = &avc_ctx->s16x_memv_data_buffer;
4148             gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
4149                                            gpe_resource,
4150                                            1,
4151                                            I965_SURFACEFORMAT_R8_UNORM,
4152                                            GEN9_AVC_ME_MV_DATA_SURFACE_INDEX);
4153
4154             if(generic_state->b32xme_enabled)
4155             {
4156                 gpe_resource = &avc_ctx->s32x_memv_data_buffer;
4157                 gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
4158                                                gpe_resource,
4159                                                1,
4160                                                I965_SURFACEFORMAT_R8_UNORM,
4161                                                GEN9_AVC_32XME_MV_DATA_SURFACE_INDEX);
4162             }
4163
4164             obj_surface = encode_state->reconstructed_object;
4165             avc_priv_surface = obj_surface->private_data;
4166             input_surface = avc_priv_surface->scaled_16x_surface_obj;
4167             gen9_add_adv_gpe_surface(ctx, gpe_context,
4168                                      input_surface,
4169                                      GEN9_AVC_ME_CURR_FOR_FWD_REF_INDEX);
4170
4171             for(i = 0; i < slice_param->num_ref_idx_l0_active_minus1 + 1; i++)
4172             {
4173                 surface_id = slice_param->RefPicList0[i].picture_id;
4174                 obj_surface = SURFACE(surface_id);
4175                 if (!obj_surface || !obj_surface->private_data)
4176                     break;
4177                 avc_priv_surface = obj_surface->private_data;
4178
4179                 input_surface = avc_priv_surface->scaled_16x_surface_obj;
4180
4181                 gen9_add_adv_gpe_surface(ctx, gpe_context,
4182                                          input_surface,
4183                                          GEN9_AVC_ME_CURR_FOR_FWD_REF_INDEX+i*2 + 1);
4184             }
4185
4186             obj_surface = encode_state->reconstructed_object;
4187             avc_priv_surface = obj_surface->private_data;
4188             input_surface = avc_priv_surface->scaled_16x_surface_obj;
4189
4190             gen9_add_adv_gpe_surface(ctx, gpe_context,
4191                                      input_surface,
4192                                      GEN9_AVC_ME_CURR_FOR_BWD_REF_INDEX);
4193
4194             for(i = 0; i < slice_param->num_ref_idx_l1_active_minus1 + 1; i++)
4195             {
4196                 surface_id = slice_param->RefPicList1[i].picture_id;
4197                 obj_surface = SURFACE(surface_id);
4198                 if (!obj_surface || !obj_surface->private_data)
4199                     break;
4200                 avc_priv_surface = obj_surface->private_data;
4201
4202                 input_surface = avc_priv_surface->scaled_16x_surface_obj;
4203
4204                 gen9_add_adv_gpe_surface(ctx, gpe_context,
4205                                          input_surface,
4206                                          GEN9_AVC_ME_CURR_FOR_BWD_REF_INDEX+i*2 + 1);
4207             }
4208             break;
4209         }
4210     case INTEL_ENC_HME_32x :
4211         {
4212             gpe_resource = &avc_ctx->s32x_memv_data_buffer;
4213             gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
4214                                            gpe_resource,
4215                                            1,
4216                                            I965_SURFACEFORMAT_R8_UNORM,
4217                                            GEN9_AVC_ME_MV_DATA_SURFACE_INDEX);
4218
4219             obj_surface = encode_state->reconstructed_object;
4220             avc_priv_surface = obj_surface->private_data;
4221             input_surface = avc_priv_surface->scaled_32x_surface_obj;
4222             gen9_add_adv_gpe_surface(ctx, gpe_context,
4223                                      input_surface,
4224                                      GEN9_AVC_ME_CURR_FOR_FWD_REF_INDEX);
4225
4226             for(i = 0; i < slice_param->num_ref_idx_l0_active_minus1 + 1; i++)
4227             {
4228                 surface_id = slice_param->RefPicList0[i].picture_id;
4229                 obj_surface = SURFACE(surface_id);
4230                 if (!obj_surface || !obj_surface->private_data)
4231                     break;
4232                 avc_priv_surface = obj_surface->private_data;
4233
4234                 input_surface = avc_priv_surface->scaled_32x_surface_obj;
4235
4236                 gen9_add_adv_gpe_surface(ctx, gpe_context,
4237                                          input_surface,
4238                                          GEN9_AVC_ME_CURR_FOR_FWD_REF_INDEX+i*2 + 1);
4239             }
4240
4241             obj_surface = encode_state->reconstructed_object;
4242             avc_priv_surface = obj_surface->private_data;
4243             input_surface = avc_priv_surface->scaled_32x_surface_obj;
4244
4245             gen9_add_adv_gpe_surface(ctx, gpe_context,
4246                                      input_surface,
4247                                      GEN9_AVC_ME_CURR_FOR_BWD_REF_INDEX);
4248
4249             for(i = 0; i < slice_param->num_ref_idx_l1_active_minus1 + 1; i++)
4250             {
4251                 surface_id = slice_param->RefPicList1[i].picture_id;
4252                 obj_surface = SURFACE(surface_id);
4253                 if (!obj_surface || !obj_surface->private_data)
4254                     break;
4255                 avc_priv_surface = obj_surface->private_data;
4256
4257                 input_surface = avc_priv_surface->scaled_32x_surface_obj;
4258
4259                 gen9_add_adv_gpe_surface(ctx, gpe_context,
4260                                          input_surface,
4261                                          GEN9_AVC_ME_CURR_FOR_BWD_REF_INDEX+i*2 + 1);
4262             }
4263             break;
4264         }
4265     default:
4266         assert(0);
4267
4268     }
4269 }
4270
4271 static VAStatus
4272 gen9_avc_kernel_me(VADriverContextP ctx,
4273                    struct encode_state *encode_state,
4274                    struct intel_encoder_context *encoder_context,
4275                    int hme_type)
4276 {
4277     struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
4278     struct generic_encoder_context * generic_ctx = (struct generic_encoder_context * )vme_context->generic_enc_ctx;
4279     struct i965_avc_encoder_context * avc_ctx = (struct i965_avc_encoder_context * )vme_context->private_enc_ctx;
4280     struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
4281
4282     struct i965_gpe_context *gpe_context;
4283     struct gpe_media_object_walker_parameter media_object_walker_param;
4284     struct gpe_encoder_kernel_walker_parameter kernel_walker_param;
4285     unsigned int downscaled_width_in_mb, downscaled_height_in_mb;
4286     int media_function = 0;
4287     int kernel_idx = 0;
4288     struct me_param param ;
4289     unsigned int scale_factor = 0;
4290
4291     switch(hme_type)
4292     {
4293     case INTEL_ENC_HME_4x :
4294         {
4295             media_function = INTEL_MEDIA_STATE_4X_ME;
4296             scale_factor = 4;
4297             break;
4298         }
4299     case INTEL_ENC_HME_16x :
4300         {
4301             media_function = INTEL_MEDIA_STATE_16X_ME;
4302             scale_factor = 16;
4303             break;
4304         }
4305     case INTEL_ENC_HME_32x :
4306         {
4307             media_function = INTEL_MEDIA_STATE_32X_ME;
4308             scale_factor = 32;
4309             break;
4310         }
4311     default:
4312         assert(0);
4313
4314     }
4315
4316     downscaled_width_in_mb = ALIGN(generic_state->frame_width_in_pixel/scale_factor,16)/16;
4317     downscaled_height_in_mb = ALIGN(generic_state->frame_height_in_pixel/scale_factor,16)/16;
4318
4319     /* I frame should not come here.*/
4320     kernel_idx = (generic_state->frame_type == SLICE_TYPE_P)? GEN9_AVC_KERNEL_ME_P_IDX : GEN9_AVC_KERNEL_ME_B_IDX;
4321     gpe_context = &(avc_ctx->context_me.gpe_contexts[kernel_idx]);
4322
4323     gen8_gpe_context_init(ctx, gpe_context);
4324     gen9_gpe_reset_binding_table(ctx, gpe_context);
4325
4326     /*set curbe*/
4327     memset(&param,0,sizeof(param));
4328     param.hme_type = hme_type;
4329     generic_ctx->pfn_set_curbe_me(ctx,encode_state,gpe_context,encoder_context,&param);
4330
4331     /*send surface*/
4332     generic_ctx->pfn_send_me_surface(ctx,encode_state,gpe_context,encoder_context,&param);
4333
4334     gen8_gpe_setup_interface_data(ctx, gpe_context);
4335
4336     memset(&kernel_walker_param, 0, sizeof(kernel_walker_param));
4337     /* the scaling is based on 8x8 blk level */
4338     kernel_walker_param.resolution_x = downscaled_width_in_mb ;
4339     kernel_walker_param.resolution_y = downscaled_height_in_mb ;
4340     kernel_walker_param.no_dependency = 1;
4341
4342     i965_init_media_object_walker_parameter(&kernel_walker_param, &media_object_walker_param);
4343
4344     gen9_avc_run_kernel_media_object_walker(ctx, encoder_context,
4345                                         gpe_context,
4346                                         media_function,
4347                                         &media_object_walker_param);
4348
4349     return VA_STATUS_SUCCESS;
4350 }
4351
4352 /*
4353 wp related function
4354 */
4355 static void
4356 gen9_avc_set_curbe_wp(VADriverContextP ctx,
4357                      struct encode_state *encode_state,
4358                      struct i965_gpe_context *gpe_context,
4359                      struct intel_encoder_context *encoder_context,
4360                      void * param)
4361 {
4362     gen9_avc_wp_curbe_data *cmd;
4363     struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
4364     struct avc_enc_state * avc_state = (struct avc_enc_state * )vme_context->private_enc_state;
4365     VAEncSliceParameterBufferH264 * slice_param = avc_state->slice_param[0];
4366     struct wp_param * curbe_param = (struct wp_param *)param;
4367
4368     cmd = i965_gpe_context_map_curbe(gpe_context);
4369
4370     if (!cmd)
4371         return;
4372     memset(cmd,0,sizeof(gen9_avc_wp_curbe_data));
4373     if(curbe_param->ref_list_idx)
4374     {
4375         cmd->dw0.default_weight = slice_param->luma_weight_l1[0];
4376         cmd->dw0.default_offset = slice_param->luma_offset_l1[0];
4377     }else
4378     {
4379         cmd->dw0.default_weight = slice_param->luma_weight_l0[0];
4380         cmd->dw0.default_offset = slice_param->luma_offset_l0[0];
4381     }
4382
4383     cmd->dw49.input_surface = GEN9_AVC_WP_INPUT_REF_SURFACE_INDEX;
4384     cmd->dw50.output_surface = GEN9_AVC_WP_OUTPUT_SCALED_SURFACE_INDEX;
4385
4386     i965_gpe_context_unmap_curbe(gpe_context);
4387
4388 }
4389
4390 static void
4391 gen9_avc_send_surface_wp(VADriverContextP ctx,
4392                          struct encode_state *encode_state,
4393                          struct i965_gpe_context *gpe_context,
4394                          struct intel_encoder_context *encoder_context,
4395                          void * param)
4396 {
4397     struct i965_driver_data *i965 = i965_driver_data(ctx);
4398     struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
4399     struct i965_avc_encoder_context * avc_ctx = (struct i965_avc_encoder_context * )vme_context->private_enc_ctx;
4400     struct avc_enc_state * avc_state = (struct avc_enc_state * )vme_context->private_enc_state;
4401     struct wp_param * curbe_param = (struct wp_param *)param;
4402     struct object_surface *obj_surface;
4403     VAEncSliceParameterBufferH264 * slice_param = avc_state->slice_param[0];
4404     VASurfaceID surface_id;
4405
4406     if(curbe_param->ref_list_idx)
4407     {
4408         surface_id = slice_param->RefPicList1[0].picture_id;
4409         obj_surface = SURFACE(surface_id);
4410         if (!obj_surface || !obj_surface->private_data)
4411             avc_state->weighted_ref_l1_enable = 0;
4412         else
4413             avc_state->weighted_ref_l1_enable = 1;
4414     }else
4415     {
4416         surface_id = slice_param->RefPicList0[0].picture_id;
4417         obj_surface = SURFACE(surface_id);
4418         if (!obj_surface || !obj_surface->private_data)
4419             avc_state->weighted_ref_l0_enable = 0;
4420         else
4421             avc_state->weighted_ref_l0_enable = 1;
4422     }
4423     if(!obj_surface)
4424         obj_surface = encode_state->reference_objects[0];
4425
4426
4427     gen9_add_adv_gpe_surface(ctx, gpe_context,
4428                              obj_surface,
4429                              GEN9_AVC_WP_INPUT_REF_SURFACE_INDEX);
4430
4431     obj_surface = avc_ctx->wp_output_pic_select_surface_obj[curbe_param->ref_list_idx];
4432     gen9_add_adv_gpe_surface(ctx, gpe_context,
4433                              obj_surface,
4434                              GEN9_AVC_WP_OUTPUT_SCALED_SURFACE_INDEX);
4435 }
4436
4437
4438 static VAStatus
4439 gen9_avc_kernel_wp(VADriverContextP ctx,
4440                    struct encode_state *encode_state,
4441                    struct intel_encoder_context *encoder_context,
4442                    unsigned int list1_in_use)
4443 {
4444     struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
4445     struct i965_avc_encoder_context * avc_ctx = (struct i965_avc_encoder_context * )vme_context->private_enc_ctx;
4446     struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
4447     struct generic_encoder_context * generic_ctx = (struct generic_encoder_context * )vme_context->generic_enc_ctx;
4448
4449     struct i965_gpe_context *gpe_context;
4450     struct gpe_media_object_walker_parameter media_object_walker_param;
4451     struct gpe_encoder_kernel_walker_parameter kernel_walker_param;
4452     int media_function = INTEL_MEDIA_STATE_ENC_WP;
4453     struct wp_param param;
4454
4455     gpe_context = &(avc_ctx->context_wp.gpe_contexts);
4456
4457     gen8_gpe_context_init(ctx, gpe_context);
4458     gen9_gpe_reset_binding_table(ctx, gpe_context);
4459
4460     memset(&param,0,sizeof(param));
4461     param.ref_list_idx = (list1_in_use == 1)? 1: 0;
4462     /*set curbe*/
4463     generic_ctx->pfn_set_curbe_wp(ctx,encode_state,gpe_context,encoder_context,&param);
4464
4465     /*send surface*/
4466     generic_ctx->pfn_send_wp_surface(ctx,encode_state,gpe_context,encoder_context,&param);
4467
4468     gen8_gpe_setup_interface_data(ctx, gpe_context);
4469
4470     memset(&kernel_walker_param, 0, sizeof(kernel_walker_param));
4471     /* the scaling is based on 8x8 blk level */
4472     kernel_walker_param.resolution_x = generic_state->frame_width_in_mbs;
4473     kernel_walker_param.resolution_y = generic_state->frame_height_in_mbs;
4474     kernel_walker_param.no_dependency = 1;
4475
4476     i965_init_media_object_walker_parameter(&kernel_walker_param, &media_object_walker_param);
4477
4478     gen9_avc_run_kernel_media_object_walker(ctx, encoder_context,
4479                                         gpe_context,
4480                                         media_function,
4481                                         &media_object_walker_param);
4482
4483     return VA_STATUS_SUCCESS;
4484 }
4485
4486
4487 /*
4488 sfd related function
4489 */
4490 static void
4491 gen9_avc_set_curbe_sfd(VADriverContextP ctx,
4492                      struct encode_state *encode_state,
4493                      struct i965_gpe_context *gpe_context,
4494                      struct intel_encoder_context *encoder_context,
4495                      void * param)
4496 {
4497     gen9_avc_sfd_curbe_data *cmd;
4498     struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
4499     struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
4500     struct avc_enc_state * avc_state = (struct avc_enc_state * )vme_context->private_enc_state;
4501     VAEncSliceParameterBufferH264 * slice_param = avc_state->slice_param[0];
4502
4503     cmd = i965_gpe_context_map_curbe(gpe_context);
4504
4505     if (!cmd)
4506         return;
4507     memset(cmd,0,sizeof(gen9_avc_sfd_curbe_data));
4508
4509     cmd->dw0.enable_intra_cost_scaling_for_static_frame = 1 ;
4510     cmd->dw0.enable_adaptive_mv_stream_in = 0 ;
4511     cmd->dw0.stream_in_type = 7 ;
4512     cmd->dw0.slice_type = slice_type_kernel[generic_state->frame_type]  ;
4513     cmd->dw0.brc_mode_enable = generic_state->brc_enabled ;
4514     cmd->dw0.vdenc_mode_disable = 1 ;
4515
4516     cmd->dw1.hme_stream_in_ref_cost = 5 ;
4517     cmd->dw1.num_of_refs = slice_param->num_ref_idx_l0_active_minus1 ;
4518     cmd->dw1.qp_value = avc_state->pic_param->pic_init_qp + slice_param->slice_qp_delta ;
4519
4520     cmd->dw2.frame_width_in_mbs = generic_state->frame_width_in_mbs ;
4521     cmd->dw2.frame_height_in_mbs = generic_state->frame_height_in_mbs ;
4522
4523     cmd->dw3.large_mv_threshold = 128 ;
4524     cmd->dw4.total_large_mv_threshold = (generic_state->frame_width_in_mbs * generic_state->frame_height_in_mbs)/100 ;
4525     cmd->dw5.zmv_threshold = 4 ;
4526     cmd->dw6.total_zmv_threshold = (generic_state->frame_width_in_mbs * generic_state->frame_height_in_mbs * avc_state->zero_mv_threshold)/100 ; // zero_mv_threshold = 60;
4527     cmd->dw7.min_dist_threshold = 10 ;
4528
4529     if(generic_state->frame_type == SLICE_TYPE_P)
4530     {
4531         memcpy(cmd->cost_table,gen9_avc_sfd_cost_table_p_frame,52* sizeof(unsigned char));
4532
4533     }else if(generic_state->frame_type == SLICE_TYPE_B)
4534     {
4535         memcpy(cmd->cost_table,gen9_avc_sfd_cost_table_b_frame,52* sizeof(unsigned char));
4536     }
4537
4538     cmd->dw21.actual_width_in_mb = cmd->dw2.frame_width_in_mbs ;
4539     cmd->dw21.actual_height_in_mb = cmd->dw2.frame_height_in_mbs ;
4540     cmd->dw24.vdenc_input_image_state_index = GEN9_AVC_SFD_VDENC_INPUT_IMAGE_STATE_INDEX ;
4541     cmd->dw26.mv_data_surface_index = GEN9_AVC_SFD_MV_DATA_SURFACE_INDEX ;
4542     cmd->dw27.inter_distortion_surface_index = GEN9_AVC_SFD_INTER_DISTORTION_SURFACE_INDEX ;
4543     cmd->dw28.output_data_surface_index = GEN9_AVC_SFD_OUTPUT_DATA_SURFACE_INDEX ;
4544     cmd->dw29.vdenc_output_image_state_index = GEN9_AVC_SFD_VDENC_OUTPUT_IMAGE_STATE_INDEX ;
4545
4546     i965_gpe_context_unmap_curbe(gpe_context);
4547
4548 }
4549
4550 static void
4551 gen9_avc_send_surface_sfd(VADriverContextP ctx,
4552                           struct encode_state *encode_state,
4553                           struct i965_gpe_context *gpe_context,
4554                           struct intel_encoder_context *encoder_context,
4555                           void * param)
4556 {
4557     struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
4558     struct i965_avc_encoder_context * avc_ctx = (struct i965_avc_encoder_context * )vme_context->private_enc_ctx;
4559     struct i965_gpe_resource *gpe_resource;
4560     int size = 0;
4561
4562     /*HME mv data surface memv output 4x*/
4563     gpe_resource = &avc_ctx->s4x_memv_data_buffer;
4564     gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
4565                                    gpe_resource,
4566                                    1,
4567                                    I965_SURFACEFORMAT_R8_UNORM,
4568                                    GEN9_AVC_SFD_MV_DATA_SURFACE_INDEX);
4569
4570     /* memv distortion */
4571     gpe_resource = &avc_ctx->s4x_memv_distortion_buffer;
4572     gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
4573                                    gpe_resource,
4574                                    1,
4575                                    I965_SURFACEFORMAT_R8_UNORM,
4576                                    GEN9_AVC_SFD_INTER_DISTORTION_SURFACE_INDEX);
4577     /*buffer output*/
4578     size = 32 * 4 *4;
4579     gpe_resource = &avc_ctx->res_sfd_output_buffer;
4580     gen9_add_buffer_gpe_surface(ctx,
4581                                 gpe_context,
4582                                 gpe_resource,
4583                                 0,
4584                                 size / 4,
4585                                 0,
4586                                 GEN9_AVC_SFD_OUTPUT_DATA_SURFACE_INDEX);
4587
4588 }
4589
4590 static VAStatus
4591 gen9_avc_kernel_sfd(VADriverContextP ctx,
4592                     struct encode_state *encode_state,
4593                     struct intel_encoder_context *encoder_context)
4594 {
4595     struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
4596     struct i965_avc_encoder_context * avc_ctx = (struct i965_avc_encoder_context * )vme_context->private_enc_ctx;
4597     struct generic_encoder_context * generic_ctx = (struct generic_encoder_context * )vme_context->generic_enc_ctx;
4598
4599     struct i965_gpe_context *gpe_context;
4600     struct gpe_media_object_parameter media_object_param;
4601     struct gpe_media_object_inline_data media_object_inline_data;
4602     int media_function = INTEL_MEDIA_STATE_STATIC_FRAME_DETECTION;
4603     gpe_context = &(avc_ctx->context_sfd.gpe_contexts);
4604
4605     gen8_gpe_context_init(ctx, gpe_context);
4606     gen9_gpe_reset_binding_table(ctx, gpe_context);
4607
4608     /*set curbe*/
4609     generic_ctx->pfn_set_curbe_sfd(ctx,encode_state,gpe_context,encoder_context,NULL);
4610
4611     /*send surface*/
4612     generic_ctx->pfn_send_sfd_surface(ctx,encode_state,gpe_context,encoder_context,NULL);
4613
4614     gen8_gpe_setup_interface_data(ctx, gpe_context);
4615
4616     memset(&media_object_param, 0, sizeof(media_object_param));
4617     memset(&media_object_inline_data, 0, sizeof(media_object_inline_data));
4618     media_object_param.pinline_data = &media_object_inline_data;
4619     media_object_param.inline_size = sizeof(media_object_inline_data);
4620
4621     gen9_avc_run_kernel_media_object(ctx, encoder_context,
4622                                      gpe_context,
4623                                      media_function,
4624                                      &media_object_param);
4625
4626     return VA_STATUS_SUCCESS;
4627 }
4628
4629 /*
4630 kernel related function:init/destroy etc
4631 */
4632 static void
4633 gen9_avc_kernel_init_scaling(VADriverContextP ctx,
4634                              struct generic_encoder_context *generic_context,
4635                              struct gen_avc_scaling_context *kernel_context)
4636 {
4637     struct i965_gpe_context *gpe_context = NULL;
4638     struct encoder_kernel_parameter kernel_param ;
4639     struct encoder_scoreboard_parameter scoreboard_param;
4640     struct i965_kernel common_kernel;
4641
4642     /* 4x scaling kernel*/
4643     kernel_param.curbe_size = sizeof(gen9_avc_scaling4x_curbe_data);
4644     kernel_param.inline_data_size = sizeof(gen9_avc_scaling4x_curbe_data);
4645     kernel_param.sampler_size = 0;
4646
4647     memset(&scoreboard_param, 0, sizeof(scoreboard_param));
4648     scoreboard_param.mask = 0xFF;
4649     scoreboard_param.enable = generic_context->use_hw_scoreboard;
4650     scoreboard_param.type = generic_context->use_hw_non_stalling_scoreboard;
4651     scoreboard_param.walkpat_flag = 0;
4652
4653     gpe_context = &kernel_context->gpe_contexts[GEN9_AVC_KERNEL_SCALING_4X_IDX];
4654     gen9_init_gpe_context_avc(ctx, gpe_context, &kernel_param);
4655     gen9_init_vfe_scoreboard_avc(gpe_context, &scoreboard_param);
4656
4657     memset(&common_kernel, 0, sizeof(common_kernel));
4658
4659     intel_avc_get_kernel_header_and_size((void *)(generic_context->enc_kernel_ptr),
4660                                          generic_context->enc_kernel_size,
4661                                          INTEL_GENERIC_ENC_SCALING4X,
4662                                          0,
4663                                          &common_kernel);
4664
4665     gen8_gpe_load_kernels(ctx,
4666                           gpe_context,
4667                           &common_kernel,
4668                           1);
4669
4670     /*2x scaling kernel*/
4671     kernel_param.curbe_size = sizeof(gen9_avc_scaling2x_curbe_data);
4672     kernel_param.inline_data_size = 0;
4673     kernel_param.sampler_size = 0;
4674
4675     gpe_context = &kernel_context->gpe_contexts[GEN9_AVC_KERNEL_SCALING_2X_IDX];
4676     gen9_init_gpe_context_avc(ctx, gpe_context, &kernel_param);
4677     gen9_init_vfe_scoreboard_avc(gpe_context, &scoreboard_param);
4678
4679     memset(&common_kernel, 0, sizeof(common_kernel));
4680
4681     intel_avc_get_kernel_header_and_size((void *)(generic_context->enc_kernel_ptr),
4682                                          generic_context->enc_kernel_size,
4683                                          INTEL_GENERIC_ENC_SCALING2X,
4684                                          0,
4685                                          &common_kernel);
4686
4687     gen8_gpe_load_kernels(ctx,
4688                           gpe_context,
4689                           &common_kernel,
4690                           1);
4691
4692 }
4693
4694 static void
4695 gen9_avc_kernel_init_me(VADriverContextP ctx,
4696                         struct generic_encoder_context *generic_context,
4697                         struct gen_avc_me_context *kernel_context)
4698 {
4699     struct i965_gpe_context *gpe_context = NULL;
4700     struct encoder_kernel_parameter kernel_param ;
4701     struct encoder_scoreboard_parameter scoreboard_param;
4702     struct i965_kernel common_kernel;
4703     int i = 0;
4704
4705     kernel_param.curbe_size = sizeof(gen9_avc_me_curbe_data);
4706     kernel_param.inline_data_size = 0;
4707     kernel_param.sampler_size = 0;
4708
4709     memset(&scoreboard_param, 0, sizeof(scoreboard_param));
4710     scoreboard_param.mask = 0xFF;
4711     scoreboard_param.enable = generic_context->use_hw_scoreboard;
4712     scoreboard_param.type = generic_context->use_hw_non_stalling_scoreboard;
4713     scoreboard_param.walkpat_flag = 0;
4714
4715     for (i = 0; i < 2; i++) {
4716         gpe_context = &kernel_context->gpe_contexts[i];
4717         gen9_init_gpe_context_avc(ctx, gpe_context, &kernel_param);
4718         gen9_init_vfe_scoreboard_avc(gpe_context, &scoreboard_param);
4719
4720         memset(&common_kernel, 0, sizeof(common_kernel));
4721
4722         intel_avc_get_kernel_header_and_size((void *)(generic_context->enc_kernel_ptr),
4723                                              generic_context->enc_kernel_size,
4724                                              INTEL_GENERIC_ENC_ME,
4725                                              i,
4726                                              &common_kernel);
4727
4728         gen8_gpe_load_kernels(ctx,
4729                               gpe_context,
4730                               &common_kernel,
4731                               1);
4732     }
4733
4734 }
4735
4736 static void
4737 gen9_avc_kernel_init_mbenc(VADriverContextP ctx,
4738                            struct generic_encoder_context *generic_context,
4739                            struct gen_avc_mbenc_context *kernel_context)
4740 {
4741     struct i965_gpe_context *gpe_context = NULL;
4742     struct encoder_kernel_parameter kernel_param ;
4743     struct encoder_scoreboard_parameter scoreboard_param;
4744     struct i965_kernel common_kernel;
4745     int i = 0;
4746
4747     kernel_param.curbe_size = sizeof(gen9_avc_mbenc_curbe_data);
4748     kernel_param.inline_data_size = 0;
4749     kernel_param.sampler_size = 0;
4750
4751     memset(&scoreboard_param, 0, sizeof(scoreboard_param));
4752     scoreboard_param.mask = 0xFF;
4753     scoreboard_param.enable = generic_context->use_hw_scoreboard;
4754     scoreboard_param.type = generic_context->use_hw_non_stalling_scoreboard;
4755     scoreboard_param.walkpat_flag = 0;
4756
4757     for (i = 0; i < NUM_GEN9_AVC_KERNEL_MBENC ; i++) {
4758         gpe_context = &kernel_context->gpe_contexts[i];
4759         gen9_init_gpe_context_avc(ctx, gpe_context, &kernel_param);
4760         gen9_init_vfe_scoreboard_avc(gpe_context, &scoreboard_param);
4761
4762         memset(&common_kernel, 0, sizeof(common_kernel));
4763
4764         intel_avc_get_kernel_header_and_size((void *)(generic_context->enc_kernel_ptr),
4765                                              generic_context->enc_kernel_size,
4766                                              INTEL_GENERIC_ENC_MBENC,
4767                                              i,
4768                                              &common_kernel);
4769
4770         gen8_gpe_load_kernels(ctx,
4771                               gpe_context,
4772                               &common_kernel,
4773                               1);
4774     }
4775
4776 }
4777
4778 static void
4779 gen9_avc_kernel_init_brc(VADriverContextP ctx,
4780                          struct generic_encoder_context *generic_context,
4781                          struct gen_avc_brc_context *kernel_context)
4782 {
4783     struct i965_gpe_context *gpe_context = NULL;
4784     struct encoder_kernel_parameter kernel_param ;
4785     struct encoder_scoreboard_parameter scoreboard_param;
4786     struct i965_kernel common_kernel;
4787     int i = 0;
4788
4789     static const int brc_curbe_size[NUM_GEN9_AVC_KERNEL_BRC] = {
4790         (sizeof(gen9_avc_brc_init_reset_curbe_data)),
4791         (sizeof(gen9_avc_frame_brc_update_curbe_data)),
4792         (sizeof(gen9_avc_brc_init_reset_curbe_data)),
4793         (sizeof(gen9_avc_mbenc_curbe_data)),
4794         0,
4795         (sizeof(gen9_avc_mb_brc_curbe_data))
4796     };
4797
4798     kernel_param.inline_data_size = 0;
4799     kernel_param.sampler_size = 0;
4800
4801     memset(&scoreboard_param, 0, sizeof(scoreboard_param));
4802     scoreboard_param.mask = 0xFF;
4803     scoreboard_param.enable = generic_context->use_hw_scoreboard;
4804     scoreboard_param.type = generic_context->use_hw_non_stalling_scoreboard;
4805     scoreboard_param.walkpat_flag = 0;
4806
4807     for (i = 0; i < NUM_GEN9_AVC_KERNEL_BRC; i++) {
4808         kernel_param.curbe_size = brc_curbe_size[i];
4809         gpe_context = &kernel_context->gpe_contexts[i];
4810         gen9_init_gpe_context_avc(ctx, gpe_context, &kernel_param);
4811         gen9_init_vfe_scoreboard_avc(gpe_context, &scoreboard_param);
4812
4813         memset(&common_kernel, 0, sizeof(common_kernel));
4814
4815         intel_avc_get_kernel_header_and_size((void *)(generic_context->enc_kernel_ptr),
4816                                              generic_context->enc_kernel_size,
4817                                              INTEL_GENERIC_ENC_BRC,
4818                                              i,
4819                                              &common_kernel);
4820
4821         gen8_gpe_load_kernels(ctx,
4822                               gpe_context,
4823                               &common_kernel,
4824                               1);
4825     }
4826
4827 }
4828
4829 static void
4830 gen9_avc_kernel_init_wp(VADriverContextP ctx,
4831                         struct generic_encoder_context *generic_context,
4832                         struct gen_avc_wp_context *kernel_context)
4833 {
4834     struct i965_gpe_context *gpe_context = NULL;
4835     struct encoder_kernel_parameter kernel_param ;
4836     struct encoder_scoreboard_parameter scoreboard_param;
4837     struct i965_kernel common_kernel;
4838
4839     kernel_param.curbe_size = sizeof(gen9_avc_wp_curbe_data);
4840     kernel_param.inline_data_size = 0;
4841     kernel_param.sampler_size = 0;
4842
4843     memset(&scoreboard_param, 0, sizeof(scoreboard_param));
4844     scoreboard_param.mask = 0xFF;
4845     scoreboard_param.enable = generic_context->use_hw_scoreboard;
4846     scoreboard_param.type = generic_context->use_hw_non_stalling_scoreboard;
4847     scoreboard_param.walkpat_flag = 0;
4848
4849     gpe_context = &kernel_context->gpe_contexts;
4850     gen9_init_gpe_context_avc(ctx, gpe_context, &kernel_param);
4851     gen9_init_vfe_scoreboard_avc(gpe_context, &scoreboard_param);
4852
4853     memset(&common_kernel, 0, sizeof(common_kernel));
4854
4855     intel_avc_get_kernel_header_and_size((void *)(generic_context->enc_kernel_ptr),
4856                                          generic_context->enc_kernel_size,
4857                                          INTEL_GENERIC_ENC_WP,
4858                                          0,
4859                                          &common_kernel);
4860
4861     gen8_gpe_load_kernels(ctx,
4862                           gpe_context,
4863                           &common_kernel,
4864                           1);
4865
4866 }
4867
4868 static void
4869 gen9_avc_kernel_init_sfd(VADriverContextP ctx,
4870                          struct generic_encoder_context *generic_context,
4871                          struct gen_avc_sfd_context *kernel_context)
4872 {
4873     struct i965_gpe_context *gpe_context = NULL;
4874     struct encoder_kernel_parameter kernel_param ;
4875     struct encoder_scoreboard_parameter scoreboard_param;
4876     struct i965_kernel common_kernel;
4877
4878     kernel_param.curbe_size = sizeof(gen9_avc_sfd_curbe_data);
4879     kernel_param.inline_data_size = 0;
4880     kernel_param.sampler_size = 0;
4881
4882     memset(&scoreboard_param, 0, sizeof(scoreboard_param));
4883     scoreboard_param.mask = 0xFF;
4884     scoreboard_param.enable = generic_context->use_hw_scoreboard;
4885     scoreboard_param.type = generic_context->use_hw_non_stalling_scoreboard;
4886     scoreboard_param.walkpat_flag = 0;
4887
4888     gpe_context = &kernel_context->gpe_contexts;
4889     gen9_init_gpe_context_avc(ctx, gpe_context, &kernel_param);
4890     gen9_init_vfe_scoreboard_avc(gpe_context, &scoreboard_param);
4891
4892     memset(&common_kernel, 0, sizeof(common_kernel));
4893
4894     intel_avc_get_kernel_header_and_size((void *)(generic_context->enc_kernel_ptr),
4895                                          generic_context->enc_kernel_size,
4896                                          INTEL_GENERIC_ENC_SFD,
4897                                          0,
4898                                          &common_kernel);
4899
4900     gen8_gpe_load_kernels(ctx,
4901                           gpe_context,
4902                           &common_kernel,
4903                           1);
4904
4905 }
4906
4907 static void
4908 gen9_avc_kernel_destroy(struct encoder_vme_mfc_context * vme_context)
4909 {
4910
4911     struct i965_avc_encoder_context * avc_ctx = (struct i965_avc_encoder_context * )vme_context->private_enc_ctx;
4912
4913     int i = 0;
4914
4915     gen9_avc_free_resources(vme_context);
4916
4917     for(i = 0; i < NUM_GEN9_AVC_KERNEL_SCALING; i++)
4918         gen8_gpe_context_destroy(&avc_ctx->context_scaling.gpe_contexts[i]);
4919
4920     for(i = 0; i < NUM_GEN9_AVC_KERNEL_BRC; i++)
4921         gen8_gpe_context_destroy(&avc_ctx->context_brc.gpe_contexts[i]);
4922
4923     for(i = 0; i < NUM_GEN9_AVC_KERNEL_ME; i++)
4924         gen8_gpe_context_destroy(&avc_ctx->context_me.gpe_contexts[i]);
4925
4926     for(i = 0; i < NUM_GEN9_AVC_KERNEL_MBENC; i++)
4927         gen8_gpe_context_destroy(&avc_ctx->context_mbenc.gpe_contexts[i]);
4928
4929     gen8_gpe_context_destroy(&avc_ctx->context_wp.gpe_contexts);
4930
4931     gen8_gpe_context_destroy(&avc_ctx->context_sfd.gpe_contexts);
4932
4933 }
4934
4935 /*
4936 vme pipeline
4937 */
4938 static void
4939 gen9_avc_update_parameters(VADriverContextP ctx,
4940                              VAProfile profile,
4941                              struct encode_state *encode_state,
4942                              struct intel_encoder_context *encoder_context)
4943 {
4944     struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
4945     struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
4946     struct avc_enc_state * avc_state = (struct avc_enc_state * )vme_context->private_enc_state;
4947     VAEncSequenceParameterBufferH264 *seq_param;
4948     VAEncPictureParameterBufferH264 *pic_param ;
4949     VAEncSliceParameterBufferH264 * slice_param;
4950     int i,j;
4951     unsigned int preset = generic_state->preset;
4952
4953     /* seq/pic/slice parameter setting */
4954     generic_state->b16xme_supported = gen9_avc_super_hme[preset];
4955     generic_state->b32xme_supported = gen9_avc_ultra_hme[preset];
4956
4957     avc_state->seq_param =  (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
4958     avc_state->pic_param = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
4959
4960
4961     avc_state->enable_avc_ildb = 0;
4962     avc_state->slice_num = 0;
4963     for (j = 0; j < encode_state->num_slice_params_ext && avc_state->enable_avc_ildb == 0; j++) {
4964         assert(encode_state->slice_params_ext && encode_state->slice_params_ext[j]->buffer);
4965         slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[j]->buffer;
4966
4967         for (i = 0; i < encode_state->slice_params_ext[j]->num_elements; i++) {
4968             assert((slice_param->slice_type == SLICE_TYPE_I) ||
4969                    (slice_param->slice_type == SLICE_TYPE_SI) ||
4970                    (slice_param->slice_type == SLICE_TYPE_P) ||
4971                    (slice_param->slice_type == SLICE_TYPE_SP) ||
4972                    (slice_param->slice_type == SLICE_TYPE_B));
4973
4974             if (slice_param->disable_deblocking_filter_idc != 1) {
4975                 avc_state->enable_avc_ildb = 1;
4976             }
4977
4978             avc_state->slice_param[i] = slice_param;
4979             slice_param++;
4980             avc_state->slice_num++;
4981         }
4982     }
4983
4984     /* how many slices support by now? 1 slice or multi slices, but row slice.not slice group. */
4985     seq_param = avc_state->seq_param;
4986     pic_param = avc_state->pic_param;
4987     slice_param = avc_state->slice_param[0];
4988
4989     generic_state->frame_type = avc_state->slice_param[0]->slice_type;
4990
4991     if (slice_param->slice_type == SLICE_TYPE_I ||
4992         slice_param->slice_type == SLICE_TYPE_SI)
4993         generic_state->frame_type = SLICE_TYPE_I;
4994     else if(slice_param->slice_type == SLICE_TYPE_P)
4995         generic_state->frame_type = SLICE_TYPE_P;
4996     else if(slice_param->slice_type == SLICE_TYPE_B)
4997         generic_state->frame_type = SLICE_TYPE_B;
4998     if (profile == VAProfileH264High)
4999         avc_state->transform_8x8_mode_enable = !!pic_param->pic_fields.bits.transform_8x8_mode_flag;
5000     else
5001         avc_state->transform_8x8_mode_enable = 0;
5002
5003     /* rc init*/
5004     if(generic_state->brc_enabled &&(!generic_state->brc_inited || generic_state->brc_need_reset ))
5005     {
5006         generic_state->target_bit_rate = ALIGN(seq_param->bits_per_second, 1000) / 1000;
5007         generic_state->init_vbv_buffer_fullness_in_bit = seq_param->bits_per_second;
5008         generic_state->vbv_buffer_size_in_bit = (uint64_t)seq_param->bits_per_second << 1;
5009         generic_state->frames_per_100s = 3000; /* 30fps */
5010     }
5011
5012     generic_state->gop_size = seq_param->intra_period;
5013     generic_state->gop_ref_distance = seq_param->ip_period;
5014
5015     if (generic_state->internal_rate_mode == VA_RC_CBR) {
5016         generic_state->max_bit_rate = generic_state->target_bit_rate;
5017         generic_state->min_bit_rate = generic_state->target_bit_rate;
5018     }
5019
5020     if(generic_state->frame_type == SLICE_TYPE_I || generic_state->first_frame)
5021     {
5022         gen9_avc_update_misc_parameters(ctx, encode_state, encoder_context);
5023     }
5024
5025     generic_state->preset = encoder_context->quality_level;
5026     if(encoder_context->quality_level == INTEL_PRESET_UNKNOWN)
5027     {
5028         generic_state->preset = INTEL_PRESET_RT_SPEED;
5029     }
5030     generic_state->kernel_mode = gen9_avc_kernel_mode[generic_state->preset];
5031
5032     if(!generic_state->brc_inited)
5033     {
5034         generic_state->brc_init_reset_input_bits_per_frame = ((double)(generic_state->max_bit_rate * 1000) * 100) / generic_state->frames_per_100s;;
5035         generic_state->brc_init_current_target_buf_full_in_bits = generic_state->init_vbv_buffer_fullness_in_bit;
5036         generic_state->brc_init_reset_buf_size_in_bits = generic_state->vbv_buffer_size_in_bit;
5037         generic_state->brc_target_size = generic_state->init_vbv_buffer_fullness_in_bit;
5038     }
5039
5040
5041     generic_state->curr_pak_pass = 0;
5042     generic_state->num_pak_passes = MAX_AVC_PAK_PASS_NUM;
5043
5044     if (generic_state->internal_rate_mode == VA_RC_CBR ||
5045         generic_state->internal_rate_mode == VA_RC_VBR)
5046         generic_state->brc_enabled = 1;
5047     else
5048         generic_state->brc_enabled = 0;
5049
5050     if (generic_state->brc_enabled &&
5051         (!generic_state->init_vbv_buffer_fullness_in_bit ||
5052          !generic_state->vbv_buffer_size_in_bit ||
5053          !generic_state->max_bit_rate ||
5054          !generic_state->target_bit_rate ||
5055          !generic_state->frames_per_100s))
5056     {
5057         WARN_ONCE("Rate control parameter is required for BRC\n");
5058         generic_state->brc_enabled = 0;
5059     }
5060
5061     if (!generic_state->brc_enabled) {
5062         generic_state->target_bit_rate = 0;
5063         generic_state->max_bit_rate = 0;
5064         generic_state->min_bit_rate = 0;
5065         generic_state->init_vbv_buffer_fullness_in_bit = 0;
5066         generic_state->vbv_buffer_size_in_bit = 0;
5067         generic_state->num_pak_passes = 1;
5068     } else {
5069         generic_state->num_pak_passes = MAX_AVC_PAK_PASS_NUM;
5070     }
5071
5072
5073     generic_state->frame_width_in_mbs = seq_param->picture_width_in_mbs;
5074     generic_state->frame_height_in_mbs = seq_param->picture_height_in_mbs;
5075     generic_state->frame_width_in_pixel = generic_state->frame_width_in_mbs * 16;
5076     generic_state->frame_height_in_pixel = generic_state->frame_height_in_mbs * 16;
5077
5078     generic_state->frame_width_4x  = ALIGN(generic_state->frame_width_in_pixel/4,16);
5079     generic_state->frame_height_4x = ALIGN(generic_state->frame_height_in_pixel/4,16);
5080     generic_state->downscaled_width_4x_in_mb  = generic_state->frame_width_4x/16 ;
5081     generic_state->downscaled_height_4x_in_mb = generic_state->frame_height_4x/16;
5082
5083     generic_state->frame_width_16x  =  ALIGN(generic_state->frame_width_in_pixel/16,16);
5084     generic_state->frame_height_16x =  ALIGN(generic_state->frame_height_in_pixel/16,16);
5085     generic_state->downscaled_width_16x_in_mb  = generic_state->frame_width_16x/16 ;
5086     generic_state->downscaled_height_16x_in_mb = generic_state->frame_height_16x/16;
5087
5088     generic_state->frame_width_32x  = ALIGN(generic_state->frame_width_in_pixel/32,16);
5089     generic_state->frame_height_32x = ALIGN(generic_state->frame_height_in_pixel/32,16);
5090     generic_state->downscaled_width_32x_in_mb  = generic_state->frame_width_32x/16 ;
5091     generic_state->downscaled_height_32x_in_mb = generic_state->frame_height_32x/16;
5092
5093     if (generic_state->hme_supported) {
5094         generic_state->hme_enabled = 1;
5095     } else {
5096         generic_state->hme_enabled = 0;
5097     }
5098
5099     if (generic_state->b16xme_supported) {
5100         generic_state->b16xme_enabled = 1;
5101     } else {
5102         generic_state->b16xme_enabled = 0;
5103     }
5104
5105     if (generic_state->b32xme_supported) {
5106         generic_state->b32xme_enabled = 1;
5107     } else {
5108         generic_state->b32xme_enabled = 0;
5109     }
5110     /* disable HME/16xME if the size is too small */
5111     if (generic_state->frame_width_4x <= INTEL_VME_MIN_ALLOWED_WIDTH_HEIGHT) {
5112         generic_state->b32xme_supported = 0;
5113         generic_state->b32xme_enabled = 0;
5114         generic_state->b16xme_supported = 0;
5115         generic_state->b16xme_enabled = 0;
5116         generic_state->frame_width_4x = INTEL_VME_MIN_ALLOWED_WIDTH_HEIGHT;
5117         generic_state->downscaled_width_4x_in_mb = WIDTH_IN_MACROBLOCKS(INTEL_VME_MIN_ALLOWED_WIDTH_HEIGHT);
5118     }
5119     if (generic_state->frame_height_4x <= INTEL_VME_MIN_ALLOWED_WIDTH_HEIGHT) {
5120         generic_state->b32xme_supported = 0;
5121         generic_state->b32xme_enabled = 0;
5122         generic_state->b16xme_supported = 0;
5123         generic_state->b16xme_enabled = 0;
5124         generic_state->frame_height_4x = INTEL_VME_MIN_ALLOWED_WIDTH_HEIGHT;
5125         generic_state->downscaled_height_4x_in_mb = WIDTH_IN_MACROBLOCKS(INTEL_VME_MIN_ALLOWED_WIDTH_HEIGHT);
5126     }
5127
5128     if (generic_state->frame_width_16x < INTEL_VME_MIN_ALLOWED_WIDTH_HEIGHT)
5129     {
5130         generic_state->b32xme_supported = 0;
5131         generic_state->b32xme_enabled = 0;
5132         generic_state->frame_width_16x = INTEL_VME_MIN_ALLOWED_WIDTH_HEIGHT;
5133         generic_state->downscaled_width_16x_in_mb = WIDTH_IN_MACROBLOCKS(INTEL_VME_MIN_ALLOWED_WIDTH_HEIGHT);
5134     }
5135     if (generic_state->frame_height_16x < INTEL_VME_MIN_ALLOWED_WIDTH_HEIGHT) {
5136         generic_state->b32xme_supported = 0;
5137         generic_state->b32xme_enabled = 0;
5138         generic_state->frame_height_16x = INTEL_VME_MIN_ALLOWED_WIDTH_HEIGHT;
5139         generic_state->downscaled_height_16x_in_mb = WIDTH_IN_MACROBLOCKS(INTEL_VME_MIN_ALLOWED_WIDTH_HEIGHT);
5140     }
5141
5142     if (generic_state->frame_width_32x < INTEL_VME_MIN_ALLOWED_WIDTH_HEIGHT)
5143     {
5144         generic_state->frame_width_32x = INTEL_VME_MIN_ALLOWED_WIDTH_HEIGHT;
5145         generic_state->downscaled_width_32x_in_mb = WIDTH_IN_MACROBLOCKS(INTEL_VME_MIN_ALLOWED_WIDTH_HEIGHT);
5146     }
5147     if (generic_state->frame_height_32x < INTEL_VME_MIN_ALLOWED_WIDTH_HEIGHT) {
5148         generic_state->frame_height_32x = INTEL_VME_MIN_ALLOWED_WIDTH_HEIGHT;
5149         generic_state->downscaled_height_32x_in_mb = WIDTH_IN_MACROBLOCKS(INTEL_VME_MIN_ALLOWED_WIDTH_HEIGHT);
5150     }
5151
5152 }
5153
5154 static VAStatus
5155 gen9_avc_encode_check_parameter(VADriverContextP ctx,
5156                                 struct encode_state *encode_state,
5157                                 struct intel_encoder_context *encoder_context)
5158 {
5159     struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
5160     struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
5161     struct avc_enc_state * avc_state = (struct avc_enc_state * )vme_context->private_enc_state;
5162     unsigned int rate_control_mode = encoder_context->rate_control_mode;
5163     unsigned int preset = generic_state->preset;
5164     VAEncPictureParameterBufferH264 *pic_param ;
5165     int i = 0;
5166
5167     /*resolution change detection*/
5168     pic_param = avc_state->pic_param;
5169
5170     /*avbr init*/
5171     generic_state->avbr_curracy = 30;
5172     generic_state->avbr_convergence = 150;
5173
5174     switch (rate_control_mode & 0x7f) {
5175     case VA_RC_CBR:
5176         generic_state->internal_rate_mode = VA_RC_CBR;
5177         break;
5178
5179     case VA_RC_VBR:
5180         generic_state->internal_rate_mode = VA_RC_VBR;
5181         break;
5182
5183     case VA_RC_CQP:
5184     default:
5185         generic_state->internal_rate_mode = VA_RC_CQP;
5186         break;
5187     }
5188
5189     if (rate_control_mode != VA_RC_NONE &&
5190         rate_control_mode != VA_RC_CQP) {
5191         generic_state->brc_enabled = 1;
5192         generic_state->brc_distortion_buffer_supported = 1;
5193         generic_state->brc_constant_buffer_supported = 1;
5194         generic_state->num_pak_passes = MAX_AVC_PAK_PASS_NUM;
5195     }
5196
5197     /*check brc parameter*/
5198     if(generic_state->brc_enabled)
5199     {
5200        avc_state->mb_qp_data_enable = 0;
5201     }
5202
5203     /*set the brc init and reset accordingly*/
5204     if(generic_state->brc_need_reset &&
5205         (generic_state->brc_distortion_buffer_supported == 0 ||
5206         rate_control_mode == VA_RC_CQP))
5207     {
5208        generic_state->brc_need_reset = 0;// not support by CQP
5209     }
5210
5211     if(generic_state->brc_need_reset && !avc_state->sfd_mb_enable)
5212     {
5213         avc_state->sfd_enable = 0;
5214     }
5215
5216     if(generic_state->frames_per_window_size == 0)
5217     {
5218         generic_state->frames_per_window_size = (generic_state->frames_per_100s/100 < 60)?(generic_state->frames_per_100s/100):60;
5219     }else if(generic_state->frames_per_window_size > 2 * generic_state->frames_per_100s/100)
5220     {
5221         generic_state->frames_per_window_size = (generic_state->frames_per_100s/100 < 60)?(generic_state->frames_per_100s/100):60;
5222     }
5223
5224     if(generic_state->brc_enabled)
5225     {
5226         generic_state->hme_enabled = generic_state->frame_type != SLICE_TYPE_I;
5227         if(avc_state->min_max_qp_enable)
5228         {
5229             generic_state->num_pak_passes = 1;
5230         }
5231         generic_state->brc_roi_enable = (rate_control_mode != VA_RC_CQP) && (generic_state->num_roi > 0);// only !CQP
5232         generic_state->mb_brc_enabled = generic_state->mb_brc_enabled || generic_state->brc_roi_enable;
5233     }else
5234     {
5235         generic_state->num_pak_passes = 1;// CQP only one pass
5236     }
5237
5238     avc_state->mbenc_i_frame_dist_in_use = 0;
5239     avc_state->mbenc_i_frame_dist_in_use = (generic_state->brc_enabled) && (generic_state->brc_distortion_buffer_supported) && (generic_state->frame_type == SLICE_TYPE_I);
5240
5241     /*ROI must enable mbbrc.*/
5242
5243     /*CAD check*/
5244     if(avc_state->caf_supported)
5245     {
5246         switch(generic_state->frame_type)
5247         {
5248         case SLICE_TYPE_I:
5249             break;
5250         case SLICE_TYPE_P:
5251             avc_state->caf_enable = gen9_avc_all_fractional[preset] & 0x01;
5252             break;
5253         case SLICE_TYPE_B:
5254             avc_state->caf_enable = (gen9_avc_all_fractional[preset] >> 1) & 0x01;
5255             break;
5256         }
5257
5258         if(avc_state->caf_enable && avc_state->caf_disable_hd && gen9_avc_disable_all_fractional_check_for_high_res[preset])
5259         {
5260             if(generic_state->frame_width_in_pixel >= 1280 && generic_state->frame_height_in_pixel >= 720)
5261                  avc_state->caf_enable = 0;
5262         }
5263     }
5264
5265     avc_state->adaptive_transform_decision_enable &= gen9_avc_enable_adaptive_tx_decision[preset&0x7];
5266
5267     /* Flatness check is enabled only if scaling will be performed and CAF is enabled. here only frame */
5268     if(avc_state->flatness_check_supported )
5269     {
5270         avc_state->flatness_check_enable = ((avc_state->caf_enable) && (generic_state->brc_enabled || generic_state->hme_supported)) ;
5271     }else
5272     {
5273         avc_state->flatness_check_enable = 0;
5274     }
5275
5276     /* check mb_status_supported/enbale*/
5277     if(avc_state->adaptive_transform_decision_enable)
5278     {
5279        avc_state->mb_status_enable = 1;
5280     }else
5281     {
5282        avc_state->mb_status_enable = 0;
5283     }
5284     /*slice check,all the slices use the same slice height except the last slice*/
5285     avc_state->arbitrary_num_mbs_in_slice = 0;
5286     for(i = 0; i < avc_state->slice_num;i++)
5287     {
5288         assert(avc_state->slice_param[i]->num_macroblocks % generic_state->frame_width_in_mbs == 0);
5289         avc_state->slice_height = avc_state->slice_param[i]->num_macroblocks / generic_state->frame_width_in_mbs;
5290         /*add it later for muli slices map*/
5291     }
5292
5293     if(generic_state->frame_type == SLICE_TYPE_I)
5294     {
5295        generic_state->hme_enabled = 0;
5296        generic_state->b16xme_enabled = 0;
5297        generic_state->b32xme_enabled = 0;
5298     }
5299
5300     if(generic_state->frame_type == SLICE_TYPE_B)
5301     {
5302         gen9_avc_get_dist_scale_factor(ctx,encode_state,encoder_context);
5303         avc_state->bi_weight = gen9_avc_get_biweight(avc_state->dist_scale_factor_list0[0],pic_param->pic_fields.bits.weighted_bipred_idc);
5304     }
5305
5306     /* Determine if SkipBiasAdjustment should be enabled for P picture 1. No B frame 2. Qp >= 22 3. CQP mode */
5307     avc_state->skip_bias_adjustment_enable = avc_state->skip_bias_adjustment_supported && (generic_state->frame_type == SLICE_TYPE_P)
5308         && (generic_state->gop_ref_distance == 1) && (avc_state->pic_param->pic_init_qp + avc_state->slice_param[0]->slice_qp_delta >= 22) && !generic_state->brc_enabled;
5309
5310     if(generic_state->kernel_mode == INTEL_ENC_KERNEL_QUALITY)
5311     {
5312         avc_state->tq_enable = 1;
5313         avc_state->tq_rounding = 6;
5314         if(generic_state->brc_enabled)
5315         {
5316             generic_state->mb_brc_enabled = 1;
5317         }
5318     }
5319
5320     return VA_STATUS_SUCCESS;
5321 }
5322
5323 static VAStatus
5324 gen9_avc_vme_gpe_kernel_prepare(VADriverContextP ctx,
5325                                 struct encode_state *encode_state,
5326                                 struct intel_encoder_context *encoder_context)
5327 {
5328     VAStatus va_status;
5329     struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
5330     struct generic_encoder_context * generic_ctx = (struct generic_encoder_context * )vme_context->generic_enc_ctx;
5331     struct i965_avc_encoder_context * avc_ctx = (struct i965_avc_encoder_context * )vme_context->private_enc_ctx;
5332     struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
5333     struct avc_enc_state * avc_state = (struct avc_enc_state * )vme_context->private_enc_state;
5334
5335     struct object_surface *obj_surface;
5336     struct object_buffer *obj_buffer;
5337     VAEncSliceParameterBufferH264 * slice_param = avc_state->slice_param[0];
5338     VAEncPictureParameterBufferH264  *pic_param = avc_state->pic_param;
5339     struct i965_coded_buffer_segment *coded_buffer_segment;
5340
5341     struct gen9_surface_avc *avc_priv_surface;
5342     dri_bo *bo;
5343     struct avc_surface_param surface_param;
5344     int i,j = 0;
5345     unsigned char * pdata;
5346
5347     /* Setup current reconstruct frame */
5348     obj_surface = encode_state->reconstructed_object;
5349     va_status = i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
5350
5351     if (va_status != VA_STATUS_SUCCESS)
5352         return va_status;
5353
5354     memset(&surface_param,0,sizeof(surface_param));
5355     surface_param.frame_width = generic_state->frame_width_in_pixel;
5356     surface_param.frame_height = generic_state->frame_height_in_pixel;
5357     va_status = gen9_avc_init_check_surfaces(ctx,
5358                                              obj_surface,
5359                                              encoder_context,
5360                                              &surface_param);
5361     if (va_status != VA_STATUS_SUCCESS)
5362         return va_status;
5363     {
5364     /* init the member of avc_priv_surface,frame_store_id,qp_value*/
5365        avc_priv_surface = (struct gen9_surface_avc *)obj_surface->private_data;
5366        avc_state->top_field_poc[NUM_MFC_AVC_DMV_BUFFERS-2] = 0;
5367        avc_state->top_field_poc[NUM_MFC_AVC_DMV_BUFFERS-1] = 0;
5368        i965_free_gpe_resource(&avc_ctx->res_direct_mv_buffersr[NUM_MFC_AVC_DMV_BUFFERS-2]);
5369        i965_free_gpe_resource(&avc_ctx->res_direct_mv_buffersr[NUM_MFC_AVC_DMV_BUFFERS-1]);
5370        i965_dri_object_to_buffer_gpe_resource(&avc_ctx->res_direct_mv_buffersr[NUM_MFC_AVC_DMV_BUFFERS-2],avc_priv_surface->dmv_top);
5371        i965_dri_object_to_buffer_gpe_resource(&avc_ctx->res_direct_mv_buffersr[NUM_MFC_AVC_DMV_BUFFERS-1],avc_priv_surface->dmv_bottom);
5372        avc_priv_surface->qp_value = pic_param->pic_init_qp + slice_param->slice_qp_delta;
5373        avc_priv_surface->frame_store_id = 0;
5374        avc_priv_surface->frame_idx = pic_param->CurrPic.frame_idx;
5375        avc_priv_surface->top_field_order_cnt = pic_param->CurrPic.TopFieldOrderCnt;
5376        avc_priv_surface->is_as_ref = pic_param->pic_fields.bits.reference_pic_flag;
5377        avc_state->top_field_poc[NUM_MFC_AVC_DMV_BUFFERS-2] = avc_priv_surface->top_field_order_cnt;
5378        avc_state->top_field_poc[NUM_MFC_AVC_DMV_BUFFERS-1] = avc_priv_surface->top_field_order_cnt + 1;
5379     }
5380     i965_free_gpe_resource(&generic_ctx->res_reconstructed_surface);
5381     i965_object_surface_to_2d_gpe_resource_with_align(&generic_ctx->res_reconstructed_surface, obj_surface,GPE_RESOURCE_ALIGNMENT);
5382
5383     /* input YUV surface*/
5384     obj_surface = encode_state->input_yuv_object;
5385     va_status = i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
5386
5387     if (va_status != VA_STATUS_SUCCESS)
5388         return va_status;
5389     i965_free_gpe_resource(&generic_ctx->res_uncompressed_input_surface);
5390     i965_object_surface_to_2d_gpe_resource_with_align(&generic_ctx->res_uncompressed_input_surface, obj_surface,GPE_RESOURCE_ALIGNMENT);
5391
5392     /* Reference surfaces */
5393     for (i = 0; i < ARRAY_ELEMS(avc_ctx->list_reference_res); i++) {
5394         i965_free_gpe_resource(&avc_ctx->list_reference_res[i]);
5395         i965_free_gpe_resource(&avc_ctx->res_direct_mv_buffersr[i*2]);
5396         i965_free_gpe_resource(&avc_ctx->res_direct_mv_buffersr[i*2 + 1]);
5397         obj_surface = encode_state->reference_objects[i];
5398         avc_state->top_field_poc[2*i] = 0;
5399         avc_state->top_field_poc[2*i+1] = 0;
5400
5401         if (obj_surface && obj_surface->bo) {
5402             i965_object_surface_to_2d_gpe_resource_with_align(&avc_ctx->list_reference_res[i], obj_surface,GPE_RESOURCE_ALIGNMENT);
5403
5404             /* actually it should be handled when it is reconstructed surface*/
5405             va_status = gen9_avc_init_check_surfaces(ctx,
5406                 obj_surface,encoder_context,
5407                 &surface_param);
5408             if (va_status != VA_STATUS_SUCCESS)
5409                 return va_status;
5410             avc_priv_surface = (struct gen9_surface_avc *)obj_surface->private_data;
5411             i965_dri_object_to_buffer_gpe_resource(&avc_ctx->res_direct_mv_buffersr[i*2],avc_priv_surface->dmv_top);
5412             i965_dri_object_to_buffer_gpe_resource(&avc_ctx->res_direct_mv_buffersr[i*2 + 1],avc_priv_surface->dmv_bottom);
5413             avc_state->top_field_poc[2*i] = avc_priv_surface->top_field_order_cnt;
5414             avc_state->top_field_poc[2*i+1] = avc_priv_surface->top_field_order_cnt + 1;
5415             avc_priv_surface->frame_store_id = i;
5416         }else
5417         {
5418             break;
5419         }
5420     }
5421
5422     /* Encoded bitstream ?*/
5423     obj_buffer = encode_state->coded_buf_object;
5424     bo = obj_buffer->buffer_store->bo;
5425     i965_free_gpe_resource(&generic_ctx->compressed_bitstream.res);
5426     i965_dri_object_to_buffer_gpe_resource(&generic_ctx->compressed_bitstream.res, bo);
5427     generic_ctx->compressed_bitstream.start_offset = I965_CODEDBUFFER_HEADER_SIZE;
5428     generic_ctx->compressed_bitstream.end_offset = ALIGN(obj_buffer->size_element - 0x1000, 0x1000);
5429
5430     /*status buffer */
5431     avc_ctx->status_buffer.bo = bo;
5432
5433     /* set the internal flag to 0 to indicate the coded size is unknown */
5434     dri_bo_map(bo, 1);
5435     coded_buffer_segment = (struct i965_coded_buffer_segment *)bo->virtual;
5436     coded_buffer_segment->mapped = 0;
5437     coded_buffer_segment->codec = encoder_context->codec;
5438     coded_buffer_segment->status_support = 1;
5439
5440     pdata = bo->virtual + avc_ctx->status_buffer.base_offset;
5441     memset(pdata,0,avc_ctx->status_buffer.status_buffer_size);
5442     dri_bo_unmap(bo);
5443
5444     //frame id, it is the ref pic id in the reference_objects list.
5445     avc_state->num_refs[0] = 0;
5446     avc_state->num_refs[1] = 0;
5447     if (generic_state->frame_type == SLICE_TYPE_P) {
5448         avc_state->num_refs[0] = pic_param->num_ref_idx_l0_active_minus1 + 1;
5449
5450         if (slice_param->num_ref_idx_active_override_flag)
5451             avc_state->num_refs[0] = slice_param->num_ref_idx_l0_active_minus1 + 1;
5452     } else if (generic_state->frame_type == SLICE_TYPE_B) {
5453         avc_state->num_refs[0] = pic_param->num_ref_idx_l0_active_minus1 + 1;
5454         avc_state->num_refs[1] = pic_param->num_ref_idx_l1_active_minus1 + 1;
5455
5456         if (slice_param->num_ref_idx_active_override_flag) {
5457             avc_state->num_refs[0] = slice_param->num_ref_idx_l0_active_minus1 + 1;
5458             avc_state->num_refs[1] = slice_param->num_ref_idx_l1_active_minus1 + 1;
5459         }
5460     }
5461
5462     if (avc_state->num_refs[0] > ARRAY_ELEMS(avc_state->list_ref_idx[0]))
5463         return VA_STATUS_ERROR_INVALID_VALUE;
5464     if (avc_state->num_refs[1] > ARRAY_ELEMS(avc_state->list_ref_idx[1]))
5465         return VA_STATUS_ERROR_INVALID_VALUE;
5466
5467     for (i = 0; i < ARRAY_ELEMS(avc_state->list_ref_idx[0]); i++) {
5468         VAPictureH264 *va_pic;
5469
5470         assert(ARRAY_ELEMS(slice_param->RefPicList0) == ARRAY_ELEMS(avc_state->list_ref_idx[0]));
5471         avc_state->list_ref_idx[0][i] = 0;
5472
5473         if (i >= avc_state->num_refs[0])
5474             continue;
5475
5476         va_pic = &slice_param->RefPicList0[i];
5477
5478         for (j = 0; j < ARRAY_ELEMS(encode_state->reference_objects); j++) {
5479             obj_surface = encode_state->reference_objects[j];
5480
5481             if (obj_surface &&
5482                 obj_surface->bo &&
5483                 obj_surface->base.id == va_pic->picture_id) {
5484
5485                 assert(obj_surface->base.id != VA_INVALID_SURFACE);
5486                 avc_state->list_ref_idx[0][i] = j;
5487
5488                 break;
5489             }
5490         }
5491     }
5492     for (i = 0; i < ARRAY_ELEMS(avc_state->list_ref_idx[1]); i++) {
5493         VAPictureH264 *va_pic;
5494
5495         assert(ARRAY_ELEMS(slice_param->RefPicList1) == ARRAY_ELEMS(avc_state->list_ref_idx[1]));
5496         avc_state->list_ref_idx[1][i] = 0;
5497
5498         if (i >= avc_state->num_refs[1])
5499             continue;
5500
5501         va_pic = &slice_param->RefPicList1[i];
5502
5503         for (j = 0; j < ARRAY_ELEMS(encode_state->reference_objects); j++) {
5504             obj_surface = encode_state->reference_objects[j];
5505
5506             if (obj_surface &&
5507                 obj_surface->bo &&
5508                 obj_surface->base.id == va_pic->picture_id) {
5509
5510                 assert(obj_surface->base.id != VA_INVALID_SURFACE);
5511                 avc_state->list_ref_idx[1][i] = j;
5512
5513                 break;
5514             }
5515         }
5516     }
5517
5518     return VA_STATUS_SUCCESS;
5519 }
5520
5521 static VAStatus
5522 gen9_avc_vme_gpe_kernel_init(VADriverContextP ctx,
5523                              struct encode_state *encode_state,
5524                              struct intel_encoder_context *encoder_context)
5525 {
5526     return VA_STATUS_SUCCESS;
5527 }
5528
5529 static VAStatus
5530 gen9_avc_vme_gpe_kernel_final(VADriverContextP ctx,
5531                               struct encode_state *encode_state,
5532                               struct intel_encoder_context *encoder_context)
5533 {
5534
5535     struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
5536     struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
5537     struct avc_enc_state * avc_state = (struct avc_enc_state * )vme_context->private_enc_state;
5538
5539     /*set this flag when all kernel is finished*/
5540     if(generic_state->brc_enabled)
5541     {
5542         generic_state->brc_inited = 1;
5543         generic_state->brc_need_reset = 0;
5544         avc_state->mbenc_curbe_set_in_brc_update = 0;
5545     }
5546     return VA_STATUS_SUCCESS;
5547 }
5548
5549 static VAStatus
5550 gen9_avc_vme_gpe_kernel_run(VADriverContextP ctx,
5551                             struct encode_state *encode_state,
5552                             struct intel_encoder_context *encoder_context)
5553 {
5554     struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
5555     struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
5556     struct avc_enc_state * avc_state = (struct avc_enc_state * )vme_context->private_enc_state;
5557
5558     VAEncPictureParameterBufferH264  *pic_param = avc_state->pic_param;
5559     VAEncSliceParameterBufferH264 *slice_param = avc_state->slice_param[0];
5560     int sfd_in_use = 0;
5561
5562     /* BRC init/reset needs to be called before HME since it will reset the Brc Distortion surface*/
5563     if(generic_state->brc_enabled &&(!generic_state->brc_inited || generic_state->brc_need_reset ))
5564     {
5565         gen9_avc_kernel_brc_init_reset(ctx,encode_state,encoder_context);
5566     }
5567
5568     /*down scaling*/
5569     if(generic_state->hme_supported)
5570     {
5571         gen9_avc_kernel_scaling(ctx,encode_state,encoder_context,INTEL_ENC_HME_4x);
5572         if(generic_state->b16xme_supported)
5573         {
5574             gen9_avc_kernel_scaling(ctx,encode_state,encoder_context,INTEL_ENC_HME_16x);
5575             if(generic_state->b32xme_supported)
5576             {
5577                 gen9_avc_kernel_scaling(ctx,encode_state,encoder_context,INTEL_ENC_HME_32x);
5578             }
5579         }
5580     }
5581
5582     /*me kernel*/
5583     if(generic_state->hme_enabled)
5584     {
5585         if(generic_state->b16xme_enabled)
5586         {
5587             if(generic_state->b32xme_enabled)
5588             {
5589                 gen9_avc_kernel_me(ctx,encode_state,encoder_context,INTEL_ENC_HME_32x);
5590             }
5591             gen9_avc_kernel_me(ctx,encode_state,encoder_context,INTEL_ENC_HME_16x);
5592         }
5593         gen9_avc_kernel_me(ctx,encode_state,encoder_context,INTEL_ENC_HME_4x);
5594     }
5595
5596     /*call SFD kernel after HME in same command buffer*/
5597     sfd_in_use = avc_state->sfd_enable && generic_state->hme_enabled;
5598     sfd_in_use = sfd_in_use && !avc_state->sfd_mb_enable;
5599     if(sfd_in_use)
5600     {
5601         gen9_avc_kernel_sfd(ctx,encode_state,encoder_context);
5602     }
5603
5604     /* BRC and MbEnc are included in the same task phase*/
5605     if(generic_state->brc_enabled)
5606     {
5607         if(avc_state->mbenc_i_frame_dist_in_use)
5608         {
5609             gen9_avc_kernel_mbenc(ctx,encode_state,encoder_context,true);
5610         }
5611         gen9_avc_kernel_brc_frame_update(ctx,encode_state,encoder_context);
5612
5613         if(generic_state->mb_brc_enabled)
5614         {
5615             gen9_avc_kernel_brc_mb_update(ctx,encode_state,encoder_context);
5616         }
5617     }
5618
5619     /*weight prediction,disable by now */
5620     avc_state->weighted_ref_l0_enable = 0;
5621     avc_state->weighted_ref_l1_enable = 0;
5622     if(avc_state->weighted_prediction_supported &&
5623         ((generic_state->frame_type == SLICE_TYPE_P && pic_param->pic_fields.bits.weighted_pred_flag) ||
5624         (generic_state->frame_type == SLICE_TYPE_B && pic_param->pic_fields.bits.weighted_bipred_idc == INTEL_AVC_WP_MODE_EXPLICIT)))
5625     {
5626         if(slice_param->luma_weight_l0_flag & 1)
5627         {
5628             gen9_avc_kernel_wp(ctx,encode_state,encoder_context,0);
5629
5630         }else if(!(slice_param->chroma_weight_l0_flag & 1))
5631         {
5632             pic_param->pic_fields.bits.weighted_pred_flag = 0;// it should be handled in app
5633         }
5634
5635         if(generic_state->frame_type == SLICE_TYPE_B && pic_param->pic_fields.bits.weighted_bipred_idc == INTEL_AVC_WP_MODE_EXPLICIT)
5636         {
5637             if(slice_param->luma_weight_l1_flag & 1)
5638             {
5639                 gen9_avc_kernel_wp(ctx,encode_state,encoder_context,1);
5640             }else if(!((slice_param->luma_weight_l0_flag & 1)||
5641                        (slice_param->chroma_weight_l0_flag & 1)||
5642                        (slice_param->chroma_weight_l1_flag & 1)))
5643             {
5644                 pic_param->pic_fields.bits.weighted_bipred_idc = INTEL_AVC_WP_MODE_DEFAULT;// it should be handled in app
5645             }
5646         }
5647     }
5648
5649     /*mbenc kernel*/
5650     gen9_avc_kernel_mbenc(ctx,encode_state,encoder_context,false);
5651
5652     /*ignore the reset vertical line kernel*/
5653
5654     return VA_STATUS_SUCCESS;
5655 }
5656
5657 static VAStatus
5658 gen9_avc_vme_pipeline(VADriverContextP ctx,
5659                       VAProfile profile,
5660                       struct encode_state *encode_state,
5661                       struct intel_encoder_context *encoder_context)
5662 {
5663     VAStatus va_status;
5664
5665     gen9_avc_update_parameters(ctx, profile, encode_state, encoder_context);
5666
5667     va_status = gen9_avc_encode_check_parameter(ctx, encode_state, encoder_context);
5668     if (va_status != VA_STATUS_SUCCESS)
5669         return va_status;
5670
5671     va_status = gen9_avc_allocate_resources(ctx, encode_state, encoder_context);
5672     if (va_status != VA_STATUS_SUCCESS)
5673         return va_status;
5674
5675     va_status = gen9_avc_vme_gpe_kernel_prepare(ctx, encode_state, encoder_context);
5676     if (va_status != VA_STATUS_SUCCESS)
5677         return va_status;
5678
5679     va_status = gen9_avc_vme_gpe_kernel_init(ctx, encode_state, encoder_context);
5680     if (va_status != VA_STATUS_SUCCESS)
5681         return va_status;
5682
5683     va_status = gen9_avc_vme_gpe_kernel_run(ctx, encode_state, encoder_context);
5684     if (va_status != VA_STATUS_SUCCESS)
5685         return va_status;
5686
5687     gen9_avc_vme_gpe_kernel_final(ctx, encode_state, encoder_context);
5688
5689     return VA_STATUS_SUCCESS;
5690 }
5691
5692 static void
5693 gen9_avc_vme_context_destroy(void * context)
5694 {
5695     struct encoder_vme_mfc_context *vme_context = (struct encoder_vme_mfc_context *)context;
5696     struct generic_encoder_context *generic_ctx;
5697     struct i965_avc_encoder_context *avc_ctx;
5698     struct generic_enc_codec_state *generic_state;
5699     struct avc_enc_state *avc_state;
5700
5701     if (!vme_context)
5702         return;
5703
5704     generic_ctx = (struct generic_encoder_context * )vme_context->generic_enc_ctx;
5705     avc_ctx = (struct i965_avc_encoder_context * )vme_context->private_enc_ctx;
5706     generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
5707     avc_state = (struct avc_enc_state * )vme_context->private_enc_state;
5708
5709     gen9_avc_kernel_destroy(vme_context);
5710
5711     free(generic_ctx);
5712     free(avc_ctx);
5713     free(generic_state);
5714     free(avc_state);
5715     free(vme_context);
5716     return;
5717
5718 }
5719
5720 static void
5721 gen9_avc_kernel_init(VADriverContextP ctx,
5722                      struct intel_encoder_context *encoder_context)
5723 {
5724     struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
5725     struct i965_avc_encoder_context * avc_ctx = (struct i965_avc_encoder_context * )vme_context->private_enc_ctx;
5726     struct generic_encoder_context * generic_ctx = (struct generic_encoder_context * )vme_context->generic_enc_ctx;
5727
5728     gen9_avc_kernel_init_scaling(ctx,generic_ctx,&avc_ctx->context_scaling);
5729     gen9_avc_kernel_init_brc(ctx,generic_ctx,&avc_ctx->context_brc);
5730     gen9_avc_kernel_init_me(ctx,generic_ctx,&avc_ctx->context_me);
5731     gen9_avc_kernel_init_mbenc(ctx,generic_ctx,&avc_ctx->context_mbenc);
5732     gen9_avc_kernel_init_wp(ctx,generic_ctx,&avc_ctx->context_wp);
5733     gen9_avc_kernel_init_sfd(ctx,generic_ctx,&avc_ctx->context_sfd);
5734
5735     //function pointer
5736     generic_ctx->pfn_set_curbe_scaling2x = gen9_avc_set_curbe_scaling2x;
5737     generic_ctx->pfn_set_curbe_scaling4x = gen9_avc_set_curbe_scaling4x;
5738     generic_ctx->pfn_set_curbe_me = gen9_avc_set_curbe_me;
5739     generic_ctx->pfn_set_curbe_mbenc = gen9_avc_set_curbe_mbenc;
5740     generic_ctx->pfn_set_curbe_brc_init_reset = gen9_avc_set_curbe_brc_init_reset;
5741     generic_ctx->pfn_set_curbe_brc_frame_update = gen9_avc_set_curbe_brc_frame_update;
5742     generic_ctx->pfn_set_curbe_brc_mb_update = gen9_avc_set_curbe_brc_mb_update;
5743     generic_ctx->pfn_set_curbe_sfd = gen9_avc_set_curbe_sfd;
5744     generic_ctx->pfn_set_curbe_wp = gen9_avc_set_curbe_wp;
5745
5746     generic_ctx->pfn_send_scaling_surface = gen9_avc_send_surface_scaling;
5747     generic_ctx->pfn_send_me_surface = gen9_avc_send_surface_me;
5748     generic_ctx->pfn_send_mbenc_surface = gen9_avc_send_surface_mbenc;
5749     generic_ctx->pfn_send_brc_init_reset_surface = gen9_avc_send_surface_brc_init_reset;
5750     generic_ctx->pfn_send_brc_frame_update_surface = gen9_avc_send_surface_brc_frame_update;
5751     generic_ctx->pfn_send_brc_mb_update_surface = gen9_avc_send_surface_brc_mb_update;
5752     generic_ctx->pfn_send_sfd_surface = gen9_avc_send_surface_sfd;
5753     generic_ctx->pfn_send_wp_surface = gen9_avc_send_surface_wp;
5754 }
5755
5756
5757 /*
5758 PAK pipeline related function
5759 */
5760 extern int
5761 intel_avc_enc_slice_type_fixup(int slice_type);
5762
5763 static void
5764 gen9_mfc_avc_pipe_mode_select(VADriverContextP ctx,
5765                               struct encode_state *encode_state,
5766                               struct intel_encoder_context *encoder_context)
5767 {
5768     struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
5769     struct i965_avc_encoder_context * avc_ctx = (struct i965_avc_encoder_context * )pak_context->private_enc_ctx;
5770     struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )pak_context->generic_enc_state;
5771     struct intel_batchbuffer *batch = encoder_context->base.batch;
5772
5773     BEGIN_BCS_BATCH(batch, 5);
5774
5775     OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2));
5776     OUT_BCS_BATCH(batch,
5777                   (0 << 29) |
5778                   (MFX_LONG_MODE << 17) |       /* Must be long format for encoder */
5779                   (MFD_MODE_VLD << 15) |
5780                   (0 << 13) |                   /* Non-VDEnc mode  is 0*/
5781                   ((generic_state->curr_pak_pass != (generic_state->num_pak_passes -1)) << 10) |                   /* Stream-Out Enable */
5782                   ((!!avc_ctx->res_post_deblocking_output.bo) << 9)  |    /* Post Deblocking Output */
5783                   ((!!avc_ctx->res_pre_deblocking_output.bo) << 8)  |     /* Pre Deblocking Output */
5784                   (0 << 7)  |                   /* Scaled surface enable */
5785                   (0 << 6)  |                   /* Frame statistics stream out enable */
5786                   (0 << 5)  |                   /* not in stitch mode */
5787                   (1 << 4)  |                   /* encoding mode */
5788                   (MFX_FORMAT_AVC << 0));
5789     OUT_BCS_BATCH(batch,
5790                   (0 << 7)  | /* expand NOA bus flag */
5791                   (0 << 6)  | /* disable slice-level clock gating */
5792                   (0 << 5)  | /* disable clock gating for NOA */
5793                   (0 << 4)  | /* terminate if AVC motion and POC table error occurs */
5794                   (0 << 3)  | /* terminate if AVC mbdata error occurs */
5795                   (0 << 2)  | /* terminate if AVC CABAC/CAVLC decode error occurs */
5796                   (0 << 1)  |
5797                   (0 << 0));
5798     OUT_BCS_BATCH(batch, 0);
5799     OUT_BCS_BATCH(batch, 0);
5800
5801     ADVANCE_BCS_BATCH(batch);
5802 }
5803
5804 static void
5805 gen9_mfc_avc_surface_state(VADriverContextP ctx,
5806                            struct intel_encoder_context *encoder_context,
5807                            struct i965_gpe_resource *gpe_resource,
5808                            int id)
5809 {
5810     struct intel_batchbuffer *batch = encoder_context->base.batch;
5811
5812     BEGIN_BCS_BATCH(batch, 6);
5813
5814     OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
5815     OUT_BCS_BATCH(batch, id);
5816     OUT_BCS_BATCH(batch,
5817                   ((gpe_resource->height - 1) << 18) |
5818                   ((gpe_resource->width - 1) << 4));
5819     OUT_BCS_BATCH(batch,
5820                   (MFX_SURFACE_PLANAR_420_8 << 28) |    /* 420 planar YUV surface */
5821                   (1 << 27) |                           /* must be 1 for interleave U/V, hardware requirement */
5822                   ((gpe_resource->pitch - 1) << 3) |    /* pitch */
5823                   (0 << 2)  |                           /* must be 0 for interleave U/V */
5824                   (1 << 1)  |                           /* must be tiled */
5825                   (I965_TILEWALK_YMAJOR << 0));         /* tile walk, TILEWALK_YMAJOR */
5826     OUT_BCS_BATCH(batch,
5827                   (0 << 16) |                           /* must be 0 for interleave U/V */
5828                   (gpe_resource->y_cb_offset));         /* y offset for U(cb) */
5829     OUT_BCS_BATCH(batch,
5830                   (0 << 16) |                           /* must be 0 for interleave U/V */
5831                   (gpe_resource->y_cb_offset));         /* y offset for U(cb) */
5832
5833     ADVANCE_BCS_BATCH(batch);
5834 }
5835
5836 static void
5837 gen9_mfc_avc_pipe_buf_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
5838 {
5839     struct i965_driver_data *i965 = i965_driver_data(ctx);
5840     struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
5841     struct generic_encoder_context * generic_ctx = (struct generic_encoder_context * )pak_context->generic_enc_ctx;
5842     struct i965_avc_encoder_context * avc_ctx = (struct i965_avc_encoder_context * )pak_context->private_enc_ctx;
5843     struct intel_batchbuffer *batch = encoder_context->base.batch;
5844     int i;
5845
5846     BEGIN_BCS_BATCH(batch, 65);
5847
5848     OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (65 - 2));
5849
5850     /* the DW1-3 is for pre_deblocking */
5851     OUT_BUFFER_3DW(batch, avc_ctx->res_pre_deblocking_output.bo, 1, 0, i965->intel.mocs_state);
5852
5853     /* the DW4-6 is for the post_deblocking */
5854     OUT_BUFFER_3DW(batch, avc_ctx->res_post_deblocking_output.bo, 1, 0, i965->intel.mocs_state);
5855
5856     /* the DW7-9 is for the uncompressed_picture */
5857     OUT_BUFFER_3DW(batch, generic_ctx->res_uncompressed_input_surface.bo, 0, 0, i965->intel.mocs_state);
5858
5859     /* the DW10-12 is for PAK information (write) */
5860     OUT_BUFFER_3DW(batch, avc_ctx->res_pak_mb_status_buffer.bo, 1, 0, i965->intel.mocs_state);//?
5861
5862     /* the DW13-15 is for the intra_row_store_scratch */
5863     OUT_BUFFER_3DW(batch, avc_ctx->res_intra_row_store_scratch_buffer.bo, 1, 0, i965->intel.mocs_state);
5864
5865     /* the DW16-18 is for the deblocking filter */
5866     OUT_BUFFER_3DW(batch, avc_ctx->res_deblocking_filter_row_store_scratch_buffer.bo, 1, 0, i965->intel.mocs_state);
5867
5868     /* the DW 19-50 is for Reference pictures*/
5869     for (i = 0; i < ARRAY_ELEMS(avc_ctx->list_reference_res); i++) {
5870         OUT_BUFFER_2DW(batch, avc_ctx->list_reference_res[i].bo, 0, 0);
5871     }
5872
5873     /* DW 51, reference picture attributes */
5874     OUT_BCS_BATCH(batch, i965->intel.mocs_state);
5875
5876     /* The DW 52-54 is for PAK information (read) */
5877     OUT_BUFFER_3DW(batch, avc_ctx->res_pak_mb_status_buffer.bo, 1, 0, i965->intel.mocs_state);
5878
5879     /* the DW 55-57 is the ILDB buffer */
5880     OUT_BUFFER_3DW(batch, NULL, 0, 0, 0);
5881
5882     /* the DW 58-60 is the second ILDB buffer */
5883     OUT_BUFFER_3DW(batch, NULL, 0, 0, 0);
5884
5885     /* DW 61, memory compress enable & mode */
5886     OUT_BCS_BATCH(batch, 0);
5887
5888     /* the DW 62-64 is the buffer */
5889     OUT_BUFFER_3DW(batch, NULL, 0, 0, 0);
5890
5891     ADVANCE_BCS_BATCH(batch);
5892 }
5893
5894 static void
5895 gen9_mfc_avc_ind_obj_base_addr_state(VADriverContextP ctx,
5896                                      struct encode_state *encode_state,
5897                                      struct intel_encoder_context *encoder_context)
5898 {
5899     struct i965_driver_data *i965 = i965_driver_data(ctx);
5900     struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
5901     struct generic_encoder_context * generic_ctx = (struct generic_encoder_context * )pak_context->generic_enc_ctx;
5902     struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )pak_context->generic_enc_state;
5903     struct intel_batchbuffer *batch = encoder_context->base.batch;
5904     struct object_surface *obj_surface;
5905     struct gen9_surface_avc *avc_priv_surface;
5906     unsigned int size = 0;
5907     unsigned int w_mb = generic_state->frame_width_in_mbs;
5908     unsigned int h_mb = generic_state->frame_height_in_mbs;
5909
5910     obj_surface = encode_state->reconstructed_object;
5911
5912     if (!obj_surface || !obj_surface->private_data)
5913         return;
5914     avc_priv_surface = obj_surface->private_data;
5915
5916     BEGIN_BCS_BATCH(batch, 26);
5917
5918     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (26 - 2));
5919     /* The DW1-5 is for the MFX indirect bistream offset */
5920     OUT_BUFFER_3DW(batch, NULL, 0, 0, 0);
5921     OUT_BUFFER_2DW(batch, NULL, 0, 0);
5922
5923     /* the DW6-10 is for MFX Indirect MV Object Base Address */
5924     size = w_mb * h_mb * 32 * 4;
5925     OUT_BUFFER_3DW(batch,
5926                    avc_priv_surface->res_mv_data_surface.bo,
5927                    1,
5928                    0,
5929                    i965->intel.mocs_state);
5930     OUT_BUFFER_2DW(batch,
5931                    avc_priv_surface->res_mv_data_surface.bo,
5932                    1,
5933                    ALIGN(size,0x1000));
5934
5935     /* The DW11-15 is for MFX IT-COFF. Not used on encoder */
5936     OUT_BUFFER_3DW(batch, NULL, 0, 0, 0);
5937     OUT_BUFFER_2DW(batch, NULL, 0, 0);
5938
5939     /* The DW16-20 is for MFX indirect DBLK. Not used on encoder */
5940     OUT_BUFFER_3DW(batch, NULL, 0, 0, 0);
5941     OUT_BUFFER_2DW(batch, NULL, 0, 0);
5942
5943     /* The DW21-25 is for MFC Indirect PAK-BSE Object Base Address for Encoder
5944      * Note: an offset is specified in MFX_AVC_SLICE_STATE
5945      */
5946     OUT_BUFFER_3DW(batch,
5947                    generic_ctx->compressed_bitstream.res.bo,
5948                    1,
5949                    0,
5950                    i965->intel.mocs_state);
5951     OUT_BUFFER_2DW(batch,
5952                    generic_ctx->compressed_bitstream.res.bo,
5953                    1,
5954                    generic_ctx->compressed_bitstream.end_offset);
5955
5956     ADVANCE_BCS_BATCH(batch);
5957 }
5958
5959 static void
5960 gen9_mfc_avc_bsp_buf_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
5961 {
5962     struct i965_driver_data *i965 = i965_driver_data(ctx);
5963     struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
5964     struct i965_avc_encoder_context * avc_ctx = (struct i965_avc_encoder_context * )pak_context->private_enc_ctx;
5965     struct intel_batchbuffer *batch = encoder_context->base.batch;
5966
5967     BEGIN_BCS_BATCH(batch, 10);
5968
5969     OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (10 - 2));
5970
5971     /* The DW1-3 is for bsd/mpc row store scratch buffer */
5972     OUT_BUFFER_3DW(batch, avc_ctx->res_bsd_mpc_row_store_scratch_buffer.bo, 1, 0, i965->intel.mocs_state);
5973
5974     /* The DW4-6 is for MPR Row Store Scratch Buffer Base Address, ignore for encoder */
5975     OUT_BUFFER_3DW(batch, NULL, 0, 0, 0);
5976
5977     /* The DW7-9 is for Bitplane Read Buffer Base Address, ignore for encoder */
5978     OUT_BUFFER_3DW(batch, NULL, 0, 0, 0);
5979
5980     ADVANCE_BCS_BATCH(batch);
5981 }
5982
5983 static void
5984 gen9_mfc_avc_directmode_state(VADriverContextP ctx,
5985                               struct intel_encoder_context *encoder_context)
5986 {
5987     struct i965_driver_data *i965 = i965_driver_data(ctx);
5988     struct intel_batchbuffer *batch = encoder_context->base.batch;
5989     struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
5990     struct i965_avc_encoder_context * avc_ctx = (struct i965_avc_encoder_context * )pak_context->private_enc_ctx;
5991     struct avc_enc_state * avc_state = (struct avc_enc_state * )pak_context->private_enc_state;
5992
5993     int i;
5994
5995     BEGIN_BCS_BATCH(batch, 71);
5996
5997     OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (71 - 2));
5998
5999     /* Reference frames and Current frames */
6000     /* the DW1-32 is for the direct MV for reference */
6001     for(i = 0; i < NUM_MFC_AVC_DMV_BUFFERS - 2; i += 2) {
6002         if ( avc_ctx->res_direct_mv_buffersr[i].bo != NULL) {
6003             OUT_BCS_RELOC64(batch, avc_ctx->res_direct_mv_buffersr[i].bo,
6004                           I915_GEM_DOMAIN_INSTRUCTION, 0,
6005                           0);
6006         } else {
6007             OUT_BCS_BATCH(batch, 0);
6008             OUT_BCS_BATCH(batch, 0);
6009         }
6010     }
6011
6012     OUT_BCS_BATCH(batch, i965->intel.mocs_state);
6013
6014     /* the DW34-36 is the MV for the current frame */
6015     OUT_BCS_RELOC64(batch, avc_ctx->res_direct_mv_buffersr[NUM_MFC_AVC_DMV_BUFFERS - 2].bo,
6016                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
6017                   0);
6018
6019     OUT_BCS_BATCH(batch, i965->intel.mocs_state);
6020
6021     /* POL list */
6022     for(i = 0; i < 32; i++) {
6023         OUT_BCS_BATCH(batch, avc_state->top_field_poc[i]);
6024     }
6025     OUT_BCS_BATCH(batch, avc_state->top_field_poc[NUM_MFC_AVC_DMV_BUFFERS - 2]);
6026     OUT_BCS_BATCH(batch, avc_state->top_field_poc[NUM_MFC_AVC_DMV_BUFFERS - 1]);
6027
6028     ADVANCE_BCS_BATCH(batch);
6029 }
6030
6031 static void
6032 gen9_mfc_qm_state(VADriverContextP ctx,
6033                   int qm_type,
6034                   const unsigned int *qm,
6035                   int qm_length,
6036                   struct intel_encoder_context *encoder_context)
6037 {
6038     struct intel_batchbuffer *batch = encoder_context->base.batch;
6039     unsigned int qm_buffer[16];
6040
6041     assert(qm_length <= 16);
6042     assert(sizeof(*qm) == 4);
6043     memset(qm_buffer,0,16*4);
6044     memcpy(qm_buffer, qm, qm_length * 4);
6045
6046     BEGIN_BCS_BATCH(batch, 18);
6047     OUT_BCS_BATCH(batch, MFX_QM_STATE | (18 - 2));
6048     OUT_BCS_BATCH(batch, qm_type << 0);
6049     intel_batchbuffer_data(batch, qm_buffer, 16 * 4);
6050     ADVANCE_BCS_BATCH(batch);
6051 }
6052
6053 static void
6054 gen9_mfc_avc_qm_state(VADriverContextP ctx,
6055                       struct encode_state *encode_state,
6056                       struct intel_encoder_context *encoder_context)
6057 {
6058     struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
6059     struct avc_enc_state * avc_state = (struct avc_enc_state * )pak_context->private_enc_state;
6060     VAEncSequenceParameterBufferH264  *seq_param = avc_state->seq_param;
6061     VAEncPictureParameterBufferH264  *pic_param = avc_state->pic_param;
6062
6063
6064     const unsigned int *qm_4x4_intra;
6065     const unsigned int *qm_4x4_inter;
6066     const unsigned int *qm_8x8_intra;
6067     const unsigned int *qm_8x8_inter;
6068
6069     if (!seq_param->seq_fields.bits.seq_scaling_matrix_present_flag
6070         && !pic_param->pic_fields.bits.pic_scaling_matrix_present_flag) {
6071         qm_4x4_intra = qm_4x4_inter = qm_8x8_intra = qm_8x8_inter = qm_flat;
6072     } else {
6073         VAIQMatrixBufferH264 *qm;
6074         assert(encode_state->q_matrix && encode_state->q_matrix->buffer);
6075         qm = (VAIQMatrixBufferH264 *)encode_state->q_matrix->buffer;
6076         qm_4x4_intra = (unsigned int *)qm->ScalingList4x4[0];
6077         qm_4x4_inter = (unsigned int *)qm->ScalingList4x4[3];
6078         qm_8x8_intra = (unsigned int *)qm->ScalingList8x8[0];
6079         qm_8x8_inter = (unsigned int *)qm->ScalingList8x8[1];
6080     }
6081
6082     gen9_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm_4x4_intra, 12, encoder_context);
6083     gen9_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm_4x4_inter, 12, encoder_context);
6084     gen9_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm_8x8_intra, 16, encoder_context);
6085     gen9_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm_8x8_inter, 16, encoder_context);
6086 }
6087
6088 static void
6089 gen9_mfc_fqm_state(VADriverContextP ctx,
6090                    int fqm_type,
6091                    const unsigned int *fqm,
6092                    int fqm_length,
6093                    struct intel_encoder_context *encoder_context)
6094 {
6095     struct intel_batchbuffer *batch = encoder_context->base.batch;
6096     unsigned int fqm_buffer[32];
6097
6098     assert(fqm_length <= 32);
6099     assert(sizeof(*fqm) == 4);
6100     memset(fqm_buffer,0,32*4);
6101     memcpy(fqm_buffer, fqm, fqm_length * 4);
6102
6103     BEGIN_BCS_BATCH(batch, 34);
6104     OUT_BCS_BATCH(batch, MFX_FQM_STATE | (34 - 2));
6105     OUT_BCS_BATCH(batch, fqm_type << 0);
6106     intel_batchbuffer_data(batch, fqm_buffer, 32 * 4);
6107     ADVANCE_BCS_BATCH(batch);
6108 }
6109
6110 static void
6111 gen9_mfc_fill_fqm(uint8_t *qm, uint16_t *fqm, int len)
6112 {
6113     int i, j;
6114     for (i = 0; i < len; i++)
6115        for (j = 0; j < len; j++)
6116        {
6117            assert(qm[j * len + i]);
6118            fqm[i * len + j] = (1 << 16) / qm[j * len + i];
6119        }
6120 }
6121
6122 static void
6123 gen9_mfc_avc_fqm_state(VADriverContextP ctx,
6124                       struct encode_state *encode_state,
6125                       struct intel_encoder_context *encoder_context)
6126 {
6127     struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
6128     struct avc_enc_state * avc_state = (struct avc_enc_state * )pak_context->private_enc_state;
6129     VAEncSequenceParameterBufferH264  *seq_param = avc_state->seq_param;
6130     VAEncPictureParameterBufferH264  *pic_param = avc_state->pic_param;
6131
6132     if (!seq_param->seq_fields.bits.seq_scaling_matrix_present_flag
6133         && !pic_param->pic_fields.bits.pic_scaling_matrix_present_flag) {
6134         gen9_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, fqm_flat, 24, encoder_context);
6135         gen9_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, fqm_flat, 24, encoder_context);
6136         gen9_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, fqm_flat, 32, encoder_context);
6137         gen9_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, fqm_flat, 32, encoder_context);
6138     } else {
6139         int i;
6140         uint32_t fqm[32];
6141         VAIQMatrixBufferH264 *qm;
6142         assert(encode_state->q_matrix && encode_state->q_matrix->buffer);
6143         qm = (VAIQMatrixBufferH264 *)encode_state->q_matrix->buffer;
6144
6145         for (i = 0; i < 3; i++)
6146             gen9_mfc_fill_fqm(qm->ScalingList4x4[i], (uint16_t *)fqm + 16 * i, 4);
6147         gen9_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, fqm, 24, encoder_context);
6148
6149         for (i = 3; i < 6; i++)
6150             gen9_mfc_fill_fqm(qm->ScalingList4x4[i], (uint16_t *)fqm + 16 * (i - 3), 4);
6151         gen9_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, fqm, 24, encoder_context);
6152
6153         gen9_mfc_fill_fqm(qm->ScalingList8x8[0], (uint16_t *)fqm, 8);
6154         gen9_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, fqm, 32, encoder_context);
6155
6156         gen9_mfc_fill_fqm(qm->ScalingList8x8[1], (uint16_t *)fqm, 8);
6157         gen9_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, fqm, 32, encoder_context);
6158     }
6159 }
6160
6161 static void
6162 gen9_mfc_avc_insert_object(VADriverContextP ctx,
6163                            struct intel_encoder_context *encoder_context,
6164                            unsigned int *insert_data, int lenght_in_dws, int data_bits_in_last_dw,
6165                            int skip_emul_byte_count, int is_last_header, int is_end_of_slice, int emulation_flag,
6166                            int slice_header_indicator,
6167                            struct intel_batchbuffer *batch)
6168 {
6169     if (data_bits_in_last_dw == 0)
6170         data_bits_in_last_dw = 32;
6171
6172     BEGIN_BCS_BATCH(batch, lenght_in_dws + 2);
6173
6174     OUT_BCS_BATCH(batch, MFX_INSERT_OBJECT | (lenght_in_dws));
6175     OUT_BCS_BATCH(batch,
6176                   (0 << 16) |   /* always start at offset 0 */
6177                   (slice_header_indicator << 14) |
6178                   (data_bits_in_last_dw << 8) |
6179                   (skip_emul_byte_count << 4) |
6180                   (!!emulation_flag << 3) |
6181                   ((!!is_last_header) << 2) |
6182                   ((!!is_end_of_slice) << 1) |
6183                   (0 << 0));    /* check this flag */
6184     intel_batchbuffer_data(batch, insert_data, lenght_in_dws * 4);
6185
6186     ADVANCE_BCS_BATCH(batch);
6187 }
6188
6189 static void
6190 gen9_mfc_avc_insert_slice_packed_data(VADriverContextP ctx,
6191                                       struct encode_state *encode_state,
6192                                       struct intel_encoder_context *encoder_context,
6193                                       int slice_index,
6194                                       struct intel_batchbuffer *batch)
6195 {
6196     VAEncPackedHeaderParameterBuffer *param = NULL;
6197     unsigned int length_in_bits;
6198     unsigned int *header_data = NULL;
6199     int count, i, start_index;
6200     int slice_header_index;
6201
6202     if (encode_state->slice_header_index[slice_index] == 0)
6203         slice_header_index = -1;
6204     else
6205         slice_header_index = (encode_state->slice_header_index[slice_index] & SLICE_PACKED_DATA_INDEX_MASK);
6206
6207     count = encode_state->slice_rawdata_count[slice_index];
6208     start_index = (encode_state->slice_rawdata_index[slice_index] & SLICE_PACKED_DATA_INDEX_MASK);
6209
6210     for (i = 0; i < count; i++) {
6211         unsigned int skip_emul_byte_cnt;
6212
6213         header_data = (unsigned int *)encode_state->packed_header_data_ext[start_index + i]->buffer;
6214
6215         param = (VAEncPackedHeaderParameterBuffer *)(encode_state->packed_header_params_ext[start_index + i]->buffer);
6216
6217         /* skip the slice header packed data type as it is lastly inserted */
6218         if (param->type == VAEncPackedHeaderSlice)
6219             continue;
6220
6221         length_in_bits = param->bit_length;
6222
6223         skip_emul_byte_cnt = intel_avc_find_skipemulcnt((unsigned char *)header_data, length_in_bits);
6224
6225         /* as the slice header is still required, the last header flag is set to
6226          * zero.
6227          */
6228         gen9_mfc_avc_insert_object(ctx,
6229                                    encoder_context,
6230                                    header_data,
6231                                    ALIGN(length_in_bits, 32) >> 5,
6232                                    length_in_bits & 0x1f,
6233                                    skip_emul_byte_cnt,
6234                                    0,
6235                                    0,
6236                                    !param->has_emulation_bytes,
6237                                    0,
6238                                    batch);
6239     }
6240
6241     if (slice_header_index == -1) {
6242         VAEncSequenceParameterBufferH264 *seq_param = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
6243         VAEncPictureParameterBufferH264 *pic_param = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
6244         VAEncSliceParameterBufferH264 *slice_params = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer;
6245         unsigned char *slice_header = NULL;
6246         int slice_header_length_in_bits = 0;
6247
6248         /* No slice header data is passed. And the driver needs to generate it */
6249         /* For the Normal H264 */
6250         slice_header_length_in_bits = build_avc_slice_header(seq_param,
6251                                                              pic_param,
6252                                                              slice_params,
6253                                                              &slice_header);
6254         gen9_mfc_avc_insert_object(ctx,
6255                                    encoder_context,
6256                                    (unsigned int *)slice_header,
6257                                    ALIGN(slice_header_length_in_bits, 32) >> 5,
6258                                    slice_header_length_in_bits & 0x1f,
6259                                    5,  /* first 5 bytes are start code + nal unit type */
6260                                    1, 0, 1,
6261                                    1,
6262                                    batch);
6263
6264         free(slice_header);
6265     } else {
6266         unsigned int skip_emul_byte_cnt;
6267
6268         header_data = (unsigned int *)encode_state->packed_header_data_ext[slice_header_index]->buffer;
6269
6270         param = (VAEncPackedHeaderParameterBuffer *)(encode_state->packed_header_params_ext[slice_header_index]->buffer);
6271         length_in_bits = param->bit_length;
6272
6273         /* as the slice header is the last header data for one slice,
6274          * the last header flag is set to one.
6275          */
6276         skip_emul_byte_cnt = intel_avc_find_skipemulcnt((unsigned char *)header_data, length_in_bits);
6277
6278         gen9_mfc_avc_insert_object(ctx,
6279                                    encoder_context,
6280                                    header_data,
6281                                    ALIGN(length_in_bits, 32) >> 5,
6282                                    length_in_bits & 0x1f,
6283                                    skip_emul_byte_cnt,
6284                                    1,
6285                                    0,
6286                                    !param->has_emulation_bytes,
6287                                    1,
6288                                    batch);
6289     }
6290
6291     return;
6292 }
6293
6294 static void
6295 gen9_mfc_avc_inset_headers(VADriverContextP ctx,
6296                            struct encode_state *encode_state,
6297                            struct intel_encoder_context *encoder_context,
6298                            VAEncSliceParameterBufferH264 *slice_param,
6299                            int slice_index,
6300                            struct intel_batchbuffer *batch)
6301 {
6302     struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
6303     struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )pak_context->generic_enc_state;
6304     int idx = va_enc_packed_type_to_idx(VAEncPackedHeaderH264_SPS);
6305     unsigned int internal_rate_mode = generic_state->internal_rate_mode;
6306     unsigned int skip_emul_byte_cnt;
6307
6308     if (slice_index == 0) {
6309         if (encode_state->packed_header_data[idx]) {
6310             VAEncPackedHeaderParameterBuffer *param = NULL;
6311             unsigned int *header_data = (unsigned int *)encode_state->packed_header_data[idx]->buffer;
6312             unsigned int length_in_bits;
6313
6314             assert(encode_state->packed_header_param[idx]);
6315             param = (VAEncPackedHeaderParameterBuffer *)encode_state->packed_header_param[idx]->buffer;
6316             length_in_bits = param->bit_length;
6317
6318             skip_emul_byte_cnt = intel_avc_find_skipemulcnt((unsigned char *)header_data, length_in_bits);
6319             gen9_mfc_avc_insert_object(ctx,
6320                                        encoder_context,
6321                                        header_data,
6322                                        ALIGN(length_in_bits, 32) >> 5,
6323                                        length_in_bits & 0x1f,
6324                                        skip_emul_byte_cnt,
6325                                        0,
6326                                        0,
6327                                        !param->has_emulation_bytes,
6328                                        0,
6329                                        batch);
6330         }
6331
6332         idx = va_enc_packed_type_to_idx(VAEncPackedHeaderH264_PPS);
6333
6334         if (encode_state->packed_header_data[idx]) {
6335             VAEncPackedHeaderParameterBuffer *param = NULL;
6336             unsigned int *header_data = (unsigned int *)encode_state->packed_header_data[idx]->buffer;
6337             unsigned int length_in_bits;
6338
6339             assert(encode_state->packed_header_param[idx]);
6340             param = (VAEncPackedHeaderParameterBuffer *)encode_state->packed_header_param[idx]->buffer;
6341             length_in_bits = param->bit_length;
6342
6343             skip_emul_byte_cnt = intel_avc_find_skipemulcnt((unsigned char *)header_data, length_in_bits);
6344
6345             gen9_mfc_avc_insert_object(ctx,
6346                                        encoder_context,
6347                                        header_data,
6348                                        ALIGN(length_in_bits, 32) >> 5,
6349                                        length_in_bits & 0x1f,
6350                                        skip_emul_byte_cnt,
6351                                        0,
6352                                        0,
6353                                        !param->has_emulation_bytes,
6354                                        0,
6355                                        batch);
6356         }
6357
6358         idx = va_enc_packed_type_to_idx(VAEncPackedHeaderH264_SEI);
6359
6360         if (encode_state->packed_header_data[idx]) {
6361             VAEncPackedHeaderParameterBuffer *param = NULL;
6362             unsigned int *header_data = (unsigned int *)encode_state->packed_header_data[idx]->buffer;
6363             unsigned int length_in_bits;
6364
6365             assert(encode_state->packed_header_param[idx]);
6366             param = (VAEncPackedHeaderParameterBuffer *)encode_state->packed_header_param[idx]->buffer;
6367             length_in_bits = param->bit_length;
6368
6369             skip_emul_byte_cnt = intel_avc_find_skipemulcnt((unsigned char *)header_data, length_in_bits);
6370             gen9_mfc_avc_insert_object(ctx,
6371                                        encoder_context,
6372                                        header_data,
6373                                        ALIGN(length_in_bits, 32) >> 5,
6374                                        length_in_bits & 0x1f,
6375                                        skip_emul_byte_cnt,
6376                                        0,
6377                                        0,
6378                                        !param->has_emulation_bytes,
6379                                        0,
6380                                        batch);
6381         } else if (internal_rate_mode == VA_RC_CBR) {
6382             /* insert others */
6383         }
6384     }
6385
6386     gen9_mfc_avc_insert_slice_packed_data(ctx,
6387                                           encode_state,
6388                                           encoder_context,
6389                                           slice_index,
6390                                           batch);
6391 }
6392
6393 static void
6394 gen9_mfc_avc_slice_state(VADriverContextP ctx,
6395                          struct encode_state *encode_state,
6396                          struct intel_encoder_context *encoder_context,
6397                          VAEncPictureParameterBufferH264 *pic_param,
6398                          VAEncSliceParameterBufferH264 *slice_param,
6399                          VAEncSliceParameterBufferH264 *next_slice_param,
6400                          struct intel_batchbuffer *batch)
6401 {
6402     struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
6403     struct generic_encoder_context * generic_ctx = (struct generic_encoder_context * )pak_context->generic_enc_ctx;
6404     struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )pak_context->generic_enc_state;
6405     struct avc_enc_state * avc_state = (struct avc_enc_state * )pak_context->private_enc_state;
6406     unsigned int luma_log2_weight_denom = slice_param->luma_log2_weight_denom;
6407     unsigned int chroma_log2_weight_denom = slice_param->chroma_log2_weight_denom;
6408     unsigned char correct[6], grow, shrink;
6409     int slice_hor_pos, slice_ver_pos, next_slice_hor_pos, next_slice_ver_pos;
6410     int max_qp_n, max_qp_p;
6411     int i;
6412     int weighted_pred_idc = 0;
6413     int num_ref_l0 = 0, num_ref_l1 = 0;
6414     int slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type);
6415     int slice_qp = pic_param->pic_init_qp + slice_param->slice_qp_delta;
6416     unsigned int rc_panic_enable = 0;
6417     unsigned int rate_control_counter_enable = 0;
6418     unsigned int rounding_value = 0;
6419     unsigned int rounding_inter_enable = 0;
6420
6421     //check the inter rounding
6422     if(generic_state->frame_type == SLICE_TYPE_P)
6423     {
6424         if(avc_state->rounding_inter_p == AVC_INVALID_ROUNDING_VALUE)
6425         {
6426             if(avc_state->adaptive_rounding_inter_enable && !(generic_state->brc_enabled))
6427             {
6428                 if(generic_state->gop_ref_distance == 1)
6429                     avc_state->rounding_value = gen9_avc_adaptive_inter_rounding_p_without_b[slice_qp];
6430                 else
6431                     avc_state->rounding_value = gen9_avc_adaptive_inter_rounding_p[slice_qp];
6432             }
6433             else
6434             {
6435                 avc_state->rounding_value = gen9_avc_inter_rounding_p[generic_state->preset];
6436             }
6437
6438         }else
6439         {
6440             avc_state->rounding_value = avc_state->rounding_inter_p;
6441         }
6442     }else if(generic_state->frame_type == SLICE_TYPE_B)
6443     {
6444         if(pic_param->pic_fields.bits.reference_pic_flag)
6445         {
6446             if(avc_state->rounding_inter_b_ref == AVC_INVALID_ROUNDING_VALUE)
6447                 avc_state->rounding_value = gen9_avc_inter_rounding_b_ref[generic_state->preset];
6448             else
6449                 avc_state->rounding_value = avc_state->rounding_inter_b_ref;
6450         }
6451         else
6452         {
6453             if(avc_state->rounding_inter_b == AVC_INVALID_ROUNDING_VALUE)
6454             {
6455                 if(avc_state->adaptive_rounding_inter_enable && !(generic_state->brc_enabled))
6456                     avc_state->rounding_value = gen9_avc_adaptive_inter_rounding_b[slice_qp];
6457                 else
6458                     avc_state->rounding_value = gen9_avc_inter_rounding_b[generic_state->preset];
6459             }else
6460             {
6461                 avc_state->rounding_value = avc_state->rounding_inter_b;
6462             }
6463         }
6464     }
6465
6466     slice_hor_pos = slice_param->macroblock_address % generic_state->frame_width_in_mbs;
6467     slice_ver_pos = slice_param->macroblock_address / generic_state->frame_width_in_mbs;
6468
6469     if (next_slice_param) {
6470         next_slice_hor_pos = next_slice_param->macroblock_address % generic_state->frame_width_in_mbs;
6471         next_slice_ver_pos = next_slice_param->macroblock_address / generic_state->frame_width_in_mbs;
6472     } else {
6473         next_slice_hor_pos = 0;
6474         next_slice_ver_pos = generic_state->frame_height_in_mbs;
6475     }
6476
6477     if (slice_type == SLICE_TYPE_I) {
6478         luma_log2_weight_denom = 0;
6479         chroma_log2_weight_denom = 0;
6480     } else if (slice_type == SLICE_TYPE_P) {
6481         weighted_pred_idc = pic_param->pic_fields.bits.weighted_pred_flag;
6482         num_ref_l0 = pic_param->num_ref_idx_l0_active_minus1 + 1;
6483         rounding_inter_enable = avc_state->rounding_inter_enable;
6484         rounding_value = avc_state->rounding_value;
6485
6486         if (slice_param->num_ref_idx_active_override_flag)
6487             num_ref_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
6488     } else if (slice_type == SLICE_TYPE_B) {
6489         weighted_pred_idc = pic_param->pic_fields.bits.weighted_bipred_idc;
6490         num_ref_l0 = pic_param->num_ref_idx_l0_active_minus1 + 1;
6491         num_ref_l1 = pic_param->num_ref_idx_l1_active_minus1 + 1;
6492         rounding_inter_enable = avc_state->rounding_inter_enable;
6493         rounding_value = avc_state->rounding_value;
6494
6495         if (slice_param->num_ref_idx_active_override_flag) {
6496             num_ref_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
6497             num_ref_l1 = slice_param->num_ref_idx_l1_active_minus1 + 1;
6498         }
6499
6500         if (weighted_pred_idc == 2) {
6501             /* 8.4.3 - Derivation process for prediction weights (8-279) */
6502             luma_log2_weight_denom = 5;
6503             chroma_log2_weight_denom = 5;
6504         }
6505     }
6506
6507     max_qp_n = 0;
6508     max_qp_p = 0;
6509     grow = 0;
6510     shrink = 0;
6511
6512     rate_control_counter_enable = (generic_state->brc_enabled && (generic_state->curr_pak_pass != 0));
6513     rc_panic_enable = (avc_state->rc_panic_enable &&
6514                       (!avc_state->min_max_qp_enable) &&
6515                       (encoder_context->rate_control_mode != VA_RC_CQP) &&
6516                       (generic_state->curr_pak_pass == (generic_state->num_pak_passes - 1)));
6517
6518     for (i = 0; i < 6; i++)
6519         correct[i] = 0;
6520
6521     BEGIN_BCS_BATCH(batch, 11);
6522
6523     OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2) );
6524     OUT_BCS_BATCH(batch, slice_type);
6525     OUT_BCS_BATCH(batch,
6526                   (num_ref_l1 << 24) |
6527                   (num_ref_l0 << 16) |
6528                   (chroma_log2_weight_denom << 8) |
6529                   (luma_log2_weight_denom << 0));
6530     OUT_BCS_BATCH(batch,
6531                   (weighted_pred_idc << 30) |
6532                   (((slice_type == SLICE_TYPE_B)?slice_param->direct_spatial_mv_pred_flag:0) << 29) |
6533                   (slice_param->disable_deblocking_filter_idc << 27) |
6534                   (slice_param->cabac_init_idc << 24) |
6535                   (slice_qp << 16) |
6536                   ((slice_param->slice_beta_offset_div2 & 0xf) << 8) |
6537                   ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0));
6538
6539     OUT_BCS_BATCH(batch,
6540                   slice_ver_pos << 24 |
6541                   slice_hor_pos << 16 |
6542                   slice_param->macroblock_address);
6543     OUT_BCS_BATCH(batch,
6544                   next_slice_ver_pos << 16 |
6545                   next_slice_hor_pos);
6546
6547     OUT_BCS_BATCH(batch,
6548                   (rate_control_counter_enable << 31) |
6549                   (1 << 30) |           /* ResetRateControlCounter */
6550                   (2 << 28) |           /* Loose Rate Control */
6551                   (0 << 24) |           /* RC Stable Tolerance */
6552                   (rc_panic_enable << 23) |           /* RC Panic Enable */
6553                   (1 << 22) |           /* CBP mode */
6554                   (0 << 21) |           /* MB Type Direct Conversion, 0: Enable, 1: Disable */
6555                   (0 << 20) |           /* MB Type Skip Conversion, 0: Enable, 1: Disable */
6556                   (!next_slice_param << 19) |                   /* Is Last Slice */
6557                   (0 << 18) |           /* BitstreamOutputFlag Compressed BitStream Output Disable Flag 0:enable 1:disable */
6558                   (1 << 17) |           /* HeaderPresentFlag */
6559                   (1 << 16) |           /* SliceData PresentFlag */
6560                   (0 << 15) |           /* TailPresentFlag  */
6561                   (1 << 13) |           /* RBSP NAL TYPE */
6562                   (1 << 12));           /* CabacZeroWordInsertionEnable */
6563
6564     OUT_BCS_BATCH(batch, generic_ctx->compressed_bitstream.start_offset);
6565
6566     OUT_BCS_BATCH(batch,
6567                   (max_qp_n << 24) |     /*Target QP - 24 is lowest QP*/
6568                   (max_qp_p << 16) |     /*Target QP + 20 is highest QP*/
6569                   (shrink << 8) |
6570                   (grow << 0));
6571     OUT_BCS_BATCH(batch,
6572                   (rounding_inter_enable << 31) |
6573                   (rounding_value << 28) |
6574                   (1 << 27) |
6575                   (5 << 24) |
6576                   (correct[5] << 20) |
6577                   (correct[4] << 16) |
6578                   (correct[3] << 12) |
6579                   (correct[2] << 8) |
6580                   (correct[1] << 4) |
6581                   (correct[0] << 0));
6582     OUT_BCS_BATCH(batch, 0);
6583
6584     ADVANCE_BCS_BATCH(batch);
6585 }
6586
6587 static uint8_t
6588 gen9_mfc_avc_get_ref_idx_state(VAPictureH264 *va_pic, unsigned int frame_store_id)
6589 {
6590     unsigned int is_long_term =
6591         !!(va_pic->flags & VA_PICTURE_H264_LONG_TERM_REFERENCE);
6592     unsigned int is_top_field =
6593         !!(va_pic->flags & VA_PICTURE_H264_TOP_FIELD);
6594     unsigned int is_bottom_field =
6595         !!(va_pic->flags & VA_PICTURE_H264_BOTTOM_FIELD);
6596
6597     return ((is_long_term                         << 6) |
6598             (0 << 5) |
6599             (frame_store_id                       << 1) |
6600             ((is_top_field ^ 1) & is_bottom_field));
6601 }
6602
6603 static void
6604 gen9_mfc_avc_ref_idx_state(VADriverContextP ctx,
6605                                  struct encode_state *encode_state,
6606                                  struct intel_encoder_context *encoder_context,
6607                                  VAEncSliceParameterBufferH264 *slice_param,
6608                                  struct intel_batchbuffer *batch)
6609 {
6610     struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
6611     struct avc_enc_state * avc_state = (struct avc_enc_state * )pak_context->private_enc_state;
6612     VAPictureH264 *ref_pic;
6613     int i, slice_type, ref_idx_shift;
6614     unsigned int fwd_ref_entry;
6615     unsigned int bwd_ref_entry;
6616
6617     /* max 4 ref frames are allowed for l0 and l1 */
6618     fwd_ref_entry = 0x80808080;
6619     slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type);
6620
6621     if ((slice_type == SLICE_TYPE_P) ||
6622         (slice_type == SLICE_TYPE_B)) {
6623           for (i = 0; i < MIN(avc_state->num_refs[0],4); i++) {
6624               ref_pic = &slice_param->RefPicList0[i];
6625               ref_idx_shift = i * 8;
6626
6627               fwd_ref_entry &= ~(0xFF << ref_idx_shift);
6628               fwd_ref_entry += (gen9_mfc_avc_get_ref_idx_state(ref_pic, avc_state->list_ref_idx[0][i]) << ref_idx_shift);
6629           }
6630     }
6631
6632     bwd_ref_entry = 0x80808080;
6633     if (slice_type == SLICE_TYPE_B) {
6634         for (i = 0; i < MIN(avc_state->num_refs[1],4); i++) {
6635             ref_pic = &slice_param->RefPicList1[i];
6636             ref_idx_shift = i * 8;
6637
6638             bwd_ref_entry &= ~(0xFF << ref_idx_shift);
6639             bwd_ref_entry += (gen9_mfc_avc_get_ref_idx_state(ref_pic, avc_state->list_ref_idx[1][i]) << ref_idx_shift);
6640         }
6641     }
6642
6643     if ((slice_type == SLICE_TYPE_P) ||
6644         (slice_type == SLICE_TYPE_B)) {
6645         BEGIN_BCS_BATCH(batch, 10);
6646         OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8);
6647         OUT_BCS_BATCH(batch, 0);                        // L0
6648         OUT_BCS_BATCH(batch, fwd_ref_entry);
6649
6650         for (i = 0; i < 7; i++) {
6651             OUT_BCS_BATCH(batch, 0x80808080);
6652         }
6653
6654         ADVANCE_BCS_BATCH(batch);
6655     }
6656
6657     if (slice_type == SLICE_TYPE_B) {
6658         BEGIN_BCS_BATCH(batch, 10);
6659         OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8);
6660         OUT_BCS_BATCH(batch, 1);                  //Select L1
6661         OUT_BCS_BATCH(batch, bwd_ref_entry);      //max 4 reference allowed
6662         for(i = 0; i < 7; i++) {
6663             OUT_BCS_BATCH(batch, 0x80808080);
6664         }
6665         ADVANCE_BCS_BATCH(batch);
6666     }
6667 }
6668
6669 static void
6670 gen9_mfc_avc_weightoffset_state(VADriverContextP ctx,
6671                                 struct encode_state *encode_state,
6672                                 struct intel_encoder_context *encoder_context,
6673                                 VAEncPictureParameterBufferH264 *pic_param,
6674                                 VAEncSliceParameterBufferH264 *slice_param,
6675                                 struct intel_batchbuffer *batch)
6676 {
6677     int i, slice_type;
6678     short weightoffsets[32 * 6];
6679
6680     slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type);
6681
6682     if (slice_type == SLICE_TYPE_P &&
6683         pic_param->pic_fields.bits.weighted_pred_flag == 1) {
6684         memset(weightoffsets,0,32*6 * sizeof(short));
6685         for (i = 0; i < 32; i++) {
6686             weightoffsets[i * 6 + 0] = slice_param->luma_weight_l0[i];
6687             weightoffsets[i * 6 + 1] = slice_param->luma_offset_l0[i];
6688             weightoffsets[i * 6 + 2] = slice_param->chroma_weight_l0[i][0];
6689             weightoffsets[i * 6 + 3] = slice_param->chroma_offset_l0[i][0];
6690             weightoffsets[i * 6 + 4] = slice_param->chroma_weight_l0[i][1];
6691             weightoffsets[i * 6 + 5] = slice_param->chroma_offset_l0[i][1];
6692         }
6693
6694         BEGIN_BCS_BATCH(batch, 98);
6695         OUT_BCS_BATCH(batch, MFX_AVC_WEIGHTOFFSET_STATE | (98 - 2));
6696         OUT_BCS_BATCH(batch, 0);
6697         intel_batchbuffer_data(batch, weightoffsets, sizeof(weightoffsets));
6698
6699         ADVANCE_BCS_BATCH(batch);
6700     }
6701
6702     if (slice_type == SLICE_TYPE_B &&
6703         (pic_param->pic_fields.bits.weighted_bipred_idc == 1)) {
6704         memset(weightoffsets,0,32*6 * sizeof(short));
6705         for (i = 0; i < 32; i++) {
6706             weightoffsets[i * 6 + 0] = slice_param->luma_weight_l0[i];
6707             weightoffsets[i * 6 + 1] = slice_param->luma_offset_l0[i];
6708             weightoffsets[i * 6 + 2] = slice_param->chroma_weight_l0[i][0];
6709             weightoffsets[i * 6 + 3] = slice_param->chroma_offset_l0[i][0];
6710             weightoffsets[i * 6 + 4] = slice_param->chroma_weight_l0[i][1];
6711             weightoffsets[i * 6 + 5] = slice_param->chroma_offset_l0[i][1];
6712         }
6713
6714         BEGIN_BCS_BATCH(batch, 98);
6715         OUT_BCS_BATCH(batch, MFX_AVC_WEIGHTOFFSET_STATE | (98 - 2));
6716         OUT_BCS_BATCH(batch, 0);
6717         intel_batchbuffer_data(batch, weightoffsets, sizeof(weightoffsets));
6718         ADVANCE_BCS_BATCH(batch);
6719
6720         memset(weightoffsets,0,32*6 * sizeof(short));
6721         for (i = 0; i < 32; i++) {
6722             weightoffsets[i * 6 + 0] = slice_param->luma_weight_l1[i];
6723             weightoffsets[i * 6 + 1] = slice_param->luma_offset_l1[i];
6724             weightoffsets[i * 6 + 2] = slice_param->chroma_weight_l1[i][0];
6725             weightoffsets[i * 6 + 3] = slice_param->chroma_offset_l1[i][0];
6726             weightoffsets[i * 6 + 4] = slice_param->chroma_weight_l1[i][1];
6727             weightoffsets[i * 6 + 5] = slice_param->chroma_offset_l1[i][1];
6728         }
6729
6730         BEGIN_BCS_BATCH(batch, 98);
6731         OUT_BCS_BATCH(batch, MFX_AVC_WEIGHTOFFSET_STATE | (98 - 2));
6732         OUT_BCS_BATCH(batch, 1);
6733         intel_batchbuffer_data(batch, weightoffsets, sizeof(weightoffsets));
6734         ADVANCE_BCS_BATCH(batch);
6735     }
6736 }
6737
6738 static void
6739 gen9_mfc_avc_single_slice(VADriverContextP ctx,
6740                           struct encode_state *encode_state,
6741                           struct intel_encoder_context *encoder_context,
6742                           VAEncSliceParameterBufferH264 *slice_param,
6743                           VAEncSliceParameterBufferH264 *next_slice_param,
6744                           int slice_index)
6745 {
6746     struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
6747     struct i965_avc_encoder_context * avc_ctx = (struct i965_avc_encoder_context * )pak_context->private_enc_ctx;
6748     struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )pak_context->generic_enc_state;
6749     struct avc_enc_state * avc_state = (struct avc_enc_state * )pak_context->private_enc_state;
6750     struct intel_batchbuffer *batch = encoder_context->base.batch;
6751     struct intel_batchbuffer *slice_batch = avc_ctx->pres_slice_batch_buffer_2nd_level;
6752     VAEncPictureParameterBufferH264 *pic_param = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
6753     struct gpe_mi_batch_buffer_start_parameter second_level_batch;
6754     struct object_surface *obj_surface;
6755     struct gen9_surface_avc *avc_priv_surface;
6756
6757     unsigned int slice_offset = 0;
6758
6759     if(generic_state->curr_pak_pass == 0)
6760     {
6761         slice_offset = intel_batchbuffer_used_size(slice_batch);
6762         avc_state->slice_batch_offset[slice_index] = slice_offset;
6763         gen9_mfc_avc_ref_idx_state(ctx, encode_state, encoder_context, slice_param,slice_batch);
6764         gen9_mfc_avc_weightoffset_state(ctx,
6765                                         encode_state,
6766                                         encoder_context,
6767                                         pic_param,
6768                                         slice_param,
6769                                         slice_batch);
6770         gen9_mfc_avc_slice_state(ctx,
6771                                  encode_state,
6772                                  encoder_context,
6773                                  pic_param,
6774                                  slice_param,
6775                                  next_slice_param,
6776                                  slice_batch);
6777         gen9_mfc_avc_inset_headers(ctx,
6778                                    encode_state,
6779                                    encoder_context,
6780                                    slice_param,
6781                                    slice_index,
6782                                    slice_batch);
6783
6784         BEGIN_BCS_BATCH(slice_batch, 2);
6785         OUT_BCS_BATCH(slice_batch, 0);
6786         OUT_BCS_BATCH(slice_batch, MI_BATCH_BUFFER_END);
6787         ADVANCE_BCS_BATCH(slice_batch);
6788
6789     }else
6790     {
6791         slice_offset = avc_state->slice_batch_offset[slice_index];
6792     }
6793     /* insert slice as second levle.*/
6794     memset(&second_level_batch, 0, sizeof(second_level_batch));
6795     second_level_batch.is_second_level = 1; /* Must be the second level batch buffer */
6796     second_level_batch.offset = slice_offset;
6797     second_level_batch.bo = slice_batch->buffer;
6798     gen8_gpe_mi_batch_buffer_start(ctx, batch, &second_level_batch);
6799
6800     /* insert mb code as second levle.*/
6801     obj_surface = encode_state->reconstructed_object;
6802     assert(obj_surface->private_data);
6803     avc_priv_surface = (struct gen9_surface_avc *)obj_surface->private_data;
6804
6805     memset(&second_level_batch, 0, sizeof(second_level_batch));
6806     second_level_batch.is_second_level = 1; /* Must be the second level batch buffer */
6807     second_level_batch.offset = slice_param->macroblock_address * 16 * 4;
6808     second_level_batch.bo = avc_priv_surface->res_mb_code_surface.bo;
6809     gen8_gpe_mi_batch_buffer_start(ctx, batch, &second_level_batch);
6810
6811 }
6812
6813 static void
6814 gen9_avc_pak_slice_level(VADriverContextP ctx,
6815                          struct encode_state *encode_state,
6816                          struct intel_encoder_context *encoder_context)
6817 {
6818     struct intel_batchbuffer *batch = encoder_context->base.batch;
6819     struct gpe_mi_flush_dw_parameter mi_flush_dw_params;
6820     VAEncSliceParameterBufferH264 *slice_param, *next_slice_param, *next_slice_group_param;
6821     int i, j;
6822     int slice_index = 0;
6823     int is_frame_level = 1;       /* check it for SKL,now single slice per frame */
6824     int has_tail = 0;             /* check it later */
6825
6826     for (j = 0; j < encode_state->num_slice_params_ext; j++) {
6827         slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[j]->buffer;
6828
6829         if (j == encode_state->num_slice_params_ext - 1)
6830             next_slice_group_param = NULL;
6831         else
6832             next_slice_group_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[j + 1]->buffer;
6833
6834         for (i = 0; i < encode_state->slice_params_ext[j]->num_elements; i++) {
6835             if (i < encode_state->slice_params_ext[j]->num_elements - 1)
6836                 next_slice_param = slice_param + 1;
6837             else
6838                 next_slice_param = next_slice_group_param;
6839
6840             gen9_mfc_avc_single_slice(ctx,
6841                                       encode_state,
6842                                       encoder_context,
6843                                       slice_param,
6844                                       next_slice_param,
6845                                       slice_index);
6846             slice_param++;
6847             slice_index++;
6848
6849             if (is_frame_level)
6850                 break;
6851             else {
6852                 /* remove assert(0) and add other commands here */
6853                 assert(0);
6854             }
6855         }
6856
6857         if (is_frame_level)
6858             break;
6859     }
6860
6861     if (has_tail) {
6862         /* insert a tail if required */
6863     }
6864
6865     memset(&mi_flush_dw_params, 0, sizeof(mi_flush_dw_params));
6866     mi_flush_dw_params.video_pipeline_cache_invalidate = 1;
6867     gen8_gpe_mi_flush_dw(ctx, batch, &mi_flush_dw_params);
6868 }
6869 static void
6870 gen9_avc_pak_picture_level(VADriverContextP ctx,
6871                            struct encode_state *encode_state,
6872                            struct intel_encoder_context *encoder_context)
6873 {
6874     struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
6875     struct generic_encoder_context * generic_ctx = (struct generic_encoder_context * )pak_context->generic_enc_ctx;
6876     struct i965_avc_encoder_context * avc_ctx = (struct i965_avc_encoder_context * )pak_context->private_enc_ctx;
6877     struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )pak_context->generic_enc_state;
6878     struct gpe_mi_batch_buffer_start_parameter second_level_batch;
6879     struct intel_batchbuffer *batch = encoder_context->base.batch;
6880
6881     if (generic_state->brc_enabled &&
6882         generic_state->curr_pak_pass) {
6883         struct gpe_mi_conditional_batch_buffer_end_parameter mi_conditional_batch_buffer_end_params;
6884         struct encoder_status_buffer_internal *status_buffer;
6885         status_buffer = &(avc_ctx->status_buffer);
6886
6887         memset(&mi_conditional_batch_buffer_end_params, 0, sizeof(mi_conditional_batch_buffer_end_params));
6888         mi_conditional_batch_buffer_end_params.offset = status_buffer->image_status_mask_offset;
6889         mi_conditional_batch_buffer_end_params.bo = status_buffer->bo;
6890         mi_conditional_batch_buffer_end_params.compare_data = 0;
6891         mi_conditional_batch_buffer_end_params.compare_mask_mode_disabled = 0;
6892         gen9_gpe_mi_conditional_batch_buffer_end(ctx, batch, &mi_conditional_batch_buffer_end_params);
6893     }
6894
6895     gen9_mfc_avc_pipe_mode_select(ctx,encode_state,encoder_context);
6896     gen9_mfc_avc_surface_state(ctx,encoder_context,&(generic_ctx->res_reconstructed_surface),0);
6897     gen9_mfc_avc_surface_state(ctx,encoder_context,&(generic_ctx->res_uncompressed_input_surface),4);
6898     gen9_mfc_avc_pipe_buf_addr_state(ctx,encoder_context);
6899     gen9_mfc_avc_ind_obj_base_addr_state(ctx,encode_state,encoder_context);
6900     gen9_mfc_avc_bsp_buf_base_addr_state(ctx,encoder_context);
6901
6902     if(generic_state->brc_enabled)
6903     {
6904         memset(&second_level_batch, 0, sizeof(second_level_batch));
6905         if (generic_state->curr_pak_pass == 0) {
6906             second_level_batch.offset = 0;
6907         } else {
6908             second_level_batch.offset = generic_state->curr_pak_pass * INTEL_AVC_IMAGE_STATE_CMD_SIZE;
6909         }
6910         second_level_batch.is_second_level = 1;
6911         second_level_batch.bo = avc_ctx->res_brc_image_state_read_buffer.bo;
6912         gen8_gpe_mi_batch_buffer_start(ctx, batch, &second_level_batch);
6913     }else
6914     {
6915         /*generate a new image state */
6916         gen9_avc_set_image_state_non_brc(ctx,encode_state,encoder_context,&(avc_ctx->res_image_state_batch_buffer_2nd_level));
6917         memset(&second_level_batch, 0, sizeof(second_level_batch));
6918         second_level_batch.offset = 0;
6919         second_level_batch.is_second_level = 1;
6920         second_level_batch.bo = avc_ctx->res_image_state_batch_buffer_2nd_level.bo;
6921         gen8_gpe_mi_batch_buffer_start(ctx, batch, &second_level_batch);
6922     }
6923
6924     gen9_mfc_avc_qm_state(ctx,encode_state,encoder_context);
6925     gen9_mfc_avc_fqm_state(ctx,encode_state,encoder_context);
6926     gen9_mfc_avc_directmode_state(ctx,encoder_context);
6927
6928 }
6929
6930 static void
6931 gen9_avc_read_mfc_status(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
6932 {
6933     struct intel_batchbuffer *batch = encoder_context->base.batch;
6934     struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
6935     struct i965_avc_encoder_context * avc_ctx = (struct i965_avc_encoder_context * )pak_context->private_enc_ctx;
6936     struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )pak_context->generic_enc_state;
6937
6938     struct gpe_mi_store_register_mem_parameter mi_store_reg_mem_param;
6939     struct gpe_mi_store_data_imm_parameter mi_store_data_imm_param;
6940     struct gpe_mi_flush_dw_parameter mi_flush_dw_param;
6941     struct encoder_status_buffer_internal *status_buffer;
6942
6943     status_buffer = &(avc_ctx->status_buffer);
6944
6945     memset(&mi_flush_dw_param, 0, sizeof(mi_flush_dw_param));
6946     gen8_gpe_mi_flush_dw(ctx, batch, &mi_flush_dw_param);
6947
6948     /* read register and store into status_buffer and pak_statitistic info */
6949     memset(&mi_store_reg_mem_param, 0, sizeof(mi_store_reg_mem_param));
6950     mi_store_reg_mem_param.bo = status_buffer->bo;
6951     mi_store_reg_mem_param.offset = status_buffer->bs_byte_count_frame_offset;
6952     mi_store_reg_mem_param.mmio_offset = status_buffer->bs_byte_count_frame_reg_offset;
6953     gen8_gpe_mi_store_register_mem(ctx, batch, &mi_store_reg_mem_param);
6954
6955     mi_store_reg_mem_param.bo = status_buffer->bo;
6956     mi_store_reg_mem_param.offset = status_buffer->image_status_mask_offset;
6957     mi_store_reg_mem_param.mmio_offset = status_buffer->image_status_mask_reg_offset;
6958     gen8_gpe_mi_store_register_mem(ctx, batch, &mi_store_reg_mem_param);
6959
6960     /*update the status in the pak_statistic_surface */
6961     mi_store_reg_mem_param.bo = avc_ctx->res_brc_pre_pak_statistics_output_buffer.bo;
6962     mi_store_reg_mem_param.offset = 0;
6963     mi_store_reg_mem_param.mmio_offset = status_buffer->bs_byte_count_frame_reg_offset;
6964     gen8_gpe_mi_store_register_mem(ctx, batch, &mi_store_reg_mem_param);
6965
6966     mi_store_reg_mem_param.bo = avc_ctx->res_brc_pre_pak_statistics_output_buffer.bo;
6967     mi_store_reg_mem_param.offset = 4;
6968     mi_store_reg_mem_param.mmio_offset = status_buffer->bs_byte_count_frame_nh_reg_offset;
6969     gen8_gpe_mi_store_register_mem(ctx, batch, &mi_store_reg_mem_param);
6970
6971     memset(&mi_store_data_imm_param, 0, sizeof(mi_store_data_imm_param));
6972     mi_store_data_imm_param.bo = avc_ctx->res_brc_pre_pak_statistics_output_buffer.bo;
6973     mi_store_data_imm_param.offset = sizeof(unsigned int) * 2;
6974     mi_store_data_imm_param.dw0 = (generic_state->curr_pak_pass + 1);
6975     gen8_gpe_mi_store_data_imm(ctx, batch, &mi_store_data_imm_param);
6976
6977     mi_store_reg_mem_param.bo = avc_ctx->res_brc_pre_pak_statistics_output_buffer.bo;
6978     mi_store_reg_mem_param.offset = sizeof(unsigned int) * (4 + generic_state->curr_pak_pass) ;
6979     mi_store_reg_mem_param.mmio_offset = status_buffer->image_status_ctrl_reg_offset;
6980     gen8_gpe_mi_store_register_mem(ctx, batch, &mi_store_reg_mem_param);
6981
6982     memset(&mi_flush_dw_param, 0, sizeof(mi_flush_dw_param));
6983     gen8_gpe_mi_flush_dw(ctx, batch, &mi_flush_dw_param);
6984
6985     return;
6986 }
6987
6988 static void
6989 gen9_avc_pak_brc_prepare(struct encode_state *encode_state,
6990                           struct intel_encoder_context *encoder_context)
6991 {
6992     struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
6993     struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )pak_context->generic_enc_state;
6994     unsigned int rate_control_mode = encoder_context->rate_control_mode;
6995
6996     switch (rate_control_mode & 0x7f) {
6997     case VA_RC_CBR:
6998         generic_state->internal_rate_mode = VA_RC_CBR;
6999         break;
7000
7001     case VA_RC_VBR:
7002         generic_state->internal_rate_mode = VA_RC_VBR;//AVBR
7003         break;
7004
7005     case VA_RC_CQP:
7006     default:
7007         generic_state->internal_rate_mode = VA_RC_CQP;
7008         break;
7009     }
7010
7011     if (encoder_context->quality_level == 0)\r
7012         encoder_context->quality_level = ENCODER_DEFAULT_QUALITY_AVC;\r
7013 }
7014
7015 static VAStatus
7016 gen9_avc_pak_pipeline_prepare(VADriverContextP ctx,
7017                      struct encode_state *encode_state,
7018                      struct intel_encoder_context *encoder_context)
7019 {
7020     VAStatus va_status;
7021     struct i965_driver_data *i965 = i965_driver_data(ctx);
7022     struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
7023     struct generic_encoder_context * generic_ctx = (struct generic_encoder_context * )pak_context->generic_enc_ctx;
7024     struct i965_avc_encoder_context * avc_ctx = (struct i965_avc_encoder_context * )pak_context->private_enc_ctx;
7025     struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )pak_context->generic_enc_state;
7026     struct avc_enc_state * avc_state = (struct avc_enc_state * )pak_context->private_enc_state;
7027
7028     struct object_surface *obj_surface;
7029     VAEncPictureParameterBufferH264  *pic_param = avc_state->pic_param;
7030     VAEncSliceParameterBufferH264 *slice_param = avc_state->slice_param[0];
7031
7032     struct gen9_surface_avc *avc_priv_surface;
7033     int i, j, enable_avc_ildb = 0;
7034     unsigned int allocate_flag = 1;
7035     unsigned int size;
7036     unsigned int w_mb = generic_state->frame_width_in_mbs;
7037     unsigned int h_mb = generic_state->frame_height_in_mbs;
7038     struct avc_surface_param surface_param;
7039
7040     /* update the parameter and check slice parameter */
7041     for (j = 0; j < encode_state->num_slice_params_ext && enable_avc_ildb == 0; j++) {
7042         assert(encode_state->slice_params_ext && encode_state->slice_params_ext[j]->buffer);
7043         slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[j]->buffer;
7044
7045         for (i = 0; i < encode_state->slice_params_ext[j]->num_elements; i++) {
7046             assert((slice_param->slice_type == SLICE_TYPE_I) ||
7047                    (slice_param->slice_type == SLICE_TYPE_SI) ||
7048                    (slice_param->slice_type == SLICE_TYPE_P) ||
7049                    (slice_param->slice_type == SLICE_TYPE_SP) ||
7050                    (slice_param->slice_type == SLICE_TYPE_B));
7051
7052             if (slice_param->disable_deblocking_filter_idc != 1) {
7053                 enable_avc_ildb = 1;
7054                 break;
7055             }
7056
7057             slice_param++;
7058         }
7059     }
7060     avc_state->enable_avc_ildb = enable_avc_ildb;
7061
7062     /* setup the all surface and buffer for PAK */
7063     /* Setup current reconstruct frame */
7064     obj_surface = encode_state->reconstructed_object;
7065     va_status = i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
7066
7067     if (va_status != VA_STATUS_SUCCESS)
7068         return va_status;
7069
7070     memset(&surface_param,0,sizeof(surface_param));
7071     surface_param.frame_width = generic_state->frame_width_in_pixel;
7072     surface_param.frame_height = generic_state->frame_height_in_pixel;
7073     va_status = gen9_avc_init_check_surfaces(ctx,
7074                                              obj_surface,encoder_context,
7075                                              &surface_param);
7076     if (va_status != VA_STATUS_SUCCESS)
7077         return va_status;
7078     /* init the member of avc_priv_surface,frame_store_id,qp_value */
7079     {
7080        avc_priv_surface = (struct gen9_surface_avc *)obj_surface->private_data;
7081        avc_state->top_field_poc[NUM_MFC_AVC_DMV_BUFFERS-2] = 0;
7082        avc_state->top_field_poc[NUM_MFC_AVC_DMV_BUFFERS-1] = 0;
7083        i965_free_gpe_resource(&avc_ctx->res_direct_mv_buffersr[NUM_MFC_AVC_DMV_BUFFERS-2]);
7084        i965_free_gpe_resource(&avc_ctx->res_direct_mv_buffersr[NUM_MFC_AVC_DMV_BUFFERS-1]);
7085        i965_dri_object_to_buffer_gpe_resource(&avc_ctx->res_direct_mv_buffersr[NUM_MFC_AVC_DMV_BUFFERS-2],avc_priv_surface->dmv_top);
7086        i965_dri_object_to_buffer_gpe_resource(&avc_ctx->res_direct_mv_buffersr[NUM_MFC_AVC_DMV_BUFFERS-1],avc_priv_surface->dmv_bottom);
7087        avc_priv_surface->qp_value = pic_param->pic_init_qp + slice_param->slice_qp_delta;
7088        avc_priv_surface->frame_store_id = 0;
7089        avc_priv_surface->frame_idx = pic_param->CurrPic.frame_idx;
7090        avc_priv_surface->top_field_order_cnt = pic_param->CurrPic.TopFieldOrderCnt;
7091        avc_priv_surface->is_as_ref = pic_param->pic_fields.bits.reference_pic_flag;
7092        avc_state->top_field_poc[NUM_MFC_AVC_DMV_BUFFERS-2] = avc_priv_surface->top_field_order_cnt;
7093        avc_state->top_field_poc[NUM_MFC_AVC_DMV_BUFFERS-1] = avc_priv_surface->top_field_order_cnt + 1;
7094     }
7095     i965_free_gpe_resource(&generic_ctx->res_reconstructed_surface);
7096     i965_free_gpe_resource(&avc_ctx->res_post_deblocking_output);
7097     i965_free_gpe_resource(&avc_ctx->res_pre_deblocking_output);
7098     i965_object_surface_to_2d_gpe_resource_with_align(&generic_ctx->res_reconstructed_surface, obj_surface,GPE_RESOURCE_ALIGNMENT);
7099
7100
7101     if (avc_state->enable_avc_ildb) {
7102         i965_object_surface_to_2d_gpe_resource_with_align(&avc_ctx->res_post_deblocking_output, obj_surface,GPE_RESOURCE_ALIGNMENT);
7103     } else {
7104         i965_object_surface_to_2d_gpe_resource_with_align(&avc_ctx->res_pre_deblocking_output, obj_surface,GPE_RESOURCE_ALIGNMENT);
7105     }
7106     /* input YUV surface */
7107     obj_surface = encode_state->input_yuv_object;
7108     va_status = i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
7109
7110     if (va_status != VA_STATUS_SUCCESS)
7111         return va_status;
7112     i965_free_gpe_resource(&generic_ctx->res_uncompressed_input_surface);
7113     i965_object_surface_to_2d_gpe_resource_with_align(&generic_ctx->res_uncompressed_input_surface, obj_surface,GPE_RESOURCE_ALIGNMENT);
7114
7115     /* Reference surfaces */
7116     for (i = 0; i < ARRAY_ELEMS(avc_ctx->list_reference_res); i++) {
7117         i965_free_gpe_resource(&avc_ctx->list_reference_res[i]);
7118         i965_free_gpe_resource(&avc_ctx->res_direct_mv_buffersr[i*2]);
7119         i965_free_gpe_resource(&avc_ctx->res_direct_mv_buffersr[i*2 + 1]);
7120         obj_surface = encode_state->reference_objects[i];
7121         avc_state->top_field_poc[2*i] = 0;
7122         avc_state->top_field_poc[2*i+1] = 0;
7123
7124         if (obj_surface && obj_surface->bo) {
7125             i965_object_surface_to_2d_gpe_resource_with_align(&avc_ctx->list_reference_res[i], obj_surface,GPE_RESOURCE_ALIGNMENT);
7126
7127             /* actually it should be handled when it is reconstructed surface */
7128             va_status = gen9_avc_init_check_surfaces(ctx,
7129                 obj_surface,encoder_context,
7130                 &surface_param);
7131             if (va_status != VA_STATUS_SUCCESS)
7132                 return va_status;
7133             avc_priv_surface = (struct gen9_surface_avc *)obj_surface->private_data;
7134             i965_dri_object_to_buffer_gpe_resource(&avc_ctx->res_direct_mv_buffersr[i*2],avc_priv_surface->dmv_top);
7135             i965_dri_object_to_buffer_gpe_resource(&avc_ctx->res_direct_mv_buffersr[i*2 + 1],avc_priv_surface->dmv_bottom);
7136             avc_priv_surface->frame_store_id = i;
7137             avc_state->top_field_poc[2*i] = avc_priv_surface->top_field_order_cnt;
7138             avc_state->top_field_poc[2*i+1] = avc_priv_surface->top_field_order_cnt+1;
7139         }else
7140         {
7141             break;
7142         }
7143     }
7144
7145     if (avc_ctx->pres_slice_batch_buffer_2nd_level)
7146     {
7147         intel_batchbuffer_free(avc_ctx->pres_slice_batch_buffer_2nd_level);
7148         avc_ctx->pres_slice_batch_buffer_2nd_level = NULL;
7149     }
7150
7151     avc_ctx->pres_slice_batch_buffer_2nd_level =
7152         intel_batchbuffer_new(&i965->intel, I915_EXEC_BSD,
7153                               4096 *
7154                               encode_state->num_slice_params_ext);
7155     if (!avc_ctx->pres_slice_batch_buffer_2nd_level)
7156         return VA_STATUS_ERROR_ALLOCATION_FAILED;
7157
7158     for (i = 0;i < MAX_AVC_SLICE_NUM;i++) {
7159         avc_state->slice_batch_offset[i] = 0;
7160     }
7161
7162
7163     size = w_mb * 64;
7164     i965_free_gpe_resource(&avc_ctx->res_intra_row_store_scratch_buffer);
7165     allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
7166                                  &avc_ctx->res_intra_row_store_scratch_buffer,
7167                                  size,
7168                                 "PAK Intra row store scratch buffer");
7169     if (!allocate_flag)
7170         goto failed_allocation;
7171
7172     size = w_mb * 4 * 64;
7173     i965_free_gpe_resource(&avc_ctx->res_deblocking_filter_row_store_scratch_buffer);
7174     allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
7175                                  &avc_ctx->res_deblocking_filter_row_store_scratch_buffer,
7176                                  size,
7177                                 "PAK Deblocking filter row store scratch buffer");
7178     if (!allocate_flag)
7179         goto failed_allocation;
7180
7181     size = w_mb * 2 * 64;
7182     i965_free_gpe_resource(&avc_ctx->res_bsd_mpc_row_store_scratch_buffer);
7183     allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
7184                                  &avc_ctx->res_bsd_mpc_row_store_scratch_buffer,
7185                                  size,
7186                                 "PAK BSD/MPC row store scratch buffer");
7187     if (!allocate_flag)
7188         goto failed_allocation;
7189
7190     size = w_mb * h_mb * 16;
7191     i965_free_gpe_resource(&avc_ctx->res_pak_mb_status_buffer);
7192     allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
7193                                  &avc_ctx->res_pak_mb_status_buffer,
7194                                  size,
7195                                 "PAK MB status buffer");
7196     if (!allocate_flag)
7197         goto failed_allocation;
7198
7199     return VA_STATUS_SUCCESS;
7200
7201 failed_allocation:
7202     return VA_STATUS_ERROR_ALLOCATION_FAILED;
7203 }
7204
7205 static VAStatus
7206 gen9_avc_encode_picture(VADriverContextP ctx,
7207                         VAProfile profile,
7208                         struct encode_state *encode_state,
7209                         struct intel_encoder_context *encoder_context)
7210 {
7211     VAStatus va_status;
7212     struct i965_driver_data *i965 = i965_driver_data(ctx);
7213     struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
7214     struct i965_avc_encoder_context * avc_ctx = (struct i965_avc_encoder_context * )vme_context->private_enc_ctx;
7215     struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
7216     struct intel_batchbuffer *batch = encoder_context->base.batch;
7217
7218     va_status = gen9_avc_pak_pipeline_prepare(ctx, encode_state, encoder_context);
7219
7220     if (va_status != VA_STATUS_SUCCESS)
7221         return va_status;
7222
7223     if (i965->intel.has_bsd2)
7224         intel_batchbuffer_start_atomic_bcs_override(batch, 0x1000, BSD_RING0);
7225     else
7226         intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
7227     intel_batchbuffer_emit_mi_flush(batch);
7228
7229     for (generic_state->curr_pak_pass = 0;
7230          generic_state->curr_pak_pass < generic_state->num_pak_passes;
7231          generic_state->curr_pak_pass++) {
7232
7233          if (generic_state->curr_pak_pass == 0) {
7234              /* Initialize the avc Image Ctrl reg for the first pass,write 0 to staturs/control register, is it needed in AVC? */
7235              struct gpe_mi_load_register_imm_parameter mi_load_reg_imm;
7236              struct encoder_status_buffer_internal *status_buffer;
7237
7238              status_buffer = &(avc_ctx->status_buffer);
7239              memset(&mi_load_reg_imm, 0, sizeof(mi_load_reg_imm));
7240              mi_load_reg_imm.mmio_offset = status_buffer->image_status_ctrl_reg_offset;
7241              mi_load_reg_imm.data = 0;
7242              gen8_gpe_mi_load_register_imm(ctx, batch, &mi_load_reg_imm);
7243          }
7244          gen9_avc_pak_picture_level(ctx, encode_state, encoder_context);
7245          gen9_avc_pak_slice_level(ctx, encode_state, encoder_context);
7246          gen9_avc_read_mfc_status(ctx, encoder_context);
7247
7248     }
7249
7250     if (avc_ctx->pres_slice_batch_buffer_2nd_level)
7251     {
7252         intel_batchbuffer_free(avc_ctx->pres_slice_batch_buffer_2nd_level);
7253         avc_ctx->pres_slice_batch_buffer_2nd_level = NULL;
7254     }
7255
7256     intel_batchbuffer_end_atomic(batch);
7257     intel_batchbuffer_flush(batch);
7258
7259     generic_state->seq_frame_number++;
7260     generic_state->total_frame_number++;
7261     generic_state->first_frame = 0;
7262     return VA_STATUS_SUCCESS;
7263 }
7264
7265 static VAStatus
7266 gen9_avc_pak_pipeline(VADriverContextP ctx,
7267                       VAProfile profile,
7268                       struct encode_state *encode_state,
7269                       struct intel_encoder_context *encoder_context)
7270 {
7271     VAStatus vaStatus;
7272
7273     switch (profile) {
7274     case VAProfileH264ConstrainedBaseline:
7275     case VAProfileH264Main:
7276     case VAProfileH264High:
7277         vaStatus = gen9_avc_encode_picture(ctx, profile, encode_state, encoder_context);
7278         break;
7279
7280     default:
7281         vaStatus = VA_STATUS_ERROR_UNSUPPORTED_PROFILE;
7282         break;
7283     }
7284
7285     return vaStatus;
7286 }
7287
7288 static void
7289 gen9_avc_pak_context_destroy(void * context)
7290 {
7291     struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)context;
7292     struct generic_encoder_context * generic_ctx;
7293     struct i965_avc_encoder_context * avc_ctx;
7294     int i = 0;
7295
7296     if (!pak_context)
7297         return;
7298
7299     generic_ctx = (struct generic_encoder_context * )pak_context->generic_enc_ctx;
7300     avc_ctx = (struct i965_avc_encoder_context * )pak_context->private_enc_ctx;
7301
7302     // other things
7303     i965_free_gpe_resource(&generic_ctx->res_reconstructed_surface);
7304     i965_free_gpe_resource(&avc_ctx->res_post_deblocking_output);
7305     i965_free_gpe_resource(&avc_ctx->res_pre_deblocking_output);
7306     i965_free_gpe_resource(&generic_ctx->res_uncompressed_input_surface);
7307
7308     i965_free_gpe_resource(&generic_ctx->compressed_bitstream.res);
7309     i965_free_gpe_resource(&avc_ctx->res_intra_row_store_scratch_buffer);
7310     i965_free_gpe_resource(&avc_ctx->res_deblocking_filter_row_store_scratch_buffer);
7311     i965_free_gpe_resource(&avc_ctx->res_bsd_mpc_row_store_scratch_buffer);
7312     i965_free_gpe_resource(&avc_ctx->res_pak_mb_status_buffer);
7313
7314     for(i = 0 ; i < MAX_MFC_AVC_REFERENCE_SURFACES; i++)
7315     {
7316         i965_free_gpe_resource(&avc_ctx->list_reference_res[i]);
7317     }
7318
7319     for(i = 0 ; i < NUM_MFC_AVC_DMV_BUFFERS; i++)
7320     {
7321         i965_free_gpe_resource(&avc_ctx->res_direct_mv_buffersr[i]);
7322     }
7323
7324     if (avc_ctx->pres_slice_batch_buffer_2nd_level)
7325     {
7326         intel_batchbuffer_free(avc_ctx->pres_slice_batch_buffer_2nd_level);
7327         avc_ctx->pres_slice_batch_buffer_2nd_level = NULL;
7328     }
7329
7330 }
7331
7332 static VAStatus
7333 gen9_avc_get_coded_status(VADriverContextP ctx,
7334                           struct intel_encoder_context *encoder_context,
7335                           struct i965_coded_buffer_segment *coded_buf_seg)
7336 {
7337     struct encoder_status *avc_encode_status;
7338
7339     if (!encoder_context || !coded_buf_seg)
7340         return VA_STATUS_ERROR_INVALID_BUFFER;
7341
7342     avc_encode_status = (struct encoder_status *)coded_buf_seg->codec_private_data;
7343     coded_buf_seg->base.size = avc_encode_status->bs_byte_count_frame;
7344
7345     return VA_STATUS_SUCCESS;
7346 }
7347
7348 Bool
7349 gen9_avc_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
7350 {
7351     /* VME & PAK share the same context */
7352     struct i965_driver_data *i965 = i965_driver_data(ctx);
7353     struct encoder_vme_mfc_context * vme_context = NULL;
7354     struct generic_encoder_context * generic_ctx = NULL;
7355     struct i965_avc_encoder_context * avc_ctx = NULL;
7356     struct generic_enc_codec_state * generic_state = NULL;
7357     struct avc_enc_state * avc_state = NULL;
7358     struct encoder_status_buffer_internal *status_buffer;
7359     uint32_t base_offset = offsetof(struct i965_coded_buffer_segment, codec_private_data);
7360
7361     vme_context = calloc(1, sizeof(struct encoder_vme_mfc_context));
7362     generic_ctx = calloc(1, sizeof(struct generic_encoder_context));
7363     avc_ctx = calloc(1, sizeof(struct i965_avc_encoder_context));
7364     generic_state = calloc(1, sizeof(struct generic_enc_codec_state));
7365     avc_state = calloc(1, sizeof(struct avc_enc_state));
7366
7367     if(!vme_context || !generic_ctx || !avc_ctx || !generic_state || !avc_state)
7368         goto allocate_structure_failed;
7369
7370     memset(vme_context,0,sizeof(struct encoder_vme_mfc_context));
7371     memset(generic_ctx,0,sizeof(struct generic_encoder_context));
7372     memset(avc_ctx,0,sizeof(struct i965_avc_encoder_context));
7373     memset(generic_state,0,sizeof(struct generic_enc_codec_state));
7374     memset(avc_state,0,sizeof(struct avc_enc_state));
7375
7376     encoder_context->vme_context = vme_context;
7377     vme_context->generic_enc_ctx = generic_ctx;
7378     vme_context->private_enc_ctx = avc_ctx;
7379     vme_context->generic_enc_state = generic_state;
7380     vme_context->private_enc_state = avc_state;
7381
7382     if (IS_SKL(i965->intel.device_info)||
7383         IS_BXT(i965->intel.device_info)) {
7384         generic_ctx->enc_kernel_ptr = (void *)skl_avc_encoder_kernels;
7385         generic_ctx->enc_kernel_size = sizeof(skl_avc_encoder_kernels);
7386     }
7387     else
7388         goto allocate_structure_failed;
7389
7390     /* initialize misc ? */
7391     avc_ctx->ctx = ctx;
7392     generic_ctx->use_hw_scoreboard = 1;
7393     generic_ctx->use_hw_non_stalling_scoreboard = 1;
7394
7395     /* initialize generic state */
7396
7397     generic_state->kernel_mode = INTEL_ENC_KERNEL_NORMAL;
7398     generic_state->preset = INTEL_PRESET_RT_SPEED;
7399     generic_state->seq_frame_number = 0;
7400     generic_state->total_frame_number = 0;
7401     generic_state->frame_type = 0;
7402     generic_state->first_frame = 1;
7403
7404     generic_state->frame_width_in_pixel = 0;
7405     generic_state->frame_height_in_pixel = 0;
7406     generic_state->frame_width_in_mbs = 0;
7407     generic_state->frame_height_in_mbs = 0;
7408     generic_state->frame_width_4x = 0;
7409     generic_state->frame_height_4x = 0;
7410     generic_state->frame_width_16x = 0;
7411     generic_state->frame_height_16x = 0;
7412     generic_state->frame_width_32x = 0;
7413     generic_state->downscaled_width_4x_in_mb = 0;
7414     generic_state->downscaled_height_4x_in_mb = 0;
7415     generic_state->downscaled_width_16x_in_mb = 0;
7416     generic_state->downscaled_height_16x_in_mb = 0;
7417     generic_state->downscaled_width_32x_in_mb = 0;
7418     generic_state->downscaled_height_32x_in_mb = 0;
7419
7420     generic_state->hme_supported = 1;
7421     generic_state->b16xme_supported = 1;
7422     generic_state->b32xme_supported = 0;
7423     generic_state->hme_enabled = 0;
7424     generic_state->b16xme_enabled = 0;
7425     generic_state->b32xme_enabled = 0;
7426     generic_state->brc_distortion_buffer_supported = 1;
7427     generic_state->brc_constant_buffer_supported = 0;
7428
7429
7430     generic_state->frame_rate = 30;
7431     generic_state->brc_allocated = 0;
7432     generic_state->brc_inited = 0;
7433     generic_state->brc_need_reset = 0;
7434     generic_state->is_low_delay = 0;
7435     generic_state->brc_enabled = 0;//default
7436     generic_state->internal_rate_mode = 0;
7437     generic_state->curr_pak_pass = 0;
7438     generic_state->num_pak_passes = MAX_AVC_PAK_PASS_NUM;
7439     generic_state->is_first_pass = 1;
7440     generic_state->is_last_pass = 0;
7441     generic_state->mb_brc_enabled = 0; // enable mb brc
7442     generic_state->brc_roi_enable = 0;
7443     generic_state->brc_dirty_roi_enable = 0;
7444     generic_state->skip_frame_enbale = 0;
7445
7446     generic_state->target_bit_rate = 0;
7447     generic_state->max_bit_rate = 0;
7448     generic_state->min_bit_rate = 0;
7449     generic_state->init_vbv_buffer_fullness_in_bit = 0;
7450     generic_state->vbv_buffer_size_in_bit = 0;
7451     generic_state->frames_per_100s = 0;
7452     generic_state->gop_size = 0;
7453     generic_state->gop_ref_distance = 0;
7454     generic_state->brc_target_size = 0;
7455     generic_state->brc_mode = 0;
7456     generic_state->brc_init_current_target_buf_full_in_bits = 0.0;
7457     generic_state->brc_init_reset_input_bits_per_frame = 0.0;
7458     generic_state->brc_init_reset_buf_size_in_bits = 0;
7459     generic_state->brc_init_previous_target_buf_full_in_bits = 0;
7460     generic_state->frames_per_window_size = 0;//default
7461     generic_state->target_percentage = 0;
7462
7463     generic_state->avbr_curracy = 0;
7464     generic_state->avbr_convergence = 0;
7465
7466     generic_state->num_skip_frames = 0;
7467     generic_state->size_skip_frames = 0;
7468
7469     generic_state->num_roi = 0;
7470     generic_state->max_delta_qp = 0;
7471     generic_state->min_delta_qp = 0;
7472
7473     if (encoder_context->rate_control_mode != VA_RC_NONE &&
7474         encoder_context->rate_control_mode != VA_RC_CQP) {
7475         generic_state->brc_enabled = 1;
7476         generic_state->brc_distortion_buffer_supported = 1;
7477         generic_state->brc_constant_buffer_supported = 1;
7478         generic_state->num_pak_passes = MAX_AVC_PAK_PASS_NUM;
7479     }
7480     /*avc state initialization */
7481     avc_state->mad_enable = 0;
7482     avc_state->mb_disable_skip_map_enable = 0;
7483     avc_state->sfd_enable = 1;//default
7484     avc_state->sfd_mb_enable = 1;//set it true
7485     avc_state->adaptive_search_window_enable = 1;//default
7486     avc_state->mb_qp_data_enable = 0;
7487     avc_state->intra_refresh_i_enable = 0;
7488     avc_state->min_max_qp_enable = 0;
7489     avc_state->skip_bias_adjustment_enable = 0;//default,same as   skip_bias_adjustment_supporte? no
7490
7491     //external input
7492     avc_state->non_ftq_skip_threshold_lut_input_enable = 0;
7493     avc_state->ftq_skip_threshold_lut_input_enable = 0;
7494     avc_state->ftq_override = 0;
7495
7496     avc_state->direct_bias_adjustment_enable = 0;
7497     avc_state->global_motion_bias_adjustment_enable = 0;
7498     avc_state->disable_sub_mb_partion = 0;
7499     avc_state->arbitrary_num_mbs_in_slice = 0;
7500     avc_state->adaptive_transform_decision_enable = 0;//default
7501     avc_state->skip_check_disable = 0;
7502     avc_state->tq_enable = 0;
7503     avc_state->enable_avc_ildb = 0;
7504     avc_state->mbaff_flag = 0;
7505     avc_state->enable_force_skip = 1;//default
7506     avc_state->rc_panic_enable = 1;//default
7507     avc_state->suppress_recon_enable = 1;//default
7508
7509     avc_state->ref_pic_select_list_supported = 1;
7510     avc_state->mb_brc_supported = 1;//?,default
7511     avc_state->multi_pre_enable = 1;//default
7512     avc_state->ftq_enable = 1;//default
7513     avc_state->caf_supported = 1; //default
7514     avc_state->caf_enable = 0;
7515     avc_state->caf_disable_hd = 1;//default
7516     avc_state->skip_bias_adjustment_supported = 1;//default
7517
7518     avc_state->adaptive_intra_scaling_enable = 1;//default
7519     avc_state->old_mode_cost_enable = 0;//default
7520     avc_state->multi_ref_qp_enable = 1;//default
7521     avc_state->weighted_ref_l0_enable = 1;//default
7522     avc_state->weighted_ref_l1_enable = 1;//default
7523     avc_state->weighted_prediction_supported = 0;
7524     avc_state->brc_split_enable = 0;
7525     avc_state->slice_level_report_supported = 0;
7526
7527     avc_state->fbr_bypass_enable = 1;//default
7528     avc_state->field_scaling_output_interleaved = 0;
7529     avc_state->mb_variance_output_enable = 0;
7530     avc_state->mb_pixel_average_output_enable = 0;
7531     avc_state->rolling_intra_refresh_enable = 0;// same as intra_refresh_i_enable?
7532     avc_state->mbenc_curbe_set_in_brc_update = 0;
7533     avc_state->rounding_inter_enable = 1; //default
7534     avc_state->adaptive_rounding_inter_enable = 1;//default
7535
7536     avc_state->mbenc_i_frame_dist_in_use = 0;
7537     avc_state->mb_status_supported = 1; //set in intialization for gen9
7538     avc_state->mb_status_enable = 0;
7539     avc_state->mb_vproc_stats_enable = 0;
7540     avc_state->flatness_check_enable = 0;
7541     avc_state->flatness_check_supported = 1;//default
7542     avc_state->block_based_skip_enable = 0;
7543     avc_state->use_widi_mbenc_kernel = 0;
7544     avc_state->kernel_trellis_enable = 0;
7545     avc_state->generic_reserved = 0;
7546
7547     avc_state->rounding_value = 0;
7548     avc_state->rounding_inter_p = 255;//default
7549     avc_state->rounding_inter_b = 255; //default
7550     avc_state->rounding_inter_b_ref = 255; //default
7551     avc_state->min_qp_i = INTEL_AVC_MIN_QP;
7552     avc_state->min_qp_p = INTEL_AVC_MIN_QP;
7553     avc_state->min_qp_b = INTEL_AVC_MIN_QP;
7554     avc_state->max_qp_i = INTEL_AVC_MAX_QP;
7555     avc_state->max_qp_p = INTEL_AVC_MAX_QP;
7556     avc_state->max_qp_b = INTEL_AVC_MAX_QP;
7557
7558     memset(avc_state->non_ftq_skip_threshold_lut,0,52*sizeof(uint8_t));
7559     memset(avc_state->ftq_skip_threshold_lut,0,52*sizeof(uint8_t));
7560     memset(avc_state->lamda_value_lut,0,52*2*sizeof(uint8_t));
7561
7562     avc_state->intra_refresh_qp_threshold = 0;
7563     avc_state->trellis_flag = 0;
7564     avc_state->hme_mv_cost_scaling_factor = 0;
7565     avc_state->slice_height = 1;
7566     avc_state->slice_num = 1;
7567     memset(avc_state->dist_scale_factor_list0,0,32*sizeof(uint32_t));
7568     avc_state->bi_weight = 0;
7569     avc_state->brc_const_data_surface_width = 64;
7570     avc_state->brc_const_data_surface_height = 44;
7571
7572     avc_state->num_refs[0] = 0;
7573     avc_state->num_refs[1] = 0;
7574     memset(avc_state->list_ref_idx,0,32*2*sizeof(uint32_t));
7575     memset(avc_state->top_field_poc,0,NUM_MFC_AVC_DMV_BUFFERS*sizeof(int32_t));
7576     avc_state->tq_rounding = 0;
7577     avc_state->zero_mv_threshold = 0;
7578     avc_state->slice_second_levle_batch_buffer_in_use = 0;
7579
7580     //1. seq/pic/slice
7581
7582     /* the definition of status buffer offset for Encoder */
7583
7584     status_buffer = &avc_ctx->status_buffer;
7585     memset(status_buffer, 0,sizeof(struct encoder_status_buffer_internal));
7586
7587     status_buffer->base_offset = base_offset;
7588     status_buffer->bs_byte_count_frame_offset = base_offset + offsetof(struct encoder_status, bs_byte_count_frame);
7589     status_buffer->bs_byte_count_frame_nh_offset = base_offset + offsetof(struct encoder_status, bs_byte_count_frame_nh);
7590     status_buffer->image_status_mask_offset = base_offset + offsetof(struct encoder_status, image_status_mask);
7591     status_buffer->image_status_ctrl_offset = base_offset + offsetof(struct encoder_status, image_status_ctrl);
7592     status_buffer->mfc_qp_status_count_offset = base_offset + offsetof(struct encoder_status, mfc_qp_status_count);
7593     status_buffer->media_index_offset       = base_offset + offsetof(struct encoder_status, media_index);
7594
7595     status_buffer->status_buffer_size = sizeof(struct encoder_status);
7596     status_buffer->bs_byte_count_frame_reg_offset = MFC_BITSTREAM_BYTECOUNT_FRAME_REG;
7597     status_buffer->bs_byte_count_frame_nh_reg_offset = MFC_BITSTREAM_BYTECOUNT_SLICE_REG;
7598     status_buffer->image_status_mask_reg_offset = MFC_IMAGE_STATUS_MASK_REG;
7599     status_buffer->image_status_ctrl_reg_offset = MFC_IMAGE_STATUS_CTRL_REG;
7600     status_buffer->mfc_qp_status_count_reg_offset = MFC_QP_STATUS_COUNT_REG;
7601
7602     gen9_avc_kernel_init(ctx,encoder_context);
7603     encoder_context->vme_context = vme_context;
7604     encoder_context->vme_pipeline = gen9_avc_vme_pipeline;
7605     encoder_context->vme_context_destroy = gen9_avc_vme_context_destroy;
7606
7607     return true;
7608
7609 allocate_structure_failed:
7610
7611     free(vme_context);
7612     free(generic_ctx);
7613     free(avc_ctx);
7614     free(generic_state);
7615     free(avc_state);
7616     return false;
7617 }
7618
7619 Bool
7620 gen9_avc_pak_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
7621 {
7622     /* VME & PAK share the same context */
7623     struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
7624
7625     if (!pak_context)
7626         return false;
7627
7628     encoder_context->mfc_context = pak_context;
7629     encoder_context->mfc_context_destroy = gen9_avc_pak_context_destroy;
7630     encoder_context->mfc_pipeline = gen9_avc_pak_pipeline;
7631     encoder_context->mfc_brc_prepare = gen9_avc_pak_brc_prepare;
7632     encoder_context->get_status = gen9_avc_get_coded_status;
7633     return true;
7634 }