2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Xiang, Haihao <haihao.xiang@intel.com>
36 #include "intel_batchbuffer.h"
37 #include "intel_driver.h"
39 #include "i965_defines.h"
40 #include "i965_drv_video.h"
41 #include "i965_encoder.h"
42 #include "i965_encoder_vp8.h"
44 extern struct i965_kernel vp8_kernels_brc_init_reset[NUM_VP8_BRC_RESET];
45 extern struct i965_kernel vp8_kernels_scaling[NUM_VP8_SCALING];
46 extern struct i965_kernel vp8_kernels_me[NUM_VP8_ME];
47 extern struct i965_kernel vp8_kernels_mbenc[NUM_VP8_MBENC];
48 extern struct i965_kernel vp8_kernels_mpu[NUM_VP8_MPU];
49 extern struct i965_kernel vp8_kernels_tpu[NUM_VP8_TPU];
50 extern struct i965_kernel vp8_kernels_brc_update[NUM_VP8_BRC_UPDATE];
52 static const uint32_t gen9_brc_init_bin_vp8[][4] = {
53 #include "shaders/brc/skl/vp8_brc_init_genx_0.g9b"
56 static const uint32_t gen9_brc_reset_bin_vp8[][4] = {
57 #include "shaders/brc/skl/vp8_brc_reset_genx_0.g9b"
60 static const uint32_t gen9_scaling_bin_vp8[][4] = {
61 #include "shaders/brc/skl/hme_downscale_genx_0.g9b"
64 static const uint32_t gen9_me_bin_vp8[][4] = {
65 #include "shaders/brc/skl/hme_genx_0.g9b"
68 static const uint32_t gen9_mbenc_i_frame_dist_bin_vp8[][4] = {
69 #include "shaders/brc/skl/vp8_intra_distortion_genx_0.g9b"
72 static const uint32_t gen9_mbenc_i_frame_luma_bin_vp8[][4] = {
73 #include "shaders/brc/skl/vp8_enc_genx_0.g9b"
76 static const uint32_t gen9_mbenc_i_frame_chroma_bin_vp8[][4] = {
77 #include "shaders/brc/skl/vp8_enc_genx_1.g9b"
80 static const uint32_t gen9_mbenc_p_frame_bin_vp8[][4] = {
81 #include "shaders/brc/skl/vp8_enc_genx_2.g9b"
84 static const uint32_t gen9_mpu_bin_vp8[][4] = {
85 #include "shaders/brc/skl/vp8_mpu_genx_0.g9b"
88 static const uint32_t gen9_tpu_bin_vp8[][4] = {
89 #include "shaders/brc/skl/vp8_tpu_genx_0.g9b"
92 static const uint32_t gen9_brc_update_bin_vp8[][4] = {
93 #include "shaders/brc/skl/vp8_brc_update_genx_0.g9b"
97 gen9_encoder_vp8_context_init(VADriverContextP ctx,
98 struct intel_encoder_context *encoder_context,
99 struct i965_encoder_vp8_context *vp8_context)
101 vp8_kernels_brc_init_reset[VP8_BRC_INIT].bin = gen9_brc_init_bin_vp8;
102 vp8_kernels_brc_init_reset[VP8_BRC_INIT].size = sizeof(gen9_brc_init_bin_vp8);
103 vp8_kernels_brc_init_reset[VP8_BRC_RESET].bin = gen9_brc_reset_bin_vp8;
104 vp8_kernels_brc_init_reset[VP8_BRC_RESET].size = sizeof(gen9_brc_reset_bin_vp8);
106 /* scaling 4x and 16x use the same kernel */
107 vp8_kernels_scaling[VP8_SCALING_4X].bin = gen9_scaling_bin_vp8;
108 vp8_kernels_scaling[VP8_SCALING_4X].size = sizeof(gen9_scaling_bin_vp8);
109 vp8_kernels_scaling[VP8_SCALING_16X].bin = gen9_scaling_bin_vp8;
110 vp8_kernels_scaling[VP8_SCALING_16X].size = sizeof(gen9_scaling_bin_vp8);
112 /* me 4x and 16x use the same kernel */
113 vp8_kernels_me[VP8_ME_4X].bin = gen9_me_bin_vp8;
114 vp8_kernels_me[VP8_ME_4X].size = sizeof(gen9_me_bin_vp8);
115 vp8_kernels_me[VP8_ME_16X].bin = gen9_me_bin_vp8;
116 vp8_kernels_me[VP8_ME_16X].size = sizeof(gen9_me_bin_vp8);
118 vp8_kernels_mbenc[VP8_MBENC_I_FRAME_DIST].bin = gen9_mbenc_i_frame_dist_bin_vp8;
119 vp8_kernels_mbenc[VP8_MBENC_I_FRAME_DIST].size = sizeof(gen9_mbenc_i_frame_dist_bin_vp8);
120 vp8_kernels_mbenc[VP8_MBENC_I_FRAME_LUMA].bin = gen9_mbenc_i_frame_luma_bin_vp8;
121 vp8_kernels_mbenc[VP8_MBENC_I_FRAME_LUMA].size = sizeof(gen9_mbenc_i_frame_luma_bin_vp8);
122 vp8_kernels_mbenc[VP8_MBENC_I_FRAME_CHROMA].bin = gen9_mbenc_i_frame_chroma_bin_vp8;
123 vp8_kernels_mbenc[VP8_MBENC_I_FRAME_CHROMA].size = sizeof(gen9_mbenc_i_frame_chroma_bin_vp8);
124 vp8_kernels_mbenc[VP8_MBENC_P_FRAME].bin = gen9_mbenc_p_frame_bin_vp8;
125 vp8_kernels_mbenc[VP8_MBENC_P_FRAME].size = sizeof(gen9_mbenc_p_frame_bin_vp8);
127 vp8_kernels_mpu[VP8_MPU].bin = gen9_mpu_bin_vp8;
128 vp8_kernels_mpu[VP8_MPU].size = sizeof(gen9_mpu_bin_vp8);
130 vp8_kernels_brc_update[VP8_BRC_UPDATE].bin = gen9_brc_update_bin_vp8;
131 vp8_kernels_brc_update[VP8_BRC_UPDATE].size = sizeof(gen9_brc_update_bin_vp8);
133 vp8_kernels_tpu[VP8_TPU].bin = gen9_tpu_bin_vp8;
134 vp8_kernels_tpu[VP8_TPU].size = sizeof(gen9_tpu_bin_vp8);
136 vp8_context->idrt_entry_size = ALIGN(sizeof(struct gen8_interface_descriptor_data), 64);