2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Qu Pengfei <Pengfei.Qu@intel.com>
34 #include <intel_bufmgr.h>
36 #include "i965_gpe_utils.h"
40 #define MAX_HCP_REFERENCE_SURFACES 8
41 #define NUM_HCP_CURRENT_COLLOCATED_MV_TEMPORAL_BUFFERS 9
43 #define INTRA_MB_FLAG_MASK 0x00002000
45 /* The space required for slice header SLICE_STATE + header.
47 #define SLICE_HEADER 80
49 /* the space required for slice tail. */
52 #define __SOFTWARE__ 0
54 #define HCP_BATCHBUFFER_HEVC_INTRA 0
55 #define HCP_BATCHBUFFER_HEVC_INTER 1
56 #define NUM_HCP_KERNEL 2
58 #define BIND_IDX_VME_OUTPUT 0
59 #define BIND_IDX_HCP_SLICE_HEADER 1
60 #define BIND_IDX_HCP_BATCHBUFFER 2
62 #define CMD_LEN_IN_OWORD 4
64 struct gen9_hcpe_context {
72 //HCP_PIPE_BUF_ADDR_STATE
76 } deblocking_filter_line_buffer; //OUTPUT: reconstructed picture with deblocked
80 } deblocking_filter_tile_line_buffer; //OUTPUT: reconstructed picture with deblocked
84 } deblocking_filter_tile_column_buffer; //OUTPUT: reconstructed picture with deblocked
88 } uncompressed_picture_source; //INPUT: original compressed image
92 } metadata_line_buffer; //INTERNAL:metadata
96 } metadata_tile_line_buffer; //INTERNAL:metadata
100 } metadata_tile_column_buffer; //INTERNAL:metadata
104 } sao_line_buffer; //INTERNAL:SAO not used in skylake
108 } sao_tile_line_buffer; //INTERNAL:SAO not used in skylake
112 } sao_tile_column_buffer; //INTERNAL:SAO not used in skylake
116 } current_collocated_mv_temporal_buffer[NUM_HCP_CURRENT_COLLOCATED_MV_TEMPORAL_BUFFERS]; //
120 } reference_surfaces[MAX_HCP_REFERENCE_SURFACES]; //INTERNAL: refrence surfaces
122 //HCP_IND_OBJ_BASE_ADDR_STATE
125 } hcp_indirect_cu_object; //INPUT: the cu' mv info
131 } hcp_indirect_pak_bse_object; //OUTPUT: the compressed bitstream
133 //Bit rate tracking context
135 unsigned int QpPrimeY;
136 unsigned int MaxQpNegModifier;
137 unsigned int MaxQpPosModifier;
138 unsigned char MaxSizeInWord;
139 unsigned char TargetSizeInWord;
140 unsigned char Correct[6];
141 unsigned char GrowInit;
142 unsigned char GrowResistance;
143 unsigned char ShrinkInit;
144 unsigned char ShrinkResistance;
146 unsigned int target_mb_size;
147 unsigned int target_frame_size;
148 } bit_rate_control_context[3]; //INTERNAL: for I, P, B frames
153 int target_frame_size[3]; // I,P,B
154 double bits_per_frame;
155 double qpf_rounding_accumulator;
159 double current_buffer_fullness;
160 double target_buffer_fullness;
161 double buffer_capacity;
162 unsigned int buffer_size;
163 unsigned int violation_noted;
166 //HRD control context
168 int i_bit_rate_value; // scale?
169 int i_cpb_size_value; // scale?
171 int i_initial_cpb_removal_delay;
172 int i_cpb_removal_delay;
176 int i_initial_cpb_removal_delay_length;
177 int i_cpb_removal_delay_length;
178 int i_dpb_output_delay_length;
181 // picture width and height
183 uint16_t picture_width_in_samples;
184 uint16_t picture_height_in_samples;
185 uint16_t picture_width_in_ctbs;
186 uint16_t picture_height_in_ctbs;
187 uint16_t picture_width_in_min_cb_minus1;
188 uint16_t picture_height_in_min_cb_minus1;
189 uint16_t picture_width_in_mbs; /* to use on skylake */
190 uint16_t picture_height_in_mbs;/* to sue on skylake */
195 VAQMatrixBufferHEVC iq_matrix_hevc;
197 struct i965_gpe_context gpe_context;
198 struct i965_buffer_surface hcp_batchbuffer_surface;
199 struct intel_batchbuffer *aux_batchbuffer;
200 struct i965_buffer_surface aux_batchbuffer_surface;
202 void (*pipe_mode_select)(VADriverContextP ctx,
204 struct intel_encoder_context *encoder_context);
205 void (*set_surface_state)(VADriverContextP ctx, struct encode_state *encode_state,
206 struct intel_encoder_context *encoder_context);
207 void (*ind_obj_base_addr_state)(VADriverContextP ctx,
208 struct intel_encoder_context *encoder_context);
209 void (*fqm_state)(VADriverContextP ctx,
210 struct intel_encoder_context *encoder_context);
211 void (*qm_state)(VADriverContextP ctx,
212 struct intel_encoder_context *encoder_context);
213 void (*pic_state)(VADriverContextP ctx,
214 struct encode_state *encode_state,
215 struct intel_encoder_context *encoder_context);
216 void (*insert_object)(VADriverContextP ctx,
217 struct intel_encoder_context *encoder_context,
218 unsigned int *insert_data,
219 int lenght_in_dws, int data_bits_in_last_dw,
220 int skip_emul_byte_count,
221 int is_last_header, int is_end_of_slice,
223 struct intel_batchbuffer *batch);
224 void (*buffer_suface_setup)(VADriverContextP ctx,
225 struct i965_gpe_context *gpe_context,
226 struct i965_buffer_surface *buffer_surface,
227 unsigned long binding_table_offset,
228 unsigned long surface_state_offset);
231 VAStatus gen9_hcpe_pipeline(VADriverContextP ctx,
233 struct encode_state *encode_state,
234 struct intel_encoder_context *encoder_context);
237 extern int intel_hcpe_update_hrd(struct encode_state *encode_state,
238 struct gen9_hcpe_context *hcpe_context,
241 extern int intel_hcpe_brc_postpack(struct encode_state *encode_state,
242 struct gen9_hcpe_context *hcpe_context,
245 extern void intel_hcpe_hrd_context_update(struct encode_state *encode_state,
246 struct gen9_hcpe_context *hcpe_context);
248 extern int intel_hcpe_interlace_check(VADriverContextP ctx,
249 struct encode_state *encode_state,
250 struct intel_encoder_context *encoder_context);
252 extern void intel_hcpe_brc_prepare(struct encode_state *encode_state,
253 struct intel_encoder_context *encoder_context);
255 /* HEVC HCP pipeline */
256 extern void intel_hcpe_hevc_pipeline_header_programing(VADriverContextP ctx,
257 struct encode_state *encode_state,
258 struct intel_encoder_context *encoder_context,
259 struct intel_batchbuffer *slice_batch);
261 extern VAStatus intel_hcpe_hevc_prepare(VADriverContextP ctx,
262 struct encode_state *encode_state,
263 struct intel_encoder_context *encoder_context);
266 intel_hcpe_hevc_ref_idx_state(VADriverContextP ctx,
267 struct encode_state *encode_state,
268 struct intel_encoder_context *encoder_context);
271 intel_hevc_slice_insert_packed_data(VADriverContextP ctx,
272 struct encode_state *encode_state,
273 struct intel_encoder_context *encoder_context,
275 struct intel_batchbuffer *slice_batch);
278 Bool gen9_hcpe_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context);
280 void gen9_hcpe_context_destroy(void *context);
282 #endif /* GEN9_MFC_H */