src/gen9_mfc.h

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Qu Pengfei <Pengfei.Qu@intel.com>
  26  *
  27  */
  28
  29 #ifndef GEN9_MFC_H
  30 #define GEN9_MFC_H
  31
  32 #include <drm.h>
  33 #include <i915_drm.h>
  34 #include <intel_bufmgr.h>
  35
  36 #include "i965_gpe_utils.h"
  37
  38 struct encode_state;
  39
  40 #define MAX_HCP_REFERENCE_SURFACES      8
  41 #define NUM_HCP_CURRENT_COLLOCATED_MV_TEMPORAL_BUFFERS             9
  42
  43 #define INTRA_MB_FLAG_MASK              0x00002000
  44
  45 /* The space required for slice header SLICE_STATE + header.
  46  * Is it enough? */
  47 #define SLICE_HEADER            80
  48
  49 /* the space required for slice tail. */
  50 #define SLICE_TAIL          16
  51
  52 #define __SOFTWARE__    0
  53
  54 #define HCP_BATCHBUFFER_HEVC_INTRA       0
  55 #define HCP_BATCHBUFFER_HEVC_INTER       1
  56 #define NUM_HCP_KERNEL                   2
  57
  58 #define BIND_IDX_VME_OUTPUT             0
  59 #define BIND_IDX_HCP_SLICE_HEADER       1
  60 #define BIND_IDX_HCP_BATCHBUFFER        2
  61
  62 #define CMD_LEN_IN_OWORD        4
  63
  64 struct gen9_hcpe_context {
  65     struct {
  66         unsigned int width;
  67         unsigned int height;
  68         unsigned int w_pitch;
  69         unsigned int h_pitch;
  70     } surface_state;
  71
  72     //HCP_PIPE_BUF_ADDR_STATE
  73
  74     struct {
  75         dri_bo *bo;
  76     } deblocking_filter_line_buffer;            //OUTPUT: reconstructed picture with deblocked
  77
  78     struct {
  79         dri_bo *bo;
  80     } deblocking_filter_tile_line_buffer;       //OUTPUT: reconstructed picture with deblocked
  81
  82     struct {
  83         dri_bo *bo;
  84     } deblocking_filter_tile_column_buffer;     //OUTPUT: reconstructed picture with deblocked
  85
  86     struct {
  87         dri_bo *bo;
  88     } uncompressed_picture_source;              //INPUT: original compressed image
  89
  90     struct {
  91         dri_bo *bo;
  92     } metadata_line_buffer;                     //INTERNAL:metadata
  93
  94     struct {
  95         dri_bo *bo;
  96     } metadata_tile_line_buffer;                //INTERNAL:metadata
  97
  98     struct {
  99         dri_bo *bo;
 100     } metadata_tile_column_buffer;              //INTERNAL:metadata
 101
 102     struct {
 103         dri_bo *bo;
 104     } sao_line_buffer;                     //INTERNAL:SAO not used in skylake
 105
 106     struct {
 107         dri_bo *bo;
 108     } sao_tile_line_buffer;                //INTERNAL:SAO not used in skylake
 109
 110     struct {
 111         dri_bo *bo;
 112     } sao_tile_column_buffer;              //INTERNAL:SAO not used in skylake
 113
 114     struct {
 115         dri_bo *bo;
 116     } current_collocated_mv_temporal_buffer[NUM_HCP_CURRENT_COLLOCATED_MV_TEMPORAL_BUFFERS];       //
 117
 118     struct {
 119         dri_bo *bo;
 120     } reference_surfaces[MAX_HCP_REFERENCE_SURFACES];   //INTERNAL: refrence surfaces
 121
 122     //HCP_IND_OBJ_BASE_ADDR_STATE
 123     struct {
 124         dri_bo *bo;
 125     } hcp_indirect_cu_object;           //INPUT: the cu' mv info
 126
 127     struct {
 128         dri_bo *bo;
 129         int offset;
 130         int end_offset;
 131     } hcp_indirect_pak_bse_object;      //OUTPUT: the compressed bitstream
 132
 133     //Bit rate tracking context
 134     struct {
 135         unsigned int QpPrimeY;
 136         unsigned int MaxQpNegModifier;
 137         unsigned int MaxQpPosModifier;
 138         unsigned char MaxSizeInWord;
 139         unsigned char TargetSizeInWord;
 140         unsigned char Correct[6];
 141         unsigned char GrowInit;
 142         unsigned char GrowResistance;
 143         unsigned char ShrinkInit;
 144         unsigned char ShrinkResistance;
 145
 146         unsigned int target_mb_size;
 147         unsigned int target_frame_size;
 148     } bit_rate_control_context[3];      //INTERNAL: for I, P, B frames
 149
 150     struct {
 151         int mode;
 152         int gop_nums[3];
 153         int target_frame_size[3]; // I,P,B
 154         double bits_per_frame;
 155         double qpf_rounding_accumulator;
 156     } brc;
 157
 158     struct {
 159         double current_buffer_fullness;
 160         double target_buffer_fullness;
 161         double buffer_capacity;
 162         unsigned int buffer_size;
 163         unsigned int violation_noted;
 164     } hrd;
 165
 166     //HRD control context
 167     struct {
 168         int i_bit_rate_value; // scale?
 169         int i_cpb_size_value; // scale?
 170
 171         int i_initial_cpb_removal_delay;
 172         int i_cpb_removal_delay;
 173
 174         int i_frame_number;
 175
 176         int i_initial_cpb_removal_delay_length;
 177         int i_cpb_removal_delay_length;
 178         int i_dpb_output_delay_length;
 179     } vui_hrd;
 180
 181     // picture width and height
 182     struct {
 183         uint16_t picture_width_in_samples;
 184         uint16_t picture_height_in_samples;
 185         uint16_t picture_width_in_ctbs;
 186         uint16_t picture_height_in_ctbs;
 187         uint16_t picture_width_in_min_cb_minus1;
 188         uint16_t picture_height_in_min_cb_minus1;
 189         uint16_t picture_width_in_mbs; /* to use on skylake */
 190         uint16_t picture_height_in_mbs;/* to sue on skylake */
 191         uint8_t ctb_size;
 192         uint8_t min_cb_size;
 193     } pic_size;
 194
 195     VAQMatrixBufferHEVC  iq_matrix_hevc;
 196
 197     struct i965_gpe_context gpe_context;
 198     struct i965_buffer_surface hcp_batchbuffer_surface;
 199     struct intel_batchbuffer *aux_batchbuffer;
 200     struct i965_buffer_surface aux_batchbuffer_surface;
 201
 202     void (*pipe_mode_select)(VADriverContextP ctx,
 203                              int standard_select,
 204                              struct intel_encoder_context *encoder_context);
 205     void (*set_surface_state)(VADriverContextP ctx, struct encode_state *encode_state,
 206                               struct intel_encoder_context *encoder_context);
 207     void (*ind_obj_base_addr_state)(VADriverContextP ctx,
 208                                     struct intel_encoder_context *encoder_context);
 209     void (*fqm_state)(VADriverContextP ctx,
 210                       struct intel_encoder_context *encoder_context);
 211     void (*qm_state)(VADriverContextP ctx,
 212                      struct intel_encoder_context *encoder_context);
 213     void (*pic_state)(VADriverContextP ctx,
 214                       struct encode_state *encode_state,
 215                       struct intel_encoder_context *encoder_context);
 216     void (*insert_object)(VADriverContextP ctx,
 217                           struct intel_encoder_context *encoder_context,
 218                           unsigned int *insert_data,
 219                           int lenght_in_dws, int data_bits_in_last_dw,
 220                           int skip_emul_byte_count,
 221                           int is_last_header, int is_end_of_slice,
 222                           int emulation_flag,
 223                           struct intel_batchbuffer *batch);
 224     void (*buffer_suface_setup)(VADriverContextP ctx,
 225                                 struct i965_gpe_context *gpe_context,
 226                                 struct i965_buffer_surface *buffer_surface,
 227                                 unsigned long binding_table_offset,
 228                                 unsigned long surface_state_offset);
 229 };
 230
 231 VAStatus gen9_hcpe_pipeline(VADriverContextP ctx,
 232                             VAProfile profile,
 233                             struct encode_state *encode_state,
 234                             struct intel_encoder_context *encoder_context);
 235
 236 /* HEVC BRC */
 237 extern int intel_hcpe_update_hrd(struct encode_state *encode_state,
 238                                  struct gen9_hcpe_context *hcpe_context,
 239                                  int frame_bits);
 240
 241 extern int intel_hcpe_brc_postpack(struct encode_state *encode_state,
 242                                    struct gen9_hcpe_context *hcpe_context,
 243                                    int frame_bits);
 244
 245 extern void intel_hcpe_hrd_context_update(struct encode_state *encode_state,
 246                                           struct gen9_hcpe_context *hcpe_context);
 247
 248 extern int intel_hcpe_interlace_check(VADriverContextP ctx,
 249                                       struct encode_state *encode_state,
 250                                       struct intel_encoder_context *encoder_context);
 251
 252 extern void intel_hcpe_brc_prepare(struct encode_state *encode_state,
 253                                    struct intel_encoder_context *encoder_context);
 254
 255 /* HEVC HCP pipeline */
 256 extern void intel_hcpe_hevc_pipeline_header_programing(VADriverContextP ctx,
 257                                                        struct encode_state *encode_state,
 258                                                        struct intel_encoder_context *encoder_context,
 259                                                        struct intel_batchbuffer *slice_batch);
 260
 261 extern VAStatus intel_hcpe_hevc_prepare(VADriverContextP ctx,
 262                                         struct encode_state *encode_state,
 263                                         struct intel_encoder_context *encoder_context);
 264
 265 extern void
 266 intel_hcpe_hevc_ref_idx_state(VADriverContextP ctx,
 267                               struct encode_state *encode_state,
 268                               struct intel_encoder_context *encoder_context);
 269
 270 extern void
 271 intel_hevc_slice_insert_packed_data(VADriverContextP ctx,
 272                                     struct encode_state *encode_state,
 273                                     struct intel_encoder_context *encoder_context,
 274                                     int slice_index,
 275                                     struct intel_batchbuffer *slice_batch);
 276
 277 extern
 278 Bool gen9_hcpe_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context);
 279
 280 void gen9_hcpe_context_destroy(void *context);
 281
 282 #endif  /* GEN9_MFC_H */