2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Xiang Haihao <haihao.xiang@intel.com>
34 #include <intel_bufmgr.h>
36 #include "i965_gpe_utils.h"
37 #include "i965_encoder.h"
41 #define HUC_BRC_INIT_RESET 4
42 #define HUC_BRC_UPDATE 5
44 #define HUC_DMEM_DATA_OFFSET 0x2000
46 #define NUM_OF_BRC_PAK_PASSES 2
48 #define HUC_BRC_HISTORY_BUFFER_SIZE 832
49 #define HUC_BRC_STREAM_INOUT_BUFFER_SIZE 4096
50 #define VDENC_STATISTICS_SIZE 128
51 #define PAK_STATISTICS_SIZE 256
52 #define VDENC_AVC_IMAGE_STATE_SIZE (sizeof(struct gen9_mfx_avc_img_state) + sizeof(struct gen9_vdenc_img_state) + 2 * sizeof(int))
53 #define HME_DETECTION_SUMMARY_BUFFER_SIZE 256
54 #define BRC_CONSTANT_DATA_SIZE 4096
55 #define BRC_DEBUG_OUTPUT_SIZE 4096
57 #define HUC_STATUS_MMIO_OFFSET 0x0D000
59 #define SCALE_FACTOR_4X 4
61 #define VDENC_FRAME_I 0
62 #define VDENC_FRAME_P 1
64 #define VDENC_LUTMODE_INTRA_NONPRED 0x00
65 #define VDENC_LUTMODE_INTRA 0x01
66 #define VDENC_LUTMODE_INTRA_16x16 0x01
67 #define VDENC_LUTMODE_INTRA_8x8 0x02
68 #define VDENC_LUTMODE_INTRA_4x4 0x03
69 #define VDENC_LUTMODE_INTER_16x8 0x04
70 #define VDENC_LUTMODE_INTER_8x16 0x04
71 #define VDENC_LUTMODE_INTER_8X8Q 0x05
72 #define VDENC_LUTMODE_INTER_8X4Q 0x06
73 #define VDENC_LUTMODE_INTER_4X8Q 0x06
74 #define VDENC_LUTMODE_INTER_16x8_FIELD 0x06
75 #define VDENC_LUTMODE_INTER_4X4Q 0x07
76 #define VDENC_LUTMODE_INTER_8x8_FIELD 0x07
77 #define VDENC_LUTMODE_INTER 0x08
78 #define VDENC_LUTMODE_INTER_16x16 0x08
79 #define VDENC_LUTMODE_INTER_BWD 0x09
80 #define VDENC_LUTMODE_REF_ID 0x0A
81 #define VDENC_LUTMODE_INTRA_CHROMA 0x0B
83 struct gen9_mfx_avc_img_state {
86 uint32_t dword_length: 16;
87 uint32_t sub_opcode_b: 5;
88 uint32_t sub_opcode_a: 3;
89 uint32_t command_opcode: 3;
91 uint32_t command_type: 3;
98 uint32_t frame_size_in_mbs_minus1: 16;
103 uint32_t frame_width_in_mbs_minus1: 8;
105 uint32_t frame_height_in_mbs_minus1: 8;
111 uint32_t image_structure: 2;
112 uint32_t weighted_bipred_idc: 2;
113 uint32_t weighted_pred_flag: 1;
114 uint32_t brc_domain_rate_control_enable: 1;
116 uint32_t chroma_qp_offset: 5;
118 uint32_t second_chroma_qp_offset: 5;
123 uint32_t field_picture_flag: 1;
124 uint32_t mbaff_mode_active: 1;
125 uint32_t frame_mb_only_flag: 1;
126 uint32_t transform_8x8_idct_mode_flag: 1;
127 uint32_t direct_8x8_interface_flag: 1;
128 uint32_t constrained_intra_prediction_flag: 1;
129 uint32_t current_img_dispoable_flag: 1;
130 uint32_t entropy_coding_flag: 1;
131 uint32_t mb_mv_format_flag: 1;
133 uint32_t chroma_format_idc: 2;
134 uint32_t mv_unpacked_flag: 1;
135 uint32_t insert_test_flag: 1;
136 uint32_t load_slice_pointer_flag: 1;
137 uint32_t macroblock_stat_enable: 1;
138 uint32_t minimum_frame_size: 16;
142 uint32_t intra_mb_max_bit_flag: 1;
143 uint32_t inter_mb_max_bit_flag: 1;
144 uint32_t frame_size_over_flag: 1;
145 uint32_t frame_size_under_flag: 1;
147 uint32_t intra_mb_ipcm_flag: 1;
149 uint32_t mb_rate_ctrl_flag: 1;
150 uint32_t min_frame_size_units: 2;
151 uint32_t inter_mb_zero_cbp_flag: 1;
153 uint32_t non_first_pass_flag: 1;
155 uint32_t aq_chroma_disable: 1;
156 uint32_t aq_rounding: 3;
157 uint32_t aq_enable: 1;
161 uint32_t intra_mb_max_size: 12;
163 uint32_t inter_mb_max_size: 12;
172 uint32_t slice_delta_qp_max0: 8;
173 uint32_t slice_delta_qp_max1: 8;
174 uint32_t slice_delta_qp_max2: 8;
175 uint32_t slice_delta_qp_max3: 8;
179 uint32_t slice_delta_qp_min0: 8;
180 uint32_t slice_delta_qp_min1: 8;
181 uint32_t slice_delta_qp_min2: 8;
182 uint32_t slice_delta_qp_min3: 8;
186 uint32_t frame_bitrate_min: 14;
187 uint32_t frame_bitrate_min_unit_mode: 1;
188 uint32_t frame_bitrate_min_unit: 1;
189 uint32_t frame_bitrate_max: 14;
190 uint32_t frame_bitrate_max_unit_mode: 1;
191 uint32_t frame_bitrate_max_unit: 1;
195 uint32_t frame_bitrate_min_delta: 15;
197 uint32_t frame_bitrate_max_delta: 15;
203 uint32_t vad_error_logic: 1;
208 uint32_t pic_qp_init_minus26: 8;
209 uint32_t pic_num_ref_idx_l0_active_minus1: 6;
211 uint32_t pic_num_ref_idx_l1_active_minus1: 6;
213 uint32_t num_ref_frames: 5;
214 uint32_t is_curr_pic_has_mmco5: 1;
218 uint32_t pic_order_present_flag: 1;
219 uint32_t delta_pic_order_always_zero_flag: 1;
220 uint32_t pic_order_cnt_type: 2;
222 uint32_t slice_group_map_type: 3;
223 uint32_t redundant_pic_cnt_present_flag: 1;
224 uint32_t num_slice_groups_minus1: 3;
225 uint32_t deblock_filter_ctrl_present_flag: 1;
226 uint32_t log2_max_frame_num_minus4: 8;
227 uint32_t log2_max_pic_order_cnt_lsb_minus4: 8;
231 uint32_t slice_group_change_rate: 16;
232 uint32_t curr_pic_frame_num: 16;
236 uint32_t current_frame_view_id: 10;
238 uint32_t max_view_idx_l0: 4;
240 uint32_t max_view_idx_l1: 4;
242 uint32_t inter_view_order_disable: 1;
246 uint32_t fqp: 3; // Must be zero for SKL
247 uint32_t fqp_offset: 3; // Must be zero for SKL
249 uint32_t ext_brc_dm_stat_en: 1; // Must be zero for SKL
251 uint32_t brc_dm_avg_mb_qp: 6; // Must be zero for SKL
256 uint32_t brc_domain_target_frame_size;
260 uint32_t threshold_size_in_bytes;
264 uint32_t target_slice_size_in_bytes;
268 struct gen9_image_state_cost {
270 uint32_t mv0_cost: 8;
271 uint32_t mv1_cost: 8;
272 uint32_t mv2_cost: 8;
273 uint32_t mv3_cost: 8;
277 uint32_t mv4_cost: 8;
278 uint32_t mv5_cost: 8;
279 uint32_t mv6_cost: 8;
280 uint32_t mv7_cost: 8;
284 struct gen9_vdenc_img_state {
287 uint32_t dword_length: 12;
289 uint32_t sub_opcode_b: 5;
290 uint32_t sub_opcode_a: 2;
291 uint32_t command_opcode: 4;
292 uint32_t pipeline: 2;
293 uint32_t command_type: 3;
301 uint32_t bidirectional_mix_disable: 1;
303 uint32_t time_budget_overflow_check: 1;
305 uint32_t extended_pak_obj_cmd_enable: 1;
306 uint32_t transform_8x8_flag: 1;
307 uint32_t vdenc_l1_cache_priority: 2;
313 uint32_t bidirectional_weight: 6;
315 uint32_t unidirection_mix_disable: 1;
321 uint32_t picture_width: 16;
326 uint32_t subpel_mode: 2;
328 uint32_t forward_transform_skip_check_enable: 1;
329 uint32_t bme_disable_for_fbr_message: 1;
330 uint32_t block_based_skip_enabled: 1;
331 uint32_t inter_sad_measure_adjustment: 2;
332 uint32_t intra_sad_measure_adjustment: 2;
333 uint32_t sub_macroblock_sub_partition_mask: 7;
334 uint32_t block_based_skip_type: 1;
338 uint32_t picture_height_minus1: 16;
339 uint32_t cre_prefetch_enable: 1;
340 uint32_t hme_ref1_disable: 1;
341 uint32_t mb_slice_threshold_value: 4;
343 uint32_t constrained_intra_prediction_flag: 1;
345 uint32_t picture_type: 2;
350 uint32_t slice_macroblock_height_minus1: 16;
359 uint32_t luma_intra_partition_mask: 5;
360 uint32_t non_skip_zero_mv_const_added: 1;
361 uint32_t non_skip_mb_mode_const_added: 1;
363 uint32_t mv_cost_scaling_factor: 2;
364 uint32_t bilinear_filter_enable: 1;
366 uint32_t ref_id_cost_mode_select: 1;
371 uint32_t mode0_cost: 8;
372 uint32_t mode1_cost: 8;
373 uint32_t mode2_cost: 8;
374 uint32_t mode3_cost: 8;
378 uint32_t mode4_cost: 8;
379 uint32_t mode5_cost: 8;
380 uint32_t mode6_cost: 8;
381 uint32_t mode7_cost: 8;
385 uint32_t mode8_cost: 8;
386 uint32_t mode9_cost: 8;
387 uint32_t ref_id_cost: 8;
388 uint32_t chroma_intra_mode_cost: 8;
392 struct gen9_image_state_cost mv_cost;
396 uint32_t qp_prime_y: 8;
398 uint32_t target_size_in_word: 8;
410 uint32_t avc_intra_4x4_mode_mask: 9;
412 uint32_t avc_intra_8x8_mode_mask: 9;
417 uint32_t avc_intra_16x16_mode_mask: 4;
418 uint32_t avc_intra_chroma_mode_mask: 4;
419 uint32_t intra_compute_type_intra_compute_type: 2;
428 uint32_t penalty_for_intra_16x16_non_dc_prediction: 8;
429 uint32_t penalty_for_intra_8x8_non_dc_prediction: 8;
430 uint32_t penalty_for_intra_4x4_non_dc_prediction: 8;
439 uint32_t panic_mode_mb_threadhold: 16;
440 uint32_t small_mb_size_in_word: 8;
441 uint32_t large_mb_size_in_word: 8;
445 uint32_t l0_number_of_reference_minus1: 8;
447 uint32_t l1_number_of_reference_minus1: 8;
461 uint32_t hme_ref_windows_combining_threshold: 8;
466 uint32_t max_hmv_r: 16;
467 uint32_t max_vmv_r: 16;
471 struct gen9_image_state_cost hme_mv_cost;
475 uint32_t roi_qp_adjustment_for_zone0: 4;
476 uint32_t roi_qp_adjustment_for_zone1: 4;
477 uint32_t roi_qp_adjustment_for_zone2: 4;
478 uint32_t roi_qp_adjustment_for_zone3: 4;
479 uint32_t qp_adjustment_for_shape_best_intra_4x4_winner: 4;
480 uint32_t qp_adjustment_for_shape_best_intra_8x8_winner: 4;
481 uint32_t qp_adjustment_for_shape_best_intra_16x16_winner: 4;
486 uint32_t best_distortion_qp_adjustment_for_zone0: 4;
487 uint32_t best_distortion_qp_adjustment_for_zone1: 4;
488 uint32_t best_distortion_qp_adjustment_for_zone2: 4;
489 uint32_t best_distortion_qp_adjustment_for_zone3: 4;
490 uint32_t offset0_for_zone0_neg_zone1_boundary: 16;
494 uint32_t offset1_for_zone1_neg_zone2_boundary: 16;
495 uint32_t offset2_for_zone2_neg_zone3_boundary: 16;
499 uint32_t qp_range_check_upper_bound: 8;
500 uint32_t qp_range_check_lower_bound: 8;
502 uint32_t qp_range_check_value: 4;
507 uint32_t roi_enable: 1;
508 uint32_t fwd_predictor0_mv_enable: 1;
509 uint32_t bdw_predictor1_mv_enable: 1;
510 uint32_t mb_level_qp_enable: 1;
511 uint32_t target_size_in_words_mb_max_size_in_words_mb_enable: 1;
513 uint32_t ppmv_disable: 1;
514 uint32_t coefficient_clamp_enable: 1;
515 uint32_t long_term_reference_frame_bwd_ref0_indicator: 1;
516 uint32_t long_term_reference_frame_fwd_ref2_indicator: 1;
517 uint32_t long_term_reference_frame_fwd_ref1_indicator: 1;
518 uint32_t long_term_reference_frame_fwd_ref0_indicator: 1;
519 uint32_t image_state_qp_override: 1;
521 uint32_t midpoint_distortion: 16;
525 struct gen9_vdenc_streamin_state {
527 uint32_t roi_selection: 8;
528 uint32_t force_intra: 1;
529 uint32_t force_skip: 1;
534 uint32_t qp_prime_y: 8;
535 uint32_t target_size_in_word: 8;
536 uint32_t max_size_in_word: 8;
541 uint32_t fwd_predictor_x: 16;
542 uint32_t fwd_predictor_y: 16;
546 uint32_t bwd_predictore_x: 16;
547 uint32_t bwd_predictore_y: 16;
551 uint32_t fwd_ref_id0: 4;
552 uint32_t bdw_ref_id0: 4;
561 struct huc_brc_update_constant_data {
562 uint8_t global_rate_qp_adj_tab_i[64];
563 uint8_t global_rate_qp_adj_tab_p[64];
564 uint8_t global_rate_qp_adj_tab_b[64];
565 uint8_t dist_threshld_i[10];
566 uint8_t dist_threshld_p[10];
567 uint8_t dist_threshld_b[10];
568 uint8_t dist_qp_adj_tab_i[81];
569 uint8_t dist_qp_adj_tab_p[81];
570 uint8_t dist_qp_adj_tab_b[81];
571 int8_t buf_rate_adj_tab_i[72];
572 int8_t buf_rate_adj_tab_p[72];
573 int8_t buf_rate_adj_tab_b[72];
574 uint8_t frame_size_min_tab_p[9];
575 uint8_t frame_size_min_tab_b[9];
576 uint8_t frame_size_min_tab_i[9];
577 uint8_t frame_size_max_tab_p[9];
578 uint8_t frame_size_max_tab_b[9];
579 uint8_t frame_size_max_tab_i[9];
580 uint8_t frame_size_scg_tab_p[9];
581 uint8_t frame_size_scg_tab_b[9];
582 uint8_t frame_size_scg_tab_i[9];
583 /* cost table 14*42 = 588 bytes */
584 uint8_t i_intra_non_pred[42];
585 uint8_t i_intra_16x16[42];
586 uint8_t i_intra_8x8[42];
587 uint8_t i_intra_4x4[42];
588 uint8_t i_intra_chroma[42];
589 uint8_t p_intra_non_pred[42];
590 uint8_t p_intra_16x16[42];
591 uint8_t p_intra_8x8[42];
592 uint8_t p_intra_4x4[42];
593 uint8_t p_intra_chroma[42];
594 uint8_t p_inter_16x8[42];
595 uint8_t p_inter_8x8[42];
596 uint8_t p_inter_16x16[42];
597 uint8_t p_ref_id[42];
598 uint8_t hme_mv_cost[8][42];
602 struct huc_brc_init_dmem {
603 uint8_t brc_func; // 0: Init; 2: Reset
604 uint8_t os_enabled; // Always 1
606 uint16_t brc_flag; // ICQ or CQP with slice size control: 0x00 CBR: 0x10; VBR: 0x20; VCM: 0x40; LOWDELAY: 0x80.
608 uint16_t frame_width; // Luma width in bytes
609 uint16_t frame_height; // Luma height in bytes
610 uint32_t target_bitrate; // target bitrate, set by application
611 uint32_t min_rate; // 0
612 uint32_t max_rate; // Maximum bit rate in bits per second (bps).
613 uint32_t buffer_size; // buffer size in bits
614 uint32_t init_buffer_fullness; // initial buffer fullness in bits
615 uint32_t profile_level_max_frame; // user defined. refer to AVC BRC HLD for conformance check and correction
616 uint32_t frame_rate_m; // FrameRateM is the number of frames in FrameRateD
617 uint32_t frame_rate_d; // If driver gets this FrameRateD from VUI, it is the num_units_in_tick field (32 bits UINT).
618 uint16_t num_p_in_gop; // number of P frames in a GOP
619 uint16_t num_b_in_gop; // number of B frames in a GOP
620 uint16_t min_qp; // 10
621 uint16_t max_qp; // 51
622 int8_t dev_thresh_pb0[8]; // lowdelay ? (-45, -33, -23, -15, -8, 0, 15, 25) : (-46, -38, -30, -23, 23, 30, 40, 46)
623 int8_t dev_thresh_vbr0[8]; // lowdelay ? (-45, -35, -25, -15, -8, 0, 20, 40) : (-46, -40, -32, -23, 56, 64, 83, 93)
624 int8_t dev_thresh_i0[8]; // lowdelay ? (-40, -30, -17, -10, -5, 0, 10, 20) : (-43, -36, -25, -18, 18, 28, 38, 46)
625 uint8_t init_qp_ip; // Initial QP for I and P
627 uint8_t pad2; // Reserved
628 uint8_t init_qp_b; // Initial QP for B
629 uint8_t mb_qp_ctrl; // Enable MB level QP control (global)
630 uint8_t slice_size_ctrl_en; // Enable slice size control
631 int8_t intra_qp_delta[3]; // set to zero for all by default
632 int8_t skip_qp_delta; // Reserved
633 int8_t dist_qp_delta[4]; // lowdelay ? (-5, -2, 2, 5) : (0, 0, 0, 0)
634 uint8_t oscillation_qp_delta; // BRCFLAG_ISVCM ? 16 : 0
635 uint8_t first_iframe_no_hrd_check; // BRCFLAG_ISVCM ? 1 : 0
636 uint8_t skip_frame_enable_flag;
637 uint8_t top_qp_delta_thr_for_2nd_pass; // =1. QP Delta threshold for second pass.
638 uint8_t top_frame_size_threshold_for_2nd_pass; // lowdelay ? 10 : 50. Top frame size threshold for second pass
639 uint8_t bottom_frame_size_threshold_for_2nd_pass; // lowdelay ? 10 : 200. Bottom frame size threshold for second pass
640 uint8_t qp_select_for_first_pass; // lowdelay ? 0 : 1. =0 to use previous frame final QP; or =1 to use (targetQP + previousQP) / 2.
641 uint8_t mb_header_compensation; // Reserved
642 uint8_t over_shoot_carry_flag; // set to zero by default
643 uint8_t over_shoot_skip_frame_pct; // set to zero by default
644 uint8_t estrate_thresh_p0[7]; // 4, 8, 12, 16, 20, 24, 28
645 uint8_t estrate_thresh_b0[7]; // 4, 8, 12, 16, 20, 24, 28
646 uint8_t estrate_thresh_i0[7]; // 4, 8, 12, 16, 20, 24, 28
647 uint8_t fqp_enable; // ExtendedBrcDomainEn
648 uint8_t scenario_info; // 0: UNKNOWN, 1: DISPLAYREMOTING, 2: VIDEOCONFERENCE, 3: ARCHIVE, 4: LIVESTREAMING.
649 uint8_t static_Region_streamin; // should be programmed from par file
650 uint8_t delta_qp_adaptation; // =1,
651 uint8_t max_crf_quality_factor; // =52,
652 uint8_t crf_quality_factor; // =25,
653 uint8_t bottom_qp_delta_thr_for_2nd_pass;// =1. QP Delta threshold for second pass.
654 uint8_t sliding_window_size; // =30, the window size (in frames) used to compute bit rate
655 uint8_t sliding_widow_rc_enable; // =0, sliding window based rate control (SWRC) disabled, 1: enabled
656 uint8_t sliding_window_max_rate_ratio; // =120, ratio between the max rate within the window and average target bitrate
657 uint8_t low_delay_golden_frame_boost; // only for lowdelay mode, 0 (default): no boost for I and scene change frames, 1: boost
658 uint8_t pad3[61]; // Must be zero
661 struct huc_brc_update_dmem {
662 uint8_t brc_func; // =1 for Update, other values are reserved for future use
664 uint32_t target_size; // refer to AVC BRC HLD for calculation
665 uint32_t frame_number; // frame number
666 uint32_t peak_tx_bits_per_frame; // current global target bits - previous global target bits (global target bits += input bits per frame)
667 uint32_t frame_budget; // target time counter
668 uint32_t frame_byte_count; // PAK output via MMIO
669 uint32_t timing_budget_overflow; // PAK output via MMIO
670 uint32_t slice_size_violation; // PAK output via MMIO
671 uint32_t ipcm_non_conformant; // PAK output via MMIO
673 uint16_t start_global_adjust_frame[4]; // 10, 50, 100, 150
674 uint16_t mb_budget[52]; // MB bugdet for QP 0 - 51.
675 uint16_t target_slice_size; // target slice size
676 uint16_t slcsz_thr_deltai[42]; // slice size threshold delta for I frame
677 uint16_t slcsz_thr_deltap[42]; // slice size threshold delta for P frame
678 uint16_t num_of_frames_skipped; // Recording how many frames have been skipped.
679 uint16_t skip_frame_size; // Recording the skip frame size for one frame. =NumMBs * 1, assuming one bit per mb for skip frame.
680 uint16_t static_region_pct; // One entry, recording the percentage of static region
681 uint8_t global_rate_ratio_threshold[7]; // 80,95,99,101,105,125,160
682 uint8_t current_frame_type; // I frame: 2; P frame: 0; B frame: 1.
683 uint8_t start_global_adjust_mult[5]; // 1, 1, 3, 2, 1
684 uint8_t start_global_adjust_div[5]; // 40, 5, 5, 3, 1
685 uint8_t global_rate_ratio_threshold_qp[8]; // 253,254,255,0,1,1,2,3
686 uint8_t current_pak_pass; // current pak pass number
687 uint8_t max_num_passes; // 2
688 uint8_t scene_change_width[2]; // set both to MIN((NumP + 1) / 5, 6)
689 uint8_t scene_change_detect_enable; // Enable scene change detection
690 uint8_t scene_change_prev_intra_percent_threshold; // =96. scene change previous intra percentage threshold
691 uint8_t scene_change_cur_intra_perent_threshold; // =192. scene change current intra percentage threshold
692 uint8_t ip_average_coeff; // lowdelay ? 0 : 128
693 uint8_t min_qp_adjustment; // Minimum QP increase step
694 uint8_t timing_budget_check; // Flag indicating if kernel will check timing budget.
695 int8_t roi_qp_delta_i8[4]; // Application specified ROI QP Adjustment for Zone0, Zone1, Zone2 and Zone3.
696 uint8_t cqp_qp_value; // Application specified target QP in BRC_ICQ mode
697 uint8_t cqp_fqp; // Application specified fine position in BRC_ICQ mode
698 uint8_t hme_detection_enable; // 0: default, 1: HuC BRC kernel requires information from HME detection kernel output
699 uint8_t hme_cost_enable; // 0: default, 1: driver provides HME cost table
700 uint8_t disable_pframe_8x8_transform;
701 uint8_t skl_cabac_wa_enable;
702 uint8_t roi_source; // =0: disable, 1: ROIMap from HME Static Region or from App dirty rectangle, 2: ROIMap from App
703 uint8_t slice_size_consertative_threshold; // =0, 0: do not set conservative threshold (suggested for video conference) 1: set conservative threshold for non-video conference
704 uint16_t max_target_slice_size; // default: 1498, max target slice size from app DDI
705 uint16_t max_num_slice_allowed; // computed by driver based on level idc
706 uint16_t second_level_batchbuffer_size; // second level batch buffer (SLBB) size in bytes, the input buffer will contain two SLBBs A and B, A followed by B, A and B have the same structure.
707 uint16_t second_level_batchbuffer_b_offset; // offset in bytes from the beginning of the input buffer, it points to the start of SLBB B, set by driver for skip frame support
708 uint16_t avc_img_state_offset; // offset in bytes from the beginning of SLBB A
710 /* HME distortion based QP adjustment */
711 uint16_t ave_hme_dist;
712 uint8_t hme_dist_available; // 0: disabled, 1: enabled
717 struct gen9_vdenc_status {
718 uint32_t bytes_per_frame;
721 struct gen9_vdenc_context {
722 uint32_t frame_width_in_mbs;
723 uint32_t frame_height_in_mbs;
724 uint32_t frame_width; // frame_width_in_mbs * 16
725 uint32_t frame_height; // frame_height_in_mbs * 16
726 uint32_t down_scaled_width_in_mb4x;
727 uint32_t down_scaled_height_in_mb4x;
728 uint32_t down_scaled_width_4x; // down_scaled_width_in_mb4x * 16
729 uint32_t down_scaled_height_4x; // down_scaled_height_in_mbs * 16
731 uint32_t target_bit_rate; /* in kbps */
732 uint32_t max_bit_rate; /* in kbps */
733 uint32_t min_bit_rate; /* in kbps */
734 uint64_t init_vbv_buffer_fullness_in_bit;
735 uint64_t vbv_buffer_size_in_bit;
736 struct intel_fraction framerate;
739 double brc_target_size;
740 double brc_init_current_target_buf_full_in_bits;
741 double brc_init_reset_input_bits_per_frame;
742 uint32_t brc_init_reset_buf_size_in_bits;
743 uint32_t brc_init_previous_target_buf_full_in_bits;
745 uint8_t mode_cost[12];
747 uint8_t hme_mv_cost[8];
750 uint32_t max_delta_qp;
751 uint32_t min_delta_qp;
752 struct intel_roi roi[3];
754 uint32_t brc_initted: 1;
755 uint32_t brc_need_reset: 1;
756 uint32_t is_low_delay: 1;
757 uint32_t brc_enabled: 1;
758 uint32_t internal_rate_mode: 4;
759 uint32_t current_pass: 4;
760 uint32_t num_passes: 4;
761 uint32_t is_first_pass: 1;
762 uint32_t is_last_pass: 1;
764 uint32_t vdenc_streamin_enable: 1;
765 uint32_t vdenc_pak_threshold_check_enable: 1;
767 uint32_t transform_8x8_mode_enable: 1;
768 uint32_t frame_type: 2;
770 uint32_t mb_brc_enabled: 1;
771 uint32_t is_frame_level_vdenc: 1;
772 uint32_t use_extended_pak_obj_cmd: 1;
775 struct i965_gpe_resource brc_init_reset_dmem_res;
776 struct i965_gpe_resource brc_history_buffer_res;
777 struct i965_gpe_resource brc_stream_in_res;
778 struct i965_gpe_resource brc_stream_out_res;
779 struct i965_gpe_resource huc_dummy_res;
781 struct i965_gpe_resource brc_update_dmem_res[NUM_OF_BRC_PAK_PASSES];
782 struct i965_gpe_resource vdenc_statistics_res;
783 struct i965_gpe_resource pak_statistics_res;
784 struct i965_gpe_resource vdenc_avc_image_state_res;
785 struct i965_gpe_resource hme_detection_summary_buffer_res;
786 struct i965_gpe_resource brc_constant_data_res;
787 struct i965_gpe_resource second_level_batch_res;
789 struct i965_gpe_resource huc_status_res;
790 struct i965_gpe_resource huc_status2_res;
792 struct i965_gpe_resource recon_surface_res;
793 struct i965_gpe_resource scaled_4x_recon_surface_res;
794 struct i965_gpe_resource post_deblocking_output_res;
795 struct i965_gpe_resource pre_deblocking_output_res;
796 struct i965_gpe_resource list_reference_res[16];
797 struct i965_gpe_resource list_scaled_4x_reference_res[16];
798 struct i965_gpe_resource uncompressed_input_surface_res; // Input
801 struct i965_gpe_resource res; // Output
802 uint32_t start_offset;
804 } compressed_bitstream;
806 struct i965_gpe_resource mfx_intra_row_store_scratch_res; // MFX internal buffer
807 struct i965_gpe_resource mfx_deblocking_filter_row_store_scratch_res; // MFX internal buffer
808 struct i965_gpe_resource mfx_bsd_mpc_row_store_scratch_res; // MFX internal buffer
809 struct i965_gpe_resource vdenc_row_store_scratch_res; // VDENC internal buffer
811 struct i965_gpe_resource vdenc_streamin_res;
813 uint32_t num_refs[2];
814 uint32_t list_ref_idx[2][32];
817 struct i965_gpe_resource res;
818 uint32_t base_offset;
820 uint32_t bytes_per_frame_offset;
824 struct huc_pipe_mode_select_parameter {
825 uint32_t huc_stream_object_enable;
826 uint32_t indirect_stream_out_enable;
827 uint32_t media_soft_reset_counter;
830 struct huc_imem_state_parameter {
831 uint32_t huc_firmware_descriptor;
834 struct huc_dmem_state_parameter {
835 struct i965_gpe_resource *huc_data_source_res;
836 uint32_t huc_data_destination_base_address;
837 uint32_t huc_data_length;
840 struct huc_cfg_state_parameter {
841 uint32_t force_reset;
845 struct huc_virtual_addr_parameter {
847 struct i965_gpe_resource *huc_surface_res;
852 struct huc_ind_obj_base_addr_parameter {
853 struct i965_gpe_resource *huc_indirect_stream_in_object_res;
854 struct i965_gpe_resource *huc_indirect_stream_out_object_res;
857 struct huc_stream_object_parameter {
858 uint32_t indirect_stream_in_data_length;
859 uint32_t indirect_stream_in_start_address;
860 uint32_t indirect_stream_out_start_address;
861 uint32_t huc_bitstream_enable;
862 uint32_t length_mode;
864 uint32_t emulation_prevention_byte_removal;
865 uint32_t start_code_search_engine;
866 uint8_t start_code_byte2;
867 uint8_t start_code_byte1;
868 uint8_t start_code_byte0;
871 struct huc_start_parameter {
872 uint32_t last_stream_object;
875 struct vd_pipeline_flush_parameter {
876 uint32_t hevc_pipeline_done;
877 uint32_t vdenc_pipeline_done;
878 uint32_t mfl_pipeline_done;
879 uint32_t mfx_pipeline_done;
880 uint32_t vd_command_message_parser_done;
881 uint32_t hevc_pipeline_command_flush;
882 uint32_t vdenc_pipeline_command_flush;
883 uint32_t mfl_pipeline_command_flush;
884 uint32_t mfx_pipeline_command_flush;
888 gen9_vdenc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context);
890 #endif /* GEN9_VDENC_H */