2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Zhao Yakui <yakui.zhao@intel.com>
26 * Xiang Haihao <haihao.xiang@intel.com>
35 #include "intel_batchbuffer.h"
36 #include "intel_driver.h"
38 #include "i965_defines.h"
39 #include "i965_drv_video.h"
40 #include "i965_encoder.h"
44 #include "intel_media.h"
45 #include "gen9_vp9_encapi.h"
46 #include "i965_post_processing.h"
47 #include "i965_encoder_api.h"
49 #ifdef SURFACE_STATE_PADDED_SIZE
50 #undef SURFACE_STATE_PADDED_SIZE
53 #define SURFACE_STATE_PADDED_SIZE SURFACE_STATE_PADDED_SIZE_GEN8
54 #define SURFACE_STATE_OFFSET(index) (SURFACE_STATE_PADDED_SIZE * index)
55 #define BINDING_TABLE_OFFSET(index) (SURFACE_STATE_OFFSET(MAX_MEDIA_SURFACES_GEN6) + sizeof(unsigned int) * index)
57 #define VME_INTRA_SHADER 0
58 #define VME_INTER_SHADER 1
59 #define VME_BINTER_SHADER 2
61 #define CURBE_ALLOCATION_SIZE 37 /* in 256-bit */
62 #define CURBE_TOTAL_DATA_LENGTH (4 * 32) /* in byte, it should be less than or equal to CURBE_ALLOCATION_SIZE * 32 */
63 #define CURBE_URB_ENTRY_LENGTH 4 /* in 256-bit, it should be less than or equal to CURBE_TOTAL_DATA_LENGTH / 32 */
65 #define VME_MSG_LENGTH 32
67 static const uint32_t gen9_vme_intra_frame[][4] = {
68 #include "shaders/vme/intra_frame_gen9.g9b"
71 static const uint32_t gen9_vme_inter_frame[][4] = {
72 #include "shaders/vme/inter_frame_gen9.g9b"
75 static const uint32_t gen9_vme_inter_bframe[][4] = {
76 #include "shaders/vme/inter_bframe_gen9.g9b"
79 static struct i965_kernel gen9_vme_kernels[] = {
82 VME_INTRA_SHADER, /*index*/
84 sizeof(gen9_vme_intra_frame),
91 sizeof(gen9_vme_inter_frame),
97 gen9_vme_inter_bframe,
98 sizeof(gen9_vme_inter_bframe),
103 static const uint32_t gen9_vme_mpeg2_intra_frame[][4] = {
104 #include "shaders/vme/intra_frame_gen9.g9b"
107 static const uint32_t gen9_vme_mpeg2_inter_frame[][4] = {
108 #include "shaders/vme/mpeg2_inter_gen9.g9b"
111 static struct i965_kernel gen9_vme_mpeg2_kernels[] = {
114 VME_INTRA_SHADER, /*index*/
115 gen9_vme_mpeg2_intra_frame,
116 sizeof(gen9_vme_mpeg2_intra_frame),
122 gen9_vme_mpeg2_inter_frame,
123 sizeof(gen9_vme_mpeg2_inter_frame),
128 static const uint32_t gen9_vme_vp8_intra_frame[][4] = {
129 #include "shaders/vme/vp8_intra_frame_gen9.g9b"
132 static const uint32_t gen9_vme_vp8_inter_frame[][4] = {
133 #include "shaders/vme/vp8_inter_frame_gen9.g9b"
136 static struct i965_kernel gen9_vme_vp8_kernels[] = {
139 VME_INTRA_SHADER, /*index*/
140 gen9_vme_vp8_intra_frame,
141 sizeof(gen9_vme_vp8_intra_frame),
147 gen9_vme_vp8_inter_frame,
148 sizeof(gen9_vme_vp8_inter_frame),
155 static const uint32_t gen9_vme_hevc_intra_frame[][4] = {
156 #include "shaders/vme/intra_frame_gen9.g9b"
159 static const uint32_t gen9_vme_hevc_inter_frame[][4] = {
160 #include "shaders/vme/inter_frame_gen9.g9b"
163 static const uint32_t gen9_vme_hevc_inter_bframe[][4] = {
164 #include "shaders/vme/inter_bframe_gen9.g9b"
167 static struct i965_kernel gen9_vme_hevc_kernels[] = {
170 VME_INTRA_SHADER, /*index*/
171 gen9_vme_hevc_intra_frame,
172 sizeof(gen9_vme_hevc_intra_frame),
178 gen9_vme_hevc_inter_frame,
179 sizeof(gen9_vme_hevc_inter_frame),
185 gen9_vme_hevc_inter_bframe,
186 sizeof(gen9_vme_hevc_inter_bframe),
190 /* only used for VME source surface state */
192 gen9_vme_source_surface_state(VADriverContextP ctx,
194 struct object_surface *obj_surface,
195 struct intel_encoder_context *encoder_context)
197 struct gen6_vme_context *vme_context = encoder_context->vme_context;
199 vme_context->vme_surface2_setup(ctx,
200 &vme_context->gpe_context,
202 BINDING_TABLE_OFFSET(index),
203 SURFACE_STATE_OFFSET(index));
207 gen9_vme_media_source_surface_state(VADriverContextP ctx,
209 struct object_surface *obj_surface,
210 struct intel_encoder_context *encoder_context)
212 struct gen6_vme_context *vme_context = encoder_context->vme_context;
214 vme_context->vme_media_rw_surface_setup(ctx,
215 &vme_context->gpe_context,
217 BINDING_TABLE_OFFSET(index),
218 SURFACE_STATE_OFFSET(index),
223 gen9_vme_media_chroma_source_surface_state(VADriverContextP ctx,
225 struct object_surface *obj_surface,
226 struct intel_encoder_context *encoder_context)
228 struct gen6_vme_context *vme_context = encoder_context->vme_context;
230 vme_context->vme_media_chroma_surface_setup(ctx,
231 &vme_context->gpe_context,
233 BINDING_TABLE_OFFSET(index),
234 SURFACE_STATE_OFFSET(index),
239 gen9_vme_output_buffer_setup(VADriverContextP ctx,
240 struct encode_state *encode_state,
242 struct intel_encoder_context *encoder_context,
248 struct i965_driver_data *i965 = i965_driver_data(ctx);
249 struct gen6_vme_context *vme_context = encoder_context->vme_context;
251 vme_context->vme_output.num_blocks = width_in_mbs * height_in_mbs;
252 vme_context->vme_output.pitch = 16; /* in bytes, always 16 */
255 vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES * 2;
257 vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES * 24;
259 * Inter MV . 32-byte Intra search + 16 IME info + 128 IME MV + 32 IME Ref
260 * + 16 FBR Info + 128 FBR MV + 32 FBR Ref.
261 * 16 * (2 + 2 * (1 + 8 + 2))= 16 * 24.
264 vme_context->vme_output.bo = dri_bo_alloc(i965->intel.bufmgr,
266 vme_context->vme_output.num_blocks * vme_context->vme_output.size_block,
268 assert(vme_context->vme_output.bo);
269 vme_context->vme_buffer_suface_setup(ctx,
270 &vme_context->gpe_context,
271 &vme_context->vme_output,
272 BINDING_TABLE_OFFSET(index),
273 SURFACE_STATE_OFFSET(index));
277 gen9_vme_avc_output_buffer_setup(VADriverContextP ctx,
278 struct encode_state *encode_state,
280 struct intel_encoder_context *encoder_context)
282 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
283 VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
284 int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
285 int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
286 int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
288 gen9_vme_output_buffer_setup(ctx, encode_state, index, encoder_context, is_intra, width_in_mbs, height_in_mbs);
293 gen9_vme_output_vme_batchbuffer_setup(VADriverContextP ctx,
294 struct encode_state *encode_state,
296 struct intel_encoder_context *encoder_context,
300 struct i965_driver_data *i965 = i965_driver_data(ctx);
301 struct gen6_vme_context *vme_context = encoder_context->vme_context;
303 vme_context->vme_batchbuffer.num_blocks = width_in_mbs * height_in_mbs + 1;
304 vme_context->vme_batchbuffer.size_block = 64; /* 4 OWORDs */
305 vme_context->vme_batchbuffer.pitch = 16;
306 vme_context->vme_batchbuffer.bo = dri_bo_alloc(i965->intel.bufmgr,
308 vme_context->vme_batchbuffer.num_blocks * vme_context->vme_batchbuffer.size_block,
310 vme_context->vme_buffer_suface_setup(ctx,
311 &vme_context->gpe_context,
312 &vme_context->vme_batchbuffer,
313 BINDING_TABLE_OFFSET(index),
314 SURFACE_STATE_OFFSET(index));
318 gen9_vme_avc_output_vme_batchbuffer_setup(VADriverContextP ctx,
319 struct encode_state *encode_state,
321 struct intel_encoder_context *encoder_context)
323 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
324 int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
325 int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
327 gen9_vme_output_vme_batchbuffer_setup(ctx, encode_state, index, encoder_context, width_in_mbs, height_in_mbs);
332 gen9_vme_surface_setup(VADriverContextP ctx,
333 struct encode_state *encode_state,
335 struct intel_encoder_context *encoder_context)
337 struct object_surface *obj_surface;
339 /*Setup surfaces state*/
340 /* current picture for encoding */
341 obj_surface = encode_state->input_yuv_object;
343 gen9_vme_source_surface_state(ctx, 0, obj_surface, encoder_context);
344 gen9_vme_media_source_surface_state(ctx, 4, obj_surface, encoder_context);
345 gen9_vme_media_chroma_source_surface_state(ctx, 6, obj_surface, encoder_context);
348 VAEncSliceParameterBufferH264 *slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
351 slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type);
352 assert(slice_type != SLICE_TYPE_I && slice_type != SLICE_TYPE_SI);
354 intel_avc_vme_reference_state(ctx, encode_state, encoder_context, 0, 1, gen9_vme_source_surface_state);
356 if (slice_type == SLICE_TYPE_B)
357 intel_avc_vme_reference_state(ctx, encode_state, encoder_context, 1, 2, gen9_vme_source_surface_state);
361 gen9_vme_avc_output_buffer_setup(ctx, encode_state, 3, encoder_context);
362 gen9_vme_avc_output_vme_batchbuffer_setup(ctx, encode_state, 5, encoder_context);
363 intel_h264_setup_cost_surface(ctx, encode_state, encoder_context,
364 BINDING_TABLE_OFFSET(INTEL_COST_TABLE_OFFSET),
365 SURFACE_STATE_OFFSET(INTEL_COST_TABLE_OFFSET));
367 return VA_STATUS_SUCCESS;
370 static VAStatus gen9_vme_interface_setup(VADriverContextP ctx,
371 struct encode_state *encode_state,
372 struct intel_encoder_context *encoder_context)
374 struct gen6_vme_context *vme_context = encoder_context->vme_context;
375 struct gen8_interface_descriptor_data *desc;
378 unsigned char *desc_ptr;
380 bo = vme_context->gpe_context.idrt.bo;
383 desc_ptr = (unsigned char *)bo->virtual + vme_context->gpe_context.idrt.offset;
385 desc = (struct gen8_interface_descriptor_data *)desc_ptr;
387 for (i = 0; i < vme_context->vme_kernel_sum; i++) {
388 struct i965_kernel *kernel;
389 kernel = &vme_context->gpe_context.kernels[i];
390 assert(sizeof(*desc) == 32);
391 /*Setup the descritor table*/
392 memset(desc, 0, sizeof(*desc));
393 desc->desc0.kernel_start_pointer = kernel->kernel_offset >> 6;
394 desc->desc3.sampler_count = 0; /* FIXME: */
395 desc->desc3.sampler_state_pointer = 0;
396 desc->desc4.binding_table_entry_count = 1; /* FIXME: */
397 desc->desc4.binding_table_pointer = (BINDING_TABLE_OFFSET(0) >> 5);
398 desc->desc5.constant_urb_entry_read_offset = 0;
399 desc->desc5.constant_urb_entry_read_length = CURBE_URB_ENTRY_LENGTH;
406 return VA_STATUS_SUCCESS;
409 static VAStatus gen9_vme_constant_setup(VADriverContextP ctx,
410 struct encode_state *encode_state,
411 struct intel_encoder_context *encoder_context,
414 struct gen6_vme_context *vme_context = encoder_context->vme_context;
415 unsigned char *constant_buffer;
416 unsigned int *vme_state_message;
419 vme_state_message = (unsigned int *)vme_context->vme_state_message;
421 if (encoder_context->codec == CODEC_H264 ||
422 encoder_context->codec == CODEC_H264_MVC) {
423 if (vme_context->h264_level >= 30) {
426 if (vme_context->h264_level >= 31)
429 } else if (encoder_context->codec == CODEC_MPEG2) {
431 } else if (encoder_context->codec == CODEC_HEVC) {
432 if (vme_context->hevc_level >= 30 * 3) {
435 if (vme_context->hevc_level >= 31 * 3)
437 }/* use the avc level setting */
440 vme_state_message[31] = mv_num;
442 dri_bo_map(vme_context->gpe_context.curbe.bo, 1);
443 assert(vme_context->gpe_context.curbe.bo->virtual);
444 constant_buffer = (unsigned char *)vme_context->gpe_context.curbe.bo->virtual +
445 vme_context->gpe_context.curbe.offset;
447 /* VME MV/Mb cost table is passed by using const buffer */
448 /* Now it uses the fixed search path. So it is constructed directly
451 memcpy(constant_buffer, (char *)vme_context->vme_state_message, 128);
453 dri_bo_unmap(vme_context->gpe_context.curbe.bo);
455 return VA_STATUS_SUCCESS;
458 #define MB_SCOREBOARD_A (1 << 0)
459 #define MB_SCOREBOARD_B (1 << 1)
460 #define MB_SCOREBOARD_C (1 << 2)
462 /* check whether the mb of (x_index, y_index) is out of bound */
463 static inline int loop_in_bounds(int x_index, int y_index, int first_mb, int num_mb, int mb_width, int mb_height)
466 if (x_index < 0 || x_index >= mb_width)
468 if (y_index < 0 || y_index >= mb_height)
471 mb_index = y_index * mb_width + x_index;
472 if (mb_index < first_mb || mb_index > (first_mb + num_mb))
478 gen9wa_vme_walker_fill_vme_batchbuffer(VADriverContextP ctx,
479 struct encode_state *encode_state,
480 int mb_width, int mb_height,
482 int transform_8x8_mode_flag,
483 struct intel_encoder_context *encoder_context)
485 struct gen6_vme_context *vme_context = encoder_context->vme_context;
488 unsigned int *command_ptr;
490 #define USE_SCOREBOARD (1 << 21)
492 dri_bo_map(vme_context->vme_batchbuffer.bo, 1);
493 command_ptr = vme_context->vme_batchbuffer.bo->virtual;
495 for (s = 0; s < encode_state->num_slice_params_ext; s++) {
496 VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[s]->buffer;
497 int first_mb = pSliceParameter->macroblock_address;
498 int num_mb = pSliceParameter->num_macroblocks;
499 unsigned int mb_intra_ub, score_dep;
500 int x_outer, y_outer, x_inner, y_inner;
503 x_outer = first_mb % mb_width;
504 y_outer = first_mb / mb_width;
507 for (; x_outer < (mb_width - 2) && !loop_in_bounds(x_outer, y_outer, first_mb, num_mb, mb_width, mb_height);) {
510 for (; !loop_in_bounds(x_inner, y_inner, first_mb, num_mb, mb_width, mb_height);) {
514 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_AE;
515 score_dep |= MB_SCOREBOARD_A;
517 if (y_inner != mb_row) {
518 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_B;
519 score_dep |= MB_SCOREBOARD_B;
521 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_D;
522 if (x_inner != (mb_width - 1)) {
523 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C;
524 score_dep |= MB_SCOREBOARD_C;
528 *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2));
529 *command_ptr++ = kernel;
530 *command_ptr++ = USE_SCOREBOARD;
533 /* the (X, Y) term of scoreboard */
534 *command_ptr++ = ((y_inner << 16) | x_inner);
535 *command_ptr++ = score_dep;
537 *command_ptr++ = (mb_width << 16 | y_inner << 8 | x_inner);
538 *command_ptr++ = ((1 << 18) | (1 << 16) | transform_8x8_mode_flag | (mb_intra_ub << 8));
539 *command_ptr++ = CMD_MEDIA_STATE_FLUSH;
548 xtemp_outer = mb_width - 2;
551 x_outer = xtemp_outer;
552 y_outer = first_mb / mb_width;
553 for (; !loop_in_bounds(x_outer, y_outer, first_mb, num_mb, mb_width, mb_height);) {
556 for (; !loop_in_bounds(x_inner, y_inner, first_mb, num_mb, mb_width, mb_height);) {
560 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_AE;
561 score_dep |= MB_SCOREBOARD_A;
563 if (y_inner != mb_row) {
564 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_B;
565 score_dep |= MB_SCOREBOARD_B;
567 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_D;
569 if (x_inner != (mb_width - 1)) {
570 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C;
571 score_dep |= MB_SCOREBOARD_C;
575 *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2));
576 *command_ptr++ = kernel;
577 *command_ptr++ = USE_SCOREBOARD;
580 /* the (X, Y) term of scoreboard */
581 *command_ptr++ = ((y_inner << 16) | x_inner);
582 *command_ptr++ = score_dep;
584 *command_ptr++ = (mb_width << 16 | y_inner << 8 | x_inner);
585 *command_ptr++ = ((1 << 18) | (1 << 16) | transform_8x8_mode_flag | (mb_intra_ub << 8));
587 *command_ptr++ = CMD_MEDIA_STATE_FLUSH;
593 if (x_outer >= mb_width) {
595 x_outer = xtemp_outer;
600 *command_ptr++ = MI_BATCH_BUFFER_END;
603 dri_bo_unmap(vme_context->vme_batchbuffer.bo);
607 gen9_vme_fill_vme_batchbuffer(VADriverContextP ctx,
608 struct encode_state *encode_state,
609 int mb_width, int mb_height,
611 int transform_8x8_mode_flag,
612 struct intel_encoder_context *encoder_context)
614 struct gen6_vme_context *vme_context = encoder_context->vme_context;
615 int mb_x = 0, mb_y = 0;
617 unsigned int *command_ptr;
618 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
619 VAEncPictureParameterBufferH264 *pic_param = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
620 VAEncSliceParameterBufferH264 *slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
622 int slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type);
625 if (encoder_context->rate_control_mode == VA_RC_CQP)
626 qp = pic_param->pic_init_qp + slice_param->slice_qp_delta;
628 qp = mfc_context->brc.qp_prime_y[encoder_context->layer.curr_frame_layer_id][slice_type];
630 dri_bo_map(vme_context->vme_batchbuffer.bo, 1);
631 command_ptr = vme_context->vme_batchbuffer.bo->virtual;
633 for (s = 0; s < encode_state->num_slice_params_ext; s++) {
634 VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[s]->buffer;
635 int slice_mb_begin = pSliceParameter->macroblock_address;
636 int slice_mb_number = pSliceParameter->num_macroblocks;
637 unsigned int mb_intra_ub;
638 int slice_mb_x = pSliceParameter->macroblock_address % mb_width;
639 for (i = 0; i < slice_mb_number;) {
640 int mb_count = i + slice_mb_begin;
641 mb_x = mb_count % mb_width;
642 mb_y = mb_count / mb_width;
645 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_AE;
648 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_B;
650 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_D;
651 if (mb_x != (mb_width - 1))
652 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C;
656 mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_AE);
657 mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_BCD_MASK);
658 if ((i == (mb_width - 1)) && slice_mb_x) {
659 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C;
663 if ((i == mb_width) && slice_mb_x) {
664 mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_D);
666 *command_ptr++ = (CMD_MEDIA_OBJECT | (9 - 2));
667 *command_ptr++ = kernel;
674 *command_ptr++ = (mb_width << 16 | mb_y << 8 | mb_x);
675 *command_ptr++ = ((encoder_context->quality_level << 24) | (1 << 16) | transform_8x8_mode_flag | (mb_intra_ub << 8));
676 /* qp occupies one byte */
677 if (vme_context->roi_enabled) {
678 qp_index = mb_y * mb_width + mb_x;
679 qp_mb = *(vme_context->qp_per_mb + qp_index);
682 *command_ptr++ = qp_mb;
684 *command_ptr++ = CMD_MEDIA_STATE_FLUSH;
690 *command_ptr++ = MI_BATCH_BUFFER_END;
693 dri_bo_unmap(vme_context->vme_batchbuffer.bo);
696 static void gen9_vme_media_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
698 struct gen6_vme_context *vme_context = encoder_context->vme_context;
700 gen8_gpe_context_init(ctx, &vme_context->gpe_context);
702 /* VME output buffer */
703 dri_bo_unreference(vme_context->vme_output.bo);
704 vme_context->vme_output.bo = NULL;
706 dri_bo_unreference(vme_context->vme_batchbuffer.bo);
707 vme_context->vme_batchbuffer.bo = NULL;
710 dri_bo_unreference(vme_context->vme_state.bo);
711 vme_context->vme_state.bo = NULL;
714 static void gen9_vme_pipeline_programing(VADriverContextP ctx,
715 struct encode_state *encode_state,
716 struct intel_encoder_context *encoder_context)
718 struct gen6_vme_context *vme_context = encoder_context->vme_context;
719 struct intel_batchbuffer *batch = encoder_context->base.batch;
720 VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
721 VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
722 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
723 int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
724 int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
726 bool allow_hwscore = true;
728 unsigned int is_low_quality = (encoder_context->quality_level == ENCODER_LOW_QUALITY);
731 allow_hwscore = false;
733 for (s = 0; s < encode_state->num_slice_params_ext; s++) {
734 pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[s]->buffer;
735 if ((pSliceParameter->macroblock_address % width_in_mbs)) {
736 allow_hwscore = false;
742 if ((pSliceParameter->slice_type == SLICE_TYPE_I) ||
743 (pSliceParameter->slice_type == SLICE_TYPE_SI)) {
744 kernel_shader = VME_INTRA_SHADER;
745 } else if ((pSliceParameter->slice_type == SLICE_TYPE_P) ||
746 (pSliceParameter->slice_type == SLICE_TYPE_SP)) {
747 kernel_shader = VME_INTER_SHADER;
749 kernel_shader = VME_BINTER_SHADER;
751 kernel_shader = VME_INTER_SHADER;
754 gen9wa_vme_walker_fill_vme_batchbuffer(ctx,
756 width_in_mbs, height_in_mbs,
758 pPicParameter->pic_fields.bits.transform_8x8_mode_flag,
761 gen9_vme_fill_vme_batchbuffer(ctx,
763 width_in_mbs, height_in_mbs,
765 pPicParameter->pic_fields.bits.transform_8x8_mode_flag,
768 intel_batchbuffer_start_atomic(batch, 0x1000);
769 gen9_gpe_pipeline_setup(ctx, &vme_context->gpe_context, batch);
770 BEGIN_BATCH(batch, 3);
771 OUT_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8) | (1 << 0));
773 vme_context->vme_batchbuffer.bo,
774 I915_GEM_DOMAIN_COMMAND, 0,
776 ADVANCE_BATCH(batch);
778 gen9_gpe_pipeline_end(ctx, &vme_context->gpe_context, batch);
780 intel_batchbuffer_end_atomic(batch);
783 static VAStatus gen9_vme_prepare(VADriverContextP ctx,
784 struct encode_state *encode_state,
785 struct intel_encoder_context *encoder_context)
787 VAStatus vaStatus = VA_STATUS_SUCCESS;
788 VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
789 int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
790 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
791 struct gen6_vme_context *vme_context = encoder_context->vme_context;
793 if (!vme_context->h264_level ||
794 (vme_context->h264_level != pSequenceParameter->level_idc)) {
795 vme_context->h264_level = pSequenceParameter->level_idc;
798 intel_vme_update_mbmv_cost(ctx, encode_state, encoder_context);
799 intel_h264_initialize_mbmv_cost(ctx, encode_state, encoder_context);
800 intel_h264_enc_roi_config(ctx, encode_state, encoder_context);
802 /*Setup all the memory object*/
803 gen9_vme_surface_setup(ctx, encode_state, is_intra, encoder_context);
804 gen9_vme_interface_setup(ctx, encode_state, encoder_context);
805 //gen9_vme_vme_state_setup(ctx, encode_state, is_intra, encoder_context);
806 gen9_vme_constant_setup(ctx, encode_state, encoder_context, (pSliceParameter->slice_type == SLICE_TYPE_B) ? 2 : 1);
808 /*Programing media pipeline*/
809 gen9_vme_pipeline_programing(ctx, encode_state, encoder_context);
814 static VAStatus gen9_vme_run(VADriverContextP ctx,
815 struct encode_state *encode_state,
816 struct intel_encoder_context *encoder_context)
818 struct intel_batchbuffer *batch = encoder_context->base.batch;
820 intel_batchbuffer_flush(batch);
822 return VA_STATUS_SUCCESS;
825 static VAStatus gen9_vme_stop(VADriverContextP ctx,
826 struct encode_state *encode_state,
827 struct intel_encoder_context *encoder_context)
829 return VA_STATUS_SUCCESS;
833 gen9_vme_pipeline(VADriverContextP ctx,
835 struct encode_state *encode_state,
836 struct intel_encoder_context *encoder_context)
838 gen9_vme_media_init(ctx, encoder_context);
839 gen9_vme_prepare(ctx, encode_state, encoder_context);
840 gen9_vme_run(ctx, encode_state, encoder_context);
841 gen9_vme_stop(ctx, encode_state, encoder_context);
843 return VA_STATUS_SUCCESS;
847 gen9_vme_mpeg2_output_buffer_setup(VADriverContextP ctx,
848 struct encode_state *encode_state,
851 struct intel_encoder_context *encoder_context)
854 VAEncSequenceParameterBufferMPEG2 *seq_param = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer;
855 int width_in_mbs = ALIGN(seq_param->picture_width, 16) / 16;
856 int height_in_mbs = ALIGN(seq_param->picture_height, 16) / 16;
858 gen9_vme_output_buffer_setup(ctx, encode_state, index, encoder_context, is_intra, width_in_mbs, height_in_mbs);
862 gen9_vme_mpeg2_output_vme_batchbuffer_setup(VADriverContextP ctx,
863 struct encode_state *encode_state,
865 struct intel_encoder_context *encoder_context)
868 VAEncSequenceParameterBufferMPEG2 *seq_param = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer;
869 int width_in_mbs = ALIGN(seq_param->picture_width, 16) / 16;
870 int height_in_mbs = ALIGN(seq_param->picture_height, 16) / 16;
872 gen9_vme_output_vme_batchbuffer_setup(ctx, encode_state, index, encoder_context, width_in_mbs, height_in_mbs);
876 gen9_vme_mpeg2_surface_setup(VADriverContextP ctx,
877 struct encode_state *encode_state,
879 struct intel_encoder_context *encoder_context)
881 struct object_surface *obj_surface;
883 /*Setup surfaces state*/
884 /* current picture for encoding */
885 obj_surface = encode_state->input_yuv_object;
886 gen9_vme_source_surface_state(ctx, 0, obj_surface, encoder_context);
887 gen9_vme_media_source_surface_state(ctx, 4, obj_surface, encoder_context);
888 gen9_vme_media_chroma_source_surface_state(ctx, 6, obj_surface, encoder_context);
892 obj_surface = encode_state->reference_objects[0];
894 if (obj_surface->bo != NULL)
895 gen9_vme_source_surface_state(ctx, 1, obj_surface, encoder_context);
898 obj_surface = encode_state->reference_objects[1];
900 if (obj_surface && obj_surface->bo != NULL)
901 gen9_vme_source_surface_state(ctx, 2, obj_surface, encoder_context);
905 gen9_vme_mpeg2_output_buffer_setup(ctx, encode_state, 3, is_intra, encoder_context);
906 gen9_vme_mpeg2_output_vme_batchbuffer_setup(ctx, encode_state, 5, encoder_context);
908 return VA_STATUS_SUCCESS;
912 gen9wa_vme_mpeg2_walker_fill_vme_batchbuffer(VADriverContextP ctx,
913 struct encode_state *encode_state,
914 int mb_width, int mb_height,
916 struct intel_encoder_context *encoder_context)
918 struct gen6_vme_context *vme_context = encoder_context->vme_context;
919 unsigned int *command_ptr;
921 #define MPEG2_SCOREBOARD (1 << 21)
923 dri_bo_map(vme_context->vme_batchbuffer.bo, 1);
924 command_ptr = vme_context->vme_batchbuffer.bo->virtual;
927 unsigned int mb_intra_ub, score_dep;
928 int x_outer, y_outer, x_inner, y_inner;
931 int num_mb = mb_width * mb_height;
936 for (; x_outer < (mb_width - 2) && !loop_in_bounds(x_outer, y_outer, first_mb, num_mb, mb_width, mb_height);) {
939 for (; !loop_in_bounds(x_inner, y_inner, first_mb, num_mb, mb_width, mb_height);) {
943 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_AE;
944 score_dep |= MB_SCOREBOARD_A;
947 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_B;
948 score_dep |= MB_SCOREBOARD_B;
951 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_D;
953 if (x_inner != (mb_width - 1)) {
954 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C;
955 score_dep |= MB_SCOREBOARD_C;
959 *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2));
960 *command_ptr++ = kernel;
961 *command_ptr++ = MPEG2_SCOREBOARD;
964 /* the (X, Y) term of scoreboard */
965 *command_ptr++ = ((y_inner << 16) | x_inner);
966 *command_ptr++ = score_dep;
968 *command_ptr++ = (mb_width << 16 | y_inner << 8 | x_inner);
969 *command_ptr++ = ((1 << 18) | (1 << 16) | (mb_intra_ub << 8));
970 *command_ptr++ = CMD_MEDIA_STATE_FLUSH;
979 xtemp_outer = mb_width - 2;
982 x_outer = xtemp_outer;
984 for (; !loop_in_bounds(x_outer, y_outer, first_mb, num_mb, mb_width, mb_height);) {
987 for (; !loop_in_bounds(x_inner, y_inner, first_mb, num_mb, mb_width, mb_height);) {
991 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_AE;
992 score_dep |= MB_SCOREBOARD_A;
995 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_B;
996 score_dep |= MB_SCOREBOARD_B;
999 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_D;
1001 if (x_inner != (mb_width - 1)) {
1002 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C;
1003 score_dep |= MB_SCOREBOARD_C;
1007 *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2));
1008 *command_ptr++ = kernel;
1009 *command_ptr++ = MPEG2_SCOREBOARD;
1012 /* the (X, Y) term of scoreboard */
1013 *command_ptr++ = ((y_inner << 16) | x_inner);
1014 *command_ptr++ = score_dep;
1016 *command_ptr++ = (mb_width << 16 | y_inner << 8 | x_inner);
1017 *command_ptr++ = ((1 << 18) | (1 << 16) | (mb_intra_ub << 8));
1019 *command_ptr++ = CMD_MEDIA_STATE_FLUSH;
1025 if (x_outer >= mb_width) {
1027 x_outer = xtemp_outer;
1032 *command_ptr++ = MI_BATCH_BUFFER_END;
1035 dri_bo_unmap(vme_context->vme_batchbuffer.bo);
1040 gen9_vme_mpeg2_fill_vme_batchbuffer(VADriverContextP ctx,
1041 struct encode_state *encode_state,
1042 int mb_width, int mb_height,
1044 int transform_8x8_mode_flag,
1045 struct intel_encoder_context *encoder_context)
1047 struct gen6_vme_context *vme_context = encoder_context->vme_context;
1048 int mb_x = 0, mb_y = 0;
1050 unsigned int *command_ptr;
1053 dri_bo_map(vme_context->vme_batchbuffer.bo, 1);
1054 command_ptr = vme_context->vme_batchbuffer.bo->virtual;
1056 for (s = 0; s < encode_state->num_slice_params_ext; s++) {
1057 VAEncSliceParameterBufferMPEG2 *slice_param = (VAEncSliceParameterBufferMPEG2 *)encode_state->slice_params_ext[s]->buffer;
1059 for (j = 0; j < encode_state->slice_params_ext[s]->num_elements; j++) {
1060 int slice_mb_begin = slice_param->macroblock_address;
1061 int slice_mb_number = slice_param->num_macroblocks;
1062 unsigned int mb_intra_ub;
1064 for (i = 0; i < slice_mb_number;) {
1065 int mb_count = i + slice_mb_begin;
1067 mb_x = mb_count % mb_width;
1068 mb_y = mb_count / mb_width;
1072 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_AE;
1076 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_B;
1079 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_D;
1081 if (mb_x != (mb_width - 1))
1082 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C;
1085 *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2));
1086 *command_ptr++ = kernel;
1093 *command_ptr++ = (mb_width << 16 | mb_y << 8 | mb_x);
1094 *command_ptr++ = ((1 << 16) | transform_8x8_mode_flag | (mb_intra_ub << 8));
1096 *command_ptr++ = CMD_MEDIA_STATE_FLUSH;
1105 *command_ptr++ = MI_BATCH_BUFFER_END;
1108 dri_bo_unmap(vme_context->vme_batchbuffer.bo);
1112 gen9_vme_mpeg2_pipeline_programing(VADriverContextP ctx,
1113 struct encode_state *encode_state,
1115 struct intel_encoder_context *encoder_context)
1117 struct gen6_vme_context *vme_context = encoder_context->vme_context;
1118 struct intel_batchbuffer *batch = encoder_context->base.batch;
1119 VAEncSequenceParameterBufferMPEG2 *seq_param = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer;
1120 int width_in_mbs = ALIGN(seq_param->picture_width, 16) / 16;
1121 int height_in_mbs = ALIGN(seq_param->picture_height, 16) / 16;
1122 bool allow_hwscore = true;
1125 VAEncPictureParameterBufferMPEG2 *pic_param = NULL;
1127 for (s = 0; s < encode_state->num_slice_params_ext; s++) {
1129 VAEncSliceParameterBufferMPEG2 *slice_param = (VAEncSliceParameterBufferMPEG2 *)encode_state->slice_params_ext[s]->buffer;
1131 for (j = 0; j < encode_state->slice_params_ext[s]->num_elements; j++) {
1132 if (slice_param->macroblock_address % width_in_mbs) {
1133 allow_hwscore = false;
1139 pic_param = (VAEncPictureParameterBufferMPEG2 *)encode_state->pic_param_ext->buffer;
1140 if (pic_param->picture_type == VAEncPictureTypeIntra) {
1141 allow_hwscore = false;
1142 kernel_shader = VME_INTRA_SHADER;
1144 kernel_shader = VME_INTER_SHADER;
1148 gen9wa_vme_mpeg2_walker_fill_vme_batchbuffer(ctx,
1150 width_in_mbs, height_in_mbs,
1154 gen9_vme_mpeg2_fill_vme_batchbuffer(ctx,
1156 width_in_mbs, height_in_mbs,
1157 is_intra ? VME_INTRA_SHADER : VME_INTER_SHADER,
1161 intel_batchbuffer_start_atomic(batch, 0x1000);
1162 gen9_gpe_pipeline_setup(ctx, &vme_context->gpe_context, batch);
1163 BEGIN_BATCH(batch, 4);
1164 OUT_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8) | (1 << 0));
1166 vme_context->vme_batchbuffer.bo,
1167 I915_GEM_DOMAIN_COMMAND, 0,
1169 OUT_BATCH(batch, 0);
1170 ADVANCE_BATCH(batch);
1172 gen9_gpe_pipeline_end(ctx, &vme_context->gpe_context, batch);
1174 intel_batchbuffer_end_atomic(batch);
1178 gen9_vme_mpeg2_prepare(VADriverContextP ctx,
1179 struct encode_state *encode_state,
1180 struct intel_encoder_context *encoder_context)
1182 VAStatus vaStatus = VA_STATUS_SUCCESS;
1183 VAEncSliceParameterBufferMPEG2 *slice_param = (VAEncSliceParameterBufferMPEG2 *)encode_state->slice_params_ext[0]->buffer;
1184 VAEncSequenceParameterBufferMPEG2 *seq_param = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer;
1185 struct gen6_vme_context *vme_context = encoder_context->vme_context;
1187 if ((!vme_context->mpeg2_level) ||
1188 (vme_context->mpeg2_level != (seq_param->sequence_extension.bits.profile_and_level_indication & MPEG2_LEVEL_MASK))) {
1189 vme_context->mpeg2_level = seq_param->sequence_extension.bits.profile_and_level_indication & MPEG2_LEVEL_MASK;
1192 /*Setup all the memory object*/
1193 gen9_vme_mpeg2_surface_setup(ctx, encode_state, slice_param->is_intra_slice, encoder_context);
1194 gen9_vme_interface_setup(ctx, encode_state, encoder_context);
1195 //gen9_vme_vme_state_setup(ctx, encode_state, slice_param->is_intra_slice, encoder_context);
1196 intel_vme_mpeg2_state_setup(ctx, encode_state, encoder_context);
1197 gen9_vme_constant_setup(ctx, encode_state, encoder_context, 1);
1199 /*Programing media pipeline*/
1200 gen9_vme_mpeg2_pipeline_programing(ctx, encode_state, slice_param->is_intra_slice, encoder_context);
1206 gen9_vme_mpeg2_pipeline(VADriverContextP ctx,
1208 struct encode_state *encode_state,
1209 struct intel_encoder_context *encoder_context)
1211 gen9_vme_media_init(ctx, encoder_context);
1212 gen9_vme_mpeg2_prepare(ctx, encode_state, encoder_context);
1213 gen9_vme_run(ctx, encode_state, encoder_context);
1214 gen9_vme_stop(ctx, encode_state, encoder_context);
1216 return VA_STATUS_SUCCESS;
1220 gen9_vme_vp8_output_buffer_setup(VADriverContextP ctx,
1221 struct encode_state *encode_state,
1224 struct intel_encoder_context *encoder_context)
1226 VAEncSequenceParameterBufferVP8 *seq_param = (VAEncSequenceParameterBufferVP8 *)encode_state->seq_param_ext->buffer;
1227 int width_in_mbs = ALIGN(seq_param->frame_width, 16) / 16;
1228 int height_in_mbs = ALIGN(seq_param->frame_height, 16) / 16;
1230 gen9_vme_output_buffer_setup(ctx, encode_state, index, encoder_context, is_intra, width_in_mbs, height_in_mbs);
1234 gen9_vme_vp8_output_vme_batchbuffer_setup(VADriverContextP ctx,
1235 struct encode_state *encode_state,
1237 struct intel_encoder_context *encoder_context)
1239 VAEncSequenceParameterBufferVP8 *seq_param = (VAEncSequenceParameterBufferVP8 *)encode_state->seq_param_ext->buffer;
1240 int width_in_mbs = ALIGN(seq_param->frame_width, 16) / 16;
1241 int height_in_mbs = ALIGN(seq_param->frame_height, 16) / 16;
1243 gen9_vme_output_vme_batchbuffer_setup(ctx, encode_state, index, encoder_context, width_in_mbs, height_in_mbs);
1247 gen9_vme_vp8_surface_setup(VADriverContextP ctx,
1248 struct encode_state *encode_state,
1250 struct intel_encoder_context *encoder_context)
1252 struct object_surface *obj_surface;
1254 /*Setup surfaces state*/
1255 /* current picture for encoding */
1256 obj_surface = encode_state->input_yuv_object;
1257 gen9_vme_source_surface_state(ctx, 0, obj_surface, encoder_context);
1258 gen9_vme_media_source_surface_state(ctx, 4, obj_surface, encoder_context);
1259 gen9_vme_media_chroma_source_surface_state(ctx, 6, obj_surface, encoder_context);
1263 obj_surface = encode_state->reference_objects[0];
1265 if (obj_surface->bo != NULL)
1266 gen9_vme_source_surface_state(ctx, 1, obj_surface, encoder_context);
1269 obj_surface = encode_state->reference_objects[1];
1271 if (obj_surface && obj_surface->bo != NULL)
1272 gen9_vme_source_surface_state(ctx, 2, obj_surface, encoder_context);
1276 gen9_vme_vp8_output_buffer_setup(ctx, encode_state, 3, is_intra, encoder_context);
1277 gen9_vme_vp8_output_vme_batchbuffer_setup(ctx, encode_state, 5, encoder_context);
1279 return VA_STATUS_SUCCESS;
1283 gen9_vme_vp8_pipeline_programing(VADriverContextP ctx,
1284 struct encode_state *encode_state,
1286 struct intel_encoder_context *encoder_context)
1288 struct gen6_vme_context *vme_context = encoder_context->vme_context;
1289 struct intel_batchbuffer *batch = encoder_context->base.batch;
1290 VAEncSequenceParameterBufferVP8 *seq_param = (VAEncSequenceParameterBufferVP8 *)encode_state->seq_param_ext->buffer;
1291 int width_in_mbs = ALIGN(seq_param->frame_width, 16) / 16;
1292 int height_in_mbs = ALIGN(seq_param->frame_height, 16) / 16;
1293 int kernel_shader = (is_intra ? VME_INTRA_SHADER : VME_INTER_SHADER);
1295 gen9wa_vme_mpeg2_walker_fill_vme_batchbuffer(ctx,
1297 width_in_mbs, height_in_mbs,
1301 intel_batchbuffer_start_atomic(batch, 0x1000);
1302 gen9_gpe_pipeline_setup(ctx, &vme_context->gpe_context, batch);
1303 BEGIN_BATCH(batch, 4);
1304 OUT_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8) | (1 << 0));
1306 vme_context->vme_batchbuffer.bo,
1307 I915_GEM_DOMAIN_COMMAND, 0,
1309 OUT_BATCH(batch, 0);
1310 ADVANCE_BATCH(batch);
1312 gen9_gpe_pipeline_end(ctx, &vme_context->gpe_context, batch);
1314 intel_batchbuffer_end_atomic(batch);
1317 static VAStatus gen9_vme_vp8_prepare(VADriverContextP ctx,
1318 struct encode_state *encode_state,
1319 struct intel_encoder_context *encoder_context)
1321 VAStatus vaStatus = VA_STATUS_SUCCESS;
1322 VAEncPictureParameterBufferVP8 *pPicParameter = (VAEncPictureParameterBufferVP8 *)encode_state->pic_param_ext->buffer;
1323 int is_intra = !pPicParameter->pic_flags.bits.frame_type;
1325 /* update vp8 mbmv cost */
1326 intel_vme_vp8_update_mbmv_cost(ctx, encode_state, encoder_context);
1328 /*Setup all the memory object*/
1329 gen9_vme_vp8_surface_setup(ctx, encode_state, is_intra, encoder_context);
1330 gen9_vme_interface_setup(ctx, encode_state, encoder_context);
1331 gen9_vme_constant_setup(ctx, encode_state, encoder_context, 1);
1333 /*Programing media pipeline*/
1334 gen9_vme_vp8_pipeline_programing(ctx, encode_state, is_intra, encoder_context);
1340 gen9_vme_vp8_pipeline(VADriverContextP ctx,
1342 struct encode_state *encode_state,
1343 struct intel_encoder_context *encoder_context)
1345 gen9_vme_media_init(ctx, encoder_context);
1346 gen9_vme_vp8_prepare(ctx, encode_state, encoder_context);
1347 gen9_vme_run(ctx, encode_state, encoder_context);
1348 gen9_vme_stop(ctx, encode_state, encoder_context);
1350 return VA_STATUS_SUCCESS;
1356 gen9_vme_hevc_output_buffer_setup(VADriverContextP ctx,
1357 struct encode_state *encode_state,
1359 struct intel_encoder_context *encoder_context)
1362 struct i965_driver_data *i965 = i965_driver_data(ctx);
1363 struct gen6_vme_context *vme_context = encoder_context->vme_context;
1364 VAEncSequenceParameterBufferHEVC *pSequenceParameter = (VAEncSequenceParameterBufferHEVC *)encode_state->seq_param_ext->buffer;
1365 VAEncSliceParameterBufferHEVC *pSliceParameter = (VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[0]->buffer;
1366 int is_intra = pSliceParameter->slice_type == HEVC_SLICE_I;
1367 int width_in_mbs = (pSequenceParameter->pic_width_in_luma_samples + 15) / 16;
1368 int height_in_mbs = (pSequenceParameter->pic_height_in_luma_samples + 15) / 16;
1371 vme_context->vme_output.num_blocks = width_in_mbs * height_in_mbs;
1372 vme_context->vme_output.pitch = 16; /* in bytes, always 16 */
1375 vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES * 2;
1377 vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES * 24;
1379 * Inter MV . 32-byte Intra search + 16 IME info + 128 IME MV + 32 IME Ref
1380 * + 16 FBR Info + 128 FBR MV + 32 FBR Ref.
1381 * 16 * (2 + 2 * (1 + 8 + 2))= 16 * 24.
1384 vme_context->vme_output.bo = dri_bo_alloc(i965->intel.bufmgr,
1385 "VME output buffer",
1386 vme_context->vme_output.num_blocks * vme_context->vme_output.size_block,
1388 assert(vme_context->vme_output.bo);
1389 vme_context->vme_buffer_suface_setup(ctx,
1390 &vme_context->gpe_context,
1391 &vme_context->vme_output,
1392 BINDING_TABLE_OFFSET(index),
1393 SURFACE_STATE_OFFSET(index));
1397 gen9_vme_hevc_output_vme_batchbuffer_setup(VADriverContextP ctx,
1398 struct encode_state *encode_state,
1400 struct intel_encoder_context *encoder_context)
1403 struct i965_driver_data *i965 = i965_driver_data(ctx);
1404 struct gen6_vme_context *vme_context = encoder_context->vme_context;
1405 VAEncSequenceParameterBufferHEVC *pSequenceParameter = (VAEncSequenceParameterBufferHEVC *)encode_state->seq_param_ext->buffer;
1406 int width_in_mbs = (pSequenceParameter->pic_width_in_luma_samples + 15) / 16;
1407 int height_in_mbs = (pSequenceParameter->pic_height_in_luma_samples + 15) / 16;
1409 vme_context->vme_batchbuffer.num_blocks = width_in_mbs * height_in_mbs + 1;
1410 vme_context->vme_batchbuffer.size_block = 64; /* 4 OWORDs */
1411 vme_context->vme_batchbuffer.pitch = 16;
1412 vme_context->vme_batchbuffer.bo = dri_bo_alloc(i965->intel.bufmgr,
1414 vme_context->vme_batchbuffer.num_blocks * vme_context->vme_batchbuffer.size_block,
1418 gen9_vme_hevc_surface_setup(VADriverContextP ctx,
1419 struct encode_state *encode_state,
1421 struct intel_encoder_context *encoder_context)
1423 struct object_surface *obj_surface;
1424 VAEncSequenceParameterBufferHEVC *pSequenceParameter = (VAEncSequenceParameterBufferHEVC *)encode_state->seq_param_ext->buffer;
1425 GenHevcSurface *hevc_encoder_surface = NULL;
1427 /*Setup surfaces state*/
1428 /* current picture for encoding */
1429 obj_surface = encode_state->input_yuv_object;
1431 if ((pSequenceParameter->seq_fields.bits.bit_depth_luma_minus8 > 0)
1432 || (pSequenceParameter->seq_fields.bits.bit_depth_chroma_minus8 > 0)) {
1433 hevc_encoder_surface = (GenHevcSurface *)encode_state->reconstructed_object->private_data;
1434 assert(hevc_encoder_surface);
1435 obj_surface = hevc_encoder_surface->nv12_surface_obj;
1437 gen9_vme_source_surface_state(ctx, 0, obj_surface, encoder_context);
1438 gen9_vme_media_source_surface_state(ctx, 4, obj_surface, encoder_context);
1439 gen9_vme_media_chroma_source_surface_state(ctx, 6, obj_surface, encoder_context);
1442 VAEncSliceParameterBufferHEVC *slice_param = (VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[0]->buffer;
1445 slice_type = slice_param->slice_type;
1446 assert(slice_type != HEVC_SLICE_I);
1449 intel_hevc_vme_reference_state(ctx, encode_state, encoder_context, 0, 1, gen9_vme_source_surface_state);
1451 if (slice_type == HEVC_SLICE_B)
1452 intel_hevc_vme_reference_state(ctx, encode_state, encoder_context, 1, 2, gen9_vme_source_surface_state);
1456 gen9_vme_hevc_output_buffer_setup(ctx, encode_state, 3, encoder_context);
1457 gen9_vme_hevc_output_vme_batchbuffer_setup(ctx, encode_state, 5, encoder_context);
1459 return VA_STATUS_SUCCESS;
1462 gen9wa_vme_hevc_walker_fill_vme_batchbuffer(VADriverContextP ctx,
1463 struct encode_state *encode_state,
1464 int mb_width, int mb_height,
1466 int transform_8x8_mode_flag,
1467 struct intel_encoder_context *encoder_context)
1469 struct gen6_vme_context *vme_context = encoder_context->vme_context;
1472 unsigned int *command_ptr;
1473 VAEncSequenceParameterBufferHEVC *pSequenceParameter = (VAEncSequenceParameterBufferHEVC *)encode_state->seq_param_ext->buffer;
1474 int log2_cu_size = pSequenceParameter->log2_min_luma_coding_block_size_minus3 + 3;
1475 int log2_ctb_size = pSequenceParameter->log2_diff_max_min_luma_coding_block_size + log2_cu_size;
1476 int ctb_size = 1 << log2_ctb_size;
1477 int num_mb_in_ctb = (ctb_size + 15) / 16;
1478 num_mb_in_ctb = num_mb_in_ctb * num_mb_in_ctb;
1480 #define USE_SCOREBOARD (1 << 21)
1482 dri_bo_map(vme_context->vme_batchbuffer.bo, 1);
1483 command_ptr = vme_context->vme_batchbuffer.bo->virtual;
1485 /*slice_segment_address must picture_width_in_ctb alainment */
1486 for (s = 0; s < encode_state->num_slice_params_ext; s++) {
1487 VAEncSliceParameterBufferHEVC *pSliceParameter = (VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[s]->buffer;
1488 int first_mb = pSliceParameter->slice_segment_address * num_mb_in_ctb;
1489 int num_mb = pSliceParameter->num_ctu_in_slice * num_mb_in_ctb;
1490 unsigned int mb_intra_ub, score_dep;
1491 int x_outer, y_outer, x_inner, y_inner;
1492 int xtemp_outer = 0;
1494 x_outer = first_mb % mb_width;
1495 y_outer = first_mb / mb_width;
1498 for (; x_outer < (mb_width - 2) && !loop_in_bounds(x_outer, y_outer, first_mb, num_mb, mb_width, mb_height);) {
1501 for (; !loop_in_bounds(x_inner, y_inner, first_mb, num_mb, mb_width, mb_height);) {
1505 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_AE;
1506 score_dep |= MB_SCOREBOARD_A;
1508 if (y_inner != mb_row) {
1509 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_B;
1510 score_dep |= MB_SCOREBOARD_B;
1512 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_D;
1513 if (x_inner != (mb_width - 1)) {
1514 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C;
1515 score_dep |= MB_SCOREBOARD_C;
1519 *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2));
1520 *command_ptr++ = kernel;
1521 *command_ptr++ = USE_SCOREBOARD;
1524 /* the (X, Y) term of scoreboard */
1525 *command_ptr++ = ((y_inner << 16) | x_inner);
1526 *command_ptr++ = score_dep;
1528 *command_ptr++ = (mb_width << 16 | y_inner << 8 | x_inner);
1529 *command_ptr++ = ((1 << 18) | (1 << 16) | transform_8x8_mode_flag | (mb_intra_ub << 8));
1530 *command_ptr++ = CMD_MEDIA_STATE_FLUSH;
1539 xtemp_outer = mb_width - 2;
1540 if (xtemp_outer < 0)
1542 x_outer = xtemp_outer;
1543 y_outer = first_mb / mb_width;
1544 for (; !loop_in_bounds(x_outer, y_outer, first_mb, num_mb, mb_width, mb_height);) {
1547 for (; !loop_in_bounds(x_inner, y_inner, first_mb, num_mb, mb_width, mb_height);) {
1551 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_AE;
1552 score_dep |= MB_SCOREBOARD_A;
1554 if (y_inner != mb_row) {
1555 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_B;
1556 score_dep |= MB_SCOREBOARD_B;
1558 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_D;
1560 if (x_inner != (mb_width - 1)) {
1561 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C;
1562 score_dep |= MB_SCOREBOARD_C;
1566 *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2));
1567 *command_ptr++ = kernel;
1568 *command_ptr++ = USE_SCOREBOARD;
1571 /* the (X, Y) term of scoreboard */
1572 *command_ptr++ = ((y_inner << 16) | x_inner);
1573 *command_ptr++ = score_dep;
1575 *command_ptr++ = (mb_width << 16 | y_inner << 8 | x_inner);
1576 *command_ptr++ = ((1 << 18) | (1 << 16) | transform_8x8_mode_flag | (mb_intra_ub << 8));
1578 *command_ptr++ = CMD_MEDIA_STATE_FLUSH;
1584 if (x_outer >= mb_width) {
1586 x_outer = xtemp_outer;
1591 *command_ptr++ = MI_BATCH_BUFFER_END;
1594 dri_bo_unmap(vme_context->vme_batchbuffer.bo);
1598 gen9_vme_hevc_fill_vme_batchbuffer(VADriverContextP ctx,
1599 struct encode_state *encode_state,
1600 int mb_width, int mb_height,
1602 int transform_8x8_mode_flag,
1603 struct intel_encoder_context *encoder_context)
1605 struct gen6_vme_context *vme_context = encoder_context->vme_context;
1606 int mb_x = 0, mb_y = 0;
1608 unsigned int *command_ptr;
1609 VAEncSequenceParameterBufferHEVC *pSequenceParameter = (VAEncSequenceParameterBufferHEVC *)encode_state->seq_param_ext->buffer;
1610 int log2_cu_size = pSequenceParameter->log2_min_luma_coding_block_size_minus3 + 3;
1611 int log2_ctb_size = pSequenceParameter->log2_diff_max_min_luma_coding_block_size + log2_cu_size;
1613 int ctb_size = 1 << log2_ctb_size;
1614 int num_mb_in_ctb = (ctb_size + 15) / 16;
1615 num_mb_in_ctb = num_mb_in_ctb * num_mb_in_ctb;
1617 dri_bo_map(vme_context->vme_batchbuffer.bo, 1);
1618 command_ptr = vme_context->vme_batchbuffer.bo->virtual;
1620 for (s = 0; s < encode_state->num_slice_params_ext; s++) {
1621 VAEncSliceParameterBufferHEVC *pSliceParameter = (VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[s]->buffer;
1622 int slice_mb_begin = pSliceParameter->slice_segment_address * num_mb_in_ctb;
1623 int slice_mb_number = pSliceParameter->num_ctu_in_slice * num_mb_in_ctb;
1625 unsigned int mb_intra_ub;
1626 int slice_mb_x = slice_mb_begin % mb_width;
1627 for (i = 0; i < slice_mb_number;) {
1628 int mb_count = i + slice_mb_begin;
1629 mb_x = mb_count % mb_width;
1630 mb_y = mb_count / mb_width;
1634 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_AE;
1637 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_B;
1639 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_D;
1640 if (mb_x != (mb_width - 1))
1641 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C;
1645 mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_AE);
1646 mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_BCD_MASK);
1647 if ((i == (mb_width - 1)) && slice_mb_x) {
1648 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C;
1652 if ((i == mb_width) && slice_mb_x) {
1653 mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_D);
1656 *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2));
1657 *command_ptr++ = kernel;
1664 *command_ptr++ = (mb_width << 16 | mb_y << 8 | mb_x);
1665 *command_ptr++ = ((1 << 16) | transform_8x8_mode_flag | (mb_intra_ub << 8));
1667 *command_ptr++ = CMD_MEDIA_STATE_FLUSH;
1673 *command_ptr++ = MI_BATCH_BUFFER_END;
1676 dri_bo_unmap(vme_context->vme_batchbuffer.bo);
1679 static void gen9_vme_hevc_pipeline_programing(VADriverContextP ctx,
1680 struct encode_state *encode_state,
1681 struct intel_encoder_context *encoder_context)
1683 struct gen6_vme_context *vme_context = encoder_context->vme_context;
1684 struct intel_batchbuffer *batch = encoder_context->base.batch;
1685 VAEncSliceParameterBufferHEVC *pSliceParameter = (VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[0]->buffer;
1686 VAEncSequenceParameterBufferHEVC *pSequenceParameter = (VAEncSequenceParameterBufferHEVC *)encode_state->seq_param_ext->buffer;
1687 int width_in_mbs = (pSequenceParameter->pic_width_in_luma_samples + 15) / 16;
1688 int height_in_mbs = (pSequenceParameter->pic_height_in_luma_samples + 15) / 16;
1690 bool allow_hwscore = true;
1693 int log2_cu_size = pSequenceParameter->log2_min_luma_coding_block_size_minus3 + 3;
1694 int log2_ctb_size = pSequenceParameter->log2_diff_max_min_luma_coding_block_size + log2_cu_size;
1696 int ctb_size = 1 << log2_ctb_size;
1697 int num_mb_in_ctb = (ctb_size + 15) / 16;
1698 int transform_8x8_mode_flag = 1;
1699 num_mb_in_ctb = num_mb_in_ctb * num_mb_in_ctb;
1701 for (s = 0; s < encode_state->num_slice_params_ext; s++) {
1702 pSliceParameter = (VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[s]->buffer;
1703 int slice_mb_begin = pSliceParameter->slice_segment_address * num_mb_in_ctb;
1704 if ((slice_mb_begin % width_in_mbs)) {
1705 allow_hwscore = false;
1710 if (pSliceParameter->slice_type == HEVC_SLICE_I) {
1711 kernel_shader = VME_INTRA_SHADER;
1712 } else if (pSliceParameter->slice_type == HEVC_SLICE_P) {
1713 kernel_shader = VME_INTER_SHADER;
1715 kernel_shader = VME_BINTER_SHADER;
1717 kernel_shader = VME_INTER_SHADER;
1720 gen9wa_vme_hevc_walker_fill_vme_batchbuffer(ctx,
1722 width_in_mbs, height_in_mbs,
1724 transform_8x8_mode_flag,
1727 gen9_vme_hevc_fill_vme_batchbuffer(ctx,
1729 width_in_mbs, height_in_mbs,
1731 transform_8x8_mode_flag,
1734 intel_batchbuffer_start_atomic(batch, 0x1000);
1735 gen9_gpe_pipeline_setup(ctx, &vme_context->gpe_context, batch);
1736 BEGIN_BATCH(batch, 3);
1737 OUT_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8) | (1 << 0));
1739 vme_context->vme_batchbuffer.bo,
1740 I915_GEM_DOMAIN_COMMAND, 0,
1742 ADVANCE_BATCH(batch);
1744 gen9_gpe_pipeline_end(ctx, &vme_context->gpe_context, batch);
1746 intel_batchbuffer_end_atomic(batch);
1749 static VAStatus gen9_intel_init_hevc_surface(VADriverContextP ctx,
1750 struct intel_encoder_context *encoder_context,
1751 struct encode_state *encode_state,
1752 struct object_surface *input_obj_surface,
1753 struct object_surface *output_obj_surface,
1756 struct i965_driver_data *i965 = i965_driver_data(ctx);
1757 struct gen9_hcpe_context *mfc_context = encoder_context->mfc_context;
1758 VAEncSequenceParameterBufferHEVC *pSequenceParameter = (VAEncSequenceParameterBufferHEVC *)encode_state->seq_param_ext->buffer;
1759 GenHevcSurface *hevc_encoder_surface;
1760 struct i965_surface src_surface, dst_surface;
1761 struct object_surface *obj_surface;
1767 obj_surface = output_obj_surface;
1768 assert(obj_surface && obj_surface->bo);
1770 if (obj_surface->private_data == NULL) {
1772 if (mfc_context->pic_size.ctb_size == 16)
1773 size = ((pSequenceParameter->pic_width_in_luma_samples + 63) >> 6) *
1774 ((pSequenceParameter->pic_height_in_luma_samples + 15) >> 4);
1776 size = ((pSequenceParameter->pic_width_in_luma_samples + 31) >> 5) *
1777 ((pSequenceParameter->pic_height_in_luma_samples + 31) >> 5);
1778 size <<= 6; /* in unit of 64bytes */
1780 hevc_encoder_surface = calloc(sizeof(GenHevcSurface), 1);
1782 assert(hevc_encoder_surface);
1783 hevc_encoder_surface->motion_vector_temporal_bo =
1784 dri_bo_alloc(i965->intel.bufmgr,
1785 "motion vector temporal buffer",
1788 assert(hevc_encoder_surface->motion_vector_temporal_bo);
1790 hevc_encoder_surface->ctx = ctx;
1791 hevc_encoder_surface->nv12_surface_obj = NULL;
1792 hevc_encoder_surface->nv12_surface_id = VA_INVALID_SURFACE;
1793 hevc_encoder_surface->has_p010_to_nv12_done = 0;
1795 obj_surface->private_data = (void *)hevc_encoder_surface;
1796 obj_surface->free_private_data = (void *)gen_free_hevc_surface;
1799 hevc_encoder_surface = (GenHevcSurface *) obj_surface->private_data;
1801 if (!hevc_encoder_surface->has_p010_to_nv12_done && obj_surface->fourcc == VA_FOURCC_P010) {
1805 rect.width = obj_surface->orig_width;
1806 rect.height = obj_surface->orig_height;
1808 src_surface.base = (struct object_base *)input_obj_surface;
1809 src_surface.type = I965_SURFACE_TYPE_SURFACE;
1810 src_surface.flags = I965_SURFACE_FLAG_FRAME;
1812 if (SURFACE(hevc_encoder_surface->nv12_surface_id) == NULL) {
1813 status = i965_CreateSurfaces(ctx,
1814 obj_surface->orig_width,
1815 obj_surface->orig_height,
1816 VA_RT_FORMAT_YUV420,
1818 &hevc_encoder_surface->nv12_surface_id);
1819 assert(status == VA_STATUS_SUCCESS);
1821 if (status != VA_STATUS_SUCCESS)
1825 obj_surface = SURFACE(hevc_encoder_surface->nv12_surface_id);
1826 hevc_encoder_surface->nv12_surface_obj = obj_surface;
1827 assert(obj_surface);
1828 i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
1830 dst_surface.base = (struct object_base *)obj_surface;
1831 dst_surface.type = I965_SURFACE_TYPE_SURFACE;
1832 dst_surface.flags = I965_SURFACE_FLAG_FRAME;
1834 status = i965_image_processing(ctx,
1839 assert(status == VA_STATUS_SUCCESS);
1842 hevc_encoder_surface->has_p010_to_nv12_done = 1;
1845 return VA_STATUS_SUCCESS;
1848 static VAStatus gen9_intel_hevc_input_check(VADriverContextP ctx,
1849 struct encode_state *encode_state,
1850 struct intel_encoder_context *encoder_context)
1852 struct i965_driver_data *i965 = i965_driver_data(ctx);
1853 struct gen9_hcpe_context *mfc_context = encoder_context->mfc_context;
1854 struct object_surface *obj_surface;
1855 GenHevcSurface *hevc_encoder_surface = NULL;
1859 obj_surface = SURFACE(encoder_context->input_yuv_surface);
1860 assert(obj_surface && obj_surface->bo);
1862 fourcc = obj_surface->fourcc;
1863 /* Setup current frame and current direct mv buffer*/
1864 obj_surface = encode_state->reconstructed_object;
1865 if (fourcc == VA_FOURCC_P010)
1866 i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_P010, SUBSAMPLE_YUV420);
1868 i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
1869 hevc_encoder_surface = NULL;
1870 hevc_encoder_surface = (GenHevcSurface *) obj_surface->private_data;
1871 if (hevc_encoder_surface)
1872 hevc_encoder_surface->has_p010_to_nv12_done = 0;
1873 gen9_intel_init_hevc_surface(ctx, encoder_context, encode_state, encode_state->input_yuv_object,
1876 /* Setup reference frames and direct mv buffers*/
1877 for (i = 0; i < MAX_HCP_REFERENCE_SURFACES; i++) {
1878 obj_surface = encode_state->reference_objects[i];
1880 if (obj_surface && obj_surface->bo) {
1881 mfc_context->reference_surfaces[i].bo = obj_surface->bo;
1882 dri_bo_reference(obj_surface->bo);
1884 gen9_intel_init_hevc_surface(ctx, encoder_context, encode_state, obj_surface,
1891 return VA_STATUS_SUCCESS;
1894 static VAStatus gen9_vme_hevc_prepare(VADriverContextP ctx,
1895 struct encode_state *encode_state,
1896 struct intel_encoder_context *encoder_context)
1898 VAStatus vaStatus = VA_STATUS_SUCCESS;
1899 VAEncSliceParameterBufferHEVC *pSliceParameter = (VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[0]->buffer;
1900 int is_intra = pSliceParameter->slice_type == HEVC_SLICE_I;
1901 VAEncSequenceParameterBufferHEVC *pSequenceParameter = (VAEncSequenceParameterBufferHEVC *)encode_state->seq_param_ext->buffer;
1902 struct gen6_vme_context *vme_context = encoder_context->vme_context;
1904 /* here use the avc level for hevc vme */
1905 if (!vme_context->hevc_level ||
1906 (vme_context->hevc_level != pSequenceParameter->general_level_idc)) {
1907 vme_context->hevc_level = pSequenceParameter->general_level_idc;
1910 //internal input check for main10
1911 gen9_intel_hevc_input_check(ctx, encode_state, encoder_context);
1913 intel_vme_hevc_update_mbmv_cost(ctx, encode_state, encoder_context);
1915 /*Setup all the memory object*/
1916 gen9_vme_hevc_surface_setup(ctx, encode_state, is_intra, encoder_context);
1917 gen9_vme_interface_setup(ctx, encode_state, encoder_context);
1918 //gen9_vme_vme_state_setup(ctx, encode_state, is_intra, encoder_context);
1919 gen9_vme_constant_setup(ctx, encode_state, encoder_context, 1);
1921 /*Programing media pipeline*/
1922 gen9_vme_hevc_pipeline_programing(ctx, encode_state, encoder_context);
1929 gen9_vme_hevc_pipeline(VADriverContextP ctx,
1931 struct encode_state *encode_state,
1932 struct intel_encoder_context *encoder_context)
1934 gen9_vme_media_init(ctx, encoder_context);
1935 gen9_vme_hevc_prepare(ctx, encode_state, encoder_context);
1936 gen9_vme_run(ctx, encode_state, encoder_context);
1937 gen9_vme_stop(ctx, encode_state, encoder_context);
1939 return VA_STATUS_SUCCESS;
1944 gen9_vme_context_destroy(void *context)
1946 struct gen6_vme_context *vme_context = context;
1948 gen8_gpe_context_destroy(&vme_context->gpe_context);
1950 dri_bo_unreference(vme_context->vme_output.bo);
1951 vme_context->vme_output.bo = NULL;
1953 dri_bo_unreference(vme_context->vme_state.bo);
1954 vme_context->vme_state.bo = NULL;
1956 dri_bo_unreference(vme_context->vme_batchbuffer.bo);
1957 vme_context->vme_batchbuffer.bo = NULL;
1959 free(vme_context->vme_state_message);
1960 vme_context->vme_state_message = NULL;
1962 dri_bo_unreference(vme_context->i_qp_cost_table);
1963 vme_context->i_qp_cost_table = NULL;
1965 dri_bo_unreference(vme_context->p_qp_cost_table);
1966 vme_context->p_qp_cost_table = NULL;
1968 dri_bo_unreference(vme_context->b_qp_cost_table);
1969 vme_context->b_qp_cost_table = NULL;
1971 free(vme_context->qp_per_mb);
1972 vme_context->qp_per_mb = NULL;
1977 extern Bool i965_encoder_vp8_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context);
1979 Bool gen9_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
1981 struct i965_driver_data *i965 = i965_driver_data(ctx);
1982 struct gen6_vme_context *vme_context;
1983 struct i965_kernel *vme_kernel_list = NULL;
1984 int i965_kernel_num;
1986 if (encoder_context->low_power_mode || encoder_context->codec == CODEC_JPEG) {
1987 encoder_context->vme_context = NULL;
1988 encoder_context->vme_pipeline = NULL;
1989 encoder_context->vme_context_destroy = NULL;
1994 if (encoder_context->codec == CODEC_VP9) {
1995 return gen9_vp9_vme_context_init(ctx, encoder_context);
1996 } else if (encoder_context->codec == CODEC_VP8) {
1997 return i965_encoder_vp8_vme_context_init(ctx, encoder_context);
1998 } else if (encoder_context->codec == CODEC_H264 ||
1999 encoder_context->codec == CODEC_H264_MVC) {
2000 return gen9_avc_vme_context_init(ctx, encoder_context);
2001 } else if (encoder_context->codec == CODEC_HEVC) {
2002 if (IS_GEN10(i965->intel.device_info))
2003 return gen10_hevc_vme_context_init(ctx, encoder_context);
2005 return gen9_hevc_vme_context_init(ctx, encoder_context);
2008 vme_context = calloc(1, sizeof(struct gen6_vme_context));
2010 switch (encoder_context->codec) {
2012 case CODEC_H264_MVC:
2013 vme_kernel_list = gen9_vme_kernels;
2014 encoder_context->vme_pipeline = gen9_vme_pipeline;
2015 i965_kernel_num = sizeof(gen9_vme_kernels) / sizeof(struct i965_kernel);
2019 vme_kernel_list = gen9_vme_mpeg2_kernels;
2020 encoder_context->vme_pipeline = gen9_vme_mpeg2_pipeline;
2021 i965_kernel_num = sizeof(gen9_vme_mpeg2_kernels) / sizeof(struct i965_kernel);
2025 vme_kernel_list = gen9_vme_vp8_kernels;
2026 encoder_context->vme_pipeline = gen9_vme_vp8_pipeline;
2027 i965_kernel_num = sizeof(gen9_vme_vp8_kernels) / sizeof(struct i965_kernel);
2031 vme_kernel_list = gen9_vme_hevc_kernels;
2032 encoder_context->vme_pipeline = gen9_vme_hevc_pipeline;
2033 i965_kernel_num = sizeof(gen9_vme_hevc_kernels) / sizeof(struct i965_kernel);
2037 /* never get here */
2043 assert(vme_context);
2044 vme_context->vme_kernel_sum = i965_kernel_num;
2045 vme_context->gpe_context.surface_state_binding_table.length = (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6;
2047 vme_context->gpe_context.idrt.entry_size = ALIGN(sizeof(struct gen8_interface_descriptor_data), 64);
2048 vme_context->gpe_context.idrt.max_entries = MAX_INTERFACE_DESC_GEN6;
2049 vme_context->gpe_context.curbe.length = CURBE_TOTAL_DATA_LENGTH;
2050 vme_context->gpe_context.sampler.entry_size = 0;
2051 vme_context->gpe_context.sampler.max_entries = 0;
2053 if (i965->intel.eu_total > 0) {
2054 vme_context->gpe_context.vfe_state.max_num_threads = 6 *
2055 i965->intel.eu_total;
2057 vme_context->gpe_context.vfe_state.max_num_threads = 60 - 1;
2059 vme_context->gpe_context.vfe_state.num_urb_entries = 64;
2060 vme_context->gpe_context.vfe_state.gpgpu_mode = 0;
2061 vme_context->gpe_context.vfe_state.urb_entry_size = 16;
2062 vme_context->gpe_context.vfe_state.curbe_allocation_size = CURBE_ALLOCATION_SIZE - 1;
2064 gen7_vme_scoreboard_init(ctx, vme_context);
2066 gen8_gpe_load_kernels(ctx,
2067 &vme_context->gpe_context,
2070 vme_context->vme_surface2_setup = gen8_gpe_surface2_setup;
2071 vme_context->vme_media_rw_surface_setup = gen8_gpe_media_rw_surface_setup;
2072 vme_context->vme_buffer_suface_setup = gen8_gpe_buffer_suface_setup;
2073 vme_context->vme_media_chroma_surface_setup = gen8_gpe_media_chroma_surface_setup;
2075 encoder_context->vme_context = vme_context;
2076 encoder_context->vme_context_destroy = gen9_vme_context_destroy;
2078 vme_context->vme_state_message = malloc(VME_MSG_LENGTH * sizeof(int));