2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Zhao Yakui <yakui.zhao@intel.com>
26 * Xiang Haihao <haihao.xiang@intel.com>
35 #include "intel_batchbuffer.h"
36 #include "intel_driver.h"
38 #include "i965_defines.h"
39 #include "i965_drv_video.h"
40 #include "i965_encoder.h"
44 #include "intel_media.h"
45 #include "gen9_vp9_encapi.h"
47 #ifdef SURFACE_STATE_PADDED_SIZE
48 #undef SURFACE_STATE_PADDED_SIZE
51 #define SURFACE_STATE_PADDED_SIZE SURFACE_STATE_PADDED_SIZE_GEN8
52 #define SURFACE_STATE_OFFSET(index) (SURFACE_STATE_PADDED_SIZE * index)
53 #define BINDING_TABLE_OFFSET(index) (SURFACE_STATE_OFFSET(MAX_MEDIA_SURFACES_GEN6) + sizeof(unsigned int) * index)
55 #define VME_INTRA_SHADER 0
56 #define VME_INTER_SHADER 1
57 #define VME_BINTER_SHADER 2
59 #define CURBE_ALLOCATION_SIZE 37 /* in 256-bit */
60 #define CURBE_TOTAL_DATA_LENGTH (4 * 32) /* in byte, it should be less than or equal to CURBE_ALLOCATION_SIZE * 32 */
61 #define CURBE_URB_ENTRY_LENGTH 4 /* in 256-bit, it should be less than or equal to CURBE_TOTAL_DATA_LENGTH / 32 */
63 #define VME_MSG_LENGTH 32
65 static const uint32_t gen9_vme_intra_frame[][4] = {
66 #include "shaders/vme/intra_frame_gen9.g9b"
69 static const uint32_t gen9_vme_inter_frame[][4] = {
70 #include "shaders/vme/inter_frame_gen9.g9b"
73 static const uint32_t gen9_vme_inter_bframe[][4] = {
74 #include "shaders/vme/inter_bframe_gen9.g9b"
77 static struct i965_kernel gen9_vme_kernels[] = {
80 VME_INTRA_SHADER, /*index*/
82 sizeof(gen9_vme_intra_frame),
89 sizeof(gen9_vme_inter_frame),
95 gen9_vme_inter_bframe,
96 sizeof(gen9_vme_inter_bframe),
101 static const uint32_t gen9_vme_mpeg2_intra_frame[][4] = {
102 #include "shaders/vme/intra_frame_gen9.g9b"
105 static const uint32_t gen9_vme_mpeg2_inter_frame[][4] = {
106 #include "shaders/vme/mpeg2_inter_gen9.g9b"
109 static struct i965_kernel gen9_vme_mpeg2_kernels[] = {
112 VME_INTRA_SHADER, /*index*/
113 gen9_vme_mpeg2_intra_frame,
114 sizeof(gen9_vme_mpeg2_intra_frame),
120 gen9_vme_mpeg2_inter_frame,
121 sizeof(gen9_vme_mpeg2_inter_frame),
126 static const uint32_t gen9_vme_vp8_intra_frame[][4] = {
127 #include "shaders/vme/vp8_intra_frame_gen9.g9b"
130 static const uint32_t gen9_vme_vp8_inter_frame[][4] = {
131 #include "shaders/vme/vp8_inter_frame_gen9.g9b"
134 static struct i965_kernel gen9_vme_vp8_kernels[] = {
137 VME_INTRA_SHADER, /*index*/
138 gen9_vme_vp8_intra_frame,
139 sizeof(gen9_vme_vp8_intra_frame),
145 gen9_vme_vp8_inter_frame,
146 sizeof(gen9_vme_vp8_inter_frame),
153 static const uint32_t gen9_vme_hevc_intra_frame[][4] = {
154 #include "shaders/vme/intra_frame_gen9.g9b"
157 static const uint32_t gen9_vme_hevc_inter_frame[][4] = {
158 #include "shaders/vme/inter_frame_gen9.g9b"
161 static const uint32_t gen9_vme_hevc_inter_bframe[][4] = {
162 #include "shaders/vme/inter_bframe_gen9.g9b"
165 static struct i965_kernel gen9_vme_hevc_kernels[] = {
168 VME_INTRA_SHADER, /*index*/
169 gen9_vme_hevc_intra_frame,
170 sizeof(gen9_vme_hevc_intra_frame),
176 gen9_vme_hevc_inter_frame,
177 sizeof(gen9_vme_hevc_inter_frame),
183 gen9_vme_hevc_inter_bframe,
184 sizeof(gen9_vme_hevc_inter_bframe),
188 /* only used for VME source surface state */
190 gen9_vme_source_surface_state(VADriverContextP ctx,
192 struct object_surface *obj_surface,
193 struct intel_encoder_context *encoder_context)
195 struct gen6_vme_context *vme_context = encoder_context->vme_context;
197 vme_context->vme_surface2_setup(ctx,
198 &vme_context->gpe_context,
200 BINDING_TABLE_OFFSET(index),
201 SURFACE_STATE_OFFSET(index));
205 gen9_vme_media_source_surface_state(VADriverContextP ctx,
207 struct object_surface *obj_surface,
208 struct intel_encoder_context *encoder_context)
210 struct gen6_vme_context *vme_context = encoder_context->vme_context;
212 vme_context->vme_media_rw_surface_setup(ctx,
213 &vme_context->gpe_context,
215 BINDING_TABLE_OFFSET(index),
216 SURFACE_STATE_OFFSET(index),
221 gen9_vme_media_chroma_source_surface_state(VADriverContextP ctx,
223 struct object_surface *obj_surface,
224 struct intel_encoder_context *encoder_context)
226 struct gen6_vme_context *vme_context = encoder_context->vme_context;
228 vme_context->vme_media_chroma_surface_setup(ctx,
229 &vme_context->gpe_context,
231 BINDING_TABLE_OFFSET(index),
232 SURFACE_STATE_OFFSET(index),
237 gen9_vme_output_buffer_setup(VADriverContextP ctx,
238 struct encode_state *encode_state,
240 struct intel_encoder_context *encoder_context,
246 struct i965_driver_data *i965 = i965_driver_data(ctx);
247 struct gen6_vme_context *vme_context = encoder_context->vme_context;
249 vme_context->vme_output.num_blocks = width_in_mbs * height_in_mbs;
250 vme_context->vme_output.pitch = 16; /* in bytes, always 16 */
253 vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES * 2;
255 vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES * 24;
257 * Inter MV . 32-byte Intra search + 16 IME info + 128 IME MV + 32 IME Ref
258 * + 16 FBR Info + 128 FBR MV + 32 FBR Ref.
259 * 16 * (2 + 2 * (1 + 8 + 2))= 16 * 24.
262 vme_context->vme_output.bo = dri_bo_alloc(i965->intel.bufmgr,
264 vme_context->vme_output.num_blocks * vme_context->vme_output.size_block,
266 assert(vme_context->vme_output.bo);
267 vme_context->vme_buffer_suface_setup(ctx,
268 &vme_context->gpe_context,
269 &vme_context->vme_output,
270 BINDING_TABLE_OFFSET(index),
271 SURFACE_STATE_OFFSET(index));
275 gen9_vme_avc_output_buffer_setup(VADriverContextP ctx,
276 struct encode_state *encode_state,
278 struct intel_encoder_context *encoder_context)
280 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
281 VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
282 int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
283 int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
284 int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
286 gen9_vme_output_buffer_setup(ctx, encode_state, index, encoder_context, is_intra, width_in_mbs, height_in_mbs);
291 gen9_vme_output_vme_batchbuffer_setup(VADriverContextP ctx,
292 struct encode_state *encode_state,
294 struct intel_encoder_context *encoder_context,
298 struct i965_driver_data *i965 = i965_driver_data(ctx);
299 struct gen6_vme_context *vme_context = encoder_context->vme_context;
301 vme_context->vme_batchbuffer.num_blocks = width_in_mbs * height_in_mbs + 1;
302 vme_context->vme_batchbuffer.size_block = 64; /* 4 OWORDs */
303 vme_context->vme_batchbuffer.pitch = 16;
304 vme_context->vme_batchbuffer.bo = dri_bo_alloc(i965->intel.bufmgr,
306 vme_context->vme_batchbuffer.num_blocks * vme_context->vme_batchbuffer.size_block,
308 vme_context->vme_buffer_suface_setup(ctx,
309 &vme_context->gpe_context,
310 &vme_context->vme_batchbuffer,
311 BINDING_TABLE_OFFSET(index),
312 SURFACE_STATE_OFFSET(index));
316 gen9_vme_avc_output_vme_batchbuffer_setup(VADriverContextP ctx,
317 struct encode_state *encode_state,
319 struct intel_encoder_context *encoder_context)
321 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
322 int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
323 int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
325 gen9_vme_output_vme_batchbuffer_setup(ctx, encode_state, index, encoder_context, width_in_mbs, height_in_mbs);
330 gen9_vme_surface_setup(VADriverContextP ctx,
331 struct encode_state *encode_state,
333 struct intel_encoder_context *encoder_context)
335 struct object_surface *obj_surface;
337 /*Setup surfaces state*/
338 /* current picture for encoding */
339 obj_surface = encode_state->input_yuv_object;
341 gen9_vme_source_surface_state(ctx, 0, obj_surface, encoder_context);
342 gen9_vme_media_source_surface_state(ctx, 4, obj_surface, encoder_context);
343 gen9_vme_media_chroma_source_surface_state(ctx, 6, obj_surface, encoder_context);
346 VAEncSliceParameterBufferH264 *slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
349 slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type);
350 assert(slice_type != SLICE_TYPE_I && slice_type != SLICE_TYPE_SI);
352 intel_avc_vme_reference_state(ctx, encode_state, encoder_context, 0, 1, gen9_vme_source_surface_state);
354 if (slice_type == SLICE_TYPE_B)
355 intel_avc_vme_reference_state(ctx, encode_state, encoder_context, 1, 2, gen9_vme_source_surface_state);
359 gen9_vme_avc_output_buffer_setup(ctx, encode_state, 3, encoder_context);
360 gen9_vme_avc_output_vme_batchbuffer_setup(ctx, encode_state, 5, encoder_context);
361 intel_h264_setup_cost_surface(ctx, encode_state, encoder_context,
362 BINDING_TABLE_OFFSET(INTEL_COST_TABLE_OFFSET),
363 SURFACE_STATE_OFFSET(INTEL_COST_TABLE_OFFSET));
365 return VA_STATUS_SUCCESS;
368 static VAStatus gen9_vme_interface_setup(VADriverContextP ctx,
369 struct encode_state *encode_state,
370 struct intel_encoder_context *encoder_context)
372 struct gen6_vme_context *vme_context = encoder_context->vme_context;
373 struct gen8_interface_descriptor_data *desc;
376 unsigned char *desc_ptr;
378 bo = vme_context->gpe_context.dynamic_state.bo;
381 desc_ptr = (unsigned char *)bo->virtual + vme_context->gpe_context.idrt_offset;
383 desc = (struct gen8_interface_descriptor_data *)desc_ptr;
385 for (i = 0; i < vme_context->vme_kernel_sum; i++) {
386 struct i965_kernel *kernel;
387 kernel = &vme_context->gpe_context.kernels[i];
388 assert(sizeof(*desc) == 32);
389 /*Setup the descritor table*/
390 memset(desc, 0, sizeof(*desc));
391 desc->desc0.kernel_start_pointer = kernel->kernel_offset >> 6;
392 desc->desc3.sampler_count = 0; /* FIXME: */
393 desc->desc3.sampler_state_pointer = 0;
394 desc->desc4.binding_table_entry_count = 1; /* FIXME: */
395 desc->desc4.binding_table_pointer = (BINDING_TABLE_OFFSET(0) >> 5);
396 desc->desc5.constant_urb_entry_read_offset = 0;
397 desc->desc5.constant_urb_entry_read_length = CURBE_URB_ENTRY_LENGTH;
404 return VA_STATUS_SUCCESS;
407 static VAStatus gen9_vme_constant_setup(VADriverContextP ctx,
408 struct encode_state *encode_state,
409 struct intel_encoder_context *encoder_context,
412 struct gen6_vme_context *vme_context = encoder_context->vme_context;
413 unsigned char *constant_buffer;
414 unsigned int *vme_state_message;
417 vme_state_message = (unsigned int *)vme_context->vme_state_message;
419 if (encoder_context->codec == CODEC_H264 ||
420 encoder_context->codec == CODEC_H264_MVC) {
421 if (vme_context->h264_level >= 30) {
424 if (vme_context->h264_level >= 31)
427 } else if (encoder_context->codec == CODEC_MPEG2) {
429 }else if (encoder_context->codec == CODEC_HEVC) {
430 if (vme_context->hevc_level >= 30*3) {
433 if (vme_context->hevc_level >= 31*3)
435 }/* use the avc level setting */
438 vme_state_message[31] = mv_num;
440 dri_bo_map(vme_context->gpe_context.dynamic_state.bo, 1);
441 assert(vme_context->gpe_context.dynamic_state.bo->virtual);
442 constant_buffer = (unsigned char *)vme_context->gpe_context.dynamic_state.bo->virtual +
443 vme_context->gpe_context.curbe_offset;
445 /* VME MV/Mb cost table is passed by using const buffer */
446 /* Now it uses the fixed search path. So it is constructed directly
449 memcpy(constant_buffer, (char *)vme_context->vme_state_message, 128);
451 dri_bo_unmap(vme_context->gpe_context.dynamic_state.bo);
453 return VA_STATUS_SUCCESS;
456 #define MB_SCOREBOARD_A (1 << 0)
457 #define MB_SCOREBOARD_B (1 << 1)
458 #define MB_SCOREBOARD_C (1 << 2)
460 /* check whether the mb of (x_index, y_index) is out of bound */
461 static inline int loop_in_bounds(int x_index, int y_index, int first_mb, int num_mb, int mb_width, int mb_height)
464 if (x_index < 0 || x_index >= mb_width)
466 if (y_index < 0 || y_index >= mb_height)
469 mb_index = y_index * mb_width + x_index;
470 if (mb_index < first_mb || mb_index > (first_mb + num_mb))
476 gen9wa_vme_walker_fill_vme_batchbuffer(VADriverContextP ctx,
477 struct encode_state *encode_state,
478 int mb_width, int mb_height,
480 int transform_8x8_mode_flag,
481 struct intel_encoder_context *encoder_context)
483 struct gen6_vme_context *vme_context = encoder_context->vme_context;
486 unsigned int *command_ptr;
488 #define USE_SCOREBOARD (1 << 21)
490 dri_bo_map(vme_context->vme_batchbuffer.bo, 1);
491 command_ptr = vme_context->vme_batchbuffer.bo->virtual;
493 for (s = 0; s < encode_state->num_slice_params_ext; s++) {
494 VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[s]->buffer;
495 int first_mb = pSliceParameter->macroblock_address;
496 int num_mb = pSliceParameter->num_macroblocks;
497 unsigned int mb_intra_ub, score_dep;
498 int x_outer, y_outer, x_inner, y_inner;
501 x_outer = first_mb % mb_width;
502 y_outer = first_mb / mb_width;
505 for (; x_outer < (mb_width -2 ) && !loop_in_bounds(x_outer, y_outer, first_mb, num_mb, mb_width, mb_height); ) {
508 for (; !loop_in_bounds(x_inner, y_inner, first_mb, num_mb, mb_width, mb_height);) {
512 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_AE;
513 score_dep |= MB_SCOREBOARD_A;
515 if (y_inner != mb_row) {
516 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_B;
517 score_dep |= MB_SCOREBOARD_B;
519 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_D;
520 if (x_inner != (mb_width -1)) {
521 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C;
522 score_dep |= MB_SCOREBOARD_C;
526 *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2));
527 *command_ptr++ = kernel;
528 *command_ptr++ = USE_SCOREBOARD;
531 /* the (X, Y) term of scoreboard */
532 *command_ptr++ = ((y_inner << 16) | x_inner);
533 *command_ptr++ = score_dep;
535 *command_ptr++ = (mb_width << 16 | y_inner << 8 | x_inner);
536 *command_ptr++ = ((1 << 18) | (1 << 16) | transform_8x8_mode_flag | (mb_intra_ub << 8));
537 *command_ptr++ = CMD_MEDIA_STATE_FLUSH;
546 xtemp_outer = mb_width - 2;
549 x_outer = xtemp_outer;
550 y_outer = first_mb / mb_width;
551 for (;!loop_in_bounds(x_outer, y_outer, first_mb, num_mb, mb_width, mb_height); ) {
554 for (; !loop_in_bounds(x_inner, y_inner, first_mb, num_mb, mb_width, mb_height);) {
558 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_AE;
559 score_dep |= MB_SCOREBOARD_A;
561 if (y_inner != mb_row) {
562 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_B;
563 score_dep |= MB_SCOREBOARD_B;
565 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_D;
567 if (x_inner != (mb_width -1)) {
568 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C;
569 score_dep |= MB_SCOREBOARD_C;
573 *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2));
574 *command_ptr++ = kernel;
575 *command_ptr++ = USE_SCOREBOARD;
578 /* the (X, Y) term of scoreboard */
579 *command_ptr++ = ((y_inner << 16) | x_inner);
580 *command_ptr++ = score_dep;
582 *command_ptr++ = (mb_width << 16 | y_inner << 8 | x_inner);
583 *command_ptr++ = ((1 << 18) | (1 << 16) | transform_8x8_mode_flag | (mb_intra_ub << 8));
585 *command_ptr++ = CMD_MEDIA_STATE_FLUSH;
591 if (x_outer >= mb_width) {
593 x_outer = xtemp_outer;
598 *command_ptr++ = MI_BATCH_BUFFER_END;
601 dri_bo_unmap(vme_context->vme_batchbuffer.bo);
605 gen9_vme_fill_vme_batchbuffer(VADriverContextP ctx,
606 struct encode_state *encode_state,
607 int mb_width, int mb_height,
609 int transform_8x8_mode_flag,
610 struct intel_encoder_context *encoder_context)
612 struct gen6_vme_context *vme_context = encoder_context->vme_context;
613 int mb_x = 0, mb_y = 0;
615 unsigned int *command_ptr;
616 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
617 VAEncPictureParameterBufferH264 *pic_param = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
618 VAEncSliceParameterBufferH264 *slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
620 int slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type);
623 if (encoder_context->rate_control_mode == VA_RC_CQP)
624 qp = pic_param->pic_init_qp + slice_param->slice_qp_delta;
626 qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY;
628 dri_bo_map(vme_context->vme_batchbuffer.bo, 1);
629 command_ptr = vme_context->vme_batchbuffer.bo->virtual;
631 for (s = 0; s < encode_state->num_slice_params_ext; s++) {
632 VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[s]->buffer;
633 int slice_mb_begin = pSliceParameter->macroblock_address;
634 int slice_mb_number = pSliceParameter->num_macroblocks;
635 unsigned int mb_intra_ub;
636 int slice_mb_x = pSliceParameter->macroblock_address % mb_width;
637 for (i = 0; i < slice_mb_number; ) {
638 int mb_count = i + slice_mb_begin;
639 mb_x = mb_count % mb_width;
640 mb_y = mb_count / mb_width;
643 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_AE;
646 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_B;
648 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_D;
649 if (mb_x != (mb_width -1))
650 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C;
654 mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_AE);
655 mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_BCD_MASK);
656 if ((i == (mb_width - 1)) && slice_mb_x) {
657 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C;
661 if ((i == mb_width) && slice_mb_x) {
662 mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_D);
664 *command_ptr++ = (CMD_MEDIA_OBJECT | (9 - 2));
665 *command_ptr++ = kernel;
672 *command_ptr++ = (mb_width << 16 | mb_y << 8 | mb_x);
673 *command_ptr++ = ((encoder_context->quality_level << 24) | (1 << 16) | transform_8x8_mode_flag | (mb_intra_ub << 8));
674 /* qp occupies one byte */
675 if (vme_context->roi_enabled) {
676 qp_index = mb_y * mb_width + mb_x;
677 qp_mb = *(vme_context->qp_per_mb + qp_index);
680 *command_ptr++ = qp_mb;
682 *command_ptr++ = CMD_MEDIA_STATE_FLUSH;
688 *command_ptr++ = MI_BATCH_BUFFER_END;
691 dri_bo_unmap(vme_context->vme_batchbuffer.bo);
694 static void gen9_vme_media_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
696 struct gen6_vme_context *vme_context = encoder_context->vme_context;
698 gen8_gpe_context_init(ctx, &vme_context->gpe_context);
700 /* VME output buffer */
701 dri_bo_unreference(vme_context->vme_output.bo);
702 vme_context->vme_output.bo = NULL;
704 dri_bo_unreference(vme_context->vme_batchbuffer.bo);
705 vme_context->vme_batchbuffer.bo = NULL;
708 dri_bo_unreference(vme_context->vme_state.bo);
709 vme_context->vme_state.bo = NULL;
712 static void gen9_vme_pipeline_programing(VADriverContextP ctx,
713 struct encode_state *encode_state,
714 struct intel_encoder_context *encoder_context)
716 struct gen6_vme_context *vme_context = encoder_context->vme_context;
717 struct intel_batchbuffer *batch = encoder_context->base.batch;
718 VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
719 VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
720 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
721 int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
722 int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
724 bool allow_hwscore = true;
726 unsigned int is_low_quality = (encoder_context->quality_level == ENCODER_LOW_QUALITY);
729 allow_hwscore = false;
731 for (s = 0; s < encode_state->num_slice_params_ext; s++) {
732 pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[s]->buffer;
733 if ((pSliceParameter->macroblock_address % width_in_mbs)) {
734 allow_hwscore = false;
740 if ((pSliceParameter->slice_type == SLICE_TYPE_I) ||
741 (pSliceParameter->slice_type == SLICE_TYPE_SI)) {
742 kernel_shader = VME_INTRA_SHADER;
743 } else if ((pSliceParameter->slice_type == SLICE_TYPE_P) ||
744 (pSliceParameter->slice_type == SLICE_TYPE_SP)) {
745 kernel_shader = VME_INTER_SHADER;
747 kernel_shader = VME_BINTER_SHADER;
749 kernel_shader = VME_INTER_SHADER;
752 gen9wa_vme_walker_fill_vme_batchbuffer(ctx,
754 width_in_mbs, height_in_mbs,
756 pPicParameter->pic_fields.bits.transform_8x8_mode_flag,
759 gen9_vme_fill_vme_batchbuffer(ctx,
761 width_in_mbs, height_in_mbs,
763 pPicParameter->pic_fields.bits.transform_8x8_mode_flag,
766 intel_batchbuffer_start_atomic(batch, 0x1000);
767 gen9_gpe_pipeline_setup(ctx, &vme_context->gpe_context, batch);
768 BEGIN_BATCH(batch, 3);
769 OUT_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8) | (1 << 0));
771 vme_context->vme_batchbuffer.bo,
772 I915_GEM_DOMAIN_COMMAND, 0,
775 ADVANCE_BATCH(batch);
777 gen9_gpe_pipeline_end(ctx, &vme_context->gpe_context, batch);
779 intel_batchbuffer_end_atomic(batch);
782 static VAStatus gen9_vme_prepare(VADriverContextP ctx,
783 struct encode_state *encode_state,
784 struct intel_encoder_context *encoder_context)
786 VAStatus vaStatus = VA_STATUS_SUCCESS;
787 VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
788 int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
789 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
790 struct gen6_vme_context *vme_context = encoder_context->vme_context;
792 if (!vme_context->h264_level ||
793 (vme_context->h264_level != pSequenceParameter->level_idc)) {
794 vme_context->h264_level = pSequenceParameter->level_idc;
797 intel_vme_update_mbmv_cost(ctx, encode_state, encoder_context);
798 intel_h264_initialize_mbmv_cost(ctx, encode_state, encoder_context);
799 intel_h264_enc_roi_config(ctx, encode_state, encoder_context);
801 /*Setup all the memory object*/
802 gen9_vme_surface_setup(ctx, encode_state, is_intra, encoder_context);
803 gen9_vme_interface_setup(ctx, encode_state, encoder_context);
804 //gen9_vme_vme_state_setup(ctx, encode_state, is_intra, encoder_context);
805 gen9_vme_constant_setup(ctx, encode_state, encoder_context, (pSliceParameter->slice_type == SLICE_TYPE_B) ? 2 : 1);
807 /*Programing media pipeline*/
808 gen9_vme_pipeline_programing(ctx, encode_state, encoder_context);
813 static VAStatus gen9_vme_run(VADriverContextP ctx,
814 struct encode_state *encode_state,
815 struct intel_encoder_context *encoder_context)
817 struct intel_batchbuffer *batch = encoder_context->base.batch;
819 intel_batchbuffer_flush(batch);
821 return VA_STATUS_SUCCESS;
824 static VAStatus gen9_vme_stop(VADriverContextP ctx,
825 struct encode_state *encode_state,
826 struct intel_encoder_context *encoder_context)
828 return VA_STATUS_SUCCESS;
832 gen9_vme_pipeline(VADriverContextP ctx,
834 struct encode_state *encode_state,
835 struct intel_encoder_context *encoder_context)
837 gen9_vme_media_init(ctx, encoder_context);
838 gen9_vme_prepare(ctx, encode_state, encoder_context);
839 gen9_vme_run(ctx, encode_state, encoder_context);
840 gen9_vme_stop(ctx, encode_state, encoder_context);
842 return VA_STATUS_SUCCESS;
846 gen9_vme_mpeg2_output_buffer_setup(VADriverContextP ctx,
847 struct encode_state *encode_state,
850 struct intel_encoder_context *encoder_context)
853 VAEncSequenceParameterBufferMPEG2 *seq_param = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer;
854 int width_in_mbs = ALIGN(seq_param->picture_width, 16) / 16;
855 int height_in_mbs = ALIGN(seq_param->picture_height, 16) / 16;
857 gen9_vme_output_buffer_setup(ctx, encode_state, index, encoder_context, is_intra, width_in_mbs, height_in_mbs);
861 gen9_vme_mpeg2_output_vme_batchbuffer_setup(VADriverContextP ctx,
862 struct encode_state *encode_state,
864 struct intel_encoder_context *encoder_context)
867 VAEncSequenceParameterBufferMPEG2 *seq_param = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer;
868 int width_in_mbs = ALIGN(seq_param->picture_width, 16) / 16;
869 int height_in_mbs = ALIGN(seq_param->picture_height, 16) / 16;
871 gen9_vme_output_vme_batchbuffer_setup(ctx, encode_state, index, encoder_context, width_in_mbs, height_in_mbs);
875 gen9_vme_mpeg2_surface_setup(VADriverContextP ctx,
876 struct encode_state *encode_state,
878 struct intel_encoder_context *encoder_context)
880 struct object_surface *obj_surface;
882 /*Setup surfaces state*/
883 /* current picture for encoding */
884 obj_surface = encode_state->input_yuv_object;
885 gen9_vme_source_surface_state(ctx, 0, obj_surface, encoder_context);
886 gen9_vme_media_source_surface_state(ctx, 4, obj_surface, encoder_context);
887 gen9_vme_media_chroma_source_surface_state(ctx, 6, obj_surface, encoder_context);
891 obj_surface = encode_state->reference_objects[0];
893 if (obj_surface->bo != NULL)
894 gen9_vme_source_surface_state(ctx, 1, obj_surface, encoder_context);
897 obj_surface = encode_state->reference_objects[1];
899 if (obj_surface && obj_surface->bo != NULL)
900 gen9_vme_source_surface_state(ctx, 2, obj_surface, encoder_context);
904 gen9_vme_mpeg2_output_buffer_setup(ctx, encode_state, 3, is_intra, encoder_context);
905 gen9_vme_mpeg2_output_vme_batchbuffer_setup(ctx, encode_state, 5, encoder_context);
907 return VA_STATUS_SUCCESS;
911 gen9wa_vme_mpeg2_walker_fill_vme_batchbuffer(VADriverContextP ctx,
912 struct encode_state *encode_state,
913 int mb_width, int mb_height,
915 struct intel_encoder_context *encoder_context)
917 struct gen6_vme_context *vme_context = encoder_context->vme_context;
918 unsigned int *command_ptr;
920 #define MPEG2_SCOREBOARD (1 << 21)
922 dri_bo_map(vme_context->vme_batchbuffer.bo, 1);
923 command_ptr = vme_context->vme_batchbuffer.bo->virtual;
926 unsigned int mb_intra_ub, score_dep;
927 int x_outer, y_outer, x_inner, y_inner;
930 int num_mb = mb_width * mb_height;
935 for (; x_outer < (mb_width -2 ) && !loop_in_bounds(x_outer, y_outer, first_mb, num_mb, mb_width, mb_height); ) {
938 for (; !loop_in_bounds(x_inner, y_inner, first_mb, num_mb, mb_width, mb_height);) {
942 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_AE;
943 score_dep |= MB_SCOREBOARD_A;
946 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_B;
947 score_dep |= MB_SCOREBOARD_B;
950 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_D;
952 if (x_inner != (mb_width -1)) {
953 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C;
954 score_dep |= MB_SCOREBOARD_C;
958 *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2));
959 *command_ptr++ = kernel;
960 *command_ptr++ = MPEG2_SCOREBOARD;
963 /* the (X, Y) term of scoreboard */
964 *command_ptr++ = ((y_inner << 16) | x_inner);
965 *command_ptr++ = score_dep;
967 *command_ptr++ = (mb_width << 16 | y_inner << 8 | x_inner);
968 *command_ptr++ = ((1 << 18) | (1 << 16) | (mb_intra_ub << 8));
969 *command_ptr++ = CMD_MEDIA_STATE_FLUSH;
978 xtemp_outer = mb_width - 2;
981 x_outer = xtemp_outer;
983 for (;!loop_in_bounds(x_outer, y_outer, first_mb, num_mb, mb_width, mb_height); ) {
986 for (; !loop_in_bounds(x_inner, y_inner, first_mb, num_mb, mb_width, mb_height);) {
990 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_AE;
991 score_dep |= MB_SCOREBOARD_A;
994 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_B;
995 score_dep |= MB_SCOREBOARD_B;
998 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_D;
1000 if (x_inner != (mb_width -1)) {
1001 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C;
1002 score_dep |= MB_SCOREBOARD_C;
1006 *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2));
1007 *command_ptr++ = kernel;
1008 *command_ptr++ = MPEG2_SCOREBOARD;
1011 /* the (X, Y) term of scoreboard */
1012 *command_ptr++ = ((y_inner << 16) | x_inner);
1013 *command_ptr++ = score_dep;
1015 *command_ptr++ = (mb_width << 16 | y_inner << 8 | x_inner);
1016 *command_ptr++ = ((1 << 18) | (1 << 16) | (mb_intra_ub << 8));
1018 *command_ptr++ = CMD_MEDIA_STATE_FLUSH;
1024 if (x_outer >= mb_width) {
1026 x_outer = xtemp_outer;
1031 *command_ptr++ = MI_BATCH_BUFFER_END;
1034 dri_bo_unmap(vme_context->vme_batchbuffer.bo);
1039 gen9_vme_mpeg2_fill_vme_batchbuffer(VADriverContextP ctx,
1040 struct encode_state *encode_state,
1041 int mb_width, int mb_height,
1043 int transform_8x8_mode_flag,
1044 struct intel_encoder_context *encoder_context)
1046 struct gen6_vme_context *vme_context = encoder_context->vme_context;
1047 int mb_x = 0, mb_y = 0;
1049 unsigned int *command_ptr;
1052 dri_bo_map(vme_context->vme_batchbuffer.bo, 1);
1053 command_ptr = vme_context->vme_batchbuffer.bo->virtual;
1055 for (s = 0; s < encode_state->num_slice_params_ext; s++) {
1056 VAEncSliceParameterBufferMPEG2 *slice_param = (VAEncSliceParameterBufferMPEG2 *)encode_state->slice_params_ext[s]->buffer;
1058 for (j = 0; j < encode_state->slice_params_ext[s]->num_elements; j++) {
1059 int slice_mb_begin = slice_param->macroblock_address;
1060 int slice_mb_number = slice_param->num_macroblocks;
1061 unsigned int mb_intra_ub;
1063 for (i = 0; i < slice_mb_number;) {
1064 int mb_count = i + slice_mb_begin;
1066 mb_x = mb_count % mb_width;
1067 mb_y = mb_count / mb_width;
1071 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_AE;
1075 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_B;
1078 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_D;
1080 if (mb_x != (mb_width -1))
1081 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C;
1084 *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2));
1085 *command_ptr++ = kernel;
1092 *command_ptr++ = (mb_width << 16 | mb_y << 8 | mb_x);
1093 *command_ptr++ = ( (1 << 16) | transform_8x8_mode_flag | (mb_intra_ub << 8));
1095 *command_ptr++ = CMD_MEDIA_STATE_FLUSH;
1104 *command_ptr++ = MI_BATCH_BUFFER_END;
1107 dri_bo_unmap(vme_context->vme_batchbuffer.bo);
1111 gen9_vme_mpeg2_pipeline_programing(VADriverContextP ctx,
1112 struct encode_state *encode_state,
1114 struct intel_encoder_context *encoder_context)
1116 struct gen6_vme_context *vme_context = encoder_context->vme_context;
1117 struct intel_batchbuffer *batch = encoder_context->base.batch;
1118 VAEncSequenceParameterBufferMPEG2 *seq_param = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer;
1119 int width_in_mbs = ALIGN(seq_param->picture_width, 16) / 16;
1120 int height_in_mbs = ALIGN(seq_param->picture_height, 16) / 16;
1121 bool allow_hwscore = true;
1124 VAEncPictureParameterBufferMPEG2 *pic_param = NULL;
1126 for (s = 0; s < encode_state->num_slice_params_ext; s++) {
1128 VAEncSliceParameterBufferMPEG2 *slice_param = (VAEncSliceParameterBufferMPEG2 *)encode_state->slice_params_ext[s]->buffer;
1130 for (j = 0; j < encode_state->slice_params_ext[s]->num_elements; j++) {
1131 if (slice_param->macroblock_address % width_in_mbs) {
1132 allow_hwscore = false;
1138 pic_param = (VAEncPictureParameterBufferMPEG2 *)encode_state->pic_param_ext->buffer;
1139 if (pic_param->picture_type == VAEncPictureTypeIntra) {
1140 allow_hwscore = false;
1141 kernel_shader = VME_INTRA_SHADER;
1143 kernel_shader = VME_INTER_SHADER;
1147 gen9wa_vme_mpeg2_walker_fill_vme_batchbuffer(ctx,
1149 width_in_mbs, height_in_mbs,
1153 gen9_vme_mpeg2_fill_vme_batchbuffer(ctx,
1155 width_in_mbs, height_in_mbs,
1156 is_intra ? VME_INTRA_SHADER : VME_INTER_SHADER,
1160 intel_batchbuffer_start_atomic(batch, 0x1000);
1161 gen9_gpe_pipeline_setup(ctx, &vme_context->gpe_context, batch);
1162 BEGIN_BATCH(batch, 4);
1163 OUT_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8) | (1 << 0));
1165 vme_context->vme_batchbuffer.bo,
1166 I915_GEM_DOMAIN_COMMAND, 0,
1168 OUT_BATCH(batch, 0);
1169 OUT_BATCH(batch, 0);
1170 ADVANCE_BATCH(batch);
1172 gen9_gpe_pipeline_end(ctx, &vme_context->gpe_context, batch);
1174 intel_batchbuffer_end_atomic(batch);
1178 gen9_vme_mpeg2_prepare(VADriverContextP ctx,
1179 struct encode_state *encode_state,
1180 struct intel_encoder_context *encoder_context)
1182 VAStatus vaStatus = VA_STATUS_SUCCESS;
1183 VAEncSliceParameterBufferMPEG2 *slice_param = (VAEncSliceParameterBufferMPEG2 *)encode_state->slice_params_ext[0]->buffer;
1184 VAEncSequenceParameterBufferMPEG2 *seq_param = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer;
1185 struct gen6_vme_context *vme_context = encoder_context->vme_context;
1187 if ((!vme_context->mpeg2_level) ||
1188 (vme_context->mpeg2_level != (seq_param->sequence_extension.bits.profile_and_level_indication & MPEG2_LEVEL_MASK))) {
1189 vme_context->mpeg2_level = seq_param->sequence_extension.bits.profile_and_level_indication & MPEG2_LEVEL_MASK;
1192 /*Setup all the memory object*/
1193 gen9_vme_mpeg2_surface_setup(ctx, encode_state, slice_param->is_intra_slice, encoder_context);
1194 gen9_vme_interface_setup(ctx, encode_state, encoder_context);
1195 //gen9_vme_vme_state_setup(ctx, encode_state, slice_param->is_intra_slice, encoder_context);
1196 intel_vme_mpeg2_state_setup(ctx, encode_state, encoder_context);
1197 gen9_vme_constant_setup(ctx, encode_state, encoder_context, 1);
1199 /*Programing media pipeline*/
1200 gen9_vme_mpeg2_pipeline_programing(ctx, encode_state, slice_param->is_intra_slice, encoder_context);
1206 gen9_vme_mpeg2_pipeline(VADriverContextP ctx,
1208 struct encode_state *encode_state,
1209 struct intel_encoder_context *encoder_context)
1211 gen9_vme_media_init(ctx, encoder_context);
1212 gen9_vme_mpeg2_prepare(ctx, encode_state, encoder_context);
1213 gen9_vme_run(ctx, encode_state, encoder_context);
1214 gen9_vme_stop(ctx, encode_state, encoder_context);
1216 return VA_STATUS_SUCCESS;
1220 gen9_vme_vp8_output_buffer_setup(VADriverContextP ctx,
1221 struct encode_state *encode_state,
1224 struct intel_encoder_context *encoder_context)
1226 VAEncSequenceParameterBufferVP8 *seq_param = (VAEncSequenceParameterBufferVP8 *)encode_state->seq_param_ext->buffer;
1227 int width_in_mbs = ALIGN(seq_param->frame_width, 16) / 16;
1228 int height_in_mbs = ALIGN(seq_param->frame_height, 16) / 16;
1230 gen9_vme_output_buffer_setup(ctx, encode_state, index, encoder_context, is_intra, width_in_mbs, height_in_mbs);
1234 gen9_vme_vp8_output_vme_batchbuffer_setup(VADriverContextP ctx,
1235 struct encode_state *encode_state,
1237 struct intel_encoder_context *encoder_context)
1239 VAEncSequenceParameterBufferVP8 *seq_param = (VAEncSequenceParameterBufferVP8 *)encode_state->seq_param_ext->buffer;
1240 int width_in_mbs = ALIGN(seq_param->frame_width, 16) / 16;
1241 int height_in_mbs = ALIGN(seq_param->frame_height, 16) / 16;
1243 gen9_vme_output_vme_batchbuffer_setup(ctx, encode_state, index, encoder_context, width_in_mbs, height_in_mbs);
1247 gen9_vme_vp8_surface_setup(VADriverContextP ctx,
1248 struct encode_state *encode_state,
1250 struct intel_encoder_context *encoder_context)
1252 struct object_surface *obj_surface;
1254 /*Setup surfaces state*/
1255 /* current picture for encoding */
1256 obj_surface = encode_state->input_yuv_object;
1257 gen9_vme_source_surface_state(ctx, 0, obj_surface, encoder_context);
1258 gen9_vme_media_source_surface_state(ctx, 4, obj_surface, encoder_context);
1259 gen9_vme_media_chroma_source_surface_state(ctx, 6, obj_surface, encoder_context);
1263 obj_surface = encode_state->reference_objects[0];
1265 if (obj_surface->bo != NULL)
1266 gen9_vme_source_surface_state(ctx, 1, obj_surface, encoder_context);
1269 obj_surface = encode_state->reference_objects[1];
1271 if (obj_surface && obj_surface->bo != NULL)
1272 gen9_vme_source_surface_state(ctx, 2, obj_surface, encoder_context);
1276 gen9_vme_vp8_output_buffer_setup(ctx, encode_state, 3, is_intra, encoder_context);
1277 gen9_vme_vp8_output_vme_batchbuffer_setup(ctx, encode_state, 5, encoder_context);
1279 return VA_STATUS_SUCCESS;
1283 gen9_vme_vp8_pipeline_programing(VADriverContextP ctx,
1284 struct encode_state *encode_state,
1286 struct intel_encoder_context *encoder_context)
1288 struct gen6_vme_context *vme_context = encoder_context->vme_context;
1289 struct intel_batchbuffer *batch = encoder_context->base.batch;
1290 VAEncSequenceParameterBufferVP8 *seq_param = (VAEncSequenceParameterBufferVP8 *)encode_state->seq_param_ext->buffer;
1291 int width_in_mbs = ALIGN(seq_param->frame_width, 16) / 16;
1292 int height_in_mbs = ALIGN(seq_param->frame_height, 16) / 16;
1293 int kernel_shader = (is_intra ? VME_INTRA_SHADER : VME_INTER_SHADER);
1295 gen9wa_vme_mpeg2_walker_fill_vme_batchbuffer(ctx,
1297 width_in_mbs, height_in_mbs,
1301 intel_batchbuffer_start_atomic(batch, 0x1000);
1302 gen9_gpe_pipeline_setup(ctx, &vme_context->gpe_context, batch);
1303 BEGIN_BATCH(batch, 4);
1304 OUT_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8) | (1 << 0));
1306 vme_context->vme_batchbuffer.bo,
1307 I915_GEM_DOMAIN_COMMAND, 0,
1309 OUT_BATCH(batch, 0);
1310 OUT_BATCH(batch, 0);
1311 ADVANCE_BATCH(batch);
1313 gen9_gpe_pipeline_end(ctx, &vme_context->gpe_context, batch);
1315 intel_batchbuffer_end_atomic(batch);
1318 static VAStatus gen9_vme_vp8_prepare(VADriverContextP ctx,
1319 struct encode_state *encode_state,
1320 struct intel_encoder_context *encoder_context)
1322 VAStatus vaStatus = VA_STATUS_SUCCESS;
1323 VAEncPictureParameterBufferVP8 *pPicParameter = (VAEncPictureParameterBufferVP8 *)encode_state->pic_param_ext->buffer;
1324 int is_intra = !pPicParameter->pic_flags.bits.frame_type;
1326 /* update vp8 mbmv cost */
1327 intel_vme_vp8_update_mbmv_cost(ctx, encode_state, encoder_context);
1329 /*Setup all the memory object*/
1330 gen9_vme_vp8_surface_setup(ctx, encode_state, is_intra, encoder_context);
1331 gen9_vme_interface_setup(ctx, encode_state, encoder_context);
1332 gen9_vme_constant_setup(ctx, encode_state, encoder_context, 1);
1334 /*Programing media pipeline*/
1335 gen9_vme_vp8_pipeline_programing(ctx, encode_state, is_intra, encoder_context);
1341 gen9_vme_vp8_pipeline(VADriverContextP ctx,
1343 struct encode_state *encode_state,
1344 struct intel_encoder_context *encoder_context)
1346 gen9_vme_media_init(ctx, encoder_context);
1347 gen9_vme_vp8_prepare(ctx, encode_state, encoder_context);
1348 gen9_vme_run(ctx, encode_state, encoder_context);
1349 gen9_vme_stop(ctx, encode_state, encoder_context);
1351 return VA_STATUS_SUCCESS;
1357 gen9_vme_hevc_output_buffer_setup(VADriverContextP ctx,
1358 struct encode_state *encode_state,
1360 struct intel_encoder_context *encoder_context)
1363 struct i965_driver_data *i965 = i965_driver_data(ctx);
1364 struct gen6_vme_context *vme_context = encoder_context->vme_context;
1365 VAEncSequenceParameterBufferHEVC *pSequenceParameter = (VAEncSequenceParameterBufferHEVC *)encode_state->seq_param_ext->buffer;
1366 VAEncSliceParameterBufferHEVC *pSliceParameter = (VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[0]->buffer;
1367 int is_intra = pSliceParameter->slice_type == HEVC_SLICE_I;
1368 int width_in_mbs = (pSequenceParameter->pic_width_in_luma_samples + 15)/16;
1369 int height_in_mbs = (pSequenceParameter->pic_height_in_luma_samples + 15)/16;
1372 vme_context->vme_output.num_blocks = width_in_mbs * height_in_mbs;
1373 vme_context->vme_output.pitch = 16; /* in bytes, always 16 */
1376 vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES * 2;
1378 vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES * 24;
1380 * Inter MV . 32-byte Intra search + 16 IME info + 128 IME MV + 32 IME Ref
1381 * + 16 FBR Info + 128 FBR MV + 32 FBR Ref.
1382 * 16 * (2 + 2 * (1 + 8 + 2))= 16 * 24.
1385 vme_context->vme_output.bo = dri_bo_alloc(i965->intel.bufmgr,
1386 "VME output buffer",
1387 vme_context->vme_output.num_blocks * vme_context->vme_output.size_block,
1389 assert(vme_context->vme_output.bo);
1390 vme_context->vme_buffer_suface_setup(ctx,
1391 &vme_context->gpe_context,
1392 &vme_context->vme_output,
1393 BINDING_TABLE_OFFSET(index),
1394 SURFACE_STATE_OFFSET(index));
1398 gen9_vme_hevc_output_vme_batchbuffer_setup(VADriverContextP ctx,
1399 struct encode_state *encode_state,
1401 struct intel_encoder_context *encoder_context)
1404 struct i965_driver_data *i965 = i965_driver_data(ctx);
1405 struct gen6_vme_context *vme_context = encoder_context->vme_context;
1406 VAEncSequenceParameterBufferHEVC *pSequenceParameter = (VAEncSequenceParameterBufferHEVC *)encode_state->seq_param_ext->buffer;
1407 int width_in_mbs = (pSequenceParameter->pic_width_in_luma_samples + 15)/16;
1408 int height_in_mbs = (pSequenceParameter->pic_height_in_luma_samples + 15)/16;
1410 vme_context->vme_batchbuffer.num_blocks = width_in_mbs * height_in_mbs + 1;
1411 vme_context->vme_batchbuffer.size_block = 64; /* 4 OWORDs */
1412 vme_context->vme_batchbuffer.pitch = 16;
1413 vme_context->vme_batchbuffer.bo = dri_bo_alloc(i965->intel.bufmgr,
1415 vme_context->vme_batchbuffer.num_blocks * vme_context->vme_batchbuffer.size_block,
1419 gen9_vme_hevc_surface_setup(VADriverContextP ctx,
1420 struct encode_state *encode_state,
1422 struct intel_encoder_context *encoder_context)
1424 struct object_surface *obj_surface;
1425 VAEncSequenceParameterBufferHEVC *pSequenceParameter = (VAEncSequenceParameterBufferHEVC *)encode_state->seq_param_ext->buffer;
1426 GenHevcSurface *hevc_encoder_surface = NULL;
1428 /*Setup surfaces state*/
1429 /* current picture for encoding */
1430 obj_surface = encode_state->input_yuv_object;
1432 if((pSequenceParameter->seq_fields.bits.bit_depth_luma_minus8 > 0)
1433 || (pSequenceParameter->seq_fields.bits.bit_depth_chroma_minus8 > 0)) {
1434 hevc_encoder_surface = (GenHevcSurface *) obj_surface->private_data;
1435 assert(hevc_encoder_surface);
1436 obj_surface = hevc_encoder_surface->nv12_surface_obj;
1438 gen9_vme_source_surface_state(ctx, 0, obj_surface, encoder_context);
1439 gen9_vme_media_source_surface_state(ctx, 4, obj_surface, encoder_context);
1440 gen9_vme_media_chroma_source_surface_state(ctx, 6, obj_surface, encoder_context);
1443 VAEncSliceParameterBufferHEVC *slice_param = (VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[0]->buffer;
1446 slice_type = slice_param->slice_type;
1447 assert(slice_type != HEVC_SLICE_I);
1450 intel_hevc_vme_reference_state(ctx, encode_state, encoder_context, 0, 1, gen9_vme_source_surface_state);
1452 if (slice_type == HEVC_SLICE_B)
1453 intel_hevc_vme_reference_state(ctx, encode_state, encoder_context, 1, 2, gen9_vme_source_surface_state);
1457 gen9_vme_hevc_output_buffer_setup(ctx, encode_state, 3, encoder_context);
1458 gen9_vme_hevc_output_vme_batchbuffer_setup(ctx, encode_state, 5, encoder_context);
1460 return VA_STATUS_SUCCESS;
1463 gen9wa_vme_hevc_walker_fill_vme_batchbuffer(VADriverContextP ctx,
1464 struct encode_state *encode_state,
1465 int mb_width, int mb_height,
1467 int transform_8x8_mode_flag,
1468 struct intel_encoder_context *encoder_context)
1470 struct gen6_vme_context *vme_context = encoder_context->vme_context;
1473 unsigned int *command_ptr;
1474 VAEncSequenceParameterBufferHEVC *pSequenceParameter = (VAEncSequenceParameterBufferHEVC *)encode_state->seq_param_ext->buffer;
1475 int log2_cu_size = pSequenceParameter->log2_min_luma_coding_block_size_minus3 + 3;
1476 int log2_ctb_size = pSequenceParameter->log2_diff_max_min_luma_coding_block_size + log2_cu_size;
1477 int ctb_size = 1 << log2_ctb_size;
1478 int num_mb_in_ctb = (ctb_size + 15)/16;
1479 num_mb_in_ctb = num_mb_in_ctb * num_mb_in_ctb;
1481 #define USE_SCOREBOARD (1 << 21)
1483 dri_bo_map(vme_context->vme_batchbuffer.bo, 1);
1484 command_ptr = vme_context->vme_batchbuffer.bo->virtual;
1486 /*slice_segment_address must picture_width_in_ctb alainment */
1487 for (s = 0; s < encode_state->num_slice_params_ext; s++) {
1488 VAEncSliceParameterBufferHEVC *pSliceParameter = (VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[s]->buffer;
1489 int first_mb = pSliceParameter->slice_segment_address * num_mb_in_ctb;
1490 int num_mb = pSliceParameter->num_ctu_in_slice * num_mb_in_ctb;
1491 unsigned int mb_intra_ub, score_dep;
1492 int x_outer, y_outer, x_inner, y_inner;
1493 int xtemp_outer = 0;
1495 x_outer = first_mb % mb_width;
1496 y_outer = first_mb / mb_width;
1499 for (; x_outer < (mb_width -2 ) && !loop_in_bounds(x_outer, y_outer, first_mb, num_mb, mb_width, mb_height); ) {
1502 for (; !loop_in_bounds(x_inner, y_inner, first_mb, num_mb, mb_width, mb_height);) {
1506 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_AE;
1507 score_dep |= MB_SCOREBOARD_A;
1509 if (y_inner != mb_row) {
1510 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_B;
1511 score_dep |= MB_SCOREBOARD_B;
1513 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_D;
1514 if (x_inner != (mb_width -1)) {
1515 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C;
1516 score_dep |= MB_SCOREBOARD_C;
1520 *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2));
1521 *command_ptr++ = kernel;
1522 *command_ptr++ = USE_SCOREBOARD;
1525 /* the (X, Y) term of scoreboard */
1526 *command_ptr++ = ((y_inner << 16) | x_inner);
1527 *command_ptr++ = score_dep;
1529 *command_ptr++ = (mb_width << 16 | y_inner << 8 | x_inner);
1530 *command_ptr++ = ((1 << 18) | (1 << 16) | transform_8x8_mode_flag | (mb_intra_ub << 8));
1531 *command_ptr++ = CMD_MEDIA_STATE_FLUSH;
1540 xtemp_outer = mb_width - 2;
1541 if (xtemp_outer < 0)
1543 x_outer = xtemp_outer;
1544 y_outer = first_mb / mb_width;
1545 for (;!loop_in_bounds(x_outer, y_outer, first_mb, num_mb, mb_width, mb_height); ) {
1548 for (; !loop_in_bounds(x_inner, y_inner, first_mb, num_mb, mb_width, mb_height);) {
1552 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_AE;
1553 score_dep |= MB_SCOREBOARD_A;
1555 if (y_inner != mb_row) {
1556 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_B;
1557 score_dep |= MB_SCOREBOARD_B;
1559 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_D;
1561 if (x_inner != (mb_width -1)) {
1562 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C;
1563 score_dep |= MB_SCOREBOARD_C;
1567 *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2));
1568 *command_ptr++ = kernel;
1569 *command_ptr++ = USE_SCOREBOARD;
1572 /* the (X, Y) term of scoreboard */
1573 *command_ptr++ = ((y_inner << 16) | x_inner);
1574 *command_ptr++ = score_dep;
1576 *command_ptr++ = (mb_width << 16 | y_inner << 8 | x_inner);
1577 *command_ptr++ = ((1 << 18) | (1 << 16) | transform_8x8_mode_flag | (mb_intra_ub << 8));
1579 *command_ptr++ = CMD_MEDIA_STATE_FLUSH;
1585 if (x_outer >= mb_width) {
1587 x_outer = xtemp_outer;
1592 *command_ptr++ = MI_BATCH_BUFFER_END;
1595 dri_bo_unmap(vme_context->vme_batchbuffer.bo);
1599 gen9_vme_hevc_fill_vme_batchbuffer(VADriverContextP ctx,
1600 struct encode_state *encode_state,
1601 int mb_width, int mb_height,
1603 int transform_8x8_mode_flag,
1604 struct intel_encoder_context *encoder_context)
1606 struct gen6_vme_context *vme_context = encoder_context->vme_context;
1607 int mb_x = 0, mb_y = 0;
1609 unsigned int *command_ptr;
1610 VAEncSequenceParameterBufferHEVC *pSequenceParameter = (VAEncSequenceParameterBufferHEVC *)encode_state->seq_param_ext->buffer;
1611 int log2_cu_size = pSequenceParameter->log2_min_luma_coding_block_size_minus3 + 3;
1612 int log2_ctb_size = pSequenceParameter->log2_diff_max_min_luma_coding_block_size + log2_cu_size;
1614 int ctb_size = 1 << log2_ctb_size;
1615 int num_mb_in_ctb = (ctb_size + 15)/16;
1616 num_mb_in_ctb = num_mb_in_ctb * num_mb_in_ctb;
1618 dri_bo_map(vme_context->vme_batchbuffer.bo, 1);
1619 command_ptr = vme_context->vme_batchbuffer.bo->virtual;
1621 for (s = 0; s < encode_state->num_slice_params_ext; s++) {
1622 VAEncSliceParameterBufferHEVC *pSliceParameter = (VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[s]->buffer;
1623 int slice_mb_begin = pSliceParameter->slice_segment_address * num_mb_in_ctb;
1624 int slice_mb_number = pSliceParameter->num_ctu_in_slice * num_mb_in_ctb;
1626 unsigned int mb_intra_ub;
1627 int slice_mb_x = slice_mb_begin % mb_width;
1628 for (i = 0; i < slice_mb_number; ) {
1629 int mb_count = i + slice_mb_begin;
1630 mb_x = mb_count % mb_width;
1631 mb_y = mb_count / mb_width;
1635 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_AE;
1638 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_B;
1640 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_D;
1641 if (mb_x != (mb_width -1))
1642 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C;
1646 mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_AE);
1647 mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_BCD_MASK);
1648 if ((i == (mb_width - 1)) && slice_mb_x) {
1649 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C;
1653 if ((i == mb_width) && slice_mb_x) {
1654 mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_D);
1657 *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2));
1658 *command_ptr++ = kernel;
1665 *command_ptr++ = (mb_width << 16 | mb_y << 8 | mb_x);
1666 *command_ptr++ = ( (1 << 16) | transform_8x8_mode_flag | (mb_intra_ub << 8));
1668 *command_ptr++ = CMD_MEDIA_STATE_FLUSH;
1674 *command_ptr++ = MI_BATCH_BUFFER_END;
1677 dri_bo_unmap(vme_context->vme_batchbuffer.bo);
1680 static void gen9_vme_hevc_pipeline_programing(VADriverContextP ctx,
1681 struct encode_state *encode_state,
1682 struct intel_encoder_context *encoder_context)
1684 struct gen6_vme_context *vme_context = encoder_context->vme_context;
1685 struct intel_batchbuffer *batch = encoder_context->base.batch;
1686 VAEncSliceParameterBufferHEVC *pSliceParameter = (VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[0]->buffer;
1687 VAEncSequenceParameterBufferHEVC *pSequenceParameter = (VAEncSequenceParameterBufferHEVC *)encode_state->seq_param_ext->buffer;
1688 int width_in_mbs = (pSequenceParameter->pic_width_in_luma_samples + 15)/16;
1689 int height_in_mbs = (pSequenceParameter->pic_height_in_luma_samples + 15)/16;
1691 bool allow_hwscore = true;
1694 int log2_cu_size = pSequenceParameter->log2_min_luma_coding_block_size_minus3 + 3;
1695 int log2_ctb_size = pSequenceParameter->log2_diff_max_min_luma_coding_block_size + log2_cu_size;
1697 int ctb_size = 1 << log2_ctb_size;
1698 int num_mb_in_ctb = (ctb_size + 15)/16;
1699 int transform_8x8_mode_flag = 1;
1700 num_mb_in_ctb = num_mb_in_ctb * num_mb_in_ctb;
1702 for (s = 0; s < encode_state->num_slice_params_ext; s++) {
1703 pSliceParameter = (VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[s]->buffer;
1704 int slice_mb_begin = pSliceParameter->slice_segment_address * num_mb_in_ctb;
1705 if ((slice_mb_begin % width_in_mbs)) {
1706 allow_hwscore = false;
1711 if (pSliceParameter->slice_type == HEVC_SLICE_I) {
1712 kernel_shader = VME_INTRA_SHADER;
1713 } else if (pSliceParameter->slice_type == HEVC_SLICE_P) {
1714 kernel_shader = VME_INTER_SHADER;
1716 kernel_shader = VME_BINTER_SHADER;
1718 kernel_shader = VME_INTER_SHADER;
1721 gen9wa_vme_hevc_walker_fill_vme_batchbuffer(ctx,
1723 width_in_mbs, height_in_mbs,
1725 transform_8x8_mode_flag,
1728 gen9_vme_hevc_fill_vme_batchbuffer(ctx,
1730 width_in_mbs, height_in_mbs,
1732 transform_8x8_mode_flag,
1735 intel_batchbuffer_start_atomic(batch, 0x1000);
1736 gen9_gpe_pipeline_setup(ctx, &vme_context->gpe_context, batch);
1737 BEGIN_BATCH(batch, 3);
1738 OUT_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8) | (1 << 0));
1740 vme_context->vme_batchbuffer.bo,
1741 I915_GEM_DOMAIN_COMMAND, 0,
1743 OUT_BATCH(batch, 0);
1744 ADVANCE_BATCH(batch);
1746 gen9_gpe_pipeline_end(ctx, &vme_context->gpe_context, batch);
1748 intel_batchbuffer_end_atomic(batch);
1751 static VAStatus gen9_intel_init_hevc_surface(VADriverContextP ctx,
1752 struct intel_encoder_context *encoder_context,
1753 struct encode_state *encode_state,
1754 struct object_surface *input_obj_surface)
1756 struct i965_driver_data *i965 = i965_driver_data(ctx);
1757 struct gen9_hcpe_context *mfc_context = encoder_context->mfc_context;
1758 VAEncSequenceParameterBufferHEVC *pSequenceParameter = (VAEncSequenceParameterBufferHEVC *)encode_state->seq_param_ext->buffer;
1759 GenHevcSurface *hevc_encoder_surface;
1760 struct i965_surface src_surface, dst_surface;
1761 struct object_surface *obj_surface;
1767 obj_surface = input_obj_surface;
1768 assert(obj_surface && obj_surface->bo);
1770 if (obj_surface->private_data == NULL) {
1772 if (mfc_context->pic_size.ctb_size == 16)
1773 size = ((pSequenceParameter->pic_width_in_luma_samples + 63) >> 6) *
1774 ((pSequenceParameter->pic_height_in_luma_samples + 15) >> 4);
1776 size = ((pSequenceParameter->pic_width_in_luma_samples + 31) >> 5) *
1777 ((pSequenceParameter->pic_height_in_luma_samples + 31) >> 5);
1778 size <<= 6; /* in unit of 64bytes */
1780 hevc_encoder_surface = calloc(sizeof(GenHevcSurface), 1);
1782 assert(hevc_encoder_surface);
1783 hevc_encoder_surface->motion_vector_temporal_bo =
1784 dri_bo_alloc(i965->intel.bufmgr,
1785 "motion vector temporal buffer",
1788 assert(hevc_encoder_surface->motion_vector_temporal_bo);
1790 hevc_encoder_surface->ctx = ctx;
1791 hevc_encoder_surface->nv12_surface_obj = NULL;
1792 hevc_encoder_surface->nv12_surface_id = VA_INVALID_SURFACE;
1793 hevc_encoder_surface->has_p010_to_nv12_done = 0;
1795 obj_surface->private_data = (void *)hevc_encoder_surface;
1796 obj_surface->free_private_data = (void *)gen_free_hevc_surface;
1799 hevc_encoder_surface = (GenHevcSurface *) obj_surface->private_data;
1801 if(!hevc_encoder_surface->has_p010_to_nv12_done && obj_surface->fourcc == VA_FOURCC_P010)
1806 rect.width = obj_surface->orig_width;
1807 rect.height = obj_surface->orig_height;
1809 src_surface.base = (struct object_base *)obj_surface;
1810 src_surface.type = I965_SURFACE_TYPE_SURFACE;
1811 src_surface.flags = I965_SURFACE_FLAG_FRAME;
1813 if(SURFACE(hevc_encoder_surface->nv12_surface_id) == NULL)
1815 status = i965_CreateSurfaces(ctx,
1816 obj_surface->orig_width,
1817 obj_surface->orig_height,
1818 VA_RT_FORMAT_YUV420,
1820 &hevc_encoder_surface->nv12_surface_id);
1821 assert(status == VA_STATUS_SUCCESS);
1823 if (status != VA_STATUS_SUCCESS)
1827 obj_surface = SURFACE(hevc_encoder_surface->nv12_surface_id);
1828 hevc_encoder_surface->nv12_surface_obj = obj_surface;
1829 assert(obj_surface);
1830 i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
1832 dst_surface.base = (struct object_base *)obj_surface;
1833 dst_surface.type = I965_SURFACE_TYPE_SURFACE;
1834 dst_surface.flags = I965_SURFACE_FLAG_FRAME;
1836 status = i965_image_processing(ctx,
1841 assert(status == VA_STATUS_SUCCESS);
1842 hevc_encoder_surface->has_p010_to_nv12_done = 1;
1843 i965_SyncSurface(ctx,hevc_encoder_surface->nv12_surface_id);
1845 return VA_STATUS_SUCCESS;
1848 static VAStatus gen9_intel_hevc_input_check(VADriverContextP ctx,
1849 struct encode_state *encode_state,
1850 struct intel_encoder_context *encoder_context)
1852 struct i965_driver_data *i965 = i965_driver_data(ctx);
1853 struct gen9_hcpe_context *mfc_context = encoder_context->mfc_context;
1854 struct object_surface *obj_surface;
1855 GenHevcSurface *hevc_encoder_surface = NULL;
1858 obj_surface = SURFACE(encode_state->current_render_target);
1859 assert(obj_surface && obj_surface->bo);
1860 hevc_encoder_surface = (GenHevcSurface *) obj_surface->private_data;
1861 if(hevc_encoder_surface)
1862 hevc_encoder_surface->has_p010_to_nv12_done = 0;
1863 gen9_intel_init_hevc_surface(ctx,encoder_context,encode_state,obj_surface);
1865 /* Setup current frame and current direct mv buffer*/
1866 obj_surface = encode_state->reconstructed_object;
1867 hevc_encoder_surface = NULL;
1868 hevc_encoder_surface = (GenHevcSurface *) obj_surface->private_data;
1869 if(hevc_encoder_surface)
1870 hevc_encoder_surface->has_p010_to_nv12_done = 1;
1871 gen9_intel_init_hevc_surface(ctx,encoder_context,encode_state,obj_surface);
1873 /* Setup reference frames and direct mv buffers*/
1874 for (i = 0; i < MAX_HCP_REFERENCE_SURFACES; i++) {
1875 obj_surface = encode_state->reference_objects[i];
1877 if (obj_surface && obj_surface->bo) {
1878 mfc_context->reference_surfaces[i].bo = obj_surface->bo;
1879 dri_bo_reference(obj_surface->bo);
1881 gen9_intel_init_hevc_surface(ctx,encoder_context,encode_state,obj_surface);
1887 return VA_STATUS_SUCCESS;
1890 static VAStatus gen9_vme_hevc_prepare(VADriverContextP ctx,
1891 struct encode_state *encode_state,
1892 struct intel_encoder_context *encoder_context)
1894 VAStatus vaStatus = VA_STATUS_SUCCESS;
1895 VAEncSliceParameterBufferHEVC *pSliceParameter = (VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[0]->buffer;
1896 int is_intra = pSliceParameter->slice_type == HEVC_SLICE_I;
1897 VAEncSequenceParameterBufferHEVC *pSequenceParameter = (VAEncSequenceParameterBufferHEVC *)encode_state->seq_param_ext->buffer;
1898 struct gen6_vme_context *vme_context = encoder_context->vme_context;
1900 /* here use the avc level for hevc vme */
1901 if (!vme_context->hevc_level ||
1902 (vme_context->hevc_level != pSequenceParameter->general_level_idc)) {
1903 vme_context->hevc_level = pSequenceParameter->general_level_idc;
1906 //internal input check for main10
1907 gen9_intel_hevc_input_check(ctx,encode_state,encoder_context);
1909 intel_vme_hevc_update_mbmv_cost(ctx, encode_state, encoder_context);
1911 /*Setup all the memory object*/
1912 gen9_vme_hevc_surface_setup(ctx, encode_state, is_intra, encoder_context);
1913 gen9_vme_interface_setup(ctx, encode_state, encoder_context);
1914 //gen9_vme_vme_state_setup(ctx, encode_state, is_intra, encoder_context);
1915 gen9_vme_constant_setup(ctx, encode_state, encoder_context, 1);
1917 /*Programing media pipeline*/
1918 gen9_vme_hevc_pipeline_programing(ctx, encode_state, encoder_context);
1925 gen9_vme_hevc_pipeline(VADriverContextP ctx,
1927 struct encode_state *encode_state,
1928 struct intel_encoder_context *encoder_context)
1930 gen9_vme_media_init(ctx, encoder_context);
1931 gen9_vme_hevc_prepare(ctx, encode_state, encoder_context);
1932 gen9_vme_run(ctx, encode_state, encoder_context);
1933 gen9_vme_stop(ctx, encode_state, encoder_context);
1935 return VA_STATUS_SUCCESS;
1940 gen9_vme_context_destroy(void *context)
1942 struct gen6_vme_context *vme_context = context;
1944 gen8_gpe_context_destroy(&vme_context->gpe_context);
1946 dri_bo_unreference(vme_context->vme_output.bo);
1947 vme_context->vme_output.bo = NULL;
1949 dri_bo_unreference(vme_context->vme_state.bo);
1950 vme_context->vme_state.bo = NULL;
1952 dri_bo_unreference(vme_context->vme_batchbuffer.bo);
1953 vme_context->vme_batchbuffer.bo = NULL;
1955 free(vme_context->vme_state_message);
1956 vme_context->vme_state_message = NULL;
1958 dri_bo_unreference(vme_context->i_qp_cost_table);
1959 vme_context->i_qp_cost_table = NULL;
1961 dri_bo_unreference(vme_context->p_qp_cost_table);
1962 vme_context->p_qp_cost_table = NULL;
1964 dri_bo_unreference(vme_context->b_qp_cost_table);
1965 vme_context->b_qp_cost_table = NULL;
1967 free(vme_context->qp_per_mb);
1968 vme_context->qp_per_mb = NULL;
1973 Bool gen9_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
1975 struct gen6_vme_context *vme_context;
1976 struct i965_kernel *vme_kernel_list = NULL;
1977 int i965_kernel_num;
1979 if (encoder_context->low_power_mode || encoder_context->codec == CODEC_JPEG) {
1980 encoder_context->vme_context = NULL;
1981 encoder_context->vme_pipeline = NULL;
1982 encoder_context->vme_context_destroy = NULL;
1985 } else if (encoder_context->codec == CODEC_VP9) {
1986 return gen9_vp9_vme_context_init(ctx, encoder_context);
1989 vme_context = calloc(1, sizeof(struct gen6_vme_context));
1991 switch (encoder_context->codec) {
1993 case CODEC_H264_MVC:
1994 vme_kernel_list = gen9_vme_kernels;
1995 encoder_context->vme_pipeline = gen9_vme_pipeline;
1996 i965_kernel_num = sizeof(gen9_vme_kernels) / sizeof(struct i965_kernel);
2000 vme_kernel_list = gen9_vme_mpeg2_kernels;
2001 encoder_context->vme_pipeline = gen9_vme_mpeg2_pipeline;
2002 i965_kernel_num = sizeof(gen9_vme_mpeg2_kernels) / sizeof(struct i965_kernel);
2006 vme_kernel_list = gen9_vme_vp8_kernels;
2007 encoder_context->vme_pipeline = gen9_vme_vp8_pipeline;
2008 i965_kernel_num = sizeof(gen9_vme_vp8_kernels) / sizeof(struct i965_kernel);
2012 vme_kernel_list = gen9_vme_hevc_kernels;
2013 encoder_context->vme_pipeline = gen9_vme_hevc_pipeline;
2014 i965_kernel_num = sizeof(gen9_vme_hevc_kernels) / sizeof(struct i965_kernel);
2018 /* never get here */
2024 assert(vme_context);
2025 vme_context->vme_kernel_sum = i965_kernel_num;
2026 vme_context->gpe_context.surface_state_binding_table.length = (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6;
2028 vme_context->gpe_context.idrt_size = sizeof(struct gen8_interface_descriptor_data) * MAX_INTERFACE_DESC_GEN6;
2029 vme_context->gpe_context.curbe_size = CURBE_TOTAL_DATA_LENGTH;
2030 vme_context->gpe_context.sampler_size = 0;
2033 vme_context->gpe_context.vfe_state.max_num_threads = 60 - 1;
2034 vme_context->gpe_context.vfe_state.num_urb_entries = 64;
2035 vme_context->gpe_context.vfe_state.gpgpu_mode = 0;
2036 vme_context->gpe_context.vfe_state.urb_entry_size = 16;
2037 vme_context->gpe_context.vfe_state.curbe_allocation_size = CURBE_ALLOCATION_SIZE - 1;
2039 gen7_vme_scoreboard_init(ctx, vme_context);
2041 gen8_gpe_load_kernels(ctx,
2042 &vme_context->gpe_context,
2045 vme_context->vme_surface2_setup = gen8_gpe_surface2_setup;
2046 vme_context->vme_media_rw_surface_setup = gen8_gpe_media_rw_surface_setup;
2047 vme_context->vme_buffer_suface_setup = gen8_gpe_buffer_suface_setup;
2048 vme_context->vme_media_chroma_surface_setup = gen8_gpe_media_chroma_surface_setup;
2050 encoder_context->vme_context = vme_context;
2051 encoder_context->vme_context_destroy = gen9_vme_context_destroy;
2053 vme_context->vme_state_message = malloc(VME_MSG_LENGTH * sizeof(int));