2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Xiang Haihao <haihao.xiang@intel.com>
33 #include "intel_batchbuffer.h"
34 #include "intel_driver.h"
36 #include "i965_defines.h"
37 #include "i965_drv_video.h"
38 #include "i965_avc_bsd.h"
39 #include "i965_media_h264.h"
40 #include "i965_media.h"
43 i965_avc_bsd_free_avc_bsd_surface(void **data)
45 struct i965_avc_bsd_surface *avc_bsd_surface = *data;
50 dri_bo_unreference(avc_bsd_surface->dmv_top);
51 avc_bsd_surface->dmv_top = NULL;
52 dri_bo_unreference(avc_bsd_surface->dmv_bottom);
53 avc_bsd_surface->dmv_bottom = NULL;
55 free(avc_bsd_surface);
60 i965_avc_bsd_init_avc_bsd_surface(VADriverContextP ctx,
61 struct object_surface *obj_surface,
62 VAPictureParameterBufferH264 *pic_param,
63 struct i965_h264_context *i965_h264_context)
65 struct i965_driver_data *i965 = i965_driver_data(ctx);
66 struct i965_avc_bsd_context *i965_avc_bsd_context = &i965_h264_context->i965_avc_bsd_context;
67 struct i965_avc_bsd_surface *avc_bsd_surface = obj_surface->private_data;
69 obj_surface->free_private_data = i965_avc_bsd_free_avc_bsd_surface;
71 if (!avc_bsd_surface) {
72 avc_bsd_surface = calloc(sizeof(struct i965_avc_bsd_surface), 1);
73 assert((obj_surface->size & 0x3f) == 0);
74 obj_surface->private_data = avc_bsd_surface;
77 avc_bsd_surface->ctx = i965_avc_bsd_context;
78 avc_bsd_surface->dmv_bottom_flag = (pic_param->pic_fields.bits.field_pic_flag &&
79 !pic_param->seq_fields.bits.direct_8x8_inference_flag);
81 if (avc_bsd_surface->dmv_top == NULL) {
82 avc_bsd_surface->dmv_top = dri_bo_alloc(i965->intel.bufmgr,
83 "direct mv w/r buffer",
88 if (avc_bsd_surface->dmv_bottom_flag &&
89 avc_bsd_surface->dmv_bottom == NULL) {
90 avc_bsd_surface->dmv_bottom = dri_bo_alloc(i965->intel.bufmgr,
91 "direct mv w/r buffer",
98 i965_bsd_ind_obj_base_address(VADriverContextP ctx,
99 struct decode_state *decode_state,
101 struct i965_h264_context *i965_h264_context)
104 struct intel_batchbuffer *batch = i965_h264_context->batch;
106 dri_bo *ind_bo = decode_state->slice_datas[slice]->bo;
108 BEGIN_BCS_BATCH(batch, 3);
109 OUT_BCS_BATCH(batch, CMD_BSD_IND_OBJ_BASE_ADDR | (3 - 2));
110 OUT_BCS_RELOC(batch, ind_bo,
111 I915_GEM_DOMAIN_INSTRUCTION, 0,
113 OUT_BCS_BATCH(batch, 0);
114 ADVANCE_BCS_BATCH(batch);
118 i965_avc_bsd_img_state(VADriverContextP ctx,
119 struct decode_state *decode_state,
120 struct i965_h264_context *i965_h264_context)
122 struct intel_batchbuffer *batch = i965_h264_context->batch;
125 int mbaff_frame_flag;
126 unsigned int avc_it_command_header;
127 unsigned int width_in_mbs, height_in_mbs;
128 VAPictureParameterBufferH264 *pic_param;
130 if (decode_state->iq_matrix && decode_state->iq_matrix->buffer)
133 qm_present_flag = 0; /* built-in QM matrices */
135 assert(decode_state->pic_param && decode_state->pic_param->buffer);
136 pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
138 assert(!(pic_param->CurrPic.flags & VA_PICTURE_H264_INVALID));
140 if (pic_param->CurrPic.flags & VA_PICTURE_H264_TOP_FIELD)
142 else if (pic_param->CurrPic.flags & VA_PICTURE_H264_BOTTOM_FIELD)
147 if ((img_struct & 0x1) == 0x1) {
148 assert(pic_param->pic_fields.bits.field_pic_flag == 0x1);
150 assert(pic_param->pic_fields.bits.field_pic_flag == 0x0);
153 if (pic_param->seq_fields.bits.frame_mbs_only_flag) { /* a frame containing only frame macroblocks */
154 assert(pic_param->seq_fields.bits.mb_adaptive_frame_field_flag == 0);
155 assert(pic_param->pic_fields.bits.field_pic_flag == 0);
157 assert(pic_param->seq_fields.bits.direct_8x8_inference_flag == 1); /* see H.264 spec */
160 mbaff_frame_flag = (pic_param->seq_fields.bits.mb_adaptive_frame_field_flag &&
161 !pic_param->pic_fields.bits.field_pic_flag);
163 width_in_mbs = ((pic_param->picture_width_in_mbs_minus1 + 1) & 0xff);
164 height_in_mbs = ((pic_param->picture_height_in_mbs_minus1 + 1) & 0xff); /* frame height */
166 assert(!((width_in_mbs * height_in_mbs) & 0x8000)); /* hardware requirement */
168 /* BSD unit doesn't support 4:2:2 and 4:4:4 picture */
169 assert(pic_param->seq_fields.bits.chroma_format_idc == 0 || /* monochrome picture */
170 pic_param->seq_fields.bits.chroma_format_idc == 1); /* 4:2:0 */
171 assert(pic_param->seq_fields.bits.residual_colour_transform_flag == 0); /* only available for 4:4:4 */
173 avc_it_command_header = (CMD_MEDIA_OBJECT_EX | (12 - 2));
175 BEGIN_BCS_BATCH(batch, 6);
176 OUT_BCS_BATCH(batch, CMD_AVC_BSD_IMG_STATE | (6 - 2));
178 ((width_in_mbs * height_in_mbs) & 0x7fff));
180 (height_in_mbs << 16) |
181 (width_in_mbs << 0));
183 ((pic_param->second_chroma_qp_index_offset & 0x1f) << 24) |
184 ((pic_param->chroma_qp_index_offset & 0x1f) << 16) |
185 (SCAN_RASTER_ORDER << 15) | /* AVC ILDB Data */
186 (SCAN_SPECIAL_ORDER << 14) | /* AVC IT Command */
187 (SCAN_RASTER_ORDER << 13) | /* AVC IT Data */
188 (1 << 12) | /* always 1, hardware requirement */
189 (qm_present_flag << 10) |
191 (16 << 0)); /* FIXME: always support 16 reference frames ??? */
193 (RESIDUAL_DATA_OFFSET << 24) | /* residual data offset */
194 (0 << 17) | /* don't overwrite SRT */
195 (0 << 16) | /* Un-SRT (Unsynchronized Root Thread) */
196 (0 << 12) | /* FIXME: no 16MV ??? */
197 (pic_param->seq_fields.bits.chroma_format_idc << 10) |
198 (i965_h264_context->enable_avc_ildb << 8) | /* Enable ILDB writing output */
199 (pic_param->pic_fields.bits.entropy_coding_mode_flag << 7) |
200 ((!pic_param->pic_fields.bits.reference_pic_flag) << 6) |
201 (pic_param->pic_fields.bits.constrained_intra_pred_flag << 5) |
202 (pic_param->seq_fields.bits.direct_8x8_inference_flag << 4) |
203 (pic_param->pic_fields.bits.transform_8x8_mode_flag << 3) |
204 (pic_param->seq_fields.bits.frame_mbs_only_flag << 2) |
205 (mbaff_frame_flag << 1) |
206 (pic_param->pic_fields.bits.field_pic_flag << 0));
207 OUT_BCS_BATCH(batch, avc_it_command_header);
208 ADVANCE_BCS_BATCH(batch);
212 i965_avc_bsd_qm_state(VADriverContextP ctx,
213 struct decode_state *decode_state,
214 struct i965_h264_context *i965_h264_context)
216 struct intel_batchbuffer *batch = i965_h264_context->batch;
218 VAIQMatrixBufferH264 *iq_matrix;
219 VAPictureParameterBufferH264 *pic_param;
221 if (!decode_state->iq_matrix || !decode_state->iq_matrix->buffer)
224 iq_matrix = (VAIQMatrixBufferH264 *)decode_state->iq_matrix->buffer;
226 assert(decode_state->pic_param && decode_state->pic_param->buffer);
227 pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
229 cmd_len = 2 + 6 * 4; /* always load six 4x4 scaling matrices */
231 if (pic_param->pic_fields.bits.transform_8x8_mode_flag)
232 cmd_len += 2 * 16; /* load two 8x8 scaling matrices */
234 BEGIN_BCS_BATCH(batch, cmd_len);
235 OUT_BCS_BATCH(batch, CMD_AVC_BSD_QM_STATE | (cmd_len - 2));
237 if (pic_param->pic_fields.bits.transform_8x8_mode_flag)
239 (0x0 << 8) | /* don't use default built-in matrices */
240 (0xff << 0)); /* six 4x4 and two 8x8 scaling matrices */
243 (0x0 << 8) | /* don't use default built-in matrices */
244 (0x3f << 0)); /* six 4x4 scaling matrices */
246 intel_batchbuffer_data(batch, &iq_matrix->ScalingList4x4[0][0], 6 * 4 * 4);
248 if (pic_param->pic_fields.bits.transform_8x8_mode_flag)
249 intel_batchbuffer_data(batch, &iq_matrix->ScalingList8x8[0][0], 2 * 16 * 4);
251 ADVANCE_BCS_BATCH(batch);
255 i965_avc_bsd_slice_state(VADriverContextP ctx,
256 VAPictureParameterBufferH264 *pic_param,
257 VASliceParameterBufferH264 *slice_param,
258 struct i965_h264_context *i965_h264_context)
260 struct intel_batchbuffer *batch = i965_h264_context->batch;
261 int present_flag, cmd_len, list, j;
263 unsigned char bottom_idc:1;
264 unsigned char frame_store_index:4;
265 unsigned char field_picture:1;
266 unsigned char long_term:1;
267 unsigned char non_exist:1;
269 char weightoffsets[32 * 6];
271 /* don't issue SLICE_STATE for intra-prediction decoding */
272 if (slice_param->slice_type == SLICE_TYPE_I ||
273 slice_param->slice_type == SLICE_TYPE_SI)
278 if (slice_param->slice_type == SLICE_TYPE_P ||
279 slice_param->slice_type == SLICE_TYPE_SP) {
280 present_flag = PRESENT_REF_LIST0;
283 present_flag = PRESENT_REF_LIST0 | PRESENT_REF_LIST1;
287 if ((slice_param->slice_type == SLICE_TYPE_P ||
288 slice_param->slice_type == SLICE_TYPE_SP) &&
289 (pic_param->pic_fields.bits.weighted_pred_flag == 1)) {
290 present_flag |= PRESENT_WEIGHT_OFFSET_L0;
294 if ((slice_param->slice_type == SLICE_TYPE_B) &&
295 (pic_param->pic_fields.bits.weighted_bipred_idc == 1)) {
296 present_flag |= PRESENT_WEIGHT_OFFSET_L0 | PRESENT_WEIGHT_OFFSET_L1;
300 BEGIN_BCS_BATCH(batch, cmd_len);
301 OUT_BCS_BATCH(batch, CMD_AVC_BSD_SLICE_STATE | (cmd_len - 2));
302 OUT_BCS_BATCH(batch, present_flag);
304 for (list = 0; list < 2; list++) {
306 VAPictureH264 *va_pic;
309 flag = PRESENT_REF_LIST0;
310 va_pic = slice_param->RefPicList0;
312 flag = PRESENT_REF_LIST1;
313 va_pic = slice_param->RefPicList1;
316 if (!(present_flag & flag))
319 for (j = 0; j < 32; j++) {
320 if (va_pic->flags & VA_PICTURE_H264_INVALID) {
321 refs[j].non_exist = 1;
322 refs[j].long_term = 1;
323 refs[j].field_picture = 1;
324 refs[j].frame_store_index = 0xf;
325 refs[j].bottom_idc = 1;
329 for (frame_idx = 0; frame_idx < ARRAY_ELEMS(i965_h264_context->fsid_list); frame_idx++) {
330 if (i965_h264_context->fsid_list[frame_idx].surface_id != VA_INVALID_ID &&
331 va_pic->picture_id == i965_h264_context->fsid_list[frame_idx].surface_id) {
332 assert(frame_idx == i965_h264_context->fsid_list[frame_idx].frame_store_id);
337 assert(frame_idx < ARRAY_ELEMS(i965_h264_context->fsid_list));
339 refs[j].non_exist = 0;
340 refs[j].long_term = !!(va_pic->flags & VA_PICTURE_H264_LONG_TERM_REFERENCE);
341 refs[j].field_picture = !!(va_pic->flags &
342 (VA_PICTURE_H264_TOP_FIELD |
343 VA_PICTURE_H264_BOTTOM_FIELD));
344 refs[j].frame_store_index = frame_idx;
345 refs[j].bottom_idc = !!(va_pic->flags & VA_PICTURE_H264_BOTTOM_FIELD);
351 intel_batchbuffer_data(batch, refs, sizeof(refs));
354 i965_h264_context->weight128_luma_l0 = 0;
355 i965_h264_context->weight128_luma_l1 = 0;
356 i965_h264_context->weight128_chroma_l0 = 0;
357 i965_h264_context->weight128_chroma_l1 = 0;
359 i965_h264_context->weight128_offset0_flag = 0;
360 i965_h264_context->weight128_offset0 = 0;
362 if (present_flag & PRESENT_WEIGHT_OFFSET_L0) {
363 for (j = 0; j < 32; j++) {
364 weightoffsets[j * 6 + 0] = slice_param->luma_offset_l0[j];
365 weightoffsets[j * 6 + 1] = slice_param->luma_weight_l0[j];
366 weightoffsets[j * 6 + 2] = slice_param->chroma_offset_l0[j][0];
367 weightoffsets[j * 6 + 3] = slice_param->chroma_weight_l0[j][0];
368 weightoffsets[j * 6 + 4] = slice_param->chroma_offset_l0[j][1];
369 weightoffsets[j * 6 + 5] = slice_param->chroma_weight_l0[j][1];
371 if (pic_param->pic_fields.bits.weighted_pred_flag == 1 ||
372 pic_param->pic_fields.bits.weighted_bipred_idc == 1) {
373 if (i965_h264_context->use_hw_w128) {
374 if (slice_param->luma_weight_l0[j] == 128)
375 i965_h264_context->weight128_luma_l0 |= (1 << j);
377 if (slice_param->chroma_weight_l0[j][0] == 128 ||
378 slice_param->chroma_weight_l0[j][1] == 128)
379 i965_h264_context->weight128_chroma_l0 |= (1 << j);
381 /* FIXME: workaround for weight 128 */
382 if (slice_param->luma_weight_l0[j] == 128 ||
383 slice_param->chroma_weight_l0[j][0] == 128 ||
384 slice_param->chroma_weight_l0[j][1] == 128)
385 i965_h264_context->weight128_offset0_flag = 1;
390 intel_batchbuffer_data(batch, weightoffsets, sizeof(weightoffsets));
393 if (present_flag & PRESENT_WEIGHT_OFFSET_L1) {
394 for (j = 0; j < 32; j++) {
395 weightoffsets[j * 6 + 0] = slice_param->luma_offset_l1[j];
396 weightoffsets[j * 6 + 1] = slice_param->luma_weight_l1[j];
397 weightoffsets[j * 6 + 2] = slice_param->chroma_offset_l1[j][0];
398 weightoffsets[j * 6 + 3] = slice_param->chroma_weight_l1[j][0];
399 weightoffsets[j * 6 + 4] = slice_param->chroma_offset_l1[j][1];
400 weightoffsets[j * 6 + 5] = slice_param->chroma_weight_l1[j][1];
402 if (pic_param->pic_fields.bits.weighted_bipred_idc == 1) {
403 if (i965_h264_context->use_hw_w128) {
404 if (slice_param->luma_weight_l1[j] == 128)
405 i965_h264_context->weight128_luma_l1 |= (1 << j);
407 if (slice_param->chroma_weight_l1[j][0] == 128 ||
408 slice_param->chroma_weight_l1[j][1] == 128)
409 i965_h264_context->weight128_chroma_l1 |= (1 << j);
411 if (slice_param->luma_weight_l0[j] == 128 ||
412 slice_param->chroma_weight_l0[j][0] == 128 ||
413 slice_param->chroma_weight_l0[j][1] == 128)
414 i965_h264_context->weight128_offset0_flag = 1;
419 intel_batchbuffer_data(batch, weightoffsets, sizeof(weightoffsets));
422 ADVANCE_BCS_BATCH(batch);
426 i965_avc_bsd_buf_base_state(VADriverContextP ctx,
427 VAPictureParameterBufferH264 *pic_param,
428 VASliceParameterBufferH264 *slice_param,
429 struct i965_h264_context *i965_h264_context)
431 struct i965_driver_data *i965 = i965_driver_data(ctx);
432 struct intel_batchbuffer *batch = i965_h264_context->batch;
433 struct i965_avc_bsd_context *i965_avc_bsd_context;
435 VAPictureH264 *va_pic;
436 struct object_surface *obj_surface;
437 struct i965_avc_bsd_surface *avc_bsd_surface;
439 i965_avc_bsd_context = &i965_h264_context->i965_avc_bsd_context;
441 BEGIN_BCS_BATCH(batch, 74);
442 OUT_BCS_BATCH(batch, CMD_AVC_BSD_BUF_BASE_STATE | (74 - 2));
443 OUT_BCS_RELOC(batch, i965_avc_bsd_context->bsd_raw_store.bo,
444 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
446 OUT_BCS_RELOC(batch, i965_avc_bsd_context->mpr_row_store.bo,
447 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
449 OUT_BCS_RELOC(batch, i965_h264_context->avc_it_command_mb_info.bo,
450 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
451 i965_h264_context->avc_it_command_mb_info.mbs * i965_h264_context->use_avc_hw_scoreboard * MB_CMD_IN_BYTES);
452 OUT_BCS_RELOC(batch, i965_h264_context->avc_it_data.bo,
453 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
454 (i965_h264_context->avc_it_data.write_offset << 6));
456 if (i965_h264_context->enable_avc_ildb)
457 OUT_BCS_RELOC(batch, i965_h264_context->avc_ildb_data.bo,
458 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
461 OUT_BCS_BATCH(batch, 0);
463 for (i = 0; i < ARRAY_ELEMS(i965_h264_context->fsid_list); i++) {
464 if (i965_h264_context->fsid_list[i].surface_id != VA_INVALID_ID) {
466 for (j = 0; j < ARRAY_ELEMS(pic_param->ReferenceFrames); j++) {
467 va_pic = &pic_param->ReferenceFrames[j];
469 if (va_pic->flags & VA_PICTURE_H264_INVALID)
472 if (va_pic->picture_id == i965_h264_context->fsid_list[i].surface_id) {
480 if (!(va_pic->flags & VA_PICTURE_H264_INVALID)) {
481 obj_surface = SURFACE(va_pic->picture_id);
483 avc_bsd_surface = obj_surface->private_data;
485 if (avc_bsd_surface == NULL) {
486 OUT_BCS_BATCH(batch, 0);
487 OUT_BCS_BATCH(batch, 0);
489 OUT_BCS_RELOC(batch, avc_bsd_surface->dmv_top,
490 I915_GEM_DOMAIN_INSTRUCTION, 0,
493 if (avc_bsd_surface->dmv_bottom_flag == 1)
494 OUT_BCS_RELOC(batch, avc_bsd_surface->dmv_bottom,
495 I915_GEM_DOMAIN_INSTRUCTION, 0,
498 OUT_BCS_RELOC(batch, avc_bsd_surface->dmv_top,
499 I915_GEM_DOMAIN_INSTRUCTION, 0,
504 OUT_BCS_BATCH(batch, 0);
505 OUT_BCS_BATCH(batch, 0);
509 va_pic = &pic_param->CurrPic;
510 assert(!(va_pic->flags & VA_PICTURE_H264_INVALID));
511 obj_surface = SURFACE(va_pic->picture_id);
513 obj_surface->flags &= ~SURFACE_REF_DIS_MASK;
514 obj_surface->flags |= (pic_param->pic_fields.bits.reference_pic_flag ? SURFACE_REFERENCED : 0);
515 i965_check_alloc_surface_bo(ctx, obj_surface, 0, VA_FOURCC('N','V','1','2'));
516 i965_avc_bsd_init_avc_bsd_surface(ctx, obj_surface, pic_param, i965_h264_context);
517 avc_bsd_surface = obj_surface->private_data;
519 OUT_BCS_RELOC(batch, avc_bsd_surface->dmv_top,
520 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
523 if (avc_bsd_surface->dmv_bottom_flag == 1)
524 OUT_BCS_RELOC(batch, avc_bsd_surface->dmv_bottom,
525 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
528 OUT_BCS_RELOC(batch, avc_bsd_surface->dmv_top,
529 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
533 for (i = 0; i < ARRAY_ELEMS(i965_h264_context->fsid_list); i++) {
534 if (i965_h264_context->fsid_list[i].surface_id != VA_INVALID_ID) {
536 for (j = 0; j < ARRAY_ELEMS(pic_param->ReferenceFrames); j++) {
537 va_pic = &pic_param->ReferenceFrames[j];
539 if (va_pic->flags & VA_PICTURE_H264_INVALID)
542 if (va_pic->picture_id == i965_h264_context->fsid_list[i].surface_id) {
550 if (!(va_pic->flags & VA_PICTURE_H264_INVALID)) {
551 OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
552 OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
555 OUT_BCS_BATCH(batch, 0);
556 OUT_BCS_BATCH(batch, 0);
560 va_pic = &pic_param->CurrPic;
561 OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
562 OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
564 ADVANCE_BCS_BATCH(batch);
568 * Return the bit offset to the first bit of the slice data
570 * VASliceParameterBufferH264.slice_data_bit_offset will point into the part
571 * of slice header if there are some escaped bytes in the slice header. The offset
572 * to slice data is needed for BSD unit so that BSD unit can fetch right slice data
573 * for processing. This fixes conformance case BASQP1_Sony_C.jsv
576 i965_avc_bsd_get_slice_bit_offset(uint8_t *buf, int mode_flag, int in_slice_data_bit_offset)
578 int out_slice_data_bit_offset;
579 int slice_header_size = in_slice_data_bit_offset / 8;
582 for (i = 0, j = 0; i < slice_header_size; i++, j++) {
583 if (!buf[j] && !buf[j + 1] && buf[j + 2] == 3) {
588 out_slice_data_bit_offset = 8 * j + in_slice_data_bit_offset % 8;
590 if (mode_flag == ENTROPY_CABAC)
591 out_slice_data_bit_offset = ALIGN(out_slice_data_bit_offset, 0x8);
593 return out_slice_data_bit_offset;
597 g4x_avc_bsd_object(VADriverContextP ctx,
598 struct decode_state *decode_state,
599 VAPictureParameterBufferH264 *pic_param,
600 VASliceParameterBufferH264 *slice_param,
602 struct i965_h264_context *i965_h264_context)
604 struct intel_batchbuffer *batch = i965_h264_context->batch;
605 int width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
606 int height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; /* frame height */
609 int encrypted, counter_value, cmd_len;
610 int slice_hor_pos, slice_ver_pos;
611 int num_ref_idx_l0, num_ref_idx_l1;
612 int mbaff_picture = (!pic_param->pic_fields.bits.field_pic_flag &&
613 pic_param->seq_fields.bits.mb_adaptive_frame_field_flag);
614 int slice_data_bit_offset;
615 int weighted_pred_idc = 0;
616 int first_mb_in_slice = 0;
618 uint8_t *slice_data = NULL;
620 encrypted = 0; /* FIXME: which flag in VAAPI is used for encryption? */
624 counter_value = 0; /* FIXME: ??? */
628 dri_bo_map(decode_state->slice_datas[slice_index]->bo, 0);
629 slice_data = (uint8_t *)(decode_state->slice_datas[slice_index]->bo->virtual + slice_param->slice_data_offset);
630 slice_data_bit_offset = i965_avc_bsd_get_slice_bit_offset(slice_data,
631 pic_param->pic_fields.bits.entropy_coding_mode_flag,
632 slice_param->slice_data_bit_offset);
633 dri_bo_unmap(decode_state->slice_datas[slice_index]->bo);
635 if (slice_param->slice_type == SLICE_TYPE_I ||
636 slice_param->slice_type == SLICE_TYPE_SI)
637 slice_type = SLICE_TYPE_I;
638 else if (slice_param->slice_type == SLICE_TYPE_P ||
639 slice_param->slice_type == SLICE_TYPE_SP)
640 slice_type = SLICE_TYPE_P;
642 assert(slice_param->slice_type == SLICE_TYPE_B);
643 slice_type = SLICE_TYPE_B;
646 if (slice_type == SLICE_TYPE_I) {
647 assert(slice_param->num_ref_idx_l0_active_minus1 == 0);
648 assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
651 } else if (slice_type == SLICE_TYPE_P) {
652 assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
653 num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
656 num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
657 num_ref_idx_l1 = slice_param->num_ref_idx_l1_active_minus1 + 1;
660 if (slice_type == SLICE_TYPE_P)
661 weighted_pred_idc = pic_param->pic_fields.bits.weighted_pred_flag;
662 else if (slice_type == SLICE_TYPE_B)
663 weighted_pred_idc = pic_param->pic_fields.bits.weighted_bipred_idc;
665 first_mb_in_slice = slice_param->first_mb_in_slice << mbaff_picture;
666 slice_hor_pos = first_mb_in_slice % width_in_mbs;
667 slice_ver_pos = first_mb_in_slice / width_in_mbs;
669 BEGIN_BCS_BATCH(batch, cmd_len);
670 OUT_BCS_BATCH(batch, CMD_AVC_BSD_OBJECT | (cmd_len - 2));
673 ((slice_param->slice_data_size - (slice_data_bit_offset >> 3)) << 0));
675 (slice_param->slice_data_offset +
676 (slice_data_bit_offset >> 3)));
678 (0 << 31) | /* concealment mode: 0->intra 16x16 prediction, 1->inter P Copy */
679 (0 << 14) | /* ignore BSDPrematureComplete Error handling */
680 (0 << 13) | /* FIXME: ??? */
681 (0 << 12) | /* ignore MPR Error handling */
682 (0 << 10) | /* ignore Entropy Error handling */
683 (0 << 8) | /* ignore MB Header Error handling */
686 (num_ref_idx_l1 << 24) |
687 (num_ref_idx_l0 << 16) |
688 (slice_param->chroma_log2_weight_denom << 8) |
689 (slice_param->luma_log2_weight_denom << 0));
691 (weighted_pred_idc << 30) |
692 (slice_param->direct_spatial_mv_pred_flag << 29) |
693 (slice_param->disable_deblocking_filter_idc << 27) |
694 (slice_param->cabac_init_idc << 24) |
695 ((pic_param->pic_init_qp_minus26 + 26 + slice_param->slice_qp_delta) << 16) |
696 ((slice_param->slice_beta_offset_div2 & 0xf) << 8) |
697 ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0));
699 (slice_ver_pos << 24) |
700 (slice_hor_pos << 16) |
701 (first_mb_in_slice << 0));
703 (0 << 7) | /* FIXME: ??? */
704 ((0x7 - (slice_data_bit_offset & 0x7)) << 0));
707 OUT_BCS_BATCH(batch, counter_value);
710 ADVANCE_BCS_BATCH(batch);
712 BEGIN_BCS_BATCH(batch, 8);
713 OUT_BCS_BATCH(batch, CMD_AVC_BSD_OBJECT | (8 - 2));
714 OUT_BCS_BATCH(batch, 0); /* indirect data length for phantom slice is 0 */
715 OUT_BCS_BATCH(batch, 0); /* indirect data start address for phantom slice is 0 */
716 OUT_BCS_BATCH(batch, 0);
717 OUT_BCS_BATCH(batch, 0);
718 OUT_BCS_BATCH(batch, 0);
719 OUT_BCS_BATCH(batch, width_in_mbs * height_in_mbs / (1 + !!pic_param->pic_fields.bits.field_pic_flag));
720 OUT_BCS_BATCH(batch, 0);
721 ADVANCE_BCS_BATCH(batch);
726 ironlake_avc_bsd_object(VADriverContextP ctx,
727 struct decode_state *decode_state,
728 VAPictureParameterBufferH264 *pic_param,
729 VASliceParameterBufferH264 *slice_param,
731 struct i965_h264_context *i965_h264_context)
733 struct intel_batchbuffer *batch = i965_h264_context->batch;
734 int width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
735 int height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; /* frame height */
738 int encrypted, counter_value;
739 int slice_hor_pos, slice_ver_pos;
740 int num_ref_idx_l0, num_ref_idx_l1;
741 int mbaff_picture = (!pic_param->pic_fields.bits.field_pic_flag &&
742 pic_param->seq_fields.bits.mb_adaptive_frame_field_flag);
743 int slice_data_bit_offset;
744 int weighted_pred_idc = 0;
745 int first_mb_in_slice;
747 uint8_t *slice_data = NULL;
749 encrypted = 0; /* FIXME: which flag in VAAPI is used for encryption? */
752 counter_value = 0; /* FIXME: ??? */
756 dri_bo_map(decode_state->slice_datas[slice_index]->bo, 0);
757 slice_data = (uint8_t *)(decode_state->slice_datas[slice_index]->bo->virtual + slice_param->slice_data_offset);
758 slice_data_bit_offset = i965_avc_bsd_get_slice_bit_offset(slice_data,
759 pic_param->pic_fields.bits.entropy_coding_mode_flag,
760 slice_param->slice_data_bit_offset);
761 dri_bo_unmap(decode_state->slice_datas[slice_index]->bo);
763 if (slice_param->slice_type == SLICE_TYPE_I ||
764 slice_param->slice_type == SLICE_TYPE_SI)
765 slice_type = SLICE_TYPE_I;
766 else if (slice_param->slice_type == SLICE_TYPE_P ||
767 slice_param->slice_type == SLICE_TYPE_SP)
768 slice_type = SLICE_TYPE_P;
770 assert(slice_param->slice_type == SLICE_TYPE_B);
771 slice_type = SLICE_TYPE_B;
774 if (slice_type == SLICE_TYPE_I) {
775 assert(slice_param->num_ref_idx_l0_active_minus1 == 0);
776 assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
779 } else if (slice_type == SLICE_TYPE_P) {
780 assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
781 num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
784 num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
785 num_ref_idx_l1 = slice_param->num_ref_idx_l1_active_minus1 + 1;
788 if (slice_type == SLICE_TYPE_P)
789 weighted_pred_idc = pic_param->pic_fields.bits.weighted_pred_flag;
790 else if (slice_type == SLICE_TYPE_B)
791 weighted_pred_idc = pic_param->pic_fields.bits.weighted_bipred_idc;
793 first_mb_in_slice = slice_param->first_mb_in_slice << mbaff_picture;
794 slice_hor_pos = first_mb_in_slice % width_in_mbs;
795 slice_ver_pos = first_mb_in_slice / width_in_mbs;
797 BEGIN_BCS_BATCH(batch, 16);
798 OUT_BCS_BATCH(batch, CMD_AVC_BSD_OBJECT | (16 - 2));
801 (0 << 30) | /* FIXME: packet based bit stream */
802 (0 << 29) | /* FIXME: packet format */
803 ((slice_param->slice_data_size - (slice_data_bit_offset >> 3)) << 0));
805 (slice_param->slice_data_offset +
806 (slice_data_bit_offset >> 3)));
808 (0 << 31) | /* concealment mode: 0->intra 16x16 prediction, 1->inter P Copy */
809 (0 << 14) | /* ignore BSDPrematureComplete Error handling */
810 (0 << 13) | /* FIXME: ??? */
811 (0 << 12) | /* ignore MPR Error handling */
812 (0 << 10) | /* ignore Entropy Error handling */
813 (0 << 8) | /* ignore MB Header Error handling */
816 (num_ref_idx_l1 << 24) |
817 (num_ref_idx_l0 << 16) |
818 (slice_param->chroma_log2_weight_denom << 8) |
819 (slice_param->luma_log2_weight_denom << 0));
821 (weighted_pred_idc << 30) |
822 (slice_param->direct_spatial_mv_pred_flag << 29) |
823 (slice_param->disable_deblocking_filter_idc << 27) |
824 (slice_param->cabac_init_idc << 24) |
825 ((pic_param->pic_init_qp_minus26 + 26 + slice_param->slice_qp_delta) << 16) |
826 ((slice_param->slice_beta_offset_div2 & 0xf) << 8) |
827 ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0));
829 (slice_ver_pos << 24) |
830 (slice_hor_pos << 16) |
831 (first_mb_in_slice << 0));
833 (0 << 7) | /* FIXME: ??? */
834 ((0x7 - (slice_data_bit_offset & 0x7)) << 0));
835 OUT_BCS_BATCH(batch, counter_value);
837 /* FIXME: dw9-dw11 */
838 OUT_BCS_BATCH(batch, 0);
839 OUT_BCS_BATCH(batch, 0);
840 OUT_BCS_BATCH(batch, 0);
841 OUT_BCS_BATCH(batch, i965_h264_context->weight128_luma_l0);
842 OUT_BCS_BATCH(batch, i965_h264_context->weight128_luma_l1);
843 OUT_BCS_BATCH(batch, i965_h264_context->weight128_chroma_l0);
844 OUT_BCS_BATCH(batch, i965_h264_context->weight128_chroma_l1);
846 ADVANCE_BCS_BATCH(batch);
848 BEGIN_BCS_BATCH(batch, 16);
849 OUT_BCS_BATCH(batch, CMD_AVC_BSD_OBJECT | (16 - 2));
850 OUT_BCS_BATCH(batch, 0); /* indirect data length for phantom slice is 0 */
851 OUT_BCS_BATCH(batch, 0); /* indirect data start address for phantom slice is 0 */
852 OUT_BCS_BATCH(batch, 0);
853 OUT_BCS_BATCH(batch, 0);
854 OUT_BCS_BATCH(batch, 0);
855 OUT_BCS_BATCH(batch, width_in_mbs * height_in_mbs / (1 + !!pic_param->pic_fields.bits.field_pic_flag));
856 OUT_BCS_BATCH(batch, 0);
857 OUT_BCS_BATCH(batch, 0);
858 OUT_BCS_BATCH(batch, 0);
859 OUT_BCS_BATCH(batch, 0);
860 OUT_BCS_BATCH(batch, 0);
861 OUT_BCS_BATCH(batch, 0);
862 OUT_BCS_BATCH(batch, 0);
863 OUT_BCS_BATCH(batch, 0);
864 OUT_BCS_BATCH(batch, 0);
865 ADVANCE_BCS_BATCH(batch);
870 i965_avc_bsd_object(VADriverContextP ctx,
871 struct decode_state *decode_state,
872 VAPictureParameterBufferH264 *pic_param,
873 VASliceParameterBufferH264 *slice_param,
875 struct i965_h264_context *i965_h264_context)
877 struct i965_driver_data *i965 = i965_driver_data(ctx);
879 if (IS_IRONLAKE(i965->intel.device_id))
880 ironlake_avc_bsd_object(ctx, decode_state, pic_param, slice_param, slice_index, i965_h264_context);
882 g4x_avc_bsd_object(ctx, decode_state, pic_param, slice_param, slice_index, i965_h264_context);
886 i965_avc_bsd_phantom_slice(VADriverContextP ctx,
887 struct decode_state *decode_state,
888 VAPictureParameterBufferH264 *pic_param,
889 struct i965_h264_context *i965_h264_context)
891 i965_avc_bsd_object(ctx, decode_state, pic_param, NULL, 0, i965_h264_context);
895 i965_avc_bsd_frame_store_index(VADriverContextP ctx,
896 VAPictureParameterBufferH264 *pic_param,
897 struct i965_h264_context *i965_h264_context)
899 struct i965_driver_data *i965 = i965_driver_data(ctx);
902 assert(ARRAY_ELEMS(i965_h264_context->fsid_list) == ARRAY_ELEMS(pic_param->ReferenceFrames));
904 for (i = 0; i < ARRAY_ELEMS(i965_h264_context->fsid_list); i++) {
907 if (i965_h264_context->fsid_list[i].surface_id == VA_INVALID_ID)
910 for (j = 0; j < ARRAY_ELEMS(pic_param->ReferenceFrames); j++) {
911 VAPictureH264 *ref_pic = &pic_param->ReferenceFrames[j];
912 if (ref_pic->flags & VA_PICTURE_H264_INVALID)
915 if (i965_h264_context->fsid_list[i].surface_id == ref_pic->picture_id) {
922 struct object_surface *obj_surface = SURFACE(i965_h264_context->fsid_list[i].surface_id);
923 obj_surface->flags &= ~SURFACE_REFERENCED;
925 if ((obj_surface->flags & SURFACE_ALL_MASK) == SURFACE_DISPLAYED) {
926 dri_bo_unreference(obj_surface->bo);
927 obj_surface->bo = NULL;
928 obj_surface->flags &= ~SURFACE_REF_DIS_MASK;
931 if (obj_surface->free_private_data)
932 obj_surface->free_private_data(&obj_surface->private_data);
934 i965_h264_context->fsid_list[i].surface_id = VA_INVALID_ID;
935 i965_h264_context->fsid_list[i].frame_store_id = -1;
939 for (i = 0; i < ARRAY_ELEMS(pic_param->ReferenceFrames); i++) {
940 VAPictureH264 *ref_pic = &pic_param->ReferenceFrames[i];
943 if (ref_pic->flags & VA_PICTURE_H264_INVALID)
946 for (j = 0; j < ARRAY_ELEMS(i965_h264_context->fsid_list); j++) {
947 if (i965_h264_context->fsid_list[j].surface_id == VA_INVALID_ID)
950 if (i965_h264_context->fsid_list[j].surface_id == ref_pic->picture_id) {
958 struct object_surface *obj_surface = SURFACE(ref_pic->picture_id);
960 i965_check_alloc_surface_bo(ctx, obj_surface, 0, VA_FOURCC('N','V','1','2'));
962 for (frame_idx = 0; frame_idx < ARRAY_ELEMS(i965_h264_context->fsid_list); frame_idx++) {
963 for (j = 0; j < ARRAY_ELEMS(i965_h264_context->fsid_list); j++) {
964 if (i965_h264_context->fsid_list[j].surface_id == VA_INVALID_ID)
967 if (i965_h264_context->fsid_list[j].frame_store_id == frame_idx)
971 if (j == ARRAY_ELEMS(i965_h264_context->fsid_list))
975 assert(frame_idx < ARRAY_ELEMS(i965_h264_context->fsid_list));
977 for (j = 0; j < ARRAY_ELEMS(i965_h264_context->fsid_list); j++) {
978 if (i965_h264_context->fsid_list[j].surface_id == VA_INVALID_ID) {
979 i965_h264_context->fsid_list[j].surface_id = ref_pic->picture_id;
980 i965_h264_context->fsid_list[j].frame_store_id = frame_idx;
987 for (i = 0; i < ARRAY_ELEMS(i965_h264_context->fsid_list) - 1; i++) {
988 if (i965_h264_context->fsid_list[i].surface_id != VA_INVALID_ID &&
989 i965_h264_context->fsid_list[i].frame_store_id == i)
992 for (j = i + 1; j < ARRAY_ELEMS(i965_h264_context->fsid_list); j++) {
993 if (i965_h264_context->fsid_list[j].surface_id != VA_INVALID_ID &&
994 i965_h264_context->fsid_list[j].frame_store_id == i) {
995 VASurfaceID id = i965_h264_context->fsid_list[i].surface_id;
996 int frame_idx = i965_h264_context->fsid_list[i].frame_store_id;
998 i965_h264_context->fsid_list[i].surface_id = i965_h264_context->fsid_list[j].surface_id;
999 i965_h264_context->fsid_list[i].frame_store_id = i965_h264_context->fsid_list[j].frame_store_id;
1000 i965_h264_context->fsid_list[j].surface_id = id;
1001 i965_h264_context->fsid_list[j].frame_store_id = frame_idx;
1009 i965_avc_bsd_pipeline(VADriverContextP ctx, struct decode_state *decode_state, void *h264_context)
1011 struct i965_h264_context *i965_h264_context = (struct i965_h264_context *)h264_context;
1012 struct intel_batchbuffer *batch = i965_h264_context->batch;
1013 VAPictureParameterBufferH264 *pic_param;
1014 VASliceParameterBufferH264 *slice_param;
1017 assert(decode_state->pic_param && decode_state->pic_param->buffer);
1018 pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
1019 i965_avc_bsd_frame_store_index(ctx, pic_param, i965_h264_context);
1021 i965_h264_context->enable_avc_ildb = 0;
1022 i965_h264_context->picture.i_flag = 1;
1024 for (j = 0; j < decode_state->num_slice_params && i965_h264_context->enable_avc_ildb == 0; j++) {
1025 assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
1026 slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
1028 for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
1029 assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
1030 assert((slice_param->slice_type == SLICE_TYPE_I) ||
1031 (slice_param->slice_type == SLICE_TYPE_SI) ||
1032 (slice_param->slice_type == SLICE_TYPE_P) ||
1033 (slice_param->slice_type == SLICE_TYPE_SP) ||
1034 (slice_param->slice_type == SLICE_TYPE_B));
1036 if (slice_param->disable_deblocking_filter_idc != 1) {
1037 i965_h264_context->enable_avc_ildb = 1;
1045 intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
1047 i965_avc_bsd_img_state(ctx, decode_state, i965_h264_context);
1048 i965_avc_bsd_qm_state(ctx, decode_state, i965_h264_context);
1050 for (j = 0; j < decode_state->num_slice_params; j++) {
1051 assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
1052 slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
1054 i965_bsd_ind_obj_base_address(ctx, decode_state, j, i965_h264_context);
1056 for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
1057 assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
1058 assert((slice_param->slice_type == SLICE_TYPE_I) ||
1059 (slice_param->slice_type == SLICE_TYPE_SI) ||
1060 (slice_param->slice_type == SLICE_TYPE_P) ||
1061 (slice_param->slice_type == SLICE_TYPE_SP) ||
1062 (slice_param->slice_type == SLICE_TYPE_B));
1064 if (i965_h264_context->picture.i_flag &&
1065 (slice_param->slice_type != SLICE_TYPE_I ||
1066 slice_param->slice_type != SLICE_TYPE_SI))
1067 i965_h264_context->picture.i_flag = 0;
1069 i965_avc_bsd_slice_state(ctx, pic_param, slice_param, i965_h264_context);
1070 i965_avc_bsd_buf_base_state(ctx, pic_param, slice_param, i965_h264_context);
1071 i965_avc_bsd_object(ctx, decode_state, pic_param, slice_param, j, i965_h264_context);
1076 i965_avc_bsd_phantom_slice(ctx, decode_state, pic_param, i965_h264_context);
1077 intel_batchbuffer_emit_mi_flush(batch);
1078 intel_batchbuffer_end_atomic(batch);
1079 intel_batchbuffer_flush(batch);
1083 i965_avc_bsd_decode_init(VADriverContextP ctx, void *h264_context)
1085 struct i965_driver_data *i965 = i965_driver_data(ctx);
1086 struct i965_h264_context *i965_h264_context = (struct i965_h264_context *)h264_context;
1087 struct i965_avc_bsd_context *i965_avc_bsd_context;
1090 assert(i965_h264_context);
1091 i965_avc_bsd_context = &i965_h264_context->i965_avc_bsd_context;
1093 dri_bo_unreference(i965_avc_bsd_context->bsd_raw_store.bo);
1094 bo = dri_bo_alloc(i965->intel.bufmgr,
1096 0x3000, /* at least 11520 bytes to support 120 MBs per row */
1099 i965_avc_bsd_context->bsd_raw_store.bo = bo;
1101 dri_bo_unreference(i965_avc_bsd_context->mpr_row_store.bo);
1102 bo = dri_bo_alloc(i965->intel.bufmgr,
1104 0x2000, /* at least 7680 bytes to support 120 MBs per row */
1107 i965_avc_bsd_context->mpr_row_store.bo = bo;
1111 i965_avc_bsd_ternimate(struct i965_avc_bsd_context *i965_avc_bsd_context)
1113 dri_bo_unreference(i965_avc_bsd_context->bsd_raw_store.bo);
1114 dri_bo_unreference(i965_avc_bsd_context->mpr_row_store.bo);