2 * Copyright @ 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWAR OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Pengfei Qu <Pengfei.Qu@intel.com>
29 #ifndef _I965_AVC_ENCODER_COMMON_H
30 #define _I965_AVC_ENCODER_COMMON_H
37 #include "intel_driver.h"
38 #include "i965_avc_encoder.h"
40 // SubMbPartMask defined in CURBE for AVC ENC
41 #define INTEL_AVC_DISABLE_4X4_SUB_MB_PARTITION 0x40
42 #define INTEL_AVC_DISABLE_4X8_SUB_MB_PARTITION 0x20
43 #define INTEL_AVC_DISABLE_8X4_SUB_MB_PARTITION 0x10
44 #define INTEL_AVC_MAX_BWD_REF_NUM 2
45 #define INTEL_AVC_MAX_FWD_REF_NUM 8
47 #define MAX_MFC_AVC_REFERENCE_SURFACES 16
48 #define NUM_MFC_AVC_DMV_BUFFERS 34
49 #define MAX_HCP_REFERENCE_SURFACES 8
50 #define NUM_HCP_CURRENT_COLLOCATED_MV_TEMPORAL_BUFFERS 9
52 #define INTEL_AVC_IMAGE_STATE_CMD_SIZE 128
53 #define INTEL_AVC_MIN_QP 1
54 #define INTEL_AVC_MAX_QP 51
56 #define INTEL_AVC_WP_MODE_DEFAULT 0
57 #define INTEL_AVC_WP_MODE_EXPLICIT 1
58 #define INTEL_AVC_WP_MODE_IMPLICIT 2
60 #define AVC_NAL_DELIMITER 9
64 // original width/height
65 uint32_t frame_width_in_pixel;
66 uint32_t frame_height_in_pixel;
67 uint32_t frame_width_in_mbs;
68 uint32_t frame_height_in_mbs;
69 uint32_t frames_per_100s;
70 uint32_t vbv_buffer_size_in_bit;
71 uint32_t target_bit_rate;
75 INTEL_AVC_BASE_PROFILE = 66,
76 INTEL_AVC_MAIN_PROFILE = 77,
77 INTEL_AVC_EXTENDED_PROFILE = 88,
78 INTEL_AVC_HIGH_PROFILE = 100,
79 INTEL_AVC_HIGH10_PROFILE = 110
80 } INTEL_AVC_PROFILE_IDC;
83 INTEL_AVC_LEVEL_1 = 10,
84 INTEL_AVC_LEVEL_11 = 11,
85 INTEL_AVC_LEVEL_12 = 12,
86 INTEL_AVC_LEVEL_13 = 13,
87 INTEL_AVC_LEVEL_2 = 20,
88 INTEL_AVC_LEVEL_21 = 21,
89 INTEL_AVC_LEVEL_22 = 22,
90 INTEL_AVC_LEVEL_3 = 30,
91 INTEL_AVC_LEVEL_31 = 31,
92 INTEL_AVC_LEVEL_32 = 32,
93 INTEL_AVC_LEVEL_4 = 40,
94 INTEL_AVC_LEVEL_41 = 41,
95 INTEL_AVC_LEVEL_42 = 42,
96 INTEL_AVC_LEVEL_5 = 50,
97 INTEL_AVC_LEVEL_51 = 51,
98 INTEL_AVC_LEVEL_52 = 52,
99 INTEL_AVC_LEVEL_6 = 60,
100 INTEL_AVC_LEVEL_61 = 61,
101 INTEL_AVC_LEVEL_62 = 62,
102 } INTEL_AVC_LEVEL_IDC;
105 common structure and define
107 struct i965_avc_encoder_context {
109 VADriverContextP ctx;
112 //mbbrc/brc:init/reset/update
113 struct i965_gpe_resource res_brc_history_buffer;
114 struct i965_gpe_resource res_brc_dist_data_surface;
116 struct i965_gpe_resource res_brc_pre_pak_statistics_output_buffer;
117 struct i965_gpe_resource res_brc_image_state_read_buffer;
118 struct i965_gpe_resource res_brc_image_state_write_buffer;
119 struct i965_gpe_resource res_brc_mbenc_curbe_read_buffer;
120 struct i965_gpe_resource res_brc_mbenc_curbe_write_buffer;
121 struct i965_gpe_resource res_brc_const_data_buffer;
123 struct i965_gpe_resource res_mb_status_buffer;
125 struct i965_gpe_resource res_mbbrc_mb_qp_data_surface;
126 struct i965_gpe_resource res_mbbrc_roi_surface;
127 struct i965_gpe_resource res_mbbrc_const_data_buffer;
130 struct i965_gpe_resource res_mbenc_slice_map_surface;
131 struct i965_gpe_resource res_mbenc_brc_buffer;//gen95
133 //scaling flatness check surface
134 struct i965_gpe_resource res_flatness_check_surface;
136 struct i965_gpe_resource s4x_memv_min_distortion_brc_buffer;
137 struct i965_gpe_resource s4x_memv_distortion_buffer;
138 struct i965_gpe_resource s4x_memv_data_buffer;
139 struct i965_gpe_resource s16x_memv_data_buffer;
140 struct i965_gpe_resource s32x_memv_data_buffer;
143 struct i965_gpe_resource res_image_state_batch_buffer_2nd_level;
144 struct intel_batchbuffer *pres_slice_batch_buffer_2nd_level;
145 // mb code/data or indrirect mv data, define in private avc surface
148 struct i965_gpe_resource res_sfd_output_buffer;
149 struct i965_gpe_resource res_sfd_cost_table_p_frame_buffer;
150 struct i965_gpe_resource res_sfd_cost_table_b_frame_buffer;
152 //external mb qp data,application input
153 struct i965_gpe_resource res_mb_qp_data_surface;
155 struct i965_gpe_resource res_mad_data_buffer;
158 VASurfaceID wp_output_pic_select_surface_id[2];
159 struct object_surface *wp_output_pic_select_surface_obj[2];
160 struct i965_gpe_resource res_wp_output_pic_select_surface_list[2];
163 struct i965_gpe_resource res_mb_disable_skip_map_surface;
167 struct i965_gpe_resource res_intra_row_store_scratch_buffer;
168 struct i965_gpe_resource res_deblocking_filter_row_store_scratch_buffer;
169 struct i965_gpe_resource res_deblocking_filter_tile_col_buffer;
170 struct i965_gpe_resource res_bsd_mpc_row_store_scratch_buffer;
171 struct i965_gpe_resource res_mfc_indirect_bse_object;
172 struct i965_gpe_resource res_pak_mb_status_buffer;
173 struct i965_gpe_resource res_direct_mv_buffersr[NUM_MFC_AVC_DMV_BUFFERS];//INTERNAL: 0-31 as input,32 and 33 as output
176 struct i965_gpe_resource res_post_deblocking_output;
177 struct i965_gpe_resource res_pre_deblocking_output;
180 struct i965_gpe_resource list_reference_res[MAX_MFC_AVC_REFERENCE_SURFACES];
182 //preenc downscale surfae
183 VASurfaceID preenc_scaled_4x_surface_id;
184 struct object_surface *preenc_scaled_4x_surface_obj;
185 VASurfaceID preenc_past_ref_scaled_4x_surface_id;
186 struct object_surface *preenc_past_ref_scaled_4x_surface_obj;
187 VASurfaceID preenc_future_ref_scaled_4x_surface_id;
188 struct object_surface *preenc_future_ref_scaled_4x_surface_obj;
189 struct i965_gpe_resource preenc_past_ref_stat_data_out_buffer;
190 struct i965_gpe_resource preenc_future_ref_stat_data_out_buffer;
193 struct i965_gpe_resource preproc_mv_predictor_buffer;
194 struct i965_gpe_resource preproc_mb_qp_buffer;
195 struct i965_gpe_resource preproc_mv_data_out_buffer;
196 struct i965_gpe_resource preproc_stat_data_out_buffer;
199 struct gen_avc_scaling_context context_scaling;
200 struct gen_avc_me_context context_me;
201 struct gen_avc_brc_context context_brc;
202 struct gen_avc_mbenc_context context_mbenc;
203 struct gen_avc_wp_context context_wp;
204 struct gen_avc_sfd_context context_sfd;
205 struct gen_avc_preproc_context context_preproc;
207 struct encoder_status_buffer_internal status_buffer;
211 #define MAX_AVC_SLICE_NUM 256
212 struct avc_enc_state {
214 VAEncSequenceParameterBufferH264 *seq_param;
215 VAEncPictureParameterBufferH264 *pic_param;
216 VAEncSliceParameterBufferH264 *slice_param[MAX_AVC_SLICE_NUM];
217 VAEncMacroblockParameterBufferH264 *mb_param;
218 VAEncMiscParameterFEIFrameControlH264 *fei_framectl_param;
219 VAStatsStatisticsParameterH264 *stat_param;
220 uint32_t mad_enable: 1;
222 uint32_t mb_disable_skip_map_enable: 1;
223 //static frame detection
224 uint32_t sfd_enable: 1;
225 uint32_t sfd_mb_enable: 1;
226 uint32_t adaptive_search_window_enable: 1;
228 uint32_t mb_qp_data_enable: 1;
229 //rolling intra refresh
230 uint32_t intra_refresh_i_enable: 1;
231 uint32_t min_max_qp_enable: 1;
232 uint32_t skip_bias_adjustment_enable: 1;
234 uint32_t non_ftq_skip_threshold_lut_input_enable: 1;
235 uint32_t ftq_skip_threshold_lut_input_enable: 1;
236 uint32_t ftq_override: 1;
237 uint32_t direct_bias_adjustment_enable: 1;
238 uint32_t global_motion_bias_adjustment_enable: 1;
239 uint32_t disable_sub_mb_partion: 1;
240 uint32_t arbitrary_num_mbs_in_slice: 1;
241 uint32_t adaptive_transform_decision_enable: 1;
242 uint32_t skip_check_disable: 1;
243 uint32_t tq_enable: 1;
244 uint32_t enable_avc_ildb: 1;
245 uint32_t suppress_recon_enable: 1;
246 uint32_t flatness_check_supported: 1;
247 uint32_t transform_8x8_mode_enable: 1;
248 uint32_t caf_supported: 1;
249 uint32_t mb_status_enable: 1;
250 uint32_t mbaff_flag: 1;
251 uint32_t enable_force_skip: 1;
252 uint32_t rc_panic_enable: 1;
253 uint32_t reserved0: 7;
256 uint32_t ref_pic_select_list_supported: 1;
257 uint32_t mb_brc_supported: 1;
258 uint32_t multi_pre_enable: 1;
259 uint32_t ftq_enable: 1;
260 uint32_t caf_enable: 1;
261 uint32_t caf_disable_hd: 1;
262 uint32_t skip_bias_adjustment_supported: 1;
264 uint32_t adaptive_intra_scaling_enable: 1;
265 uint32_t old_mode_cost_enable: 1;
266 uint32_t multi_ref_qp_enable: 1;
267 uint32_t weighted_ref_l0_enable: 1;
268 uint32_t weighted_ref_l1_enable: 1;
269 uint32_t weighted_prediction_supported: 1;
270 uint32_t brc_split_enable: 1;
271 uint32_t slice_level_report_supported: 1;
273 uint32_t fbr_bypass_enable: 1;
274 //mb status output in scaling kernel
275 uint32_t field_scaling_output_interleaved: 1;
276 uint32_t mb_variance_output_enable: 1;
277 uint32_t mb_pixel_average_output_enable: 1;
278 uint32_t rolling_intra_refresh_enable: 1;
279 uint32_t mbenc_curbe_set_in_brc_update: 1;
281 uint32_t rounding_inter_enable: 1;
282 uint32_t adaptive_rounding_inter_enable: 1;
284 uint32_t mbenc_i_frame_dist_in_use: 1;
285 uint32_t mb_status_supported: 1;
286 uint32_t mb_vproc_stats_enable: 1;
287 uint32_t flatness_check_enable: 1;
288 uint32_t block_based_skip_enable: 1;
289 uint32_t use_widi_mbenc_kernel: 1;
290 uint32_t kernel_trellis_enable: 1;
291 uint32_t generic_reserved: 1;
295 uint32_t rounding_value;
296 uint32_t rounding_inter_p;
297 uint32_t rounding_inter_b;
298 uint32_t rounding_inter_b_ref;
308 uint8_t non_ftq_skip_threshold_lut[52];
309 uint8_t ftq_skip_threshold_lut[52];
310 uint32_t lamda_value_lut[52][2];
313 uint32_t intra_refresh_qp_threshold;
314 uint32_t trellis_flag;
315 uint32_t hme_mv_cost_scaling_factor;
316 uint32_t slice_height;//default 1
317 uint32_t slice_num;//default 1
318 uint32_t dist_scale_factor_list0[32];
320 uint32_t brc_const_data_surface_width;
321 uint32_t brc_const_data_surface_height;
323 uint32_t num_refs[2];
324 uint32_t list_ref_idx[2][32];
325 int32_t top_field_poc[NUM_MFC_AVC_DMV_BUFFERS];
327 uint32_t tq_rounding;
329 uint32_t zero_mv_threshold; //sfd
331 uint32_t slice_second_levle_batch_buffer_in_use;
332 uint32_t slice_batch_offset[MAX_AVC_SLICE_NUM];
335 uint32_t decouple_mbenc_curbe_from_brc_enable : 1;
336 uint32_t extended_mv_cost_range_enable : 1;
337 uint32_t lambda_table_enable : 1;
338 uint32_t reserved_g95 : 30;
339 uint32_t mbenc_brc_buffer_size;
343 extern int i965_avc_level_is_valid(int level_idc);
344 extern int i965_avc_get_max_mbps(int level_idc);
345 extern int i965_avc_calculate_initial_qp(struct avc_param * param);
346 extern unsigned int i965_avc_get_profile_level_max_frame(struct avc_param * param, int level_idc);
347 extern int i965_avc_get_max_mv_len(int level_idc);
348 extern int i965_avc_get_max_mv_per_2mb(int level_idc);
349 extern unsigned short i965_avc_calc_skip_value(unsigned int enc_block_based_sip_en, unsigned int transform_8x8_flag, unsigned short skip_value);
350 #endif // _I965_AVC_ENCODER_COMMON_H