src/i965_avc_hw_scoreboard.c

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Xiang Haihao <haihao.xiang@intel.com>
  26  *
  27  */
  28
  29 #include <stdio.h>
  30 #include <string.h>
  31 #include <assert.h>
  32
  33 #include "intel_batchbuffer.h"
  34 #include "intel_driver.h"
  35
  36 #include "i965_defines.h"
  37 #include "i965_drv_video.h"
  38 #include "i965_avc_hw_scoreboard.h"
  39 #include "i965_media_h264.h"
  40 #include "i965_media.h"
  41
  42 /* On Ironlake */
  43 #include "shaders/h264/mc/export.inc.gen5"
  44
  45 enum {
  46     AVC_HW_SCOREBOARD = 0,
  47     AVC_HW_SCOREBOARD_MBAFF
  48 };
  49
  50 static unsigned long avc_hw_scoreboard_kernel_offset[] = {
  51     SETHWSCOREBOARD_IP_GEN5 * INST_UNIT_GEN5,
  52     SETHWSCOREBOARD_MBAFF_IP_GEN5 * INST_UNIT_GEN5
  53 };
  54
  55 static unsigned int avc_hw_scoreboard_constants[] = {
  56     0x08040201,
  57     0x00000010,
  58     0x08000210,
  59     0x00000000,
  60     0x08040201,
  61     0x08040210,
  62     0x01000010,
  63     0x08040200
  64 };
  65
  66 static void
  67 i965_avc_hw_scoreboard_surface_state(struct i965_h264_context *i965_h264_context)
  68 {
  69     struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context;
  70     struct i965_surface_state *ss;
  71     dri_bo *bo;
  72
  73     bo = avc_hw_scoreboard_context->surface.ss_bo;
  74     dri_bo_map(bo, 1);
  75     assert(bo->virtual);
  76     ss = bo->virtual;
  77     memset(ss, 0, sizeof(*ss));
  78     ss->ss0.surface_type = I965_SURFACE_BUFFER;
  79     ss->ss1.base_addr = avc_hw_scoreboard_context->surface.s_bo->offset;
  80     ss->ss2.width = ((avc_hw_scoreboard_context->surface.total_mbs * MB_CMD_IN_OWS - 1) & 0x7f);
  81     ss->ss2.height = (((avc_hw_scoreboard_context->surface.total_mbs * MB_CMD_IN_OWS - 1) >> 7) & 0x1fff);
  82     ss->ss3.depth = (((avc_hw_scoreboard_context->surface.total_mbs * MB_CMD_IN_OWS - 1) >> 20) & 0x7f);
  83     dri_bo_emit_reloc(bo,
  84                       I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
  85                       0,
  86                       offsetof(struct i965_surface_state, ss1),
  87                       avc_hw_scoreboard_context->surface.s_bo);
  88     dri_bo_unmap(bo);
  89 }
  90
  91 static void
  92 i965_avc_hw_scoreboard_interface_descriptor_table(struct i965_h264_context *i965_h264_context)
  93 {
  94     struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context;
  95     struct i965_interface_descriptor *desc;
  96     dri_bo *bo;
  97
  98     bo = avc_hw_scoreboard_context->idrt.bo;
  99     dri_bo_map(bo, 1);
 100     assert(bo->virtual);
 101     desc = bo->virtual;
 102     memset(desc, 0, sizeof(*desc));
 103     desc->desc0.grf_reg_blocks = 7;
 104     desc->desc0.kernel_start_pointer = (avc_hw_scoreboard_context->hw_kernel.bo->offset +
 105                                         avc_hw_scoreboard_context->hw_kernel.offset) >> 6; /* reloc */
 106     desc->desc1.const_urb_entry_read_offset = 0;
 107     desc->desc1.const_urb_entry_read_len = 1;
 108     desc->desc3.binding_table_entry_count = 0;
 109     desc->desc3.binding_table_pointer =
 110         avc_hw_scoreboard_context->binding_table.bo->offset >> 5; /*reloc */
 111
 112     dri_bo_emit_reloc(bo,
 113                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 114                       desc->desc0.grf_reg_blocks + avc_hw_scoreboard_context->hw_kernel.offset,
 115                       offsetof(struct i965_interface_descriptor, desc0),
 116                       avc_hw_scoreboard_context->hw_kernel.bo);
 117
 118     dri_bo_emit_reloc(bo,
 119                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 120                       desc->desc3.binding_table_entry_count,
 121                       offsetof(struct i965_interface_descriptor, desc3),
 122                       avc_hw_scoreboard_context->binding_table.bo);
 123
 124     dri_bo_unmap(bo);
 125 }
 126
 127 static void
 128 i965_avc_hw_scoreboard_binding_table(struct i965_h264_context *i965_h264_context)
 129 {
 130     struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context;
 131     unsigned int *binding_table;
 132     dri_bo *bo = avc_hw_scoreboard_context->binding_table.bo;
 133
 134     dri_bo_map(bo, 1);
 135     assert(bo->virtual);
 136     binding_table = bo->virtual;
 137     memset(binding_table, 0, bo->size);
 138     binding_table[0] = avc_hw_scoreboard_context->surface.ss_bo->offset;
 139     dri_bo_emit_reloc(bo,
 140                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 141                       0,
 142                       0,
 143                       avc_hw_scoreboard_context->surface.ss_bo);
 144     dri_bo_unmap(bo);
 145 }
 146
 147 static void
 148 i965_avc_hw_scoreboard_vfe_state(struct i965_h264_context *i965_h264_context)
 149 {
 150     struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context;
 151     struct i965_vfe_state *vfe_state;
 152     dri_bo *bo;
 153
 154     bo = avc_hw_scoreboard_context->vfe_state.bo;
 155     dri_bo_map(bo, 1);
 156     assert(bo->virtual);
 157     vfe_state = bo->virtual;
 158     memset(vfe_state, 0, sizeof(*vfe_state));
 159     vfe_state->vfe1.max_threads = avc_hw_scoreboard_context->urb.num_vfe_entries - 1;
 160     vfe_state->vfe1.urb_entry_alloc_size = avc_hw_scoreboard_context->urb.size_vfe_entry - 1;
 161     vfe_state->vfe1.num_urb_entries = avc_hw_scoreboard_context->urb.num_vfe_entries;
 162     vfe_state->vfe1.vfe_mode = VFE_GENERIC_MODE;
 163     vfe_state->vfe1.children_present = 0;
 164     vfe_state->vfe2.interface_descriptor_base =
 165         avc_hw_scoreboard_context->idrt.bo->offset >> 4; /* reloc */
 166     dri_bo_emit_reloc(bo,
 167                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 168                       0,
 169                       offsetof(struct i965_vfe_state, vfe2),
 170                       avc_hw_scoreboard_context->idrt.bo);
 171     dri_bo_unmap(bo);
 172 }
 173
 174 static void
 175 i965_avc_hw_scoreboard_upload_constants(struct i965_h264_context *i965_h264_context)
 176 {
 177     struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context;
 178     unsigned char *constant_buffer;
 179
 180     if (avc_hw_scoreboard_context->curbe.upload)
 181         return;
 182
 183     dri_bo_map(avc_hw_scoreboard_context->curbe.bo, 1);
 184     assert(avc_hw_scoreboard_context->curbe.bo->virtual);
 185     constant_buffer = avc_hw_scoreboard_context->curbe.bo->virtual;
 186     memcpy(constant_buffer, avc_hw_scoreboard_constants, sizeof(avc_hw_scoreboard_constants));
 187     dri_bo_unmap(avc_hw_scoreboard_context->curbe.bo);
 188     avc_hw_scoreboard_context->curbe.upload = 1;
 189 }
 190
 191 static void
 192 i965_avc_hw_scoreboard_states_setup(struct i965_h264_context *i965_h264_context)
 193 {
 194     i965_avc_hw_scoreboard_surface_state(i965_h264_context);
 195     i965_avc_hw_scoreboard_binding_table(i965_h264_context);
 196     i965_avc_hw_scoreboard_interface_descriptor_table(i965_h264_context);
 197     i965_avc_hw_scoreboard_vfe_state(i965_h264_context);
 198     i965_avc_hw_scoreboard_upload_constants(i965_h264_context);
 199 }
 200
 201 static void
 202 i965_avc_hw_scoreboard_pipeline_select(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
 203 {
 204     struct intel_batchbuffer *batch = i965_h264_context->batch;
 205
 206     BEGIN_BATCH(batch, 1);
 207     OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
 208     ADVANCE_BATCH(batch);
 209 }
 210
 211 static void
 212 i965_avc_hw_scoreboard_urb_layout(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
 213 {
 214     struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context;
 215     struct i965_driver_data *i965 = i965_driver_data(ctx);
 216     struct intel_batchbuffer *batch = i965_h264_context->batch;
 217     unsigned int vfe_fence, cs_fence;
 218
 219     vfe_fence = avc_hw_scoreboard_context->urb.cs_start;
 220     cs_fence = i965->intel.device_info->urb_size;
 221
 222     BEGIN_BATCH(batch, 3);
 223     OUT_BATCH(batch, CMD_URB_FENCE | UF0_VFE_REALLOC | UF0_CS_REALLOC | 1);
 224     OUT_BATCH(batch, 0);
 225     OUT_BATCH(batch,
 226               (vfe_fence << UF2_VFE_FENCE_SHIFT) |      /* VFE_SIZE */
 227               (cs_fence << UF2_CS_FENCE_SHIFT));        /* CS_SIZE */
 228     ADVANCE_BATCH(batch);
 229 }
 230
 231 static void
 232 i965_avc_hw_scoreboard_state_base_address(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
 233 {
 234     struct intel_batchbuffer *batch = i965_h264_context->batch;
 235
 236     BEGIN_BATCH(batch, 8);
 237     OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 6);
 238     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 239     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 240     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 241     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 242     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 243     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 244     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 245     ADVANCE_BATCH(batch);
 246 }
 247
 248 static void
 249 i965_avc_hw_scoreboard_state_pointers(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
 250 {
 251     struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context;
 252     struct intel_batchbuffer *batch = i965_h264_context->batch;
 253
 254     BEGIN_BATCH(batch, 3);
 255     OUT_BATCH(batch, CMD_MEDIA_STATE_POINTERS | 1);
 256     OUT_BATCH(batch, 0);
 257     OUT_RELOC(batch, avc_hw_scoreboard_context->vfe_state.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 258     ADVANCE_BATCH(batch);
 259 }
 260
 261 static void
 262 i965_avc_hw_scoreboard_cs_urb_layout(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
 263 {
 264     struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context;
 265     struct intel_batchbuffer *batch = i965_h264_context->batch;
 266
 267     BEGIN_BATCH(batch, 2);
 268     OUT_BATCH(batch, CMD_CS_URB_STATE | 0);
 269     OUT_BATCH(batch,
 270               ((avc_hw_scoreboard_context->urb.size_cs_entry - 1) << 4) |     /* URB Entry Allocation Size */
 271               (avc_hw_scoreboard_context->urb.num_cs_entries << 0));          /* Number of URB Entries */
 272     ADVANCE_BATCH(batch);
 273 }
 274
 275 static void
 276 i965_avc_hw_scoreboard_constant_buffer(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
 277 {
 278     struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context;
 279     struct intel_batchbuffer *batch = i965_h264_context->batch;
 280
 281     BEGIN_BATCH(batch, 2);
 282     OUT_BATCH(batch, CMD_CONSTANT_BUFFER | (1 << 8) | (2 - 2));
 283     OUT_RELOC(batch, avc_hw_scoreboard_context->curbe.bo,
 284               I915_GEM_DOMAIN_INSTRUCTION, 0,
 285               avc_hw_scoreboard_context->urb.size_cs_entry - 1);
 286     ADVANCE_BATCH(batch);
 287 }
 288
 289 static void
 290 i965_avc_hw_scoreboard_objects(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
 291 {
 292     struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context;
 293     struct intel_batchbuffer *batch = i965_h264_context->batch;
 294     int number_mb_cmds = 512;
 295     int starting_mb_number = avc_hw_scoreboard_context->inline_data.starting_mb_number;
 296     int i;
 297
 298     for (i = 0; i < avc_hw_scoreboard_context->inline_data.num_mb_cmds / 512; i++) {
 299         BEGIN_BATCH(batch, 6);
 300         OUT_BATCH(batch, CMD_MEDIA_OBJECT | 4);
 301         OUT_BATCH(batch, 0); /* interface descriptor offset: 0 */
 302         OUT_BATCH(batch, 0); /* no indirect data */
 303         OUT_BATCH(batch, 0);
 304         OUT_BATCH(batch, ((number_mb_cmds << 16) |
 305                           (starting_mb_number << 0)));
 306         OUT_BATCH(batch, avc_hw_scoreboard_context->inline_data.pic_width_in_mbs);
 307         ADVANCE_BATCH(batch);
 308
 309         starting_mb_number += 512;
 310     }
 311
 312     number_mb_cmds = avc_hw_scoreboard_context->inline_data.num_mb_cmds % 512;
 313
 314     if (number_mb_cmds) {
 315         BEGIN_BATCH(batch, 6);
 316         OUT_BATCH(batch, CMD_MEDIA_OBJECT | 4);
 317         OUT_BATCH(batch, 0); /* interface descriptor offset: 0 */
 318         OUT_BATCH(batch, 0); /* no indirect data */
 319         OUT_BATCH(batch, 0);
 320         OUT_BATCH(batch, ((number_mb_cmds << 16) |
 321                           (starting_mb_number << 0)));
 322         OUT_BATCH(batch, avc_hw_scoreboard_context->inline_data.pic_width_in_mbs);
 323         ADVANCE_BATCH(batch);
 324     }
 325 }
 326
 327 static void
 328 i965_avc_hw_scoreboard_pipeline_setup(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
 329 {
 330     struct intel_batchbuffer *batch = i965_h264_context->batch;
 331
 332     intel_batchbuffer_start_atomic(batch, 0x1000);
 333     intel_batchbuffer_emit_mi_flush(batch);
 334     i965_avc_hw_scoreboard_pipeline_select(ctx, i965_h264_context);
 335     i965_avc_hw_scoreboard_state_base_address(ctx, i965_h264_context);
 336     i965_avc_hw_scoreboard_state_pointers(ctx, i965_h264_context);
 337     i965_avc_hw_scoreboard_urb_layout(ctx, i965_h264_context);
 338     i965_avc_hw_scoreboard_cs_urb_layout(ctx, i965_h264_context);
 339     i965_avc_hw_scoreboard_constant_buffer(ctx, i965_h264_context);
 340     i965_avc_hw_scoreboard_objects(ctx, i965_h264_context);
 341     intel_batchbuffer_end_atomic(batch);
 342 }
 343
 344 void
 345 i965_avc_hw_scoreboard(VADriverContextP ctx, struct decode_state *decode_state, void *h264_context)
 346 {
 347     struct i965_h264_context *i965_h264_context = (struct i965_h264_context *)h264_context;
 348
 349     if (i965_h264_context->use_avc_hw_scoreboard) {
 350         struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context;
 351
 352         avc_hw_scoreboard_context->inline_data.num_mb_cmds = i965_h264_context->avc_it_command_mb_info.mbs;
 353         avc_hw_scoreboard_context->inline_data.starting_mb_number = i965_h264_context->avc_it_command_mb_info.mbs;
 354         avc_hw_scoreboard_context->inline_data.pic_width_in_mbs = i965_h264_context->picture.width_in_mbs;
 355         avc_hw_scoreboard_context->surface.total_mbs = i965_h264_context->avc_it_command_mb_info.mbs * 2;
 356
 357         dri_bo_unreference(avc_hw_scoreboard_context->hw_kernel.bo);
 358         avc_hw_scoreboard_context->hw_kernel.bo = i965_h264_context->avc_kernels[H264_AVC_COMBINED].bo;
 359         assert(avc_hw_scoreboard_context->hw_kernel.bo != NULL);
 360         dri_bo_reference(avc_hw_scoreboard_context->hw_kernel.bo);
 361
 362         if (i965_h264_context->picture.mbaff_frame_flag)
 363             avc_hw_scoreboard_context->hw_kernel.offset = avc_hw_scoreboard_kernel_offset[AVC_HW_SCOREBOARD_MBAFF];
 364         else
 365             avc_hw_scoreboard_context->hw_kernel.offset = avc_hw_scoreboard_kernel_offset[AVC_HW_SCOREBOARD];
 366
 367         i965_avc_hw_scoreboard_states_setup(i965_h264_context);
 368         i965_avc_hw_scoreboard_pipeline_setup(ctx, i965_h264_context);
 369     }
 370 }
 371
 372 void
 373 i965_avc_hw_scoreboard_decode_init(VADriverContextP ctx, void *h264_context)
 374 {
 375     struct i965_driver_data *i965 = i965_driver_data(ctx);
 376     struct i965_h264_context *i965_h264_context = (struct i965_h264_context *)h264_context;
 377
 378     if (i965_h264_context->use_avc_hw_scoreboard) {
 379         struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context;
 380         dri_bo *bo;
 381
 382         if (avc_hw_scoreboard_context->curbe.bo == NULL) {
 383             bo = dri_bo_alloc(i965->intel.bufmgr,
 384                               "constant buffer",
 385                               4096, 64);
 386             assert(bo);
 387             avc_hw_scoreboard_context->curbe.bo = bo;
 388             avc_hw_scoreboard_context->curbe.upload = 0;
 389         }
 390
 391         dri_bo_unreference(avc_hw_scoreboard_context->surface.s_bo);
 392         avc_hw_scoreboard_context->surface.s_bo = i965_h264_context->avc_it_command_mb_info.bo;
 393         assert(avc_hw_scoreboard_context->surface.s_bo != NULL);
 394         dri_bo_reference(avc_hw_scoreboard_context->surface.s_bo);
 395
 396         dri_bo_unreference(avc_hw_scoreboard_context->surface.ss_bo);
 397         bo = dri_bo_alloc(i965->intel.bufmgr,
 398                           "surface state",
 399                           sizeof(struct i965_surface_state), 32);
 400         assert(bo);
 401         avc_hw_scoreboard_context->surface.ss_bo = bo;
 402
 403         dri_bo_unreference(avc_hw_scoreboard_context->binding_table.bo);
 404         bo = dri_bo_alloc(i965->intel.bufmgr,
 405                           "binding table",
 406                           MAX_MEDIA_SURFACES * sizeof(unsigned int), 32);
 407         assert(bo);
 408         avc_hw_scoreboard_context->binding_table.bo = bo;
 409
 410         dri_bo_unreference(avc_hw_scoreboard_context->idrt.bo);
 411         bo = dri_bo_alloc(i965->intel.bufmgr,
 412                           "interface discriptor",
 413                           MAX_INTERFACE_DESC * sizeof(struct i965_interface_descriptor), 16);
 414         assert(bo);
 415         avc_hw_scoreboard_context->idrt.bo = bo;
 416
 417         dri_bo_unreference(avc_hw_scoreboard_context->vfe_state.bo);
 418         bo = dri_bo_alloc(i965->intel.bufmgr,
 419                           "vfe state",
 420                           sizeof(struct i965_vfe_state), 32);
 421         assert(bo);
 422         avc_hw_scoreboard_context->vfe_state.bo = bo;
 423
 424         avc_hw_scoreboard_context->urb.num_vfe_entries = 32;
 425         avc_hw_scoreboard_context->urb.size_vfe_entry = 2;
 426         avc_hw_scoreboard_context->urb.num_cs_entries = 1;
 427         avc_hw_scoreboard_context->urb.size_cs_entry = 1;
 428         avc_hw_scoreboard_context->urb.vfe_start = 0;
 429         avc_hw_scoreboard_context->urb.cs_start = avc_hw_scoreboard_context->urb.vfe_start +
 430                                                   avc_hw_scoreboard_context->urb.num_vfe_entries * avc_hw_scoreboard_context->urb.size_vfe_entry;
 431         assert(avc_hw_scoreboard_context->urb.cs_start +
 432                avc_hw_scoreboard_context->urb.num_cs_entries * avc_hw_scoreboard_context->urb.size_cs_entry <= i965->intel.device_info->urb_size);
 433     }
 434 }
 435
 436 Bool
 437 i965_avc_hw_scoreboard_ternimate(struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context)
 438 {
 439     dri_bo_unreference(avc_hw_scoreboard_context->curbe.bo);
 440     avc_hw_scoreboard_context->curbe.bo = NULL;
 441
 442     dri_bo_unreference(avc_hw_scoreboard_context->surface.ss_bo);
 443     avc_hw_scoreboard_context->surface.ss_bo = NULL;
 444
 445     dri_bo_unreference(avc_hw_scoreboard_context->surface.s_bo);
 446     avc_hw_scoreboard_context->surface.s_bo = NULL;
 447
 448     dri_bo_unreference(avc_hw_scoreboard_context->binding_table.bo);
 449     avc_hw_scoreboard_context->binding_table.bo = NULL;
 450
 451     dri_bo_unreference(avc_hw_scoreboard_context->idrt.bo);
 452     avc_hw_scoreboard_context->idrt.bo = NULL;
 453
 454     dri_bo_unreference(avc_hw_scoreboard_context->vfe_state.bo);
 455     avc_hw_scoreboard_context->vfe_state.bo = NULL;
 456
 457     dri_bo_unreference(avc_hw_scoreboard_context->hw_kernel.bo);
 458     avc_hw_scoreboard_context->hw_kernel.bo = NULL;
 459
 460     return True;
 461 }