src/i965_avc_ildb.c

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Xiang Haihao <haihao.xiang@intel.com>
  26  *
  27  */
  28
  29 #include <stdio.h>
  30 #include <string.h>
  31 #include <assert.h>
  32
  33
  34 #include "intel_batchbuffer.h"
  35 #include "intel_driver.h"
  36
  37 #include "i965_defines.h"
  38 #include "i965_drv_video.h"
  39 #include "i965_avc_ildb.h"
  40 #include "i965_media_h264.h"
  41 #include "i965_media.h"
  42
  43 /* On Cantiga */
  44 #include "shaders/h264/mc/export.inc"
  45
  46 /* On Ironlake */
  47 #include "shaders/h264/mc/export.inc.gen5"
  48
  49 #define PICTURE_FRAME   0
  50 #define PICTURE_FIELD   1
  51 #define PICTURE_MBAFF   2
  52
  53 enum {
  54     AVC_ILDB_ROOT_Y_ILDB_FRAME,
  55     AVC_ILDB_CHILD_Y_ILDB_FRAME,
  56     AVC_ILDB_ROOT_UV_ILDB_FRAME,
  57     AVC_ILDB_CHILD_UV_ILDB_FRAME,
  58     AVC_ILDB_ROOT_Y_ILDB_FIELD,
  59     AVC_ILDB_CHILD_Y_ILDB_FIELD,
  60     AVC_ILDB_ROOT_UV_ILDB_FIELD,
  61     AVC_ILDB_CHILD_UV_ILDB_FIELD,
  62     AVC_ILDB_ROOT_Y_ILDB_MBAFF,
  63     AVC_ILDB_CHILD_Y_ILDB_MBAFF,
  64     AVC_ILDB_ROOT_UV_ILDB_MBAFF,
  65     AVC_ILDB_CHILD_UV_ILDB_MBAFF
  66 };
  67
  68 static unsigned long avc_ildb_kernel_offset_gen4[] = {
  69     AVC_ILDB_ROOT_Y_ILDB_FRAME_IP * INST_UNIT_GEN4,
  70     AVC_ILDB_CHILD_Y_ILDB_FRAME_IP * INST_UNIT_GEN4,
  71     AVC_ILDB_ROOT_UV_ILDB_FRAME_IP * INST_UNIT_GEN4,
  72     AVC_ILDB_CHILD_UV_ILDB_FRAME_IP * INST_UNIT_GEN4,
  73     AVC_ILDB_ROOT_Y_ILDB_FIELD_IP * INST_UNIT_GEN4,
  74     AVC_ILDB_CHILD_Y_ILDB_FIELD_IP * INST_UNIT_GEN4,
  75     AVC_ILDB_ROOT_UV_ILDB_FIELD_IP * INST_UNIT_GEN4,
  76     AVC_ILDB_CHILD_UV_ILDB_FIELD_IP * INST_UNIT_GEN4,
  77     AVC_ILDB_ROOT_Y_ILDB_MBAFF_IP * INST_UNIT_GEN4,
  78     AVC_ILDB_CHILD_Y_ILDB_MBAFF_IP * INST_UNIT_GEN4,
  79     AVC_ILDB_ROOT_UV_ILDB_MBAFF_IP * INST_UNIT_GEN4,
  80     AVC_ILDB_CHILD_UV_ILDB_MBAFF_IP * INST_UNIT_GEN4
  81 };
  82
  83 static unsigned long avc_ildb_kernel_offset_gen5[] = {
  84     AVC_ILDB_ROOT_Y_ILDB_FRAME_IP_GEN5 * INST_UNIT_GEN5,
  85     AVC_ILDB_CHILD_Y_ILDB_FRAME_IP_GEN5 * INST_UNIT_GEN5,
  86     AVC_ILDB_ROOT_UV_ILDB_FRAME_IP_GEN5 * INST_UNIT_GEN5,
  87     AVC_ILDB_CHILD_UV_ILDB_FRAME_IP_GEN5 * INST_UNIT_GEN5,
  88     AVC_ILDB_ROOT_Y_ILDB_FIELD_IP_GEN5 * INST_UNIT_GEN5,
  89     AVC_ILDB_CHILD_Y_ILDB_FIELD_IP_GEN5 * INST_UNIT_GEN5,
  90     AVC_ILDB_ROOT_UV_ILDB_FIELD_IP_GEN5 * INST_UNIT_GEN5,
  91     AVC_ILDB_CHILD_UV_ILDB_FIELD_IP_GEN5 * INST_UNIT_GEN5,
  92     AVC_ILDB_ROOT_Y_ILDB_MBAFF_IP_GEN5 * INST_UNIT_GEN5,
  93     AVC_ILDB_CHILD_Y_ILDB_MBAFF_IP_GEN5 * INST_UNIT_GEN5,
  94     AVC_ILDB_ROOT_UV_ILDB_MBAFF_IP_GEN5 * INST_UNIT_GEN5,
  95     AVC_ILDB_CHILD_UV_ILDB_MBAFF_IP_GEN5 * INST_UNIT_GEN5
  96 };
  97
  98 struct avc_ildb_root_input {
  99     unsigned int blocks_per_row : 16;
 100     unsigned int blocks_per_column : 16;
 101
 102     unsigned int picture_type : 16;
 103     unsigned int max_concurrent_threads : 16;
 104
 105     unsigned int debug_field : 16;
 106     unsigned int mbaff_frame_flag : 1;
 107     unsigned int bottom_field_flag : 1;
 108     unsigned int control_data_expansion_flag : 1;
 109     unsigned int chroma_format : 1;
 110     unsigned int pad0 : 12;
 111
 112     unsigned int ramp_constant_0;
 113
 114     unsigned int ramp_constant_1;
 115
 116     int constant_0 : 8;
 117     int constant_1 : 8;
 118     int pad1 : 16;
 119
 120     unsigned int pad2;
 121     unsigned int pad3;
 122 };
 123
 124 #define NUM_AVC_ILDB_INTERFACES ARRAY_ELEMS(avc_ildb_kernel_offset_gen4)
 125 static unsigned long *avc_ildb_kernel_offset = NULL;
 126
 127 static void
 128 i965_avc_ildb_surface_state(VADriverContextP ctx,
 129                             struct decode_state *decode_state,
 130                             struct i965_h264_context *i965_h264_context)
 131 {
 132     struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
 133     struct i965_surface_state *ss;
 134     struct object_surface *obj_surface;
 135     VAPictureParameterBufferH264 *pic_param;
 136     VAPictureH264 *va_pic;
 137     dri_bo *bo;
 138     int i;
 139
 140     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 141     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 142     va_pic = &pic_param->CurrPic;
 143     obj_surface = decode_state->render_object;
 144
 145     avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].s_bo = i965_h264_context->avc_ildb_data.bo;
 146     dri_bo_reference(avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].s_bo);
 147     avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].offset = 0;
 148     avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].surface_type = I965_SURFACE_BUFFER;
 149     avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].width = ((avc_ildb_context->mbs_per_picture * EDGE_CONTROL_DATA_IN_DWS - 1) & 0x7f);
 150     avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].height = (((avc_ildb_context->mbs_per_picture * EDGE_CONTROL_DATA_IN_DWS - 1) >> 7) & 0x1fff);
 151     avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].depth = (((avc_ildb_context->mbs_per_picture * EDGE_CONTROL_DATA_IN_DWS - 1) >> 20) & 0x7f);
 152     avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].pitch = EDGE_CONTROL_DATA_IN_BTYES - 1;
 153     avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].is_target = 0;
 154
 155     avc_ildb_context->surface[SURFACE_SRC_Y].s_bo = obj_surface->bo;
 156     dri_bo_reference(avc_ildb_context->surface[SURFACE_SRC_Y].s_bo);
 157     avc_ildb_context->surface[SURFACE_SRC_Y].offset = 0;
 158     avc_ildb_context->surface[SURFACE_SRC_Y].surface_type = I965_SURFACE_2D;
 159     avc_ildb_context->surface[SURFACE_SRC_Y].format = I965_SURFACEFORMAT_R8_SINT;
 160     avc_ildb_context->surface[SURFACE_SRC_Y].width = obj_surface->width / 4 - 1;
 161     avc_ildb_context->surface[SURFACE_SRC_Y].height = obj_surface->height - 1;
 162     avc_ildb_context->surface[SURFACE_SRC_Y].depth = 0;
 163     avc_ildb_context->surface[SURFACE_SRC_Y].pitch = obj_surface->width - 1;
 164     avc_ildb_context->surface[SURFACE_SRC_Y].vert_line_stride = !!(va_pic->flags & (VA_PICTURE_H264_TOP_FIELD | VA_PICTURE_H264_BOTTOM_FIELD));
 165     avc_ildb_context->surface[SURFACE_SRC_Y].vert_line_stride_ofs = !!(va_pic->flags & VA_PICTURE_H264_BOTTOM_FIELD);
 166     avc_ildb_context->surface[SURFACE_SRC_Y].is_target = 0;
 167
 168     avc_ildb_context->surface[SURFACE_SRC_UV].s_bo = obj_surface->bo;
 169     dri_bo_reference(avc_ildb_context->surface[SURFACE_SRC_UV].s_bo);
 170     avc_ildb_context->surface[SURFACE_SRC_UV].offset = obj_surface->width * obj_surface->height;
 171     avc_ildb_context->surface[SURFACE_SRC_UV].surface_type = I965_SURFACE_2D;
 172     avc_ildb_context->surface[SURFACE_SRC_UV].format = I965_SURFACEFORMAT_R8G8_SINT;
 173     avc_ildb_context->surface[SURFACE_SRC_UV].width = obj_surface->width / 4 - 1;
 174     avc_ildb_context->surface[SURFACE_SRC_UV].height = obj_surface->height / 2 - 1;
 175     avc_ildb_context->surface[SURFACE_SRC_UV].depth = 0;
 176     avc_ildb_context->surface[SURFACE_SRC_UV].pitch = obj_surface->width - 1;
 177     avc_ildb_context->surface[SURFACE_SRC_UV].vert_line_stride = !!(va_pic->flags & (VA_PICTURE_H264_TOP_FIELD | VA_PICTURE_H264_BOTTOM_FIELD));
 178     avc_ildb_context->surface[SURFACE_SRC_UV].vert_line_stride_ofs = !!(va_pic->flags & VA_PICTURE_H264_BOTTOM_FIELD);
 179     avc_ildb_context->surface[SURFACE_SRC_UV].is_target = 0;
 180
 181     avc_ildb_context->surface[SURFACE_DEST_Y].s_bo = obj_surface->bo;
 182     dri_bo_reference(avc_ildb_context->surface[SURFACE_DEST_Y].s_bo);
 183     avc_ildb_context->surface[SURFACE_DEST_Y].offset = 0;
 184     avc_ildb_context->surface[SURFACE_DEST_Y].surface_type = I965_SURFACE_2D;
 185     avc_ildb_context->surface[SURFACE_DEST_Y].format = I965_SURFACEFORMAT_R8_SINT;
 186     avc_ildb_context->surface[SURFACE_DEST_Y].width = obj_surface->width / 4 - 1;
 187     avc_ildb_context->surface[SURFACE_DEST_Y].height = obj_surface->height - 1;
 188     avc_ildb_context->surface[SURFACE_DEST_Y].depth = 0;
 189     avc_ildb_context->surface[SURFACE_DEST_Y].pitch = obj_surface->width - 1;
 190     avc_ildb_context->surface[SURFACE_DEST_Y].vert_line_stride = !!(va_pic->flags & (VA_PICTURE_H264_TOP_FIELD | VA_PICTURE_H264_BOTTOM_FIELD));
 191     avc_ildb_context->surface[SURFACE_DEST_Y].vert_line_stride_ofs = !!(va_pic->flags & VA_PICTURE_H264_BOTTOM_FIELD);
 192     avc_ildb_context->surface[SURFACE_DEST_Y].is_target = 1;
 193
 194     avc_ildb_context->surface[SURFACE_DEST_UV].s_bo = obj_surface->bo;
 195     dri_bo_reference(avc_ildb_context->surface[SURFACE_DEST_UV].s_bo);
 196     avc_ildb_context->surface[SURFACE_DEST_UV].offset = obj_surface->width * obj_surface->height;
 197     avc_ildb_context->surface[SURFACE_DEST_UV].surface_type = I965_SURFACE_2D;
 198     avc_ildb_context->surface[SURFACE_DEST_UV].format = I965_SURFACEFORMAT_R8G8_SINT;
 199     avc_ildb_context->surface[SURFACE_DEST_UV].width = obj_surface->width / 4 - 1;
 200     avc_ildb_context->surface[SURFACE_DEST_UV].height = obj_surface->height / 2 - 1;
 201     avc_ildb_context->surface[SURFACE_DEST_UV].depth = 0;
 202     avc_ildb_context->surface[SURFACE_DEST_UV].pitch = obj_surface->width - 1;
 203     avc_ildb_context->surface[SURFACE_DEST_UV].vert_line_stride = !!(va_pic->flags & (VA_PICTURE_H264_TOP_FIELD | VA_PICTURE_H264_BOTTOM_FIELD));
 204     avc_ildb_context->surface[SURFACE_DEST_UV].vert_line_stride_ofs = !!(va_pic->flags & VA_PICTURE_H264_BOTTOM_FIELD);
 205     avc_ildb_context->surface[SURFACE_DEST_UV].is_target = 1;
 206
 207     for (i = 0; i < NUM_AVC_ILDB_SURFACES; i++) {
 208         bo = avc_ildb_context->surface[i].ss_bo;
 209         dri_bo_map(bo, 1);
 210         assert(bo->virtual);
 211         ss = bo->virtual;
 212         memset(ss, 0, sizeof(*ss));
 213         ss->ss0.surface_type = avc_ildb_context->surface[i].surface_type;
 214         ss->ss0.surface_format = avc_ildb_context->surface[i].format;
 215         ss->ss0.vert_line_stride = avc_ildb_context->surface[i].vert_line_stride;
 216         ss->ss0.vert_line_stride_ofs = avc_ildb_context->surface[i].vert_line_stride_ofs;
 217         ss->ss1.base_addr = avc_ildb_context->surface[i].s_bo->offset + avc_ildb_context->surface[i].offset;
 218         ss->ss2.width = avc_ildb_context->surface[i].width;
 219         ss->ss2.height = avc_ildb_context->surface[i].height;
 220         ss->ss3.depth = avc_ildb_context->surface[i].depth;
 221         ss->ss3.pitch = avc_ildb_context->surface[i].pitch;
 222         dri_bo_emit_reloc(bo,
 223                           I915_GEM_DOMAIN_RENDER,
 224                           avc_ildb_context->surface[i].is_target ? I915_GEM_DOMAIN_RENDER : 0,
 225                           avc_ildb_context->surface[i].offset,
 226                           offsetof(struct i965_surface_state, ss1),
 227                           avc_ildb_context->surface[i].s_bo);
 228         dri_bo_unmap(bo);
 229     }
 230 }
 231
 232 static void
 233 i965_avc_ildb_binding_table(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
 234 {
 235     struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
 236     unsigned int *binding_table;
 237     dri_bo *bo = avc_ildb_context->binding_table.bo;
 238     int i;
 239
 240     dri_bo_map(bo, 1);
 241     assert(bo->virtual);
 242     binding_table = bo->virtual;
 243     memset(binding_table, 0, bo->size);
 244
 245     for (i = 0; i < NUM_AVC_ILDB_SURFACES; i++) {
 246         binding_table[i] = avc_ildb_context->surface[i].ss_bo->offset;
 247         dri_bo_emit_reloc(bo,
 248                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 249                           0,
 250                           i * sizeof(*binding_table),
 251                           avc_ildb_context->surface[i].ss_bo);
 252     }
 253
 254     dri_bo_unmap(bo);
 255 }
 256
 257 static void
 258 i965_avc_ildb_interface_descriptor_table(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
 259 {
 260     struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
 261     struct i965_interface_descriptor *desc;
 262     dri_bo *bo;
 263     int i;
 264
 265     bo = avc_ildb_context->idrt.bo;
 266     dri_bo_map(bo, 1);
 267     assert(bo->virtual);
 268     desc = bo->virtual;
 269
 270     for (i = 0; i < NUM_AVC_ILDB_INTERFACES; i++) {
 271         int kernel_offset = avc_ildb_kernel_offset[i];
 272         memset(desc, 0, sizeof(*desc));
 273         desc->desc0.grf_reg_blocks = 7;
 274         desc->desc0.kernel_start_pointer = (i965_h264_context->avc_kernels[H264_AVC_COMBINED].bo->offset + kernel_offset) >> 6; /* reloc */
 275         desc->desc1.const_urb_entry_read_offset = 0;
 276         desc->desc1.const_urb_entry_read_len = ((i == AVC_ILDB_ROOT_Y_ILDB_FRAME ||
 277                                                  i == AVC_ILDB_ROOT_Y_ILDB_FIELD ||
 278                                                  i == AVC_ILDB_ROOT_Y_ILDB_MBAFF) ? 1 : 0);
 279         desc->desc3.binding_table_entry_count = 0;
 280         desc->desc3.binding_table_pointer =
 281             avc_ildb_context->binding_table.bo->offset >> 5; /*reloc */
 282
 283         dri_bo_emit_reloc(bo,
 284                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 285                           desc->desc0.grf_reg_blocks + kernel_offset,
 286                           i * sizeof(*desc) + offsetof(struct i965_interface_descriptor, desc0),
 287                           i965_h264_context->avc_kernels[H264_AVC_COMBINED].bo);
 288
 289         dri_bo_emit_reloc(bo,
 290                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 291                           desc->desc3.binding_table_entry_count,
 292                           i * sizeof(*desc) + offsetof(struct i965_interface_descriptor, desc3),
 293                           avc_ildb_context->binding_table.bo);
 294         desc++;
 295     }
 296
 297     dri_bo_unmap(bo);
 298 }
 299
 300 static void
 301 i965_avc_ildb_vfe_state(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
 302 {
 303     struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
 304     struct i965_vfe_state *vfe_state;
 305     dri_bo *bo;
 306
 307     bo = avc_ildb_context->vfe_state.bo;
 308     dri_bo_map(bo, 1);
 309     assert(bo->virtual);
 310     vfe_state = bo->virtual;
 311     memset(vfe_state, 0, sizeof(*vfe_state));
 312     vfe_state->vfe1.max_threads = 0;
 313     vfe_state->vfe1.urb_entry_alloc_size = avc_ildb_context->urb.size_vfe_entry - 1;
 314     vfe_state->vfe1.num_urb_entries = avc_ildb_context->urb.num_vfe_entries;
 315     vfe_state->vfe1.vfe_mode = VFE_GENERIC_MODE;
 316     vfe_state->vfe1.children_present = 1;
 317     vfe_state->vfe2.interface_descriptor_base =
 318         avc_ildb_context->idrt.bo->offset >> 4; /* reloc */
 319     dri_bo_emit_reloc(bo,
 320                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 321                       0,
 322                       offsetof(struct i965_vfe_state, vfe2),
 323                       avc_ildb_context->idrt.bo);
 324     dri_bo_unmap(bo);
 325 }
 326
 327 static void
 328 i965_avc_ildb_upload_constants(VADriverContextP ctx,
 329                                struct decode_state *decode_state,
 330                                struct i965_h264_context *i965_h264_context)
 331 {
 332     struct i965_driver_data *i965 = i965_driver_data(ctx);
 333     struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
 334     VAPictureParameterBufferH264 *pic_param;
 335     struct avc_ildb_root_input *root_input;
 336
 337     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 338     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 339
 340     dri_bo_map(avc_ildb_context->curbe.bo, 1);
 341     assert(avc_ildb_context->curbe.bo->virtual);
 342     root_input = avc_ildb_context->curbe.bo->virtual;
 343
 344     if (IS_IRONLAKE(i965->intel.device_info)) {
 345         root_input->max_concurrent_threads = 76; /* 72 - 2 + 8 - 2 */
 346     } else {
 347         root_input->max_concurrent_threads = 54; /* 50 - 2 + 8 - 2 */
 348     }
 349
 350     if (pic_param->pic_fields.bits.field_pic_flag)
 351         root_input->picture_type = PICTURE_FIELD;
 352     else {
 353         if (pic_param->seq_fields.bits.mb_adaptive_frame_field_flag)
 354             root_input->picture_type = PICTURE_MBAFF;
 355         else
 356             root_input->picture_type = PICTURE_FRAME;
 357     }
 358
 359     avc_ildb_context->picture_type = root_input->picture_type;
 360     root_input->blocks_per_row = pic_param->picture_width_in_mbs_minus1 + 1;
 361     root_input->blocks_per_column = (pic_param->picture_height_in_mbs_minus1 + 1) /
 362                                     (1 + (root_input->picture_type != PICTURE_FRAME));
 363     avc_ildb_context->mbs_per_picture = (pic_param->picture_width_in_mbs_minus1 + 1) *
 364                                         (pic_param->picture_height_in_mbs_minus1 + 1);
 365
 366     root_input->mbaff_frame_flag = (root_input->picture_type == PICTURE_MBAFF);
 367     root_input->bottom_field_flag = !!(pic_param->CurrPic.flags & VA_PICTURE_H264_BOTTOM_FIELD);
 368     root_input->control_data_expansion_flag = 1; /* Always 1 on G4x+ */
 369     root_input->chroma_format = (pic_param->seq_fields.bits.chroma_format_idc != 1); /* 0=4:0:0, 1=4:2:0 */
 370
 371     root_input->ramp_constant_0 = 0x03020100;
 372
 373     root_input->ramp_constant_1 = 0x07060504;
 374
 375     root_input->constant_0 = -2;
 376     root_input->constant_1 = 1;
 377
 378     dri_bo_unmap(avc_ildb_context->curbe.bo);
 379 }
 380
 381 static void
 382 i965_avc_ildb_states_setup(VADriverContextP ctx,
 383                            struct decode_state *decode_state,
 384                            struct i965_h264_context *i965_h264_context)
 385 {
 386     i965_avc_ildb_surface_state(ctx, decode_state, i965_h264_context);
 387     i965_avc_ildb_binding_table(ctx, i965_h264_context);
 388     i965_avc_ildb_interface_descriptor_table(ctx, i965_h264_context);
 389     i965_avc_ildb_vfe_state(ctx, i965_h264_context);
 390     i965_avc_ildb_upload_constants(ctx, decode_state, i965_h264_context);
 391 }
 392
 393 static void
 394 i965_avc_ildb_pipeline_select(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
 395 {
 396     struct intel_batchbuffer *batch = i965_h264_context->batch;
 397
 398     BEGIN_BATCH(batch, 1);
 399     OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
 400     ADVANCE_BATCH(batch);
 401 }
 402
 403 static void
 404 i965_avc_ildb_urb_layout(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
 405 {
 406     struct i965_driver_data *i965 = i965_driver_data(ctx);
 407     struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
 408     struct intel_batchbuffer *batch = i965_h264_context->batch;
 409     unsigned int vfe_fence, cs_fence;
 410
 411     vfe_fence = avc_ildb_context->urb.cs_start;
 412     cs_fence = i965->intel.device_info->urb_size;
 413
 414     BEGIN_BATCH(batch, 3);
 415     OUT_BATCH(batch, CMD_URB_FENCE | UF0_VFE_REALLOC | UF0_CS_REALLOC | 1);
 416     OUT_BATCH(batch, 0);
 417     OUT_BATCH(batch,
 418               (vfe_fence << UF2_VFE_FENCE_SHIFT) |      /* VFE_SIZE */
 419               (cs_fence << UF2_CS_FENCE_SHIFT));        /* CS_SIZE */
 420     ADVANCE_BATCH(batch);
 421 }
 422
 423 static void
 424 i965_avc_ildb_state_base_address(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
 425 {
 426     struct i965_driver_data *i965 = i965_driver_data(ctx);
 427     struct intel_batchbuffer *batch = i965_h264_context->batch;
 428
 429     if (IS_IRONLAKE(i965->intel.device_info)) {
 430         BEGIN_BATCH(batch, 8);
 431         OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 6);
 432         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 433         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 434         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 435         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 436         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 437         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 438         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 439         ADVANCE_BATCH(batch);
 440     } else {
 441         BEGIN_BATCH(batch, 6);
 442         OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 4);
 443         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 444         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 445         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 446         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 447         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 448         ADVANCE_BATCH(batch);
 449     }
 450 }
 451
 452 static void
 453 i965_avc_ildb_state_pointers(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
 454 {
 455     struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
 456     struct intel_batchbuffer *batch = i965_h264_context->batch;
 457
 458     BEGIN_BATCH(batch, 3);
 459     OUT_BATCH(batch, CMD_MEDIA_STATE_POINTERS | 1);
 460     OUT_BATCH(batch, 0);
 461     OUT_RELOC(batch, avc_ildb_context->vfe_state.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 462     ADVANCE_BATCH(batch);
 463 }
 464
 465 static void
 466 i965_avc_ildb_cs_urb_layout(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
 467 {
 468     struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
 469     struct intel_batchbuffer *batch = i965_h264_context->batch;
 470
 471     BEGIN_BATCH(batch, 2);
 472     OUT_BATCH(batch, CMD_CS_URB_STATE | 0);
 473     OUT_BATCH(batch,
 474               ((avc_ildb_context->urb.size_cs_entry - 1) << 4) |     /* URB Entry Allocation Size */
 475               (avc_ildb_context->urb.num_cs_entries << 0));          /* Number of URB Entries */
 476     ADVANCE_BATCH(batch);
 477 }
 478
 479 static void
 480 i965_avc_ildb_constant_buffer(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
 481 {
 482     struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
 483     struct intel_batchbuffer *batch = i965_h264_context->batch;
 484
 485     BEGIN_BATCH(batch, 2);
 486     OUT_BATCH(batch, CMD_CONSTANT_BUFFER | (1 << 8) | (2 - 2));
 487     OUT_RELOC(batch, avc_ildb_context->curbe.bo,
 488               I915_GEM_DOMAIN_INSTRUCTION, 0,
 489               avc_ildb_context->urb.size_cs_entry - 1);
 490     ADVANCE_BATCH(batch);
 491 }
 492
 493 static void
 494 i965_avc_ildb_objects(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
 495 {
 496     struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
 497     struct intel_batchbuffer *batch = i965_h264_context->batch;
 498
 499     BEGIN_BATCH(batch, 6);
 500     OUT_BATCH(batch, CMD_MEDIA_OBJECT | 4);
 501
 502     switch (avc_ildb_context->picture_type) {
 503     case PICTURE_FRAME:
 504         OUT_BATCH(batch, AVC_ILDB_ROOT_Y_ILDB_FRAME);
 505         break;
 506
 507     case PICTURE_FIELD:
 508         OUT_BATCH(batch, AVC_ILDB_ROOT_Y_ILDB_FIELD);
 509         break;
 510
 511     case PICTURE_MBAFF:
 512         OUT_BATCH(batch, AVC_ILDB_ROOT_Y_ILDB_MBAFF);
 513         break;
 514
 515     default:
 516         assert(0);
 517         OUT_BATCH(batch, 0);
 518         break;
 519     }
 520
 521     OUT_BATCH(batch, 0); /* no indirect data */
 522     OUT_BATCH(batch, 0);
 523     OUT_BATCH(batch, 0);
 524     OUT_BATCH(batch, 0);
 525     ADVANCE_BATCH(batch);
 526 }
 527
 528 static void
 529 i965_avc_ildb_pipeline_setup(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
 530 {
 531     struct intel_batchbuffer *batch = i965_h264_context->batch;
 532
 533     intel_batchbuffer_emit_mi_flush(batch);
 534     i965_avc_ildb_pipeline_select(ctx, i965_h264_context);
 535     i965_avc_ildb_state_base_address(ctx, i965_h264_context);
 536     i965_avc_ildb_state_pointers(ctx, i965_h264_context);
 537     i965_avc_ildb_urb_layout(ctx, i965_h264_context);
 538     i965_avc_ildb_cs_urb_layout(ctx, i965_h264_context);
 539     i965_avc_ildb_constant_buffer(ctx, i965_h264_context);
 540     i965_avc_ildb_objects(ctx, i965_h264_context);
 541 }
 542
 543 void
 544 i965_avc_ildb(VADriverContextP ctx, struct decode_state *decode_state, void *h264_context)
 545 {
 546     struct i965_h264_context *i965_h264_context = (struct i965_h264_context *)h264_context;
 547
 548     if (i965_h264_context->enable_avc_ildb) {
 549         i965_avc_ildb_states_setup(ctx, decode_state, i965_h264_context);
 550         i965_avc_ildb_pipeline_setup(ctx, i965_h264_context);
 551     }
 552 }
 553
 554 void
 555 i965_avc_ildb_decode_init(VADriverContextP ctx, void *h264_context)
 556 {
 557     struct i965_driver_data *i965 = i965_driver_data(ctx);
 558     struct i965_h264_context *i965_h264_context = (struct i965_h264_context *)h264_context;
 559     struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;;
 560     dri_bo *bo;
 561     int i;
 562
 563     dri_bo_unreference(avc_ildb_context->curbe.bo);
 564     bo = dri_bo_alloc(i965->intel.bufmgr,
 565                       "constant buffer",
 566                       4096, 64);
 567     assert(bo);
 568     avc_ildb_context->curbe.bo = bo;
 569
 570     dri_bo_unreference(avc_ildb_context->binding_table.bo);
 571     bo = dri_bo_alloc(i965->intel.bufmgr,
 572                       "binding table",
 573                       NUM_AVC_ILDB_SURFACES * sizeof(unsigned int), 32);
 574     assert(bo);
 575     avc_ildb_context->binding_table.bo = bo;
 576
 577     dri_bo_unreference(avc_ildb_context->idrt.bo);
 578     bo = dri_bo_alloc(i965->intel.bufmgr,
 579                       "interface discriptor",
 580                       NUM_AVC_ILDB_INTERFACES * sizeof(struct i965_interface_descriptor), 16);
 581     assert(bo);
 582     avc_ildb_context->idrt.bo = bo;
 583
 584     dri_bo_unreference(avc_ildb_context->vfe_state.bo);
 585     bo = dri_bo_alloc(i965->intel.bufmgr,
 586                       "vfe state",
 587                       sizeof(struct i965_vfe_state), 32);
 588     assert(bo);
 589     avc_ildb_context->vfe_state.bo = bo;
 590
 591     avc_ildb_context->urb.num_vfe_entries = 1;
 592     avc_ildb_context->urb.size_vfe_entry = 640;
 593     avc_ildb_context->urb.num_cs_entries = 1;
 594     avc_ildb_context->urb.size_cs_entry = 1;
 595     avc_ildb_context->urb.vfe_start = 0;
 596     avc_ildb_context->urb.cs_start = avc_ildb_context->urb.vfe_start +
 597                                      avc_ildb_context->urb.num_vfe_entries * avc_ildb_context->urb.size_vfe_entry;
 598     assert(avc_ildb_context->urb.cs_start +
 599            avc_ildb_context->urb.num_cs_entries * avc_ildb_context->urb.size_cs_entry <= i965->intel.device_info->urb_size);
 600
 601     for (i = 0; i < NUM_AVC_ILDB_SURFACES; i++) {
 602         dri_bo_unreference(avc_ildb_context->surface[i].s_bo);
 603         avc_ildb_context->surface[i].s_bo = NULL;
 604
 605         dri_bo_unreference(avc_ildb_context->surface[i].ss_bo);
 606         bo = dri_bo_alloc(i965->intel.bufmgr,
 607                           "surface state",
 608                           sizeof(struct i965_surface_state), 32);
 609         assert(bo);
 610         avc_ildb_context->surface[i].ss_bo = bo;
 611     }
 612
 613     /* kernel offset */
 614     assert(NUM_AVC_ILDB_INTERFACES == ARRAY_ELEMS(avc_ildb_kernel_offset_gen5));
 615
 616     if (IS_IRONLAKE(i965->intel.device_info)) {
 617         avc_ildb_kernel_offset = avc_ildb_kernel_offset_gen5;
 618     } else {
 619         avc_ildb_kernel_offset = avc_ildb_kernel_offset_gen4;
 620     }
 621 }
 622
 623 Bool
 624 i965_avc_ildb_ternimate(struct i965_avc_ildb_context *avc_ildb_context)
 625 {
 626     int i;
 627
 628     dri_bo_unreference(avc_ildb_context->curbe.bo);
 629     avc_ildb_context->curbe.bo = NULL;
 630
 631     dri_bo_unreference(avc_ildb_context->binding_table.bo);
 632     avc_ildb_context->binding_table.bo = NULL;
 633
 634     dri_bo_unreference(avc_ildb_context->idrt.bo);
 635     avc_ildb_context->idrt.bo = NULL;
 636
 637     dri_bo_unreference(avc_ildb_context->vfe_state.bo);
 638     avc_ildb_context->vfe_state.bo = NULL;
 639
 640     for (i = 0; i < NUM_AVC_ILDB_SURFACES; i++) {
 641         dri_bo_unreference(avc_ildb_context->surface[i].ss_bo);
 642         avc_ildb_context->surface[i].ss_bo = NULL;
 643
 644         dri_bo_unreference(avc_ildb_context->surface[i].s_bo);
 645         avc_ildb_context->surface[i].s_bo = NULL;
 646     }
 647
 648     return True;
 649 }