2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Xiang Haihao <haihao.xiang@intel.com>
34 #include "intel_batchbuffer.h"
35 #include "intel_driver.h"
37 #include "i965_defines.h"
38 #include "i965_drv_video.h"
39 #include "i965_avc_ildb.h"
40 #include "i965_media_h264.h"
41 #include "i965_media.h"
44 #include "shaders/h264/mc/export.inc"
47 #include "shaders/h264/mc/export.inc.gen5"
49 #define PICTURE_FRAME 0
50 #define PICTURE_FIELD 1
51 #define PICTURE_MBAFF 2
54 AVC_ILDB_ROOT_Y_ILDB_FRAME,
55 AVC_ILDB_CHILD_Y_ILDB_FRAME,
56 AVC_ILDB_ROOT_UV_ILDB_FRAME,
57 AVC_ILDB_CHILD_UV_ILDB_FRAME,
58 AVC_ILDB_ROOT_Y_ILDB_FIELD,
59 AVC_ILDB_CHILD_Y_ILDB_FIELD,
60 AVC_ILDB_ROOT_UV_ILDB_FIELD,
61 AVC_ILDB_CHILD_UV_ILDB_FIELD,
62 AVC_ILDB_ROOT_Y_ILDB_MBAFF,
63 AVC_ILDB_CHILD_Y_ILDB_MBAFF,
64 AVC_ILDB_ROOT_UV_ILDB_MBAFF,
65 AVC_ILDB_CHILD_UV_ILDB_MBAFF
68 static unsigned long avc_ildb_kernel_offset_gen4[] = {
69 AVC_ILDB_ROOT_Y_ILDB_FRAME_IP * INST_UNIT_GEN4,
70 AVC_ILDB_CHILD_Y_ILDB_FRAME_IP * INST_UNIT_GEN4,
71 AVC_ILDB_ROOT_UV_ILDB_FRAME_IP * INST_UNIT_GEN4,
72 AVC_ILDB_CHILD_UV_ILDB_FRAME_IP * INST_UNIT_GEN4,
73 AVC_ILDB_ROOT_Y_ILDB_FIELD_IP * INST_UNIT_GEN4,
74 AVC_ILDB_CHILD_Y_ILDB_FIELD_IP * INST_UNIT_GEN4,
75 AVC_ILDB_ROOT_UV_ILDB_FIELD_IP * INST_UNIT_GEN4,
76 AVC_ILDB_CHILD_UV_ILDB_FIELD_IP * INST_UNIT_GEN4,
77 AVC_ILDB_ROOT_Y_ILDB_MBAFF_IP * INST_UNIT_GEN4,
78 AVC_ILDB_CHILD_Y_ILDB_MBAFF_IP * INST_UNIT_GEN4,
79 AVC_ILDB_ROOT_UV_ILDB_MBAFF_IP * INST_UNIT_GEN4,
80 AVC_ILDB_CHILD_UV_ILDB_MBAFF_IP * INST_UNIT_GEN4
83 static unsigned long avc_ildb_kernel_offset_gen5[] = {
84 AVC_ILDB_ROOT_Y_ILDB_FRAME_IP_GEN5 * INST_UNIT_GEN5,
85 AVC_ILDB_CHILD_Y_ILDB_FRAME_IP_GEN5 * INST_UNIT_GEN5,
86 AVC_ILDB_ROOT_UV_ILDB_FRAME_IP_GEN5 * INST_UNIT_GEN5,
87 AVC_ILDB_CHILD_UV_ILDB_FRAME_IP_GEN5 * INST_UNIT_GEN5,
88 AVC_ILDB_ROOT_Y_ILDB_FIELD_IP_GEN5 * INST_UNIT_GEN5,
89 AVC_ILDB_CHILD_Y_ILDB_FIELD_IP_GEN5 * INST_UNIT_GEN5,
90 AVC_ILDB_ROOT_UV_ILDB_FIELD_IP_GEN5 * INST_UNIT_GEN5,
91 AVC_ILDB_CHILD_UV_ILDB_FIELD_IP_GEN5 * INST_UNIT_GEN5,
92 AVC_ILDB_ROOT_Y_ILDB_MBAFF_IP_GEN5 * INST_UNIT_GEN5,
93 AVC_ILDB_CHILD_Y_ILDB_MBAFF_IP_GEN5 * INST_UNIT_GEN5,
94 AVC_ILDB_ROOT_UV_ILDB_MBAFF_IP_GEN5 * INST_UNIT_GEN5,
95 AVC_ILDB_CHILD_UV_ILDB_MBAFF_IP_GEN5 * INST_UNIT_GEN5
98 struct avc_ildb_root_input
100 unsigned int blocks_per_row : 16;
101 unsigned int blocks_per_column : 16;
103 unsigned int picture_type : 16;
104 unsigned int max_concurrent_threads : 16;
106 unsigned int debug_field : 16;
107 unsigned int mbaff_frame_flag : 1;
108 unsigned int bottom_field_flag : 1;
109 unsigned int control_data_expansion_flag : 1;
110 unsigned int chroma_format : 1;
111 unsigned int pad0 : 12;
113 unsigned int ramp_constant_0;
115 unsigned int ramp_constant_1;
125 #define NUM_AVC_ILDB_INTERFACES ARRAY_ELEMS(avc_ildb_kernel_offset_gen4)
126 static unsigned long *avc_ildb_kernel_offset = NULL;
129 i965_avc_ildb_surface_state(VADriverContextP ctx,
130 struct decode_state *decode_state,
131 struct i965_h264_context *i965_h264_context)
133 struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
134 struct i965_surface_state *ss;
135 struct object_surface *obj_surface;
136 VAPictureParameterBufferH264 *pic_param;
137 VAPictureH264 *va_pic;
141 assert(decode_state->pic_param && decode_state->pic_param->buffer);
142 pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
143 va_pic = &pic_param->CurrPic;
144 obj_surface = decode_state->render_object;
146 avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].s_bo = i965_h264_context->avc_ildb_data.bo;
147 dri_bo_reference(avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].s_bo);
148 avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].offset = 0;
149 avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].surface_type = I965_SURFACE_BUFFER;
150 avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].width = ((avc_ildb_context->mbs_per_picture * EDGE_CONTROL_DATA_IN_DWS - 1) & 0x7f);
151 avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].height = (((avc_ildb_context->mbs_per_picture * EDGE_CONTROL_DATA_IN_DWS - 1) >> 7) & 0x1fff);
152 avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].depth = (((avc_ildb_context->mbs_per_picture * EDGE_CONTROL_DATA_IN_DWS - 1) >> 20) & 0x7f);
153 avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].pitch = EDGE_CONTROL_DATA_IN_BTYES - 1;
154 avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].is_target = 0;
156 avc_ildb_context->surface[SURFACE_SRC_Y].s_bo = obj_surface->bo;
157 dri_bo_reference(avc_ildb_context->surface[SURFACE_SRC_Y].s_bo);
158 avc_ildb_context->surface[SURFACE_SRC_Y].offset = 0;
159 avc_ildb_context->surface[SURFACE_SRC_Y].surface_type = I965_SURFACE_2D;
160 avc_ildb_context->surface[SURFACE_SRC_Y].format = I965_SURFACEFORMAT_R8_SINT;
161 avc_ildb_context->surface[SURFACE_SRC_Y].width = obj_surface->width / 4 - 1;
162 avc_ildb_context->surface[SURFACE_SRC_Y].height = obj_surface->height - 1;
163 avc_ildb_context->surface[SURFACE_SRC_Y].depth = 0;
164 avc_ildb_context->surface[SURFACE_SRC_Y].pitch = obj_surface->width - 1;
165 avc_ildb_context->surface[SURFACE_SRC_Y].vert_line_stride = !!(va_pic->flags & (VA_PICTURE_H264_TOP_FIELD | VA_PICTURE_H264_BOTTOM_FIELD));
166 avc_ildb_context->surface[SURFACE_SRC_Y].vert_line_stride_ofs = !!(va_pic->flags & VA_PICTURE_H264_BOTTOM_FIELD);
167 avc_ildb_context->surface[SURFACE_SRC_Y].is_target = 0;
169 avc_ildb_context->surface[SURFACE_SRC_UV].s_bo = obj_surface->bo;
170 dri_bo_reference(avc_ildb_context->surface[SURFACE_SRC_UV].s_bo);
171 avc_ildb_context->surface[SURFACE_SRC_UV].offset = obj_surface->width * obj_surface->height;
172 avc_ildb_context->surface[SURFACE_SRC_UV].surface_type = I965_SURFACE_2D;
173 avc_ildb_context->surface[SURFACE_SRC_UV].format = I965_SURFACEFORMAT_R8G8_SINT;
174 avc_ildb_context->surface[SURFACE_SRC_UV].width = obj_surface->width / 4 - 1;
175 avc_ildb_context->surface[SURFACE_SRC_UV].height = obj_surface->height / 2 - 1;
176 avc_ildb_context->surface[SURFACE_SRC_UV].depth = 0;
177 avc_ildb_context->surface[SURFACE_SRC_UV].pitch = obj_surface->width - 1;
178 avc_ildb_context->surface[SURFACE_SRC_UV].vert_line_stride = !!(va_pic->flags & (VA_PICTURE_H264_TOP_FIELD | VA_PICTURE_H264_BOTTOM_FIELD));
179 avc_ildb_context->surface[SURFACE_SRC_UV].vert_line_stride_ofs = !!(va_pic->flags & VA_PICTURE_H264_BOTTOM_FIELD);
180 avc_ildb_context->surface[SURFACE_SRC_UV].is_target = 0;
182 avc_ildb_context->surface[SURFACE_DEST_Y].s_bo = obj_surface->bo;
183 dri_bo_reference(avc_ildb_context->surface[SURFACE_DEST_Y].s_bo);
184 avc_ildb_context->surface[SURFACE_DEST_Y].offset = 0;
185 avc_ildb_context->surface[SURFACE_DEST_Y].surface_type = I965_SURFACE_2D;
186 avc_ildb_context->surface[SURFACE_DEST_Y].format = I965_SURFACEFORMAT_R8_SINT;
187 avc_ildb_context->surface[SURFACE_DEST_Y].width = obj_surface->width / 4 - 1;
188 avc_ildb_context->surface[SURFACE_DEST_Y].height = obj_surface->height - 1;
189 avc_ildb_context->surface[SURFACE_DEST_Y].depth = 0;
190 avc_ildb_context->surface[SURFACE_DEST_Y].pitch = obj_surface->width - 1;
191 avc_ildb_context->surface[SURFACE_DEST_Y].vert_line_stride = !!(va_pic->flags & (VA_PICTURE_H264_TOP_FIELD | VA_PICTURE_H264_BOTTOM_FIELD));
192 avc_ildb_context->surface[SURFACE_DEST_Y].vert_line_stride_ofs = !!(va_pic->flags & VA_PICTURE_H264_BOTTOM_FIELD);
193 avc_ildb_context->surface[SURFACE_DEST_Y].is_target = 1;
195 avc_ildb_context->surface[SURFACE_DEST_UV].s_bo = obj_surface->bo;
196 dri_bo_reference(avc_ildb_context->surface[SURFACE_DEST_UV].s_bo);
197 avc_ildb_context->surface[SURFACE_DEST_UV].offset = obj_surface->width * obj_surface->height;
198 avc_ildb_context->surface[SURFACE_DEST_UV].surface_type = I965_SURFACE_2D;
199 avc_ildb_context->surface[SURFACE_DEST_UV].format = I965_SURFACEFORMAT_R8G8_SINT;
200 avc_ildb_context->surface[SURFACE_DEST_UV].width = obj_surface->width / 4 - 1;
201 avc_ildb_context->surface[SURFACE_DEST_UV].height = obj_surface->height / 2 - 1;
202 avc_ildb_context->surface[SURFACE_DEST_UV].depth = 0;
203 avc_ildb_context->surface[SURFACE_DEST_UV].pitch = obj_surface->width - 1;
204 avc_ildb_context->surface[SURFACE_DEST_UV].vert_line_stride = !!(va_pic->flags & (VA_PICTURE_H264_TOP_FIELD | VA_PICTURE_H264_BOTTOM_FIELD));
205 avc_ildb_context->surface[SURFACE_DEST_UV].vert_line_stride_ofs = !!(va_pic->flags & VA_PICTURE_H264_BOTTOM_FIELD);
206 avc_ildb_context->surface[SURFACE_DEST_UV].is_target = 1;
208 for (i = 0; i < NUM_AVC_ILDB_SURFACES; i++) {
209 bo = avc_ildb_context->surface[i].ss_bo;
213 memset(ss, 0, sizeof(*ss));
214 ss->ss0.surface_type = avc_ildb_context->surface[i].surface_type;
215 ss->ss0.surface_format = avc_ildb_context->surface[i].format;
216 ss->ss0.vert_line_stride = avc_ildb_context->surface[i].vert_line_stride;
217 ss->ss0.vert_line_stride_ofs = avc_ildb_context->surface[i].vert_line_stride_ofs;
218 ss->ss1.base_addr = avc_ildb_context->surface[i].s_bo->offset + avc_ildb_context->surface[i].offset;
219 ss->ss2.width = avc_ildb_context->surface[i].width;
220 ss->ss2.height = avc_ildb_context->surface[i].height;
221 ss->ss3.depth = avc_ildb_context->surface[i].depth;
222 ss->ss3.pitch = avc_ildb_context->surface[i].pitch;
223 dri_bo_emit_reloc(bo,
224 I915_GEM_DOMAIN_RENDER,
225 avc_ildb_context->surface[i].is_target ? I915_GEM_DOMAIN_RENDER : 0,
226 avc_ildb_context->surface[i].offset,
227 offsetof(struct i965_surface_state, ss1),
228 avc_ildb_context->surface[i].s_bo);
234 i965_avc_ildb_binding_table(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
236 struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
237 unsigned int *binding_table;
238 dri_bo *bo = avc_ildb_context->binding_table.bo;
243 binding_table = bo->virtual;
244 memset(binding_table, 0, bo->size);
246 for (i = 0; i < NUM_AVC_ILDB_SURFACES; i++) {
247 binding_table[i] = avc_ildb_context->surface[i].ss_bo->offset;
248 dri_bo_emit_reloc(bo,
249 I915_GEM_DOMAIN_INSTRUCTION, 0,
251 i * sizeof(*binding_table),
252 avc_ildb_context->surface[i].ss_bo);
259 i965_avc_ildb_interface_descriptor_table(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
261 struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
262 struct i965_interface_descriptor *desc;
266 bo = avc_ildb_context->idrt.bo;
271 for (i = 0; i < NUM_AVC_ILDB_INTERFACES; i++) {
272 int kernel_offset = avc_ildb_kernel_offset[i];
273 memset(desc, 0, sizeof(*desc));
274 desc->desc0.grf_reg_blocks = 7;
275 desc->desc0.kernel_start_pointer = (i965_h264_context->avc_kernels[H264_AVC_COMBINED].bo->offset + kernel_offset) >> 6; /* reloc */
276 desc->desc1.const_urb_entry_read_offset = 0;
277 desc->desc1.const_urb_entry_read_len = ((i == AVC_ILDB_ROOT_Y_ILDB_FRAME ||
278 i == AVC_ILDB_ROOT_Y_ILDB_FIELD ||
279 i == AVC_ILDB_ROOT_Y_ILDB_MBAFF) ? 1 : 0);
280 desc->desc3.binding_table_entry_count = 0;
281 desc->desc3.binding_table_pointer =
282 avc_ildb_context->binding_table.bo->offset >> 5; /*reloc */
284 dri_bo_emit_reloc(bo,
285 I915_GEM_DOMAIN_INSTRUCTION, 0,
286 desc->desc0.grf_reg_blocks + kernel_offset,
287 i * sizeof(*desc) + offsetof(struct i965_interface_descriptor, desc0),
288 i965_h264_context->avc_kernels[H264_AVC_COMBINED].bo);
290 dri_bo_emit_reloc(bo,
291 I915_GEM_DOMAIN_INSTRUCTION, 0,
292 desc->desc3.binding_table_entry_count,
293 i * sizeof(*desc) + offsetof(struct i965_interface_descriptor, desc3),
294 avc_ildb_context->binding_table.bo);
302 i965_avc_ildb_vfe_state(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
304 struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
305 struct i965_vfe_state *vfe_state;
308 bo = avc_ildb_context->vfe_state.bo;
311 vfe_state = bo->virtual;
312 memset(vfe_state, 0, sizeof(*vfe_state));
313 vfe_state->vfe1.max_threads = 0;
314 vfe_state->vfe1.urb_entry_alloc_size = avc_ildb_context->urb.size_vfe_entry - 1;
315 vfe_state->vfe1.num_urb_entries = avc_ildb_context->urb.num_vfe_entries;
316 vfe_state->vfe1.vfe_mode = VFE_GENERIC_MODE;
317 vfe_state->vfe1.children_present = 1;
318 vfe_state->vfe2.interface_descriptor_base =
319 avc_ildb_context->idrt.bo->offset >> 4; /* reloc */
320 dri_bo_emit_reloc(bo,
321 I915_GEM_DOMAIN_INSTRUCTION, 0,
323 offsetof(struct i965_vfe_state, vfe2),
324 avc_ildb_context->idrt.bo);
329 i965_avc_ildb_upload_constants(VADriverContextP ctx,
330 struct decode_state *decode_state,
331 struct i965_h264_context *i965_h264_context)
333 struct i965_driver_data *i965 = i965_driver_data(ctx);
334 struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
335 VAPictureParameterBufferH264 *pic_param;
336 struct avc_ildb_root_input *root_input;
338 assert(decode_state->pic_param && decode_state->pic_param->buffer);
339 pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
341 dri_bo_map(avc_ildb_context->curbe.bo, 1);
342 assert(avc_ildb_context->curbe.bo->virtual);
343 root_input = avc_ildb_context->curbe.bo->virtual;
345 if (IS_IRONLAKE(i965->intel.device_info)) {
346 root_input->max_concurrent_threads = 76; /* 72 - 2 + 8 - 2 */
348 root_input->max_concurrent_threads = 54; /* 50 - 2 + 8 - 2 */
351 if (pic_param->pic_fields.bits.field_pic_flag)
352 root_input->picture_type = PICTURE_FIELD;
354 if (pic_param->seq_fields.bits.mb_adaptive_frame_field_flag)
355 root_input->picture_type = PICTURE_MBAFF;
357 root_input->picture_type = PICTURE_FRAME;
360 avc_ildb_context->picture_type = root_input->picture_type;
361 root_input->blocks_per_row = pic_param->picture_width_in_mbs_minus1 + 1;
362 root_input->blocks_per_column = (pic_param->picture_height_in_mbs_minus1 + 1) /
363 (1 + (root_input->picture_type != PICTURE_FRAME));
364 avc_ildb_context->mbs_per_picture = (pic_param->picture_width_in_mbs_minus1 + 1) *
365 (pic_param->picture_height_in_mbs_minus1 + 1);
367 root_input->mbaff_frame_flag = (root_input->picture_type == PICTURE_MBAFF);
368 root_input->bottom_field_flag = !!(pic_param->CurrPic.flags & VA_PICTURE_H264_BOTTOM_FIELD);
369 root_input->control_data_expansion_flag = 1; /* Always 1 on G4x+ */
370 root_input->chroma_format = (pic_param->seq_fields.bits.chroma_format_idc != 1); /* 0=4:0:0, 1=4:2:0 */
372 root_input->ramp_constant_0 = 0x03020100;
374 root_input->ramp_constant_1 = 0x07060504;
376 root_input->constant_0 = -2;
377 root_input->constant_1 = 1;
379 dri_bo_unmap(avc_ildb_context->curbe.bo);
383 i965_avc_ildb_states_setup(VADriverContextP ctx,
384 struct decode_state *decode_state,
385 struct i965_h264_context *i965_h264_context)
387 i965_avc_ildb_surface_state(ctx, decode_state, i965_h264_context);
388 i965_avc_ildb_binding_table(ctx, i965_h264_context);
389 i965_avc_ildb_interface_descriptor_table(ctx, i965_h264_context);
390 i965_avc_ildb_vfe_state(ctx, i965_h264_context);
391 i965_avc_ildb_upload_constants(ctx, decode_state, i965_h264_context);
395 i965_avc_ildb_pipeline_select(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
397 struct intel_batchbuffer *batch = i965_h264_context->batch;
399 BEGIN_BATCH(batch, 1);
400 OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
401 ADVANCE_BATCH(batch);
405 i965_avc_ildb_urb_layout(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
407 struct i965_driver_data *i965 = i965_driver_data(ctx);
408 struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
409 struct intel_batchbuffer *batch = i965_h264_context->batch;
410 unsigned int vfe_fence, cs_fence;
412 vfe_fence = avc_ildb_context->urb.cs_start;
413 cs_fence = i965->intel.device_info->urb_size;
415 BEGIN_BATCH(batch, 3);
416 OUT_BATCH(batch, CMD_URB_FENCE | UF0_VFE_REALLOC | UF0_CS_REALLOC | 1);
419 (vfe_fence << UF2_VFE_FENCE_SHIFT) | /* VFE_SIZE */
420 (cs_fence << UF2_CS_FENCE_SHIFT)); /* CS_SIZE */
421 ADVANCE_BATCH(batch);
425 i965_avc_ildb_state_base_address(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
427 struct i965_driver_data *i965 = i965_driver_data(ctx);
428 struct intel_batchbuffer *batch = i965_h264_context->batch;
430 if (IS_IRONLAKE(i965->intel.device_info)) {
431 BEGIN_BATCH(batch, 8);
432 OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 6);
433 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
434 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
435 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
436 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
437 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
438 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
439 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
440 ADVANCE_BATCH(batch);
442 BEGIN_BATCH(batch, 6);
443 OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 4);
444 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
445 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
446 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
447 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
448 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
449 ADVANCE_BATCH(batch);
454 i965_avc_ildb_state_pointers(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
456 struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
457 struct intel_batchbuffer *batch = i965_h264_context->batch;
459 BEGIN_BATCH(batch, 3);
460 OUT_BATCH(batch, CMD_MEDIA_STATE_POINTERS | 1);
462 OUT_RELOC(batch, avc_ildb_context->vfe_state.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
463 ADVANCE_BATCH(batch);
467 i965_avc_ildb_cs_urb_layout(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
469 struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
470 struct intel_batchbuffer *batch = i965_h264_context->batch;
472 BEGIN_BATCH(batch, 2);
473 OUT_BATCH(batch, CMD_CS_URB_STATE | 0);
475 ((avc_ildb_context->urb.size_cs_entry - 1) << 4) | /* URB Entry Allocation Size */
476 (avc_ildb_context->urb.num_cs_entries << 0)); /* Number of URB Entries */
477 ADVANCE_BATCH(batch);
481 i965_avc_ildb_constant_buffer(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
483 struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
484 struct intel_batchbuffer *batch = i965_h264_context->batch;
486 BEGIN_BATCH(batch, 2);
487 OUT_BATCH(batch, CMD_CONSTANT_BUFFER | (1 << 8) | (2 - 2));
488 OUT_RELOC(batch, avc_ildb_context->curbe.bo,
489 I915_GEM_DOMAIN_INSTRUCTION, 0,
490 avc_ildb_context->urb.size_cs_entry - 1);
491 ADVANCE_BATCH(batch);
495 i965_avc_ildb_objects(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
497 struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
498 struct intel_batchbuffer *batch = i965_h264_context->batch;
500 BEGIN_BATCH(batch, 6);
501 OUT_BATCH(batch, CMD_MEDIA_OBJECT | 4);
503 switch (avc_ildb_context->picture_type) {
505 OUT_BATCH(batch, AVC_ILDB_ROOT_Y_ILDB_FRAME);
509 OUT_BATCH(batch, AVC_ILDB_ROOT_Y_ILDB_FIELD);
513 OUT_BATCH(batch, AVC_ILDB_ROOT_Y_ILDB_MBAFF);
522 OUT_BATCH(batch, 0); /* no indirect data */
526 ADVANCE_BATCH(batch);
530 i965_avc_ildb_pipeline_setup(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
532 struct intel_batchbuffer *batch = i965_h264_context->batch;
534 intel_batchbuffer_emit_mi_flush(batch);
535 i965_avc_ildb_pipeline_select(ctx, i965_h264_context);
536 i965_avc_ildb_state_base_address(ctx, i965_h264_context);
537 i965_avc_ildb_state_pointers(ctx, i965_h264_context);
538 i965_avc_ildb_urb_layout(ctx, i965_h264_context);
539 i965_avc_ildb_cs_urb_layout(ctx, i965_h264_context);
540 i965_avc_ildb_constant_buffer(ctx, i965_h264_context);
541 i965_avc_ildb_objects(ctx, i965_h264_context);
545 i965_avc_ildb(VADriverContextP ctx, struct decode_state *decode_state, void *h264_context)
547 struct i965_h264_context *i965_h264_context = (struct i965_h264_context *)h264_context;
549 if (i965_h264_context->enable_avc_ildb) {
550 i965_avc_ildb_states_setup(ctx, decode_state, i965_h264_context);
551 i965_avc_ildb_pipeline_setup(ctx, i965_h264_context);
556 i965_avc_ildb_decode_init(VADriverContextP ctx, void *h264_context)
558 struct i965_driver_data *i965 = i965_driver_data(ctx);
559 struct i965_h264_context *i965_h264_context = (struct i965_h264_context *)h264_context;
560 struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;;
564 dri_bo_unreference(avc_ildb_context->curbe.bo);
565 bo = dri_bo_alloc(i965->intel.bufmgr,
569 avc_ildb_context->curbe.bo = bo;
571 dri_bo_unreference(avc_ildb_context->binding_table.bo);
572 bo = dri_bo_alloc(i965->intel.bufmgr,
574 NUM_AVC_ILDB_SURFACES * sizeof(unsigned int), 32);
576 avc_ildb_context->binding_table.bo = bo;
578 dri_bo_unreference(avc_ildb_context->idrt.bo);
579 bo = dri_bo_alloc(i965->intel.bufmgr,
580 "interface discriptor",
581 NUM_AVC_ILDB_INTERFACES * sizeof(struct i965_interface_descriptor), 16);
583 avc_ildb_context->idrt.bo = bo;
585 dri_bo_unreference(avc_ildb_context->vfe_state.bo);
586 bo = dri_bo_alloc(i965->intel.bufmgr,
588 sizeof(struct i965_vfe_state), 32);
590 avc_ildb_context->vfe_state.bo = bo;
592 avc_ildb_context->urb.num_vfe_entries = 1;
593 avc_ildb_context->urb.size_vfe_entry = 640;
594 avc_ildb_context->urb.num_cs_entries = 1;
595 avc_ildb_context->urb.size_cs_entry = 1;
596 avc_ildb_context->urb.vfe_start = 0;
597 avc_ildb_context->urb.cs_start = avc_ildb_context->urb.vfe_start +
598 avc_ildb_context->urb.num_vfe_entries * avc_ildb_context->urb.size_vfe_entry;
599 assert(avc_ildb_context->urb.cs_start +
600 avc_ildb_context->urb.num_cs_entries * avc_ildb_context->urb.size_cs_entry <= i965->intel.device_info->urb_size);
602 for (i = 0; i < NUM_AVC_ILDB_SURFACES; i++) {
603 dri_bo_unreference(avc_ildb_context->surface[i].s_bo);
604 avc_ildb_context->surface[i].s_bo = NULL;
606 dri_bo_unreference(avc_ildb_context->surface[i].ss_bo);
607 bo = dri_bo_alloc(i965->intel.bufmgr,
609 sizeof(struct i965_surface_state), 32);
611 avc_ildb_context->surface[i].ss_bo = bo;
615 assert(NUM_AVC_ILDB_INTERFACES == ARRAY_ELEMS(avc_ildb_kernel_offset_gen5));
617 if (IS_IRONLAKE(i965->intel.device_info)) {
618 avc_ildb_kernel_offset = avc_ildb_kernel_offset_gen5;
620 avc_ildb_kernel_offset = avc_ildb_kernel_offset_gen4;
625 i965_avc_ildb_ternimate(struct i965_avc_ildb_context *avc_ildb_context)
629 dri_bo_unreference(avc_ildb_context->curbe.bo);
630 avc_ildb_context->curbe.bo = NULL;
632 dri_bo_unreference(avc_ildb_context->binding_table.bo);
633 avc_ildb_context->binding_table.bo = NULL;
635 dri_bo_unreference(avc_ildb_context->idrt.bo);
636 avc_ildb_context->idrt.bo = NULL;
638 dri_bo_unreference(avc_ildb_context->vfe_state.bo);
639 avc_ildb_context->vfe_state.bo = NULL;
641 for (i = 0; i < NUM_AVC_ILDB_SURFACES; i++) {
642 dri_bo_unreference(avc_ildb_context->surface[i].ss_bo);
643 avc_ildb_context->surface[i].ss_bo = NULL;
645 dri_bo_unreference(avc_ildb_context->surface[i].s_bo);
646 avc_ildb_context->surface[i].s_bo = NULL;