2 * Copyright ?2009 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Xiang Haihao <haihao.xiang@intel.com>
26 * Zou Nan hai <nanhai.zou@intel.com>
30 #ifndef _I965_DRV_VIDEO_H_
31 #define _I965_DRV_VIDEO_H_
34 #include <va/va_enc_h264.h>
35 #include <va/va_enc_mpeg2.h>
36 #include <va/va_enc_hevc.h>
37 #include <va/va_enc_jpeg.h>
38 #include <va/va_enc_vp8.h>
39 #include <va/va_vpp.h>
40 #include <va/va_backend.h>
41 #include <va/va_backend_vpp.h>
42 #include <va/va_fei.h>
43 #include <va/va_fei_h264.h>
45 #include "va_backend_compat.h"
47 #include "i965_mutext.h"
48 #include "object_heap.h"
49 #include "intel_driver.h"
50 #include "i965_fourcc.h"
52 #define I965_MAX_PROFILES 20
53 #define I965_MAX_ENTRYPOINTS 6
54 #define I965_MAX_CONFIG_ATTRIBUTES 32
55 #define I965_MAX_IMAGE_FORMATS 10
56 #define I965_MAX_SUBPIC_FORMATS 6
57 #define I965_MAX_SUBPIC_SUM 4
58 #define I965_MAX_SURFACE_ATTRIBUTES 32
60 #define INTEL_STR_DRIVER_VENDOR "Intel"
61 #define INTEL_STR_DRIVER_NAME "i965"
63 #define I965_SURFACE_TYPE_IMAGE 0
64 #define I965_SURFACE_TYPE_SURFACE 1
66 #define I965_SURFACE_FLAG_FRAME 0x00000000
67 #define I965_SURFACE_FLAG_TOP_FIELD_FIRST 0x00000001
68 #define I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST 0x00000002
70 #define DEFAULT_BRIGHTNESS 0
71 #define DEFAULT_CONTRAST 50
73 #define DEFAULT_SATURATION 50
75 #define ENCODER_QUALITY_RANGE 2
76 #define ENCODER_QUALITY_RANGE_AVC 7
77 #define ENCODER_QUALITY_RANGE_HEVC 7
78 #define ENCODER_DEFAULT_QUALITY 1
79 #define ENCODER_DEFAULT_QUALITY_AVC 4
80 #define ENCODER_DEFAULT_QUALITY_HEVC 4
81 #define ENCODER_HIGH_QUALITY ENCODER_DEFAULT_QUALITY
82 #define ENCODER_LOW_QUALITY 2
84 #define I965_MAX_NUM_ROI_REGIONS 8
85 #define I965_MAX_NUM_SLICE 32
87 #define ENCODER_LP_QUALITY_RANGE 8
89 #define HAS_MPEG2_DECODING(ctx) ((ctx)->codec_info->has_mpeg2_decoding && \
92 #define HAS_MPEG2_ENCODING(ctx) ((ctx)->codec_info->has_mpeg2_encoding && \
95 #define HAS_H264_DECODING(ctx) ((ctx)->codec_info->has_h264_decoding && \
98 #define HAS_H264_ENCODING(ctx) ((ctx)->codec_info->has_h264_encoding && \
101 #define HAS_LP_H264_ENCODING(ctx) ((ctx)->codec_info->has_lp_h264_encoding && \
102 (ctx)->intel.has_bsd)
104 #define HAS_FEI_H264_ENCODING(ctx) ((ctx)->codec_info->has_fei_h264_encoding && \
105 (ctx)->intel.has_bsd)
107 #define HAS_VC1_DECODING(ctx) ((ctx)->codec_info->has_vc1_decoding && \
108 (ctx)->intel.has_bsd)
110 #define HAS_JPEG_DECODING(ctx) ((ctx)->codec_info->has_jpeg_decoding && \
111 (ctx)->intel.has_bsd)
113 #define HAS_JPEG_ENCODING(ctx) ((ctx)->codec_info->has_jpeg_encoding && \
114 (ctx)->intel.has_bsd)
116 #define HAS_VPP(ctx) ((ctx)->codec_info->has_vpp)
118 #define HAS_ACCELERATED_GETIMAGE(ctx) ((ctx)->codec_info->has_accelerated_getimage)
120 #define HAS_ACCELERATED_PUTIMAGE(ctx) ((ctx)->codec_info->has_accelerated_putimage)
122 #define HAS_TILED_SURFACE(ctx) ((ctx)->codec_info->has_tiled_surface)
124 #define HAS_VP8_DECODING(ctx) ((ctx)->codec_info->has_vp8_decoding && \
125 (ctx)->intel.has_bsd)
127 #define HAS_VP8_ENCODING(ctx) ((ctx)->codec_info->has_vp8_encoding && \
128 (ctx)->intel.has_bsd)
130 #define HAS_H264_MVC_DECODING(ctx) \
131 (HAS_H264_DECODING(ctx) && (ctx)->codec_info->h264_mvc_dec_profiles)
133 #define HAS_H264_MVC_DECODING_PROFILE(ctx, profile) \
134 (HAS_H264_MVC_DECODING(ctx) && \
135 ((ctx)->codec_info->h264_mvc_dec_profiles & (1U << profile)))
137 #define HAS_H264_MVC_ENCODING(ctx) ((ctx)->codec_info->has_h264_mvc_encoding && \
138 (ctx)->intel.has_bsd)
140 #define HAS_HEVC_DECODING(ctx) ((ctx)->codec_info->has_hevc_decoding && \
141 (ctx)->intel.has_bsd)
143 #define HAS_HEVC_ENCODING(ctx) ((ctx)->codec_info->has_hevc_encoding && \
144 (ctx)->intel.has_bsd)
146 #define HAS_VP9_DECODING(ctx) ((ctx)->codec_info->has_vp9_decoding && \
147 (ctx)->intel.has_bsd)
149 #define HAS_VP9_DECODING_PROFILE(ctx, profile) \
150 (HAS_VP9_DECODING(ctx) && \
151 ((ctx)->codec_info->vp9_dec_profiles & (1U << (profile - VAProfileVP9Profile0))))
153 #define HAS_HEVC10_DECODING(ctx) ((ctx)->codec_info->has_hevc10_decoding && \
154 (ctx)->intel.has_bsd)
155 #define HAS_HEVC10_ENCODING(ctx) ((ctx)->codec_info->has_hevc10_encoding && \
156 (ctx)->intel.has_bsd)
158 #define HAS_VPP_P010(ctx) ((ctx)->codec_info->has_vpp_p010 && \
159 (ctx)->intel.has_bsd)
161 #define HAS_VP9_ENCODING(ctx) ((ctx)->codec_info->has_vp9_encoding && \
162 (ctx)->intel.has_bsd)
164 #define HAS_VP9_ENCODING_PROFILE(ctx, profile) \
165 (HAS_VP9_ENCODING(ctx) && \
166 ((ctx)->codec_info->vp9_enc_profiles & (1U << (profile - VAProfileVP9Profile0))))
168 struct i965_surface {
169 struct object_base *base;
177 const uint32_t (*bin)[4];
180 unsigned int kernel_offset;
183 struct buffer_store {
184 unsigned char *buffer;
190 struct object_config {
191 struct object_base base;
193 VAEntrypoint entrypoint;
194 VAConfigAttrib attrib_list[I965_MAX_CONFIG_ATTRIBUTES];
197 VAGenericID wrapper_config;
200 #define NUM_SLICES 10
202 struct codec_state_base {
203 uint32_t chroma_formats;
206 struct decode_state {
207 struct codec_state_base base;
208 struct buffer_store *pic_param;
209 struct buffer_store **slice_params;
210 struct buffer_store *iq_matrix;
211 struct buffer_store *bit_plane;
212 struct buffer_store *huffman_table;
213 struct buffer_store **slice_datas;
214 struct buffer_store *probability_data;
215 VASurfaceID current_render_target;
216 int max_slice_params;
218 int num_slice_params;
221 struct object_surface *render_object;
222 struct object_surface *reference_objects[16]; /* Up to 2 reference surfaces are valid for MPEG-2,*/
225 #define SLICE_PACKED_DATA_INDEX_TYPE 0x80000000
226 #define SLICE_PACKED_DATA_INDEX_MASK 0x00FFFFFF
228 struct encode_state {
229 struct codec_state_base base;
230 struct buffer_store *iq_matrix;
231 struct buffer_store *q_matrix;
232 struct buffer_store *huffman_table;
235 struct buffer_store *seq_param_ext;
236 struct buffer_store *pic_param_ext;
237 struct buffer_store *packed_header_param[5];
238 struct buffer_store *packed_header_data[5];
239 struct buffer_store **slice_params_ext;
240 struct buffer_store *encmb_map;
241 int max_slice_params_ext;
242 int num_slice_params_ext;
244 /* Check the user-configurable packed_header attribute.
245 * Currently it is mainly used to check whether the packed slice_header data
246 * is provided by user or the driver.
247 * TBD: It will check for the packed SPS/PPS/MISC/RAWDATA and so on.
249 unsigned int packed_header_flag;
250 /* For the packed data that needs to be inserted into video clip */
251 /* currently it is mainly to track packed raw data and packed slice_header data. */
252 struct buffer_store **packed_header_params_ext;
253 int max_packed_header_params_ext;
254 int num_packed_header_params_ext;
255 struct buffer_store **packed_header_data_ext;
256 int max_packed_header_data_ext;
257 int num_packed_header_data_ext;
259 /* the index of current vps and sps ,special for HEVC*/
260 int vps_sps_seq_index;
261 /* the index of current slice */
263 /* the array is determined by max_slice_params_ext */
265 /* This is to store the first index of packed data for one slice */
266 int *slice_rawdata_index;
267 /* This is to store the number of packed data for one slice.
268 * Both packed rawdata and slice_header data are tracked by this
269 * variable. That is to say: When one packed slice_header is parsed,
270 * this variable will also be increased.
272 int *slice_rawdata_count;
274 /* This is to store the index of packed slice header for one slice */
275 int *slice_header_index;
277 int last_packed_header_type;
281 struct buffer_store *misc_param[19][8];
283 VASurfaceID current_render_target;
284 struct object_surface *input_yuv_object;
285 struct object_surface *reconstructed_object;
286 struct object_buffer *coded_buf_object;
287 struct object_surface *reference_objects[16]; /* Up to 2 reference surfaces are valid for MPEG-2,*/
291 struct codec_state_base base;
292 struct buffer_store *pipeline_param;
294 VASurfaceID current_render_target;
302 struct codec_state_base base;
303 struct decode_state decode;
304 struct encode_state encode;
305 struct proc_state proc;
309 VAStatus(*run)(VADriverContextP ctx,
311 union codec_state *codec_state,
312 struct hw_context *hw_context);
313 void (*destroy)(void *);
314 VAStatus(*get_status)(VADriverContextP ctx,
315 struct hw_context *hw_context,
317 struct intel_batchbuffer *batch;
320 struct object_context {
321 struct object_base base;
322 VAContextID context_id;
323 struct object_config *obj_config;
324 VASurfaceID *render_targets; //input->encode, output->decode
325 int num_render_targets;
330 union codec_state codec_state;
331 struct hw_context *hw_context;
333 VAGenericID wrapper_context;
336 #define SURFACE_REFERENCED (1 << 0)
337 #define SURFACE_DERIVED (1 << 2)
338 #define SURFACE_ALL_MASK ((SURFACE_REFERENCED) | \
341 struct object_surface {
342 struct object_base base;
343 VASurfaceStatus status;
344 VASubpictureID subpic[I965_MAX_SUBPIC_SUM];
345 struct object_subpic *obj_subpic[I965_MAX_SUBPIC_SUM];
346 unsigned int subpic_render_idx;
348 int width; /* the pitch of plane 0 in bytes in horizontal direction */
349 int height; /* the pitch of plane 0 in bytes in vertical direction */
351 int orig_width; /* the width of plane 0 in pixels */
352 int orig_height; /* the height of plane 0 in pixels */
356 unsigned int expected_format;
357 VAImageID locked_image_id;
358 VAImageID derived_image_id;
359 void (*free_private_data)(void **data);
361 unsigned int subsampling;
369 /* user specified attributes see: VASurfaceAttribExternalBuffers/VA_SURFACE_ATTRIB_MEM_TYPE_VA */
370 uint32_t user_disable_tiling : 1;
371 uint32_t user_h_stride_set : 1;
372 uint32_t user_v_stride_set : 1;
373 /* we need clear right and bottom border for NV12.
374 * to avoid encode run to run issue*/
375 uint32_t border_cleared : 1;
377 VAGenericID wrapper_surface;
379 int exported_primefd;
382 struct object_buffer {
383 struct object_base base;
384 struct buffer_store *buffer_store;
385 int max_num_elements;
391 unsigned int export_refcount;
392 VABufferInfo export_state;
394 VAGenericID wrapper_buffer;
395 VAContextID context_id;
398 struct object_image {
399 struct object_base base;
402 unsigned int *palette;
403 VASurfaceID derived_surface;
406 struct object_subpic {
407 struct object_base base;
409 struct object_image *obj_image;
410 VARectangle src_rect;
411 VARectangle dst_rect;
421 #define I965_RING_NULL 0
422 #define I965_RING_BSD 1
423 #define I965_RING_BLT 2
424 #define I965_RING_VEBOX 3
427 VAProcFilterType type;
431 struct i965_driver_data;
433 struct hw_codec_info {
434 struct hw_context *(*dec_hw_context_init)(VADriverContextP, struct object_config *);
435 struct hw_context *(*enc_hw_context_init)(VADriverContextP, struct object_config *);
436 struct hw_context *(*proc_hw_context_init)(VADriverContextP, struct object_config *);
437 bool (*render_init)(VADriverContextP);
438 void (*post_processing_context_init)(VADriverContextP, void *, struct intel_batchbuffer *);
439 void (*preinit_hw_codec)(VADriverContextP, struct hw_codec_info *);
442 * Allows HW info to support per-codec max resolution. If this functor is
443 * not initialized, then @max_width and @max_height will be used as the
444 * default maximum resolution for all codecs on this HW info.
446 void (*max_resolution)(struct i965_driver_data *, struct object_config *, int *, int *);
450 int min_linear_wpitch;
451 int min_linear_hpitch;
453 unsigned int h264_mvc_dec_profiles;
454 unsigned int vp9_dec_profiles;
455 unsigned int vp9_enc_profiles;
457 unsigned int h264_dec_chroma_formats;
458 unsigned int jpeg_dec_chroma_formats;
459 unsigned int jpeg_enc_chroma_formats;
460 unsigned int hevc_dec_chroma_formats;
461 unsigned int vp9_dec_chroma_formats;
463 unsigned int has_mpeg2_decoding: 1;
464 unsigned int has_mpeg2_encoding: 1;
465 unsigned int has_h264_decoding: 1;
466 unsigned int has_h264_encoding: 1;
467 unsigned int has_vc1_decoding: 1;
468 unsigned int has_vc1_encoding: 1;
469 unsigned int has_jpeg_decoding: 1;
470 unsigned int has_jpeg_encoding: 1;
471 unsigned int has_vpp: 1;
472 unsigned int has_accelerated_getimage: 1;
473 unsigned int has_accelerated_putimage: 1;
474 unsigned int has_tiled_surface: 1;
475 unsigned int has_di_motion_adptive: 1;
476 unsigned int has_di_motion_compensated: 1;
477 unsigned int has_vp8_decoding: 1;
478 unsigned int has_vp8_encoding: 1;
479 unsigned int has_h264_mvc_encoding: 1;
480 unsigned int has_hevc_decoding: 1;
481 unsigned int has_hevc_encoding: 1;
482 unsigned int has_hevc10_encoding: 1;
483 unsigned int has_hevc10_decoding: 1;
484 unsigned int has_vp9_decoding: 1;
485 unsigned int has_vpp_p010: 1;
486 unsigned int has_lp_h264_encoding: 1;
487 unsigned int has_vp9_encoding: 1;
488 unsigned int has_fei_h264_encoding: 1;
490 unsigned int lp_h264_brc_mode;
491 unsigned int h264_brc_mode;
493 unsigned int num_filters;
494 struct i965_filter filters[VAProcFilterCount];
498 #include "i965_render.h"
499 #include "i965_gpe_utils.h"
501 struct i965_driver_data {
502 struct intel_driver_data intel;
503 struct object_heap config_heap;
504 struct object_heap context_heap;
505 struct object_heap surface_heap;
506 struct object_heap buffer_heap;
507 struct object_heap image_heap;
508 struct object_heap subpic_heap;
509 struct hw_codec_info *codec_info;
511 _I965Mutex render_mutex;
513 struct intel_batchbuffer *batch;
514 struct intel_batchbuffer *pp_batch;
515 struct i965_render_state render_state;
519 VADisplayAttribute *display_attributes;
520 unsigned int num_display_attributes;
521 VADisplayAttribute *rotation_attrib;
522 VADisplayAttribute *brightness_attrib;
523 VADisplayAttribute *contrast_attrib;
524 VADisplayAttribute *hue_attrib;
525 VADisplayAttribute *saturation_attrib;
526 VAContextID current_context_id;
528 /* VA/DRI (X11) specific data */
529 struct va_dri_output *dri_output;
531 /* VA/Wayland specific data */
532 struct va_wl_output *wl_output;
534 VADriverContextP wrapper_pdrvctx;
536 struct i965_gpe_table gpe_table;
539 #define NEW_CONFIG_ID() object_heap_allocate(&i965->config_heap);
540 #define NEW_CONTEXT_ID() object_heap_allocate(&i965->context_heap);
541 #define NEW_SURFACE_ID() object_heap_allocate(&i965->surface_heap);
542 #define NEW_BUFFER_ID() object_heap_allocate(&i965->buffer_heap);
543 #define NEW_IMAGE_ID() object_heap_allocate(&i965->image_heap);
544 #define NEW_SUBPIC_ID() object_heap_allocate(&i965->subpic_heap);
546 #define CONFIG(id) ((struct object_config *)object_heap_lookup(&i965->config_heap, id))
547 #define CONTEXT(id) ((struct object_context *)object_heap_lookup(&i965->context_heap, id))
548 #define SURFACE(id) ((struct object_surface *)object_heap_lookup(&i965->surface_heap, id))
549 #define BUFFER(id) ((struct object_buffer *)object_heap_lookup(&i965->buffer_heap, id))
550 #define IMAGE(id) ((struct object_image *)object_heap_lookup(&i965->image_heap, id))
551 #define SUBPIC(id) ((struct object_subpic *)object_heap_lookup(&i965->subpic_heap, id))
553 #define FOURCC_IA44 0x34344149
554 #define FOURCC_AI44 0x34344941
556 #define STRIDE(w) (((w) + 0xf) & ~0xf)
557 #define SIZE_YUV420(w, h) (h * (STRIDE(w) + STRIDE(w >> 1)))
559 static INLINE struct i965_driver_data *
560 i965_driver_data(VADriverContextP ctx)
562 return (struct i965_driver_data *)(ctx->pDriverData);
566 i965_check_alloc_surface_bo(VADriverContextP ctx,
567 struct object_surface *obj_surface,
570 unsigned int subsampling);
573 va_enc_packed_type_to_idx(int packed_type);
575 /* reserve 2 byte for internal using */
577 #define CODEC_MPEG2 1
578 #define CODEC_H264_MVC 2
584 #define H264_DELIMITER0 0x00
585 #define H264_DELIMITER1 0x00
586 #define H264_DELIMITER2 0x00
587 #define H264_DELIMITER3 0x00
588 #define H264_DELIMITER4 0x00
590 #define MPEG2_DELIMITER0 0x00
591 #define MPEG2_DELIMITER1 0x00
592 #define MPEG2_DELIMITER2 0x00
593 #define MPEG2_DELIMITER3 0x00
594 #define MPEG2_DELIMITER4 0xb0
596 #define HEVC_DELIMITER0 0x00
597 #define HEVC_DELIMITER1 0x00
598 #define HEVC_DELIMITER2 0x00
599 #define HEVC_DELIMITER3 0x00
600 #define HEVC_DELIMITER4 0x00
602 struct i965_coded_buffer_segment {
604 VACodedBufferSegment base;
605 unsigned char pad0[64]; /* change the size if sizeof(VACodedBufferSegment) > 64 */
610 unsigned int status_support;
613 unsigned int codec_private_data[512]; /* Store codec private data, must be 16-bytes aligned */
616 #define I965_CODEDBUFFER_HEADER_SIZE ALIGN(sizeof(struct i965_coded_buffer_segment), 0x1000)
618 extern VAStatus i965_MapBuffer(VADriverContextP ctx,
619 VABufferID buf_id, /* in */
620 void **pbuf); /* out */
622 extern VAStatus i965_UnmapBuffer(VADriverContextP ctx, VABufferID buf_id);
624 extern VAStatus i965_DestroySurfaces(VADriverContextP ctx,
625 VASurfaceID *surface_list,
628 extern VAStatus i965_CreateSurfaces(VADriverContextP ctx,
633 VASurfaceID *surfaces);
635 #define I965_SURFACE_MEM_NATIVE 0
636 #define I965_SURFACE_MEM_GEM_FLINK 1
637 #define I965_SURFACE_MEM_DRM_PRIME 2
640 i965_destroy_surface_storage(struct object_surface *obj_surface);
642 // Logging functions for errors (to be shown to users) and info (useful for developers).
643 void i965_log_error(VADriverContextP ctx, const char *format, ...);
644 void i965_log_info(VADriverContextP ctx, const char *format, ...);
646 #endif /* _I965_DRV_VIDEO_H_ */