2 * Copyright ?2009 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Xiang Haihao <haihao.xiang@intel.com>
26 * Zou Nan hai <nanhai.zou@intel.com>
30 #ifndef _I965_DRV_VIDEO_H_
31 #define _I965_DRV_VIDEO_H_
34 #include <va/va_enc_h264.h>
35 #include <va/va_enc_mpeg2.h>
36 #include <va/va_enc_hevc.h>
37 #include <va/va_enc_jpeg.h>
38 #include <va/va_enc_vp8.h>
39 #include <va/va_vpp.h>
40 #include <va/va_backend.h>
41 #include <va/va_backend_vpp.h>
43 #include "i965_mutext.h"
44 #include "object_heap.h"
45 #include "intel_driver.h"
46 #include "i965_fourcc.h"
48 #define I965_MAX_PROFILES 20
49 #define I965_MAX_ENTRYPOINTS 5
50 #define I965_MAX_CONFIG_ATTRIBUTES 32
51 #define I965_MAX_IMAGE_FORMATS 10
52 #define I965_MAX_SUBPIC_FORMATS 6
53 #define I965_MAX_SUBPIC_SUM 4
54 #define I965_MAX_SURFACE_ATTRIBUTES 16
56 #define INTEL_STR_DRIVER_VENDOR "Intel"
57 #define INTEL_STR_DRIVER_NAME "i965"
59 #define I965_SURFACE_TYPE_IMAGE 0
60 #define I965_SURFACE_TYPE_SURFACE 1
62 #define I965_SURFACE_FLAG_FRAME 0x00000000
63 #define I965_SURFACE_FLAG_TOP_FIELD_FIRST 0x00000001
64 #define I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST 0x00000002
66 #define DEFAULT_BRIGHTNESS 0
67 #define DEFAULT_CONTRAST 50
69 #define DEFAULT_SATURATION 50
71 #define ENCODER_QUALITY_RANGE 2
72 #define ENCODER_DEFAULT_QUALITY 1
73 #define ENCODER_HIGH_QUALITY ENCODER_DEFAULT_QUALITY
74 #define ENCODER_LOW_QUALITY 2
76 #define I965_MAX_NUM_ROI_REGIONS 8
78 #define ENCODER_LP_QUALITY_RANGE 8
80 #define HAS_MPEG2_DECODING(ctx) ((ctx)->codec_info->has_mpeg2_decoding && \
83 #define HAS_MPEG2_ENCODING(ctx) ((ctx)->codec_info->has_mpeg2_encoding && \
86 #define HAS_H264_DECODING(ctx) ((ctx)->codec_info->has_h264_decoding && \
89 #define HAS_H264_ENCODING(ctx) ((ctx)->codec_info->has_h264_encoding && \
92 #define HAS_LP_H264_ENCODING(ctx) ((ctx)->codec_info->has_lp_h264_encoding && \
95 #define HAS_VC1_DECODING(ctx) ((ctx)->codec_info->has_vc1_decoding && \
98 #define HAS_JPEG_DECODING(ctx) ((ctx)->codec_info->has_jpeg_decoding && \
101 #define HAS_JPEG_ENCODING(ctx) ((ctx)->codec_info->has_jpeg_encoding && \
102 (ctx)->intel.has_bsd)
104 #define HAS_VPP(ctx) ((ctx)->codec_info->has_vpp)
106 #define HAS_ACCELERATED_GETIMAGE(ctx) ((ctx)->codec_info->has_accelerated_getimage)
108 #define HAS_ACCELERATED_PUTIMAGE(ctx) ((ctx)->codec_info->has_accelerated_putimage)
110 #define HAS_TILED_SURFACE(ctx) ((ctx)->codec_info->has_tiled_surface)
112 #define HAS_VP8_DECODING(ctx) ((ctx)->codec_info->has_vp8_decoding && \
113 (ctx)->intel.has_bsd)
115 #define HAS_VP8_ENCODING(ctx) ((ctx)->codec_info->has_vp8_encoding && \
116 (ctx)->intel.has_bsd)
118 #define HAS_H264_MVC_DECODING(ctx) \
119 (HAS_H264_DECODING(ctx) && (ctx)->codec_info->h264_mvc_dec_profiles)
121 #define HAS_H264_MVC_DECODING_PROFILE(ctx, profile) \
122 (HAS_H264_MVC_DECODING(ctx) && \
123 ((ctx)->codec_info->h264_mvc_dec_profiles & (1U << profile)))
125 #define HAS_H264_MVC_ENCODING(ctx) ((ctx)->codec_info->has_h264_mvc_encoding && \
126 (ctx)->intel.has_bsd)
128 #define HAS_HEVC_DECODING(ctx) ((ctx)->codec_info->has_hevc_decoding && \
129 (ctx)->intel.has_bsd)
131 #define HAS_HEVC_ENCODING(ctx) ((ctx)->codec_info->has_hevc_encoding && \
132 (ctx)->intel.has_bsd)
134 #define HAS_VP9_DECODING(ctx) ((ctx)->codec_info->has_vp9_decoding && \
135 (ctx)->intel.has_bsd)
137 #define HAS_VP9_DECODING_PROFILE(ctx, profile) \
138 (HAS_VP9_DECODING(ctx) && \
139 ((ctx)->codec_info->vp9_dec_profiles & (1U << (profile - VAProfileVP9Profile0))))
141 #define HAS_HEVC10_DECODING(ctx) ((ctx)->codec_info->has_hevc10_decoding && \
142 (ctx)->intel.has_bsd)
143 #define HAS_HEVC10_ENCODING(ctx) ((ctx)->codec_info->has_hevc10_encoding && \
144 (ctx)->intel.has_bsd)
146 #define HAS_VPP_P010(ctx) ((ctx)->codec_info->has_vpp_p010 && \
147 (ctx)->intel.has_bsd)
149 #define HAS_VP9_ENCODING(ctx) ((ctx)->codec_info->has_vp9_encoding && \
150 (ctx)->intel.has_bsd)
152 #define HAS_VP9_ENCODING_PROFILE(ctx, profile) \
153 (HAS_VP9_ENCODING(ctx) && \
154 ((ctx)->codec_info->vp9_enc_profiles & (1U << (profile - VAProfileVP9Profile0))))
158 struct object_base *base;
167 const uint32_t (*bin)[4];
170 unsigned int kernel_offset;
175 unsigned char *buffer;
183 struct object_base base;
185 VAEntrypoint entrypoint;
186 VAConfigAttrib attrib_list[I965_MAX_CONFIG_ATTRIBUTES];
189 VAGenericID wrapper_config;
192 #define NUM_SLICES 10
194 struct codec_state_base {
195 uint32_t chroma_formats;
200 struct codec_state_base base;
201 struct buffer_store *pic_param;
202 struct buffer_store **slice_params;
203 struct buffer_store *iq_matrix;
204 struct buffer_store *bit_plane;
205 struct buffer_store *huffman_table;
206 struct buffer_store **slice_datas;
207 struct buffer_store *probability_data;
208 VASurfaceID current_render_target;
209 int max_slice_params;
211 int num_slice_params;
214 struct object_surface *render_object;
215 struct object_surface *reference_objects[16]; /* Up to 2 reference surfaces are valid for MPEG-2,*/
218 #define SLICE_PACKED_DATA_INDEX_TYPE 0x80000000
219 #define SLICE_PACKED_DATA_INDEX_MASK 0x00FFFFFF
223 struct codec_state_base base;
224 struct buffer_store *iq_matrix;
225 struct buffer_store *q_matrix;
226 struct buffer_store *huffman_table;
229 struct buffer_store *seq_param_ext;
230 struct buffer_store *pic_param_ext;
231 struct buffer_store *packed_header_param[5];
232 struct buffer_store *packed_header_data[5];
233 struct buffer_store **slice_params_ext;
234 struct buffer_store *encmb_map;
235 int max_slice_params_ext;
236 int num_slice_params_ext;
238 /* Check the user-configurable packed_header attribute.
239 * Currently it is mainly used to check whether the packed slice_header data
240 * is provided by user or the driver.
241 * TBD: It will check for the packed SPS/PPS/MISC/RAWDATA and so on.
243 unsigned int packed_header_flag;
244 /* For the packed data that needs to be inserted into video clip */
245 /* currently it is mainly to track packed raw data and packed slice_header data. */
246 struct buffer_store **packed_header_params_ext;
247 int max_packed_header_params_ext;
248 int num_packed_header_params_ext;
249 struct buffer_store **packed_header_data_ext;
250 int max_packed_header_data_ext;
251 int num_packed_header_data_ext;
253 /* the index of current vps and sps ,special for HEVC*/
254 int vps_sps_seq_index;
255 /* the index of current slice */
257 /* the array is determined by max_slice_params_ext */
259 /* This is to store the first index of packed data for one slice */
260 int *slice_rawdata_index;
261 /* This is to store the number of packed data for one slice.
262 * Both packed rawdata and slice_header data are tracked by this
263 * this variable. That is to say: When one packed slice_header is parsed,
264 * this variable will also be increased.
266 int *slice_rawdata_count;
268 /* This is to store the index of packed slice header for one slice */
269 int *slice_header_index;
271 int last_packed_header_type;
275 struct buffer_store *misc_param[16][8];
277 VASurfaceID current_render_target;
278 struct object_surface *input_yuv_object;
279 struct object_surface *reconstructed_object;
280 struct object_buffer *coded_buf_object;
281 struct object_surface *reference_objects[16]; /* Up to 2 reference surfaces are valid for MPEG-2,*/
286 struct codec_state_base base;
287 struct buffer_store *pipeline_param;
289 VASurfaceID current_render_target;
298 struct codec_state_base base;
299 struct decode_state decode;
300 struct encode_state encode;
301 struct proc_state proc;
306 VAStatus (*run)(VADriverContextP ctx,
308 union codec_state *codec_state,
309 struct hw_context *hw_context);
310 void (*destroy)(void *);
311 VAStatus (*get_status)(VADriverContextP ctx,
312 struct hw_context *hw_context,
314 struct intel_batchbuffer *batch;
317 struct object_context
319 struct object_base base;
320 VAContextID context_id;
321 struct object_config *obj_config;
322 VASurfaceID *render_targets; //input->encode, output->decode
323 int num_render_targets;
328 union codec_state codec_state;
329 struct hw_context *hw_context;
331 VAGenericID wrapper_context;
334 #define SURFACE_REFERENCED (1 << 0)
335 #define SURFACE_DERIVED (1 << 2)
336 #define SURFACE_ALL_MASK ((SURFACE_REFERENCED) | \
339 struct object_surface
341 struct object_base base;
342 VASurfaceStatus status;
343 VASubpictureID subpic[I965_MAX_SUBPIC_SUM];
344 struct object_subpic *obj_subpic[I965_MAX_SUBPIC_SUM];
345 unsigned int subpic_render_idx;
347 int width; /* the pitch of plane 0 in bytes in horizontal direction */
348 int height; /* the pitch of plane 0 in bytes in vertical direction */
350 int orig_width; /* the width of plane 0 in pixels */
351 int orig_height; /* the height of plane 0 in pixels */
355 unsigned int expected_format;
356 VAImageID locked_image_id;
357 VAImageID derived_image_id;
358 void (*free_private_data)(void **data);
360 unsigned int subsampling;
368 /* user specified attributes see: VASurfaceAttribExternalBuffers/VA_SURFACE_ATTRIB_MEM_TYPE_VA */
369 uint32_t user_disable_tiling : 1;
370 uint32_t user_h_stride_set : 1;
371 uint32_t user_v_stride_set : 1;
372 /* we need clear right and bottom border for NV12.
373 * to avoid encode run to run issue*/
374 uint32_t border_cleared : 1;
376 VAGenericID wrapper_surface;
378 int exported_primefd;
383 struct object_base base;
384 struct buffer_store *buffer_store;
385 int max_num_elements;
391 unsigned int export_refcount;
392 VABufferInfo export_state;
394 VAGenericID wrapper_buffer;
395 VAContextID context_id;
400 struct object_base base;
403 unsigned int *palette;
404 VASurfaceID derived_surface;
409 struct object_base base;
411 struct object_image *obj_image;
412 VARectangle src_rect;
413 VARectangle dst_rect;
423 #define I965_RING_NULL 0
424 #define I965_RING_BSD 1
425 #define I965_RING_BLT 2
426 #define I965_RING_VEBOX 3
430 VAProcFilterType type;
434 struct i965_driver_data;
438 struct hw_context *(*dec_hw_context_init)(VADriverContextP, struct object_config *);
439 struct hw_context *(*enc_hw_context_init)(VADriverContextP, struct object_config *);
440 struct hw_context *(*proc_hw_context_init)(VADriverContextP, struct object_config *);
441 bool (*render_init)(VADriverContextP);
442 void (*post_processing_context_init)(VADriverContextP, void *, struct intel_batchbuffer *);
443 void (*preinit_hw_codec)(VADriverContextP, struct hw_codec_info *);
446 * Allows HW info to support per-codec max resolution. If this functor is
447 * not initialized, then @max_width and @max_height will be used as the
448 * default maximum resolution for all codecs on this HW info.
450 void (*max_resolution)(struct i965_driver_data *, struct object_config *, int *, int *);
454 int min_linear_wpitch;
455 int min_linear_hpitch;
457 unsigned int h264_mvc_dec_profiles;
458 unsigned int vp9_dec_profiles;
459 unsigned int vp9_enc_profiles;
461 unsigned int h264_dec_chroma_formats;
462 unsigned int jpeg_dec_chroma_formats;
463 unsigned int jpeg_enc_chroma_formats;
464 unsigned int hevc_dec_chroma_formats;
465 unsigned int vp9_dec_chroma_formats;
467 unsigned int has_mpeg2_decoding:1;
468 unsigned int has_mpeg2_encoding:1;
469 unsigned int has_h264_decoding:1;
470 unsigned int has_h264_encoding:1;
471 unsigned int has_vc1_decoding:1;
472 unsigned int has_vc1_encoding:1;
473 unsigned int has_jpeg_decoding:1;
474 unsigned int has_jpeg_encoding:1;
475 unsigned int has_vpp:1;
476 unsigned int has_accelerated_getimage:1;
477 unsigned int has_accelerated_putimage:1;
478 unsigned int has_tiled_surface:1;
479 unsigned int has_di_motion_adptive:1;
480 unsigned int has_di_motion_compensated:1;
481 unsigned int has_vp8_decoding:1;
482 unsigned int has_vp8_encoding:1;
483 unsigned int has_h264_mvc_encoding:1;
484 unsigned int has_hevc_decoding:1;
485 unsigned int has_hevc_encoding:1;
486 unsigned int has_hevc10_encoding:1;
487 unsigned int has_hevc10_decoding:1;
488 unsigned int has_vp9_decoding:1;
489 unsigned int has_vpp_p010:1;
490 unsigned int has_lp_h264_encoding:1;
491 unsigned int has_vp9_encoding:1;
493 unsigned int lp_h264_brc_mode;
495 unsigned int num_filters;
496 struct i965_filter filters[VAProcFilterCount];
500 #include "i965_render.h"
502 struct i965_driver_data
504 struct intel_driver_data intel;
505 struct object_heap config_heap;
506 struct object_heap context_heap;
507 struct object_heap surface_heap;
508 struct object_heap buffer_heap;
509 struct object_heap image_heap;
510 struct object_heap subpic_heap;
511 struct hw_codec_info *codec_info;
513 _I965Mutex render_mutex;
515 struct intel_batchbuffer *batch;
516 struct intel_batchbuffer *pp_batch;
517 struct i965_render_state render_state;
521 VADisplayAttribute *display_attributes;
522 unsigned int num_display_attributes;
523 VADisplayAttribute *rotation_attrib;
524 VADisplayAttribute *brightness_attrib;
525 VADisplayAttribute *contrast_attrib;
526 VADisplayAttribute *hue_attrib;
527 VADisplayAttribute *saturation_attrib;
528 VAContextID current_context_id;
530 /* VA/DRI (X11) specific data */
531 struct va_dri_output *dri_output;
533 /* VA/Wayland specific data */
534 struct va_wl_output *wl_output;
536 VADriverContextP wrapper_pdrvctx;
539 #define NEW_CONFIG_ID() object_heap_allocate(&i965->config_heap);
540 #define NEW_CONTEXT_ID() object_heap_allocate(&i965->context_heap);
541 #define NEW_SURFACE_ID() object_heap_allocate(&i965->surface_heap);
542 #define NEW_BUFFER_ID() object_heap_allocate(&i965->buffer_heap);
543 #define NEW_IMAGE_ID() object_heap_allocate(&i965->image_heap);
544 #define NEW_SUBPIC_ID() object_heap_allocate(&i965->subpic_heap);
546 #define CONFIG(id) ((struct object_config *)object_heap_lookup(&i965->config_heap, id))
547 #define CONTEXT(id) ((struct object_context *)object_heap_lookup(&i965->context_heap, id))
548 #define SURFACE(id) ((struct object_surface *)object_heap_lookup(&i965->surface_heap, id))
549 #define BUFFER(id) ((struct object_buffer *)object_heap_lookup(&i965->buffer_heap, id))
550 #define IMAGE(id) ((struct object_image *)object_heap_lookup(&i965->image_heap, id))
551 #define SUBPIC(id) ((struct object_subpic *)object_heap_lookup(&i965->subpic_heap, id))
553 #define FOURCC_IA44 0x34344149
554 #define FOURCC_AI44 0x34344941
556 #define STRIDE(w) (((w) + 0xf) & ~0xf)
557 #define SIZE_YUV420(w, h) (h * (STRIDE(w) + STRIDE(w >> 1)))
559 static INLINE struct i965_driver_data *
560 i965_driver_data(VADriverContextP ctx)
562 return (struct i965_driver_data *)(ctx->pDriverData);
566 i965_check_alloc_surface_bo(VADriverContextP ctx,
567 struct object_surface *obj_surface,
570 unsigned int subsampling);
573 va_enc_packed_type_to_idx(int packed_type);
575 /* reserve 2 byte for internal using */
577 #define CODEC_MPEG2 1
578 #define CODEC_H264_MVC 2
584 #define H264_DELIMITER0 0x00
585 #define H264_DELIMITER1 0x00
586 #define H264_DELIMITER2 0x00
587 #define H264_DELIMITER3 0x00
588 #define H264_DELIMITER4 0x00
590 #define MPEG2_DELIMITER0 0x00
591 #define MPEG2_DELIMITER1 0x00
592 #define MPEG2_DELIMITER2 0x00
593 #define MPEG2_DELIMITER3 0x00
594 #define MPEG2_DELIMITER4 0xb0
596 #define HEVC_DELIMITER0 0x00
597 #define HEVC_DELIMITER1 0x00
598 #define HEVC_DELIMITER2 0x00
599 #define HEVC_DELIMITER3 0x00
600 #define HEVC_DELIMITER4 0x00
602 struct i965_coded_buffer_segment
605 VACodedBufferSegment base;
606 unsigned char pad0[64]; /* change the size if sizeof(VACodedBufferSegment) > 64 */
611 unsigned int status_support;
614 unsigned int codec_private_data[512]; /* Store codec private data, must be 16-bytes aligned */
617 #define I965_CODEDBUFFER_HEADER_SIZE ALIGN(sizeof(struct i965_coded_buffer_segment), 0x1000)
619 extern VAStatus i965_MapBuffer(VADriverContextP ctx,
620 VABufferID buf_id, /* in */
621 void **pbuf); /* out */
623 extern VAStatus i965_UnmapBuffer(VADriverContextP ctx, VABufferID buf_id);
625 extern VAStatus i965_DestroySurfaces(VADriverContextP ctx,
626 VASurfaceID *surface_list,
629 extern VAStatus i965_CreateSurfaces(VADriverContextP ctx,
634 VASurfaceID *surfaces);
636 #define I965_SURFACE_MEM_NATIVE 0
637 #define I965_SURFACE_MEM_GEM_FLINK 1
638 #define I965_SURFACE_MEM_DRM_PRIME 2
641 i965_destroy_surface_storage(struct object_surface *obj_surface);
643 #endif /* _I965_DRV_VIDEO_H_ */