2 * Copyright ?2009 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Xiang Haihao <haihao.xiang@intel.com>
26 * Zou Nan hai <nanhai.zou@intel.com>
30 #ifndef _I965_DRV_VIDEO_H_
31 #define _I965_DRV_VIDEO_H_
34 #include <va/va_enc_h264.h>
35 #include <va/va_enc_mpeg2.h>
36 #include <va/va_enc_hevc.h>
37 #include <va/va_enc_jpeg.h>
38 #include <va/va_enc_vp8.h>
39 #include <va/va_vpp.h>
40 #include <va/va_backend.h>
41 #include <va/va_backend_vpp.h>
43 #include "i965_mutext.h"
44 #include "object_heap.h"
45 #include "intel_driver.h"
46 #include "i965_fourcc.h"
48 #define I965_MAX_PROFILES 20
49 #define I965_MAX_ENTRYPOINTS 5
50 #define I965_MAX_CONFIG_ATTRIBUTES 32
51 #define I965_MAX_IMAGE_FORMATS 10
52 #define I965_MAX_SUBPIC_FORMATS 6
53 #define I965_MAX_SUBPIC_SUM 4
54 #define I965_MAX_SURFACE_ATTRIBUTES 16
56 #define INTEL_STR_DRIVER_VENDOR "Intel"
57 #define INTEL_STR_DRIVER_NAME "i965"
59 #define I965_SURFACE_TYPE_IMAGE 0
60 #define I965_SURFACE_TYPE_SURFACE 1
62 #define I965_SURFACE_FLAG_FRAME 0x00000000
63 #define I965_SURFACE_FLAG_TOP_FIELD_FIRST 0x00000001
64 #define I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST 0x00000002
66 #define DEFAULT_BRIGHTNESS 0
67 #define DEFAULT_CONTRAST 50
69 #define DEFAULT_SATURATION 50
71 #define ENCODER_QUALITY_RANGE 2
72 #define ENCODER_QUALITY_RANGE_AVC 8
73 #define ENCODER_DEFAULT_QUALITY 1
74 #define ENCODER_DEFAULT_QUALITY_AVC 4
75 #define ENCODER_HIGH_QUALITY ENCODER_DEFAULT_QUALITY
76 #define ENCODER_LOW_QUALITY 2
78 #define I965_MAX_NUM_ROI_REGIONS 8
79 #define I965_MAX_NUM_SLICE 32
81 #define ENCODER_LP_QUALITY_RANGE 8
83 #define HAS_MPEG2_DECODING(ctx) ((ctx)->codec_info->has_mpeg2_decoding && \
86 #define HAS_MPEG2_ENCODING(ctx) ((ctx)->codec_info->has_mpeg2_encoding && \
89 #define HAS_H264_DECODING(ctx) ((ctx)->codec_info->has_h264_decoding && \
92 #define HAS_H264_ENCODING(ctx) ((ctx)->codec_info->has_h264_encoding && \
95 #define HAS_LP_H264_ENCODING(ctx) ((ctx)->codec_info->has_lp_h264_encoding && \
98 #define HAS_VC1_DECODING(ctx) ((ctx)->codec_info->has_vc1_decoding && \
101 #define HAS_JPEG_DECODING(ctx) ((ctx)->codec_info->has_jpeg_decoding && \
102 (ctx)->intel.has_bsd)
104 #define HAS_JPEG_ENCODING(ctx) ((ctx)->codec_info->has_jpeg_encoding && \
105 (ctx)->intel.has_bsd)
107 #define HAS_VPP(ctx) ((ctx)->codec_info->has_vpp)
109 #define HAS_ACCELERATED_GETIMAGE(ctx) ((ctx)->codec_info->has_accelerated_getimage)
111 #define HAS_ACCELERATED_PUTIMAGE(ctx) ((ctx)->codec_info->has_accelerated_putimage)
113 #define HAS_TILED_SURFACE(ctx) ((ctx)->codec_info->has_tiled_surface)
115 #define HAS_VP8_DECODING(ctx) ((ctx)->codec_info->has_vp8_decoding && \
116 (ctx)->intel.has_bsd)
118 #define HAS_VP8_ENCODING(ctx) ((ctx)->codec_info->has_vp8_encoding && \
119 (ctx)->intel.has_bsd)
121 #define HAS_H264_MVC_DECODING(ctx) \
122 (HAS_H264_DECODING(ctx) && (ctx)->codec_info->h264_mvc_dec_profiles)
124 #define HAS_H264_MVC_DECODING_PROFILE(ctx, profile) \
125 (HAS_H264_MVC_DECODING(ctx) && \
126 ((ctx)->codec_info->h264_mvc_dec_profiles & (1U << profile)))
128 #define HAS_H264_MVC_ENCODING(ctx) ((ctx)->codec_info->has_h264_mvc_encoding && \
129 (ctx)->intel.has_bsd)
131 #define HAS_HEVC_DECODING(ctx) ((ctx)->codec_info->has_hevc_decoding && \
132 (ctx)->intel.has_bsd)
134 #define HAS_HEVC_ENCODING(ctx) ((ctx)->codec_info->has_hevc_encoding && \
135 (ctx)->intel.has_bsd)
137 #define HAS_VP9_DECODING(ctx) ((ctx)->codec_info->has_vp9_decoding && \
138 (ctx)->intel.has_bsd)
140 #define HAS_VP9_DECODING_PROFILE(ctx, profile) \
141 (HAS_VP9_DECODING(ctx) && \
142 ((ctx)->codec_info->vp9_dec_profiles & (1U << (profile - VAProfileVP9Profile0))))
144 #define HAS_HEVC10_DECODING(ctx) ((ctx)->codec_info->has_hevc10_decoding && \
145 (ctx)->intel.has_bsd)
146 #define HAS_HEVC10_ENCODING(ctx) ((ctx)->codec_info->has_hevc10_encoding && \
147 (ctx)->intel.has_bsd)
149 #define HAS_VPP_P010(ctx) ((ctx)->codec_info->has_vpp_p010 && \
150 (ctx)->intel.has_bsd)
152 #define HAS_VP9_ENCODING(ctx) ((ctx)->codec_info->has_vp9_encoding && \
153 (ctx)->intel.has_bsd)
155 #define HAS_VP9_ENCODING_PROFILE(ctx, profile) \
156 (HAS_VP9_ENCODING(ctx) && \
157 ((ctx)->codec_info->vp9_enc_profiles & (1U << (profile - VAProfileVP9Profile0))))
161 struct object_base *base;
170 const uint32_t (*bin)[4];
173 unsigned int kernel_offset;
178 unsigned char *buffer;
186 struct object_base base;
188 VAEntrypoint entrypoint;
189 VAConfigAttrib attrib_list[I965_MAX_CONFIG_ATTRIBUTES];
192 VAGenericID wrapper_config;
195 #define NUM_SLICES 10
197 struct codec_state_base {
198 uint32_t chroma_formats;
203 struct codec_state_base base;
204 struct buffer_store *pic_param;
205 struct buffer_store **slice_params;
206 struct buffer_store *iq_matrix;
207 struct buffer_store *bit_plane;
208 struct buffer_store *huffman_table;
209 struct buffer_store **slice_datas;
210 struct buffer_store *probability_data;
211 VASurfaceID current_render_target;
212 int max_slice_params;
214 int num_slice_params;
217 struct object_surface *render_object;
218 struct object_surface *reference_objects[16]; /* Up to 2 reference surfaces are valid for MPEG-2,*/
221 #define SLICE_PACKED_DATA_INDEX_TYPE 0x80000000
222 #define SLICE_PACKED_DATA_INDEX_MASK 0x00FFFFFF
226 struct codec_state_base base;
227 struct buffer_store *iq_matrix;
228 struct buffer_store *q_matrix;
229 struct buffer_store *huffman_table;
232 struct buffer_store *seq_param_ext;
233 struct buffer_store *pic_param_ext;
234 struct buffer_store *packed_header_param[5];
235 struct buffer_store *packed_header_data[5];
236 struct buffer_store **slice_params_ext;
237 struct buffer_store *encmb_map;
238 int max_slice_params_ext;
239 int num_slice_params_ext;
241 /* Check the user-configurable packed_header attribute.
242 * Currently it is mainly used to check whether the packed slice_header data
243 * is provided by user or the driver.
244 * TBD: It will check for the packed SPS/PPS/MISC/RAWDATA and so on.
246 unsigned int packed_header_flag;
247 /* For the packed data that needs to be inserted into video clip */
248 /* currently it is mainly to track packed raw data and packed slice_header data. */
249 struct buffer_store **packed_header_params_ext;
250 int max_packed_header_params_ext;
251 int num_packed_header_params_ext;
252 struct buffer_store **packed_header_data_ext;
253 int max_packed_header_data_ext;
254 int num_packed_header_data_ext;
256 /* the index of current vps and sps ,special for HEVC*/
257 int vps_sps_seq_index;
258 /* the index of current slice */
260 /* the array is determined by max_slice_params_ext */
262 /* This is to store the first index of packed data for one slice */
263 int *slice_rawdata_index;
264 /* This is to store the number of packed data for one slice.
265 * Both packed rawdata and slice_header data are tracked by this
266 * this variable. That is to say: When one packed slice_header is parsed,
267 * this variable will also be increased.
269 int *slice_rawdata_count;
271 /* This is to store the index of packed slice header for one slice */
272 int *slice_header_index;
274 int last_packed_header_type;
278 struct buffer_store *misc_param[16][8];
280 VASurfaceID current_render_target;
281 struct object_surface *input_yuv_object;
282 struct object_surface *reconstructed_object;
283 struct object_buffer *coded_buf_object;
284 struct object_surface *reference_objects[16]; /* Up to 2 reference surfaces are valid for MPEG-2,*/
289 struct codec_state_base base;
290 struct buffer_store *pipeline_param;
292 VASurfaceID current_render_target;
301 struct codec_state_base base;
302 struct decode_state decode;
303 struct encode_state encode;
304 struct proc_state proc;
309 VAStatus (*run)(VADriverContextP ctx,
311 union codec_state *codec_state,
312 struct hw_context *hw_context);
313 void (*destroy)(void *);
314 VAStatus (*get_status)(VADriverContextP ctx,
315 struct hw_context *hw_context,
317 struct intel_batchbuffer *batch;
320 struct object_context
322 struct object_base base;
323 VAContextID context_id;
324 struct object_config *obj_config;
325 VASurfaceID *render_targets; //input->encode, output->decode
326 int num_render_targets;
331 union codec_state codec_state;
332 struct hw_context *hw_context;
334 VAGenericID wrapper_context;
337 #define SURFACE_REFERENCED (1 << 0)
338 #define SURFACE_DERIVED (1 << 2)
339 #define SURFACE_ALL_MASK ((SURFACE_REFERENCED) | \
342 struct object_surface
344 struct object_base base;
345 VASurfaceStatus status;
346 VASubpictureID subpic[I965_MAX_SUBPIC_SUM];
347 struct object_subpic *obj_subpic[I965_MAX_SUBPIC_SUM];
348 unsigned int subpic_render_idx;
350 int width; /* the pitch of plane 0 in bytes in horizontal direction */
351 int height; /* the pitch of plane 0 in bytes in vertical direction */
353 int orig_width; /* the width of plane 0 in pixels */
354 int orig_height; /* the height of plane 0 in pixels */
358 unsigned int expected_format;
359 VAImageID locked_image_id;
360 VAImageID derived_image_id;
361 void (*free_private_data)(void **data);
363 unsigned int subsampling;
371 /* user specified attributes see: VASurfaceAttribExternalBuffers/VA_SURFACE_ATTRIB_MEM_TYPE_VA */
372 uint32_t user_disable_tiling : 1;
373 uint32_t user_h_stride_set : 1;
374 uint32_t user_v_stride_set : 1;
375 /* we need clear right and bottom border for NV12.
376 * to avoid encode run to run issue*/
377 uint32_t border_cleared : 1;
379 VAGenericID wrapper_surface;
381 int exported_primefd;
386 struct object_base base;
387 struct buffer_store *buffer_store;
388 int max_num_elements;
394 unsigned int export_refcount;
395 VABufferInfo export_state;
397 VAGenericID wrapper_buffer;
398 VAContextID context_id;
403 struct object_base base;
406 unsigned int *palette;
407 VASurfaceID derived_surface;
412 struct object_base base;
414 struct object_image *obj_image;
415 VARectangle src_rect;
416 VARectangle dst_rect;
426 #define I965_RING_NULL 0
427 #define I965_RING_BSD 1
428 #define I965_RING_BLT 2
429 #define I965_RING_VEBOX 3
433 VAProcFilterType type;
437 struct i965_driver_data;
441 struct hw_context *(*dec_hw_context_init)(VADriverContextP, struct object_config *);
442 struct hw_context *(*enc_hw_context_init)(VADriverContextP, struct object_config *);
443 struct hw_context *(*proc_hw_context_init)(VADriverContextP, struct object_config *);
444 bool (*render_init)(VADriverContextP);
445 void (*post_processing_context_init)(VADriverContextP, void *, struct intel_batchbuffer *);
446 void (*preinit_hw_codec)(VADriverContextP, struct hw_codec_info *);
449 * Allows HW info to support per-codec max resolution. If this functor is
450 * not initialized, then @max_width and @max_height will be used as the
451 * default maximum resolution for all codecs on this HW info.
453 void (*max_resolution)(struct i965_driver_data *, struct object_config *, int *, int *);
457 int min_linear_wpitch;
458 int min_linear_hpitch;
460 unsigned int h264_mvc_dec_profiles;
461 unsigned int vp9_dec_profiles;
462 unsigned int vp9_enc_profiles;
464 unsigned int h264_dec_chroma_formats;
465 unsigned int jpeg_dec_chroma_formats;
466 unsigned int jpeg_enc_chroma_formats;
467 unsigned int hevc_dec_chroma_formats;
468 unsigned int vp9_dec_chroma_formats;
470 unsigned int has_mpeg2_decoding:1;
471 unsigned int has_mpeg2_encoding:1;
472 unsigned int has_h264_decoding:1;
473 unsigned int has_h264_encoding:1;
474 unsigned int has_vc1_decoding:1;
475 unsigned int has_vc1_encoding:1;
476 unsigned int has_jpeg_decoding:1;
477 unsigned int has_jpeg_encoding:1;
478 unsigned int has_vpp:1;
479 unsigned int has_accelerated_getimage:1;
480 unsigned int has_accelerated_putimage:1;
481 unsigned int has_tiled_surface:1;
482 unsigned int has_di_motion_adptive:1;
483 unsigned int has_di_motion_compensated:1;
484 unsigned int has_vp8_decoding:1;
485 unsigned int has_vp8_encoding:1;
486 unsigned int has_h264_mvc_encoding:1;
487 unsigned int has_hevc_decoding:1;
488 unsigned int has_hevc_encoding:1;
489 unsigned int has_hevc10_encoding:1;
490 unsigned int has_hevc10_decoding:1;
491 unsigned int has_vp9_decoding:1;
492 unsigned int has_vpp_p010:1;
493 unsigned int has_lp_h264_encoding:1;
494 unsigned int has_vp9_encoding:1;
496 unsigned int lp_h264_brc_mode;
498 unsigned int num_filters;
499 struct i965_filter filters[VAProcFilterCount];
503 #include "i965_render.h"
504 #include "i965_gpe_utils.h"
506 struct i965_driver_data
508 struct intel_driver_data intel;
509 struct object_heap config_heap;
510 struct object_heap context_heap;
511 struct object_heap surface_heap;
512 struct object_heap buffer_heap;
513 struct object_heap image_heap;
514 struct object_heap subpic_heap;
515 struct hw_codec_info *codec_info;
517 _I965Mutex render_mutex;
519 struct intel_batchbuffer *batch;
520 struct intel_batchbuffer *pp_batch;
521 struct i965_render_state render_state;
525 VADisplayAttribute *display_attributes;
526 unsigned int num_display_attributes;
527 VADisplayAttribute *rotation_attrib;
528 VADisplayAttribute *brightness_attrib;
529 VADisplayAttribute *contrast_attrib;
530 VADisplayAttribute *hue_attrib;
531 VADisplayAttribute *saturation_attrib;
532 VAContextID current_context_id;
534 /* VA/DRI (X11) specific data */
535 struct va_dri_output *dri_output;
537 /* VA/Wayland specific data */
538 struct va_wl_output *wl_output;
540 VADriverContextP wrapper_pdrvctx;
542 struct i965_gpe_table gpe_table;
545 #define NEW_CONFIG_ID() object_heap_allocate(&i965->config_heap);
546 #define NEW_CONTEXT_ID() object_heap_allocate(&i965->context_heap);
547 #define NEW_SURFACE_ID() object_heap_allocate(&i965->surface_heap);
548 #define NEW_BUFFER_ID() object_heap_allocate(&i965->buffer_heap);
549 #define NEW_IMAGE_ID() object_heap_allocate(&i965->image_heap);
550 #define NEW_SUBPIC_ID() object_heap_allocate(&i965->subpic_heap);
552 #define CONFIG(id) ((struct object_config *)object_heap_lookup(&i965->config_heap, id))
553 #define CONTEXT(id) ((struct object_context *)object_heap_lookup(&i965->context_heap, id))
554 #define SURFACE(id) ((struct object_surface *)object_heap_lookup(&i965->surface_heap, id))
555 #define BUFFER(id) ((struct object_buffer *)object_heap_lookup(&i965->buffer_heap, id))
556 #define IMAGE(id) ((struct object_image *)object_heap_lookup(&i965->image_heap, id))
557 #define SUBPIC(id) ((struct object_subpic *)object_heap_lookup(&i965->subpic_heap, id))
559 #define FOURCC_IA44 0x34344149
560 #define FOURCC_AI44 0x34344941
562 #define STRIDE(w) (((w) + 0xf) & ~0xf)
563 #define SIZE_YUV420(w, h) (h * (STRIDE(w) + STRIDE(w >> 1)))
565 static INLINE struct i965_driver_data *
566 i965_driver_data(VADriverContextP ctx)
568 return (struct i965_driver_data *)(ctx->pDriverData);
572 i965_check_alloc_surface_bo(VADriverContextP ctx,
573 struct object_surface *obj_surface,
576 unsigned int subsampling);
579 va_enc_packed_type_to_idx(int packed_type);
581 /* reserve 2 byte for internal using */
583 #define CODEC_MPEG2 1
584 #define CODEC_H264_MVC 2
590 #define H264_DELIMITER0 0x00
591 #define H264_DELIMITER1 0x00
592 #define H264_DELIMITER2 0x00
593 #define H264_DELIMITER3 0x00
594 #define H264_DELIMITER4 0x00
596 #define MPEG2_DELIMITER0 0x00
597 #define MPEG2_DELIMITER1 0x00
598 #define MPEG2_DELIMITER2 0x00
599 #define MPEG2_DELIMITER3 0x00
600 #define MPEG2_DELIMITER4 0xb0
602 #define HEVC_DELIMITER0 0x00
603 #define HEVC_DELIMITER1 0x00
604 #define HEVC_DELIMITER2 0x00
605 #define HEVC_DELIMITER3 0x00
606 #define HEVC_DELIMITER4 0x00
608 struct i965_coded_buffer_segment
611 VACodedBufferSegment base;
612 unsigned char pad0[64]; /* change the size if sizeof(VACodedBufferSegment) > 64 */
617 unsigned int status_support;
620 unsigned int codec_private_data[512]; /* Store codec private data, must be 16-bytes aligned */
623 #define I965_CODEDBUFFER_HEADER_SIZE ALIGN(sizeof(struct i965_coded_buffer_segment), 0x1000)
625 extern VAStatus i965_MapBuffer(VADriverContextP ctx,
626 VABufferID buf_id, /* in */
627 void **pbuf); /* out */
629 extern VAStatus i965_UnmapBuffer(VADriverContextP ctx, VABufferID buf_id);
631 extern VAStatus i965_DestroySurfaces(VADriverContextP ctx,
632 VASurfaceID *surface_list,
635 extern VAStatus i965_CreateSurfaces(VADriverContextP ctx,
640 VASurfaceID *surfaces);
642 #define I965_SURFACE_MEM_NATIVE 0
643 #define I965_SURFACE_MEM_GEM_FLINK 1
644 #define I965_SURFACE_MEM_DRM_PRIME 2
647 i965_destroy_surface_storage(struct object_surface *obj_surface);
649 #endif /* _I965_DRV_VIDEO_H_ */