2 * Copyright ?2009 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Xiang Haihao <haihao.xiang@intel.com>
26 * Zou Nan hai <nanhai.zou@intel.com>
30 #ifndef _I965_DRV_VIDEO_H_
31 #define _I965_DRV_VIDEO_H_
34 #include <va/va_enc_h264.h>
35 #include <va/va_enc_mpeg2.h>
36 #include <va/va_enc_hevc.h>
37 #include <va/va_enc_jpeg.h>
38 #include <va/va_enc_vp8.h>
39 #include <va/va_vpp.h>
40 #include <va/va_backend.h>
41 #include <va/va_backend_vpp.h>
42 #include <va/va_fei.h>
43 #include <va/va_fei_h264.h>
45 #include "i965_mutext.h"
46 #include "object_heap.h"
47 #include "intel_driver.h"
48 #include "i965_fourcc.h"
50 #define I965_MAX_PROFILES 20
51 #define I965_MAX_ENTRYPOINTS 6
52 #define I965_MAX_CONFIG_ATTRIBUTES 32
53 #define I965_MAX_IMAGE_FORMATS 10
54 #define I965_MAX_SUBPIC_FORMATS 6
55 #define I965_MAX_SUBPIC_SUM 4
56 #define I965_MAX_SURFACE_ATTRIBUTES 32
58 #define INTEL_STR_DRIVER_VENDOR "Intel"
59 #define INTEL_STR_DRIVER_NAME "i965"
61 #define I965_SURFACE_TYPE_IMAGE 0
62 #define I965_SURFACE_TYPE_SURFACE 1
64 #define I965_SURFACE_FLAG_FRAME 0x00000000
65 #define I965_SURFACE_FLAG_TOP_FIELD_FIRST 0x00000001
66 #define I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST 0x00000002
68 #define DEFAULT_BRIGHTNESS 0
69 #define DEFAULT_CONTRAST 50
71 #define DEFAULT_SATURATION 50
73 #define ENCODER_QUALITY_RANGE 2
74 #define ENCODER_QUALITY_RANGE_AVC 7
75 #define ENCODER_QUALITY_RANGE_HEVC 7
76 #define ENCODER_DEFAULT_QUALITY 1
77 #define ENCODER_DEFAULT_QUALITY_AVC 4
78 #define ENCODER_DEFAULT_QUALITY_HEVC 4
79 #define ENCODER_HIGH_QUALITY ENCODER_DEFAULT_QUALITY
80 #define ENCODER_LOW_QUALITY 2
82 #define I965_MAX_NUM_ROI_REGIONS 8
83 #define I965_MAX_NUM_SLICE 32
85 #define ENCODER_LP_QUALITY_RANGE 8
87 #define HAS_MPEG2_DECODING(ctx) ((ctx)->codec_info->has_mpeg2_decoding && \
90 #define HAS_MPEG2_ENCODING(ctx) ((ctx)->codec_info->has_mpeg2_encoding && \
93 #define HAS_H264_DECODING(ctx) ((ctx)->codec_info->has_h264_decoding && \
96 #define HAS_H264_ENCODING(ctx) ((ctx)->codec_info->has_h264_encoding && \
99 #define HAS_LP_H264_ENCODING(ctx) ((ctx)->codec_info->has_lp_h264_encoding && \
100 (ctx)->intel.has_bsd)
102 #define HAS_FEI_H264_ENCODING(ctx) ((ctx)->codec_info->has_fei_h264_encoding && \
103 (ctx)->intel.has_bsd)
105 #define HAS_VC1_DECODING(ctx) ((ctx)->codec_info->has_vc1_decoding && \
106 (ctx)->intel.has_bsd)
108 #define HAS_JPEG_DECODING(ctx) ((ctx)->codec_info->has_jpeg_decoding && \
109 (ctx)->intel.has_bsd)
111 #define HAS_JPEG_ENCODING(ctx) ((ctx)->codec_info->has_jpeg_encoding && \
112 (ctx)->intel.has_bsd)
114 #define HAS_VPP(ctx) ((ctx)->codec_info->has_vpp)
116 #define HAS_ACCELERATED_GETIMAGE(ctx) ((ctx)->codec_info->has_accelerated_getimage)
118 #define HAS_ACCELERATED_PUTIMAGE(ctx) ((ctx)->codec_info->has_accelerated_putimage)
120 #define HAS_TILED_SURFACE(ctx) ((ctx)->codec_info->has_tiled_surface)
122 #define HAS_VP8_DECODING(ctx) ((ctx)->codec_info->has_vp8_decoding && \
123 (ctx)->intel.has_bsd)
125 #define HAS_VP8_ENCODING(ctx) ((ctx)->codec_info->has_vp8_encoding && \
126 (ctx)->intel.has_bsd)
128 #define HAS_H264_MVC_DECODING(ctx) \
129 (HAS_H264_DECODING(ctx) && (ctx)->codec_info->h264_mvc_dec_profiles)
131 #define HAS_H264_MVC_DECODING_PROFILE(ctx, profile) \
132 (HAS_H264_MVC_DECODING(ctx) && \
133 ((ctx)->codec_info->h264_mvc_dec_profiles & (1U << profile)))
135 #define HAS_H264_MVC_ENCODING(ctx) ((ctx)->codec_info->has_h264_mvc_encoding && \
136 (ctx)->intel.has_bsd)
138 #define HAS_HEVC_DECODING(ctx) ((ctx)->codec_info->has_hevc_decoding && \
139 (ctx)->intel.has_bsd)
141 #define HAS_HEVC_ENCODING(ctx) ((ctx)->codec_info->has_hevc_encoding && \
142 (ctx)->intel.has_bsd)
144 #define HAS_VP9_DECODING(ctx) ((ctx)->codec_info->has_vp9_decoding && \
145 (ctx)->intel.has_bsd)
147 #define HAS_VP9_DECODING_PROFILE(ctx, profile) \
148 (HAS_VP9_DECODING(ctx) && \
149 ((ctx)->codec_info->vp9_dec_profiles & (1U << (profile - VAProfileVP9Profile0))))
151 #define HAS_HEVC10_DECODING(ctx) ((ctx)->codec_info->has_hevc10_decoding && \
152 (ctx)->intel.has_bsd)
153 #define HAS_HEVC10_ENCODING(ctx) ((ctx)->codec_info->has_hevc10_encoding && \
154 (ctx)->intel.has_bsd)
156 #define HAS_VPP_P010(ctx) ((ctx)->codec_info->has_vpp_p010 && \
157 (ctx)->intel.has_bsd)
159 #define HAS_VP9_ENCODING(ctx) ((ctx)->codec_info->has_vp9_encoding && \
160 (ctx)->intel.has_bsd)
162 #define HAS_VP9_ENCODING_PROFILE(ctx, profile) \
163 (HAS_VP9_ENCODING(ctx) && \
164 ((ctx)->codec_info->vp9_enc_profiles & (1U << (profile - VAProfileVP9Profile0))))
166 struct i965_surface {
167 struct object_base *base;
175 const uint32_t (*bin)[4];
178 unsigned int kernel_offset;
181 struct buffer_store {
182 unsigned char *buffer;
188 struct object_config {
189 struct object_base base;
191 VAEntrypoint entrypoint;
192 VAConfigAttrib attrib_list[I965_MAX_CONFIG_ATTRIBUTES];
195 VAGenericID wrapper_config;
198 #define NUM_SLICES 10
200 struct codec_state_base {
201 uint32_t chroma_formats;
204 struct decode_state {
205 struct codec_state_base base;
206 struct buffer_store *pic_param;
207 struct buffer_store **slice_params;
208 struct buffer_store *iq_matrix;
209 struct buffer_store *bit_plane;
210 struct buffer_store *huffman_table;
211 struct buffer_store **slice_datas;
212 struct buffer_store *probability_data;
213 VASurfaceID current_render_target;
214 int max_slice_params;
216 int num_slice_params;
219 struct object_surface *render_object;
220 struct object_surface *reference_objects[16]; /* Up to 2 reference surfaces are valid for MPEG-2,*/
223 #define SLICE_PACKED_DATA_INDEX_TYPE 0x80000000
224 #define SLICE_PACKED_DATA_INDEX_MASK 0x00FFFFFF
226 struct encode_state {
227 struct codec_state_base base;
228 struct buffer_store *iq_matrix;
229 struct buffer_store *q_matrix;
230 struct buffer_store *huffman_table;
233 struct buffer_store *seq_param_ext;
234 struct buffer_store *pic_param_ext;
235 struct buffer_store *packed_header_param[5];
236 struct buffer_store *packed_header_data[5];
237 struct buffer_store **slice_params_ext;
238 struct buffer_store *encmb_map;
239 int max_slice_params_ext;
240 int num_slice_params_ext;
242 /* Check the user-configurable packed_header attribute.
243 * Currently it is mainly used to check whether the packed slice_header data
244 * is provided by user or the driver.
245 * TBD: It will check for the packed SPS/PPS/MISC/RAWDATA and so on.
247 unsigned int packed_header_flag;
248 /* For the packed data that needs to be inserted into video clip */
249 /* currently it is mainly to track packed raw data and packed slice_header data. */
250 struct buffer_store **packed_header_params_ext;
251 int max_packed_header_params_ext;
252 int num_packed_header_params_ext;
253 struct buffer_store **packed_header_data_ext;
254 int max_packed_header_data_ext;
255 int num_packed_header_data_ext;
257 /* the index of current vps and sps ,special for HEVC*/
258 int vps_sps_seq_index;
259 /* the index of current slice */
261 /* the array is determined by max_slice_params_ext */
263 /* This is to store the first index of packed data for one slice */
264 int *slice_rawdata_index;
265 /* This is to store the number of packed data for one slice.
266 * Both packed rawdata and slice_header data are tracked by this
267 * variable. That is to say: When one packed slice_header is parsed,
268 * this variable will also be increased.
270 int *slice_rawdata_count;
272 /* This is to store the index of packed slice header for one slice */
273 int *slice_header_index;
275 int last_packed_header_type;
279 struct buffer_store *misc_param[19][8];
281 VASurfaceID current_render_target;
282 struct object_surface *input_yuv_object;
283 struct object_surface *reconstructed_object;
284 struct object_buffer *coded_buf_object;
285 struct object_surface *reference_objects[16]; /* Up to 2 reference surfaces are valid for MPEG-2,*/
289 struct codec_state_base base;
290 struct buffer_store *pipeline_param;
292 VASurfaceID current_render_target;
300 struct codec_state_base base;
301 struct decode_state decode;
302 struct encode_state encode;
303 struct proc_state proc;
307 VAStatus(*run)(VADriverContextP ctx,
309 union codec_state *codec_state,
310 struct hw_context *hw_context);
311 void (*destroy)(void *);
312 VAStatus(*get_status)(VADriverContextP ctx,
313 struct hw_context *hw_context,
315 struct intel_batchbuffer *batch;
318 struct object_context {
319 struct object_base base;
320 VAContextID context_id;
321 struct object_config *obj_config;
322 VASurfaceID *render_targets; //input->encode, output->decode
323 int num_render_targets;
328 union codec_state codec_state;
329 struct hw_context *hw_context;
331 VAGenericID wrapper_context;
334 #define SURFACE_REFERENCED (1 << 0)
335 #define SURFACE_DERIVED (1 << 2)
336 #define SURFACE_ALL_MASK ((SURFACE_REFERENCED) | \
339 struct object_surface {
340 struct object_base base;
341 VASurfaceStatus status;
342 VASubpictureID subpic[I965_MAX_SUBPIC_SUM];
343 struct object_subpic *obj_subpic[I965_MAX_SUBPIC_SUM];
344 unsigned int subpic_render_idx;
346 int width; /* the pitch of plane 0 in bytes in horizontal direction */
347 int height; /* the pitch of plane 0 in bytes in vertical direction */
349 int orig_width; /* the width of plane 0 in pixels */
350 int orig_height; /* the height of plane 0 in pixels */
354 unsigned int expected_format;
355 VAImageID locked_image_id;
356 VAImageID derived_image_id;
357 void (*free_private_data)(void **data);
359 unsigned int subsampling;
367 /* user specified attributes see: VASurfaceAttribExternalBuffers/VA_SURFACE_ATTRIB_MEM_TYPE_VA */
368 uint32_t user_disable_tiling : 1;
369 uint32_t user_h_stride_set : 1;
370 uint32_t user_v_stride_set : 1;
371 /* we need clear right and bottom border for NV12.
372 * to avoid encode run to run issue*/
373 uint32_t border_cleared : 1;
375 VAGenericID wrapper_surface;
377 int exported_primefd;
380 struct object_buffer {
381 struct object_base base;
382 struct buffer_store *buffer_store;
383 int max_num_elements;
389 unsigned int export_refcount;
390 VABufferInfo export_state;
392 VAGenericID wrapper_buffer;
393 VAContextID context_id;
396 struct object_image {
397 struct object_base base;
400 unsigned int *palette;
401 VASurfaceID derived_surface;
404 struct object_subpic {
405 struct object_base base;
407 struct object_image *obj_image;
408 VARectangle src_rect;
409 VARectangle dst_rect;
419 #define I965_RING_NULL 0
420 #define I965_RING_BSD 1
421 #define I965_RING_BLT 2
422 #define I965_RING_VEBOX 3
425 VAProcFilterType type;
429 struct i965_driver_data;
431 struct hw_codec_info {
432 struct hw_context *(*dec_hw_context_init)(VADriverContextP, struct object_config *);
433 struct hw_context *(*enc_hw_context_init)(VADriverContextP, struct object_config *);
434 struct hw_context *(*proc_hw_context_init)(VADriverContextP, struct object_config *);
435 bool (*render_init)(VADriverContextP);
436 void (*post_processing_context_init)(VADriverContextP, void *, struct intel_batchbuffer *);
437 void (*preinit_hw_codec)(VADriverContextP, struct hw_codec_info *);
440 * Allows HW info to support per-codec max resolution. If this functor is
441 * not initialized, then @max_width and @max_height will be used as the
442 * default maximum resolution for all codecs on this HW info.
444 void (*max_resolution)(struct i965_driver_data *, struct object_config *, int *, int *);
448 int min_linear_wpitch;
449 int min_linear_hpitch;
451 unsigned int h264_mvc_dec_profiles;
452 unsigned int vp9_dec_profiles;
453 unsigned int vp9_enc_profiles;
455 unsigned int h264_dec_chroma_formats;
456 unsigned int jpeg_dec_chroma_formats;
457 unsigned int jpeg_enc_chroma_formats;
458 unsigned int hevc_dec_chroma_formats;
459 unsigned int vp9_dec_chroma_formats;
461 unsigned int has_mpeg2_decoding: 1;
462 unsigned int has_mpeg2_encoding: 1;
463 unsigned int has_h264_decoding: 1;
464 unsigned int has_h264_encoding: 1;
465 unsigned int has_vc1_decoding: 1;
466 unsigned int has_vc1_encoding: 1;
467 unsigned int has_jpeg_decoding: 1;
468 unsigned int has_jpeg_encoding: 1;
469 unsigned int has_vpp: 1;
470 unsigned int has_accelerated_getimage: 1;
471 unsigned int has_accelerated_putimage: 1;
472 unsigned int has_tiled_surface: 1;
473 unsigned int has_di_motion_adptive: 1;
474 unsigned int has_di_motion_compensated: 1;
475 unsigned int has_vp8_decoding: 1;
476 unsigned int has_vp8_encoding: 1;
477 unsigned int has_h264_mvc_encoding: 1;
478 unsigned int has_hevc_decoding: 1;
479 unsigned int has_hevc_encoding: 1;
480 unsigned int has_hevc10_encoding: 1;
481 unsigned int has_hevc10_decoding: 1;
482 unsigned int has_vp9_decoding: 1;
483 unsigned int has_vpp_p010: 1;
484 unsigned int has_lp_h264_encoding: 1;
485 unsigned int has_vp9_encoding: 1;
486 unsigned int has_fei_h264_encoding: 1;
488 unsigned int lp_h264_brc_mode;
489 unsigned int h264_brc_mode;
491 unsigned int num_filters;
492 struct i965_filter filters[VAProcFilterCount];
496 #include "i965_render.h"
497 #include "i965_gpe_utils.h"
499 struct i965_driver_data {
500 struct intel_driver_data intel;
501 struct object_heap config_heap;
502 struct object_heap context_heap;
503 struct object_heap surface_heap;
504 struct object_heap buffer_heap;
505 struct object_heap image_heap;
506 struct object_heap subpic_heap;
507 struct hw_codec_info *codec_info;
509 _I965Mutex render_mutex;
511 struct intel_batchbuffer *batch;
512 struct intel_batchbuffer *pp_batch;
513 struct i965_render_state render_state;
517 VADisplayAttribute *display_attributes;
518 unsigned int num_display_attributes;
519 VADisplayAttribute *rotation_attrib;
520 VADisplayAttribute *brightness_attrib;
521 VADisplayAttribute *contrast_attrib;
522 VADisplayAttribute *hue_attrib;
523 VADisplayAttribute *saturation_attrib;
524 VAContextID current_context_id;
526 /* VA/DRI (X11) specific data */
527 struct va_dri_output *dri_output;
529 /* VA/Wayland specific data */
530 struct va_wl_output *wl_output;
532 VADriverContextP wrapper_pdrvctx;
534 struct i965_gpe_table gpe_table;
537 #define NEW_CONFIG_ID() object_heap_allocate(&i965->config_heap);
538 #define NEW_CONTEXT_ID() object_heap_allocate(&i965->context_heap);
539 #define NEW_SURFACE_ID() object_heap_allocate(&i965->surface_heap);
540 #define NEW_BUFFER_ID() object_heap_allocate(&i965->buffer_heap);
541 #define NEW_IMAGE_ID() object_heap_allocate(&i965->image_heap);
542 #define NEW_SUBPIC_ID() object_heap_allocate(&i965->subpic_heap);
544 #define CONFIG(id) ((struct object_config *)object_heap_lookup(&i965->config_heap, id))
545 #define CONTEXT(id) ((struct object_context *)object_heap_lookup(&i965->context_heap, id))
546 #define SURFACE(id) ((struct object_surface *)object_heap_lookup(&i965->surface_heap, id))
547 #define BUFFER(id) ((struct object_buffer *)object_heap_lookup(&i965->buffer_heap, id))
548 #define IMAGE(id) ((struct object_image *)object_heap_lookup(&i965->image_heap, id))
549 #define SUBPIC(id) ((struct object_subpic *)object_heap_lookup(&i965->subpic_heap, id))
551 #define FOURCC_IA44 0x34344149
552 #define FOURCC_AI44 0x34344941
554 #define STRIDE(w) (((w) + 0xf) & ~0xf)
555 #define SIZE_YUV420(w, h) (h * (STRIDE(w) + STRIDE(w >> 1)))
557 static INLINE struct i965_driver_data *
558 i965_driver_data(VADriverContextP ctx)
560 return (struct i965_driver_data *)(ctx->pDriverData);
564 i965_check_alloc_surface_bo(VADriverContextP ctx,
565 struct object_surface *obj_surface,
568 unsigned int subsampling);
571 va_enc_packed_type_to_idx(int packed_type);
573 /* reserve 2 byte for internal using */
575 #define CODEC_MPEG2 1
576 #define CODEC_H264_MVC 2
582 #define H264_DELIMITER0 0x00
583 #define H264_DELIMITER1 0x00
584 #define H264_DELIMITER2 0x00
585 #define H264_DELIMITER3 0x00
586 #define H264_DELIMITER4 0x00
588 #define MPEG2_DELIMITER0 0x00
589 #define MPEG2_DELIMITER1 0x00
590 #define MPEG2_DELIMITER2 0x00
591 #define MPEG2_DELIMITER3 0x00
592 #define MPEG2_DELIMITER4 0xb0
594 #define HEVC_DELIMITER0 0x00
595 #define HEVC_DELIMITER1 0x00
596 #define HEVC_DELIMITER2 0x00
597 #define HEVC_DELIMITER3 0x00
598 #define HEVC_DELIMITER4 0x00
600 struct i965_coded_buffer_segment {
602 VACodedBufferSegment base;
603 unsigned char pad0[64]; /* change the size if sizeof(VACodedBufferSegment) > 64 */
608 unsigned int status_support;
611 unsigned int codec_private_data[512]; /* Store codec private data, must be 16-bytes aligned */
614 #define I965_CODEDBUFFER_HEADER_SIZE ALIGN(sizeof(struct i965_coded_buffer_segment), 0x1000)
616 extern VAStatus i965_MapBuffer(VADriverContextP ctx,
617 VABufferID buf_id, /* in */
618 void **pbuf); /* out */
620 extern VAStatus i965_UnmapBuffer(VADriverContextP ctx, VABufferID buf_id);
622 extern VAStatus i965_DestroySurfaces(VADriverContextP ctx,
623 VASurfaceID *surface_list,
626 extern VAStatus i965_CreateSurfaces(VADriverContextP ctx,
631 VASurfaceID *surfaces);
633 #define I965_SURFACE_MEM_NATIVE 0
634 #define I965_SURFACE_MEM_GEM_FLINK 1
635 #define I965_SURFACE_MEM_DRM_PRIME 2
638 i965_destroy_surface_storage(struct object_surface *obj_surface);
640 #endif /* _I965_DRV_VIDEO_H_ */