src/i965_drv_video.h

   1 /*
   2  * Copyright © 2009 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Xiang Haihao <haihao.xiang@intel.com>
  26  *    Zou Nan hai <nanhai.zou@intel.com>
  27  *
  28  */
  29
  30 #ifndef _I965_DRV_VIDEO_H_
  31 #define _I965_DRV_VIDEO_H_
  32
  33 #include <va/va.h>
  34 #include <va/va_enc_h264.h>
  35 #include <va/va_enc_mpeg2.h>
  36 #include <va/va_vpp.h>
  37 #include <va/va_backend.h>
  38 #include <va/va_backend_vpp.h>
  39
  40 #include "i965_mutext.h"
  41 #include "object_heap.h"
  42 #include "intel_driver.h"
  43
  44 #define I965_MAX_PROFILES                       20
  45 #define I965_MAX_ENTRYPOINTS                    5
  46 #define I965_MAX_CONFIG_ATTRIBUTES              10
  47 #define I965_MAX_IMAGE_FORMATS                  10
  48 #define I965_MAX_SUBPIC_FORMATS                 6
  49 #define I965_MAX_SUBPIC_SUM                     4
  50 #define I965_MAX_SURFACE_ATTRIBUTES             16
  51
  52 #define INTEL_STR_DRIVER_VENDOR                 "Intel"
  53 #define INTEL_STR_DRIVER_NAME                   "i965"
  54
  55 #define I965_SURFACE_TYPE_IMAGE                 0
  56 #define I965_SURFACE_TYPE_SURFACE               1
  57
  58 #define I965_SURFACE_FLAG_FRAME                 0x00000000
  59 #define I965_SURFACE_FLAG_TOP_FIELD_FIRST       0x00000001
  60 #define I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST   0x00000002
  61
  62 #define DEFAULT_BRIGHTNESS      0
  63 #define DEFAULT_CONTRAST        50
  64 #define DEFAULT_HUE             0
  65 #define DEFAULT_SATURATION      50
  66
  67 struct i965_surface
  68 {
  69     struct object_base *base;
  70     int type;
  71     int flags;
  72 };
  73
  74 struct i965_kernel
  75 {
  76     char *name;
  77     int interface;
  78     const uint32_t (*bin)[4];
  79     int size;
  80     dri_bo *bo;
  81     unsigned int kernel_offset;
  82 };
  83
  84 struct buffer_store
  85 {
  86     unsigned char *buffer;
  87     dri_bo *bo;
  88     int ref_count;
  89     int num_elements;
  90 };
  91
  92 struct object_config
  93 {
  94     struct object_base base;
  95     VAProfile profile;
  96     VAEntrypoint entrypoint;
  97     VAConfigAttrib attrib_list[I965_MAX_CONFIG_ATTRIBUTES];
  98     int num_attribs;
  99 };
 100
 101 #define NUM_SLICES     10
 102
 103 struct decode_state
 104 {
 105     struct buffer_store *pic_param;
 106     struct buffer_store **slice_params;
 107     struct buffer_store *iq_matrix;
 108     struct buffer_store *bit_plane;
 109     struct buffer_store *huffman_table;
 110     struct buffer_store **slice_datas;
 111     struct buffer_store *probability_data;
 112     VASurfaceID current_render_target;
 113     int max_slice_params;
 114     int max_slice_datas;
 115     int num_slice_params;
 116     int num_slice_datas;
 117
 118     struct object_surface *render_object;
 119     struct object_surface *reference_objects[16]; /* Up to 2 reference surfaces are valid for MPEG-2,*/
 120 };
 121
 122 struct encode_state
 123 {
 124     struct buffer_store *seq_param;
 125     struct buffer_store *pic_param;
 126     struct buffer_store *pic_control;
 127     struct buffer_store *iq_matrix;
 128     struct buffer_store *q_matrix;
 129     struct buffer_store **slice_params;
 130     int max_slice_params;
 131     int num_slice_params;
 132
 133     /* for ext */
 134     struct buffer_store *seq_param_ext;
 135     struct buffer_store *pic_param_ext;
 136     struct buffer_store *packed_header_param[4];
 137     struct buffer_store *packed_header_data[4];
 138     struct buffer_store **slice_params_ext;
 139     int max_slice_params_ext;
 140     int num_slice_params_ext;
 141     int last_packed_header_type;
 142
 143     struct buffer_store *misc_param[16];
 144
 145     VASurfaceID current_render_target;
 146     struct object_surface *input_yuv_object;
 147     struct object_surface *reconstructed_object;
 148     struct object_buffer *coded_buf_object;
 149     struct object_surface *reference_objects[16]; /* Up to 2 reference surfaces are valid for MPEG-2,*/
 150 };
 151
 152 struct proc_state
 153 {
 154     struct buffer_store *pipeline_param;
 155
 156     VASurfaceID current_render_target;
 157 };
 158
 159 #define CODEC_DEC       0
 160 #define CODEC_ENC       1
 161 #define CODEC_PROC      2
 162
 163 union codec_state
 164 {
 165     struct decode_state decode;
 166     struct encode_state encode;
 167     struct proc_state proc;
 168 };
 169
 170 struct hw_context
 171 {
 172     VAStatus (*run)(VADriverContextP ctx,
 173                     VAProfile profile,
 174                     union codec_state *codec_state,
 175                     struct hw_context *hw_context);
 176     void (*destroy)(void *);
 177     struct intel_batchbuffer *batch;
 178 };
 179
 180 struct object_context
 181 {
 182     struct object_base base;
 183     VAContextID context_id;
 184     struct object_config *obj_config;
 185     VASurfaceID *render_targets;                //input->encode, output->decode
 186     int num_render_targets;
 187     int picture_width;
 188     int picture_height;
 189     int flags;
 190     int codec_type;
 191     union codec_state codec_state;
 192     struct hw_context *hw_context;
 193 };
 194
 195 #define SURFACE_REFERENCED      (1 << 0)
 196 #define SURFACE_DISPLAYED       (1 << 1)
 197 #define SURFACE_DERIVED         (1 << 2)
 198 #define SURFACE_REF_DIS_MASK    ((SURFACE_REFERENCED) | \
 199                                  (SURFACE_DISPLAYED))
 200 #define SURFACE_ALL_MASK        ((SURFACE_REFERENCED) | \
 201                                  (SURFACE_DISPLAYED) |  \
 202                                  (SURFACE_DERIVED))
 203
 204 struct object_surface
 205 {
 206     struct object_base base;
 207     VASurfaceStatus status;
 208     VASubpictureID subpic[I965_MAX_SUBPIC_SUM];
 209     struct object_subpic *obj_subpic[I965_MAX_SUBPIC_SUM];
 210     unsigned int subpic_render_idx;
 211
 212     int width;          /* the pitch of plane 0 in bytes in horizontal direction */
 213     int height;         /* the pitch of plane 0 in bytes in vertical direction */
 214     int size;
 215     int orig_width;     /* the width of plane 0 in pixels */
 216     int orig_height;    /* the height of plane 0 in pixels */
 217     int flags;
 218     unsigned int fourcc;
 219     dri_bo *bo;
 220     VAImageID locked_image_id;
 221     void (*free_private_data)(void **data);
 222     void *private_data;
 223     unsigned int subsampling;
 224     int x_cb_offset;
 225     int y_cb_offset;
 226     int x_cr_offset;
 227     int y_cr_offset;
 228     int cb_cr_width;
 229     int cb_cr_height;
 230     int cb_cr_pitch;
 231 };
 232
 233 struct object_buffer
 234 {
 235     struct object_base base;
 236     struct buffer_store *buffer_store;
 237     int max_num_elements;
 238     int num_elements;
 239     int size_element;
 240     VABufferType type;
 241 };
 242
 243 struct object_image
 244 {
 245     struct object_base base;
 246     VAImage image;
 247     dri_bo *bo;
 248     unsigned int *palette;
 249     VASurfaceID derived_surface;
 250 };
 251
 252 struct object_subpic
 253 {
 254     struct object_base base;
 255     VAImageID image;
 256     struct object_image *obj_image;
 257     VARectangle src_rect;
 258     VARectangle dst_rect;
 259     unsigned int format;
 260     int width;
 261     int height;
 262     int pitch;
 263     float global_alpha;
 264     dri_bo *bo;
 265     unsigned int flags;
 266 };
 267
 268 #define I965_RING_NULL  0
 269 #define I965_RING_BSD   1
 270 #define I965_RING_BLT   2
 271 #define I965_RING_VEBOX 3
 272
 273 struct i965_filter
 274 {
 275     VAProcFilterType type;
 276     int ring;
 277 };
 278
 279 struct hw_codec_info
 280 {
 281     struct hw_context *(*dec_hw_context_init)(VADriverContextP, struct object_config *);
 282     struct hw_context *(*enc_hw_context_init)(VADriverContextP, struct object_config *);
 283     struct hw_context *(*proc_hw_context_init)(VADriverContextP, struct object_config *);
 284     int max_width;
 285     int max_height;
 286
 287     unsigned int has_mpeg2_decoding:1;
 288     unsigned int has_mpeg2_encoding:1;
 289     unsigned int has_h264_decoding:1;
 290     unsigned int has_h264_encoding:1;
 291     unsigned int has_vc1_decoding:1;
 292     unsigned int has_vc1_encoding:1;
 293     unsigned int has_jpeg_decoding:1;
 294     unsigned int has_jpeg_encoding:1;
 295     unsigned int has_vpp:1;
 296     unsigned int has_accelerated_getimage:1;
 297     unsigned int has_accelerated_putimage:1;
 298     unsigned int has_tiled_surface:1;
 299     unsigned int has_di_motion_adptive:1;
 300     unsigned int has_di_motion_compensated:1;
 301     unsigned int has_vp8_decoding:1;
 302     unsigned int has_vp8_encoding:1;
 303
 304     unsigned int num_filters;
 305     struct i965_filter filters[VAProcFilterCount];
 306 };
 307
 308
 309 #include "i965_render.h"
 310
 311 struct i965_driver_data
 312 {
 313     struct intel_driver_data intel;
 314     struct object_heap config_heap;
 315     struct object_heap context_heap;
 316     struct object_heap surface_heap;
 317     struct object_heap buffer_heap;
 318     struct object_heap image_heap;
 319     struct object_heap subpic_heap;
 320     struct hw_codec_info *codec_info;
 321
 322     _I965Mutex render_mutex;
 323     _I965Mutex pp_mutex;
 324     struct intel_batchbuffer *batch;
 325     struct intel_batchbuffer *pp_batch;
 326     struct i965_render_state render_state;
 327     void *pp_context;
 328     char va_vendor[256];
 329
 330     VADisplayAttribute *display_attributes;
 331     unsigned int num_display_attributes;
 332     VADisplayAttribute *rotation_attrib;
 333     VADisplayAttribute *brightness_attrib;
 334     VADisplayAttribute *contrast_attrib;
 335     VADisplayAttribute *hue_attrib;
 336     VADisplayAttribute *saturation_attrib;
 337     VAContextID current_context_id;
 338
 339     /* VA/DRI (X11) specific data */
 340     struct va_dri_output *dri_output;
 341
 342     /* VA/Wayland specific data */
 343     struct va_wl_output *wl_output;
 344 };
 345
 346 #define NEW_CONFIG_ID() object_heap_allocate(&i965->config_heap);
 347 #define NEW_CONTEXT_ID() object_heap_allocate(&i965->context_heap);
 348 #define NEW_SURFACE_ID() object_heap_allocate(&i965->surface_heap);
 349 #define NEW_BUFFER_ID() object_heap_allocate(&i965->buffer_heap);
 350 #define NEW_IMAGE_ID() object_heap_allocate(&i965->image_heap);
 351 #define NEW_SUBPIC_ID() object_heap_allocate(&i965->subpic_heap);
 352
 353 #define CONFIG(id) ((struct object_config *)object_heap_lookup(&i965->config_heap, id))
 354 #define CONTEXT(id) ((struct object_context *)object_heap_lookup(&i965->context_heap, id))
 355 #define SURFACE(id) ((struct object_surface *)object_heap_lookup(&i965->surface_heap, id))
 356 #define BUFFER(id) ((struct object_buffer *)object_heap_lookup(&i965->buffer_heap, id))
 357 #define IMAGE(id) ((struct object_image *)object_heap_lookup(&i965->image_heap, id))
 358 #define SUBPIC(id) ((struct object_subpic *)object_heap_lookup(&i965->subpic_heap, id))
 359
 360 #define FOURCC_IA44 0x34344149
 361 #define FOURCC_AI44 0x34344941
 362
 363 #define STRIDE(w)               (((w) + 0xf) & ~0xf)
 364 #define SIZE_YUV420(w, h)       (h * (STRIDE(w) + STRIDE(w >> 1)))
 365
 366 static INLINE struct i965_driver_data *
 367 i965_driver_data(VADriverContextP ctx)
 368 {
 369     return (struct i965_driver_data *)(ctx->pDriverData);
 370 }
 371
 372 void
 373 i965_check_alloc_surface_bo(VADriverContextP ctx,
 374                             struct object_surface *obj_surface,
 375                             int tiled,
 376                             unsigned int fourcc,
 377                             unsigned int subsampling);
 378
 379 int
 380 va_enc_packed_type_to_idx(int packed_type);
 381
 382 /* reserve 2 byte for internal using */
 383 #define CODEC_H264      0
 384 #define CODEC_MPEG2     1
 385
 386 #define H264_DELIMITER0 0x00
 387 #define H264_DELIMITER1 0x00
 388 #define H264_DELIMITER2 0x00
 389 #define H264_DELIMITER3 0x00
 390 #define H264_DELIMITER4 0x00
 391
 392 #define MPEG2_DELIMITER0        0x00
 393 #define MPEG2_DELIMITER1        0x00
 394 #define MPEG2_DELIMITER2        0x00
 395 #define MPEG2_DELIMITER3        0x00
 396 #define MPEG2_DELIMITER4        0xb0
 397
 398 struct i965_coded_buffer_segment
 399 {
 400     VACodedBufferSegment base;
 401     unsigned char mapped;
 402     unsigned char codec;
 403 };
 404
 405 #define I965_CODEDBUFFER_HEADER_SIZE   ALIGN(sizeof(struct i965_coded_buffer_segment), 64)
 406
 407 extern VAStatus i965_MapBuffer(VADriverContextP ctx,
 408                 VABufferID buf_id,       /* in */
 409                 void **pbuf);            /* out */
 410
 411 extern VAStatus i965_UnmapBuffer(VADriverContextP ctx, VABufferID buf_id);
 412
 413 extern VAStatus i965_DestroySurfaces(VADriverContextP ctx,
 414                      VASurfaceID *surface_list,
 415                      int num_surfaces);
 416
 417 #define I965_SURFACE_MEM_NATIVE             0
 418 #define I965_SURFACE_MEM_GEM_FLINK          1
 419 #define I965_SURFACE_MEM_DRM_PRIME          2
 420
 421 #endif /* _I965_DRV_VIDEO_H_ */