src/i965_drv_video.h

   1 /*
   2  * Copyright © 2009 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Xiang Haihao <haihao.xiang@intel.com>
  26  *    Zou Nan hai <nanhai.zou@intel.com>
  27  *
  28  */
  29
  30 #ifndef _I965_DRV_VIDEO_H_
  31 #define _I965_DRV_VIDEO_H_
  32
  33 #include <va/va.h>
  34 #include <va/va_enc_h264.h>
  35 #include <va/va_enc_mpeg2.h>
  36 #include <va/va_vpp.h>
  37 #include <va/va_backend.h>
  38 #include <va/va_backend_vpp.h>
  39
  40 #include "i965_mutext.h"
  41 #include "object_heap.h"
  42 #include "intel_driver.h"
  43
  44 #define I965_MAX_PROFILES                       11
  45 #define I965_MAX_ENTRYPOINTS                    5
  46 #define I965_MAX_CONFIG_ATTRIBUTES              10
  47 #define I965_MAX_IMAGE_FORMATS                  10
  48 #define I965_MAX_SUBPIC_FORMATS                 6
  49 #define I965_MAX_SUBPIC_SUM                     4
  50 #define I965_MAX_SURFACE_ATTRIBUTES             16
  51
  52 #define INTEL_STR_DRIVER_VENDOR                 "Intel"
  53 #define INTEL_STR_DRIVER_NAME                   "i965"
  54
  55 #define I965_SURFACE_TYPE_IMAGE                 0
  56 #define I965_SURFACE_TYPE_SURFACE               1
  57
  58 #define I965_SURFACE_FLAG_FRAME                 0x00000000
  59 #define I965_SURFACE_FLAG_TOP_FIELD_FIRST       0x00000001
  60 #define I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST   0x00000002
  61
  62 #define DEFAULT_BRIGHTNESS      0
  63 #define DEFAULT_CONTRAST        10
  64 #define DEFAULT_HUE             0
  65 #define DEFAULT_SATURATION      10
  66
  67 struct i965_surface
  68 {
  69     struct object_base *base;
  70     int type;
  71     int flags;
  72 };
  73
  74 struct i965_kernel
  75 {
  76     char *name;
  77     int interface;
  78     const uint32_t (*bin)[4];
  79     int size;
  80     dri_bo *bo;
  81 };
  82
  83 struct buffer_store
  84 {
  85     unsigned char *buffer;
  86     dri_bo *bo;
  87     int ref_count;
  88     int num_elements;
  89 };
  90
  91 struct object_config
  92 {
  93     struct object_base base;
  94     VAProfile profile;
  95     VAEntrypoint entrypoint;
  96     VAConfigAttrib attrib_list[I965_MAX_CONFIG_ATTRIBUTES];
  97     int num_attribs;
  98 };
  99
 100 #define NUM_SLICES     10
 101
 102 struct decode_state
 103 {
 104     struct buffer_store *pic_param;
 105     struct buffer_store **slice_params;
 106     struct buffer_store *iq_matrix;
 107     struct buffer_store *bit_plane;
 108     struct buffer_store *huffman_table;
 109     struct buffer_store **slice_datas;
 110     VASurfaceID current_render_target;
 111     int max_slice_params;
 112     int max_slice_datas;
 113     int num_slice_params;
 114     int num_slice_datas;
 115
 116     struct object_surface *render_object;
 117     struct object_surface *reference_objects[16]; /* Up to 2 reference surfaces are valid for MPEG-2,*/
 118 };
 119
 120 struct encode_state
 121 {
 122     struct buffer_store *seq_param;
 123     struct buffer_store *pic_param;
 124     struct buffer_store *pic_control;
 125     struct buffer_store *iq_matrix;
 126     struct buffer_store *q_matrix;
 127     struct buffer_store **slice_params;
 128     int max_slice_params;
 129     int num_slice_params;
 130
 131     /* for ext */
 132     struct buffer_store *seq_param_ext;
 133     struct buffer_store *pic_param_ext;
 134     struct buffer_store *packed_header_param[4];
 135     struct buffer_store *packed_header_data[4];
 136     struct buffer_store **slice_params_ext;
 137     int max_slice_params_ext;
 138     int num_slice_params_ext;
 139     int last_packed_header_type;
 140
 141     struct buffer_store *misc_param[8];
 142
 143     VASurfaceID current_render_target;
 144     struct object_surface *input_yuv_object;
 145     struct object_surface *reconstructed_object;
 146     struct object_buffer *coded_buf_object;
 147     struct object_surface *reference_objects[16]; /* Up to 2 reference surfaces are valid for MPEG-2,*/
 148 };
 149
 150 struct proc_state
 151 {
 152     struct buffer_store *pipeline_param;
 153
 154     VASurfaceID current_render_target;
 155 };
 156
 157 #define CODEC_DEC       0
 158 #define CODEC_ENC       1
 159 #define CODEC_PROC      2
 160
 161 union codec_state
 162 {
 163     struct decode_state decode;
 164     struct encode_state encode;
 165     struct proc_state proc;
 166 };
 167
 168 struct hw_context
 169 {
 170     VAStatus (*run)(VADriverContextP ctx,
 171                     VAProfile profile,
 172                     union codec_state *codec_state,
 173                     struct hw_context *hw_context);
 174     void (*destroy)(void *);
 175     struct intel_batchbuffer *batch;
 176 };
 177
 178 struct object_context
 179 {
 180     struct object_base base;
 181     VAContextID context_id;
 182     struct object_config *obj_config;
 183     VASurfaceID *render_targets;                //input->encode, output->decode
 184     int num_render_targets;
 185     int picture_width;
 186     int picture_height;
 187     int flags;
 188     int codec_type;
 189     union codec_state codec_state;
 190     struct hw_context *hw_context;
 191 };
 192
 193 #define SURFACE_REFERENCED      (1 << 0)
 194 #define SURFACE_DISPLAYED       (1 << 1)
 195 #define SURFACE_DERIVED         (1 << 2)
 196 #define SURFACE_REF_DIS_MASK    ((SURFACE_REFERENCED) | \
 197                                  (SURFACE_DISPLAYED))
 198 #define SURFACE_ALL_MASK        ((SURFACE_REFERENCED) | \
 199                                  (SURFACE_DISPLAYED) |  \
 200                                  (SURFACE_DERIVED))
 201
 202 struct object_surface
 203 {
 204     struct object_base base;
 205     VASurfaceStatus status;
 206     VASubpictureID subpic[I965_MAX_SUBPIC_SUM];
 207     struct object_subpic *obj_subpic[I965_MAX_SUBPIC_SUM];
 208     unsigned int subpic_render_idx;
 209
 210     int width;          /* the pitch of plane 0 in bytes in horizontal direction */
 211     int height;         /* the pitch of plane 0 in bytes in vertical direction */
 212     int size;
 213     int orig_width;     /* the width of plane 0 in pixels */
 214     int orig_height;    /* the height of plane 0 in pixels */
 215     int flags;
 216     unsigned int fourcc;
 217     dri_bo *bo;
 218     VAImageID locked_image_id;
 219     void (*free_private_data)(void **data);
 220     void *private_data;
 221     unsigned int subsampling;
 222     int x_cb_offset;
 223     int y_cb_offset;
 224     int x_cr_offset;
 225     int y_cr_offset;
 226     int cb_cr_width;
 227     int cb_cr_height;
 228     int cb_cr_pitch;
 229 };
 230
 231 struct object_buffer
 232 {
 233     struct object_base base;
 234     struct buffer_store *buffer_store;
 235     int max_num_elements;
 236     int num_elements;
 237     int size_element;
 238     VABufferType type;
 239 };
 240
 241 struct object_image
 242 {
 243     struct object_base base;
 244     VAImage image;
 245     dri_bo *bo;
 246     unsigned int *palette;
 247     VASurfaceID derived_surface;
 248 };
 249
 250 struct object_subpic
 251 {
 252     struct object_base base;
 253     VAImageID image;
 254     struct object_image *obj_image;
 255     VARectangle src_rect;
 256     VARectangle dst_rect;
 257     unsigned int format;
 258     int width;
 259     int height;
 260     int pitch;
 261     float global_alpha;
 262     dri_bo *bo;
 263     unsigned int flags;
 264 };
 265
 266 #define I965_RING_NULL  0
 267 #define I965_RING_BSD   1
 268 #define I965_RING_BLT   2
 269 #define I965_RING_VEBOX 3
 270
 271 struct i965_filter
 272 {
 273     VAProcFilterType type;
 274     int ring;
 275 };
 276
 277 struct hw_codec_info
 278 {
 279     struct hw_context *(*dec_hw_context_init)(VADriverContextP, struct object_config *);
 280     struct hw_context *(*enc_hw_context_init)(VADriverContextP, struct object_config *);
 281     struct hw_context *(*proc_hw_context_init)(VADriverContextP, struct object_config *);
 282     int max_width;
 283     int max_height;
 284
 285     unsigned int has_mpeg2_decoding:1;
 286     unsigned int has_mpeg2_encoding:1;
 287     unsigned int has_h264_decoding:1;
 288     unsigned int has_h264_encoding:1;
 289     unsigned int has_vc1_decoding:1;
 290     unsigned int has_vc1_encoding:1;
 291     unsigned int has_jpeg_decoding:1;
 292     unsigned int has_jpeg_encoding:1;
 293     unsigned int has_vpp:1;
 294     unsigned int has_accelerated_getimage:1;
 295     unsigned int has_accelerated_putimage:1;
 296     unsigned int has_tiled_surface:1;
 297     unsigned int has_di_motion_adptive:1;
 298     unsigned int has_di_motion_compensated:1;
 299
 300     unsigned int num_filters;
 301     struct i965_filter filters[VAProcFilterCount];
 302 };
 303
 304
 305 #include "i965_render.h"
 306
 307 struct i965_driver_data
 308 {
 309     struct intel_driver_data intel;
 310     struct object_heap config_heap;
 311     struct object_heap context_heap;
 312     struct object_heap surface_heap;
 313     struct object_heap buffer_heap;
 314     struct object_heap image_heap;
 315     struct object_heap subpic_heap;
 316     struct hw_codec_info *codec_info;
 317
 318     _I965Mutex render_mutex;
 319     _I965Mutex pp_mutex;
 320     struct intel_batchbuffer *batch;
 321     struct intel_batchbuffer *pp_batch;
 322     struct i965_render_state render_state;
 323     void *pp_context;
 324     char va_vendor[256];
 325
 326     VADisplayAttribute *display_attributes;
 327     unsigned int num_display_attributes;
 328     VADisplayAttribute *rotation_attrib;
 329     VADisplayAttribute *brightness_attrib;
 330     VADisplayAttribute *contrast_attrib;
 331     VADisplayAttribute *hue_attrib;
 332     VADisplayAttribute *saturation_attrib;
 333     VAContextID current_context_id;
 334
 335     /* VA/DRI (X11) specific data */
 336     struct va_dri_output *dri_output;
 337
 338     /* VA/Wayland specific data */
 339     struct va_wl_output *wl_output;
 340 };
 341
 342 #define NEW_CONFIG_ID() object_heap_allocate(&i965->config_heap);
 343 #define NEW_CONTEXT_ID() object_heap_allocate(&i965->context_heap);
 344 #define NEW_SURFACE_ID() object_heap_allocate(&i965->surface_heap);
 345 #define NEW_BUFFER_ID() object_heap_allocate(&i965->buffer_heap);
 346 #define NEW_IMAGE_ID() object_heap_allocate(&i965->image_heap);
 347 #define NEW_SUBPIC_ID() object_heap_allocate(&i965->subpic_heap);
 348
 349 #define CONFIG(id) ((struct object_config *)object_heap_lookup(&i965->config_heap, id))
 350 #define CONTEXT(id) ((struct object_context *)object_heap_lookup(&i965->context_heap, id))
 351 #define SURFACE(id) ((struct object_surface *)object_heap_lookup(&i965->surface_heap, id))
 352 #define BUFFER(id) ((struct object_buffer *)object_heap_lookup(&i965->buffer_heap, id))
 353 #define IMAGE(id) ((struct object_image *)object_heap_lookup(&i965->image_heap, id))
 354 #define SUBPIC(id) ((struct object_subpic *)object_heap_lookup(&i965->subpic_heap, id))
 355
 356 #define FOURCC_IA44 0x34344149
 357 #define FOURCC_AI44 0x34344941
 358
 359 #define STRIDE(w)               (((w) + 0xf) & ~0xf)
 360 #define SIZE_YUV420(w, h)       (h * (STRIDE(w) + STRIDE(w >> 1)))
 361
 362 static INLINE struct i965_driver_data *
 363 i965_driver_data(VADriverContextP ctx)
 364 {
 365     return (struct i965_driver_data *)(ctx->pDriverData);
 366 }
 367
 368 void
 369 i965_check_alloc_surface_bo(VADriverContextP ctx,
 370                             struct object_surface *obj_surface,
 371                             int tiled,
 372                             unsigned int fourcc,
 373                             unsigned int subsampling);
 374
 375 int
 376 va_enc_packed_type_to_idx(int packed_type);
 377
 378 /* reserve 2 byte for internal using */
 379 #define CODEC_H264      0
 380 #define CODEC_MPEG2     1
 381
 382 #define H264_DELIMITER0 0x00
 383 #define H264_DELIMITER1 0x00
 384 #define H264_DELIMITER2 0x00
 385 #define H264_DELIMITER3 0x00
 386 #define H264_DELIMITER4 0x00
 387
 388 #define MPEG2_DELIMITER0        0x00
 389 #define MPEG2_DELIMITER1        0x00
 390 #define MPEG2_DELIMITER2        0x00
 391 #define MPEG2_DELIMITER3        0x00
 392 #define MPEG2_DELIMITER4        0xb0
 393
 394 struct i965_coded_buffer_segment
 395 {
 396     VACodedBufferSegment base;
 397     unsigned char mapped;
 398     unsigned char codec;
 399 };
 400
 401 #define I965_CODEDBUFFER_HEADER_SIZE   ALIGN(sizeof(struct i965_coded_buffer_segment), 64)
 402
 403 extern VAStatus i965_MapBuffer(VADriverContextP ctx,
 404                 VABufferID buf_id,       /* in */
 405                 void **pbuf);            /* out */
 406
 407 extern VAStatus i965_UnmapBuffer(VADriverContextP ctx, VABufferID buf_id);
 408
 409 #define I965_SURFACE_MEM_NATIVE             0
 410 #define I965_SURFACE_MEM_GEM_FLINK          1
 411 #define I965_SURFACE_MEM_DRM_PRIME          2
 412
 413 #endif /* _I965_DRV_VIDEO_H_ */